Datasheet - L5964 - Automotive monolithic dual step-down switching regulator with LDO
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 49
Technical content
Datasheet sections
- 1 Simplified, general block diagram
- 2 Pin description
- 2.1 LQFP64 pins description
- 2.2 VQFPN-48 pins description
- 3 Block diagram
- 4 Applications diagram
- 5 Electrical specifications
- 5.1 Absolute maximum ratings
- 5.2 Operating voltage
- 5.3 Thermal data
- 5.4 Electrical characteristics
- 6 Functional description
- 6.1 Block description
- 6.2 Switching regulators
- 6.3 Low drop out (LDO) linear regulator
- 7 Working modes
- 7.1 Shutdown mode
- 7.2 Normal mode
- 7.3 Microcontroller mode
- 8 Application information
- 8.1 Output inductor (L)
- 8.2 Output capacitors (COUT)
- 8.3 Input capacitors (CIN)
- 8.4 Bootstrap capacitor (CBS)
- 8.5 Schottky diode
- 8.6 Compensation network
- 8.7 Power good delay time setting
- 8.8 Watch dog delay time setting
- 9 Package information
- 9.2 Package marking information
Datasheet sections
- 10 Ordering information
Features
- AEC-Q100 qualified
- Two step-down synchronous switching voltage regulators with internal power switches: – Output voltage selectable by external divider (feedback voltage at 0.9 V) – Minimum and maximum output is limited by minimum and maximum duty cycle – Internal high-side/ low-side NDMOS – 270 kHz and 2.2 MHz selectable free-run frequencies – 125 kHz < f < 2.3 MHz synchronization range at SYNCIN pin – Programmable current limits at 2 A and 4.5 A (> 2 A requires the addition of external schottky diodes) – Independent hardware enabling pins – Independent supply inputs – 180° phase shift between outputs – Synch out 90° phase shift vs DC-DC1 – Programmable switching frequency divider by 1, 2, 4, 8 between the two regulators
- Independent voltage supervisors/power-goods with selectable thresholds through external pin: – two available thresholds for UV/OV/PG signals: 90-120-95% or 80-110-85% (output voltage percentage)
- Soft-start, thermal protection
- One standby/linear regulator: – Output selectable with external resistor divider till 10 V – Soft start, hardware enable pin – 250 mA maximum current capability – Standby operative mode – Programmable power good thresholds (85% or 95% output voltage percentage) – Thermal protection
- Microcontroller reset with programmable duration, activated by output under voltage or watchdog fault
- External High Side Driver enable pin
- One integrated window watchdog (5 ms ≤ window ≤ 50 ms, with ± 20% tolerance)
- Short circuit protected outputs
- Low external components number
- Thermal shutdown junction temperature 150°C Maturity status link L5964 Automotive monolithic dual step-down switching regulator with LDO L5964 Datasheet DS15070 - Rev 1 - December 2025 For further information, contact your local STMicroelectronics sales office.
Description
L5964 is a dual step-down switching regulator with internal power switches and a low drop-out linear/standby regulator. All the regulators have independent supply voltages, enables, power goods and thermal protections. The switching regulators have selectable voltage supervisors and power goods, and selectable current limits. The LDO has power good and fixed current limitation. The two DC-DC converters can work in free-run condition, with frequency selectable between two values, 270 kHz or 2.2 MHz, or synchronize themselves to an external clock (SYNCIN pin). They are 180° out of phase, while the synchronization output signal (SYNCOUT pin) is 90° out of phase with the first regulator. The phase shift simplifies the use of two ICs in the same application (4 DC/DC regulators). DC-DC1 and DC-DC2 current limits can be independently set through the pins OCPSET1 and OCPSET2 For operation >2 A, Schottky diodes vs ground should be placed as close as possible to PHASE1/2 pins. These diodes should sustain 20 V, 2 A at room temperature and have less than 0.5 V forward voltage. The high operating frequency allowed by the synchronization input helps to reduce AM and FM interferences and grants the use of small and low cost inductors and capacitors. The L5964 can manage the microcontroller supply. A configurable reset output and a configurable watchdog input are available. This IC finds application in the automotive segment, where load dump protection and wide input voltage range are mandatory. L5964 has been qualified for car passenger cars, with a standard 14 V battery. The total quiescent current, when both DC/DCs and LDO are disabled, is less than 10 µA. The product is available in LQFP64 exposed pad up and in VQFPN48 slug down package. The slug, whenever possible, has to be connected to the ground plane. L5964 DS15070 - Rev 1 page 2/49
1 Simplified, general block diagram
Figure 1. Simplified, general block diagram
2 Pin description
2.1 LQFP64 pins description
Figure 2. LQFP64 pinout (bottom view) Table 1. LQFP64 pin list
1 MODE IN Working mode: Pin floating sets the working Mode to Normal; shorted to AGND sets
2 PGDELAY2/
from reset to watchdog input. 3 COMP2 IN/OUT DC/DC2 Error amplifier output for compensation network connection. feedback voltage to the internal reference voltage. 5 SWGND1 GROUND DC/DC analog blocks ground (Switching ground). 6 SWGND2 GROUND DC/DC analog blocks ground (Switching ground).
7 FDIVISION IN Frequency divider setting to make DC/DC2 working at a frequency that is 1/1, 1/2, 1/4
8 SUB GROUND Device substrate ground. 9 VINBUCK2 SUPPLY DC/DC2 power supply connection. 10 VINBUCK2 SUPPLY DC/DC2 power supply connection. 11 BS2 OUT Boot-strap capacitor connection for DC/DC2.
12 PHASE2 OUT DC/DC2 power stage output (for external inductor and boot-strap capacitor
13 PHASE2 OUT DC/DC2 power stage output (for external inductor and boot-strap capacitor
14 ENBUCK1 IN DC/DC1 enable (active high). 15 ENBUCK2 IN DC/DC2 enable (active high).
N# Pinname Pin type Pin description 16 PGTH1 IN Power good threshold setting for DC/DC1. Pin floating sets the threshold to 95% of Vout; shorted to AGND sets the threshold to 85% of Vout. 17 PGTH2 IN Power good threshold setting for DC/DC2. Pin floating sets the threshold to 95% of Vout; shorted to AGND sets the threshold to 85% of Vout. 18 N.C. - Not Connected. 19 PGND2 GROUND Power ground of DC/DC2. Connected to internal low-side source. 20 PGND2 GROUND Power ground of DC/DC2. Connected to internal low-side source.
21 RESET OUT Reset signal to Microprocessor in Microcontroller Mode: in Normal mode is kept in
high impedance state. Open-drain output. 22 N.C. - Not Connected.
23 IGN_BUF OUT DC/DC1 status (ON/OFF) echo to Microprocessor in Microcontroller Mode:in Normal
Mode is kept in high impedance. Open-drain output. 24 N.C. - Not Connected. 25 N.C. - Not Connected. 26 UV2 OUT Under-voltage DC/DC2 signal. Open-drain output. 27 N.C. - Not Connected. 28 UV1 OUT Under-voltage DC/DC1 signal. Open-drain output. 29 PGND1 GROUND Power ground of DC/DC1. Connected to internal low-side source. 30 PGND1 GROUND Power ground of DC/DC1. Connected to internal low-side source. 31 N.C. - Not Connected. 32 OCPSET2 IN Programmable OCP setting for DC/DC2. Pin floating sets the overcurrent threshold to 4A; shorted to AGND sets the threshold to 2 A. 33 OCPSET1 IN Programmable OCP setting for DC/DC1. Pin floating sets the overcurrent threshold to 4A; shorted to AGND sets the threshold to 2 A. 34 PGOV2 OUT Over-voltage DC/DC2 signal. Open-drain output. 35 PGOV1 OUT Over-voltage DC/DC1 signal. Open-drain output.
36 PHASE1 OUT DC/DC1 power stage output (for external inductor and boot-strap capacitor
connection).
37 PHASE1 OUT DC/DC1 power stage output (for external inductor and boot-strap capacitor
connection). 38 BS1 OUT Boot-strap capacitor connection for DC/DC1. 39 VINBUCK1 SUPPLY DC/DC1 power supply connection. 40 VINBUCK1 SUPPLY DC/DC1 power supply connection. 41 FREQSET IN Programmable internal PWM frequency for DC/DC. Pin floating sets the frequency to 2M Hz; shorted to AGND sets the frequency to 250 kHz and inhibits FDIVISION. 42 TJTEST OUT Device junction temperature information. 43 PGLDO OUT LDO regulator Power good output. Open-drain output. 44 FB1 IN/OUT DC/DC1 Output feedback. Connected to error amplifier that compares the feedback voltage to the internal reference voltage. 45 COMP1 IN/OUT DC/DC1 Error amplifier output for compensation network connection. 46 PGTHLDO IN Power good threshold setting for LDO. Pin floating sets the threshold to 95% of VOUTLDO; shorted to AGND sets the threshold to 85% of VOUTLDO. 47 AGND GROUND Device analog ground. 48 SUB GROUND Device substrate ground. 49 TAB - Device slug connection. 50 N.C. - Not Connected. L5964 Pin description DS15070 - Rev 1 page 5/49
N# Pinname Pin type Pin description 51 WDI IN Watchdog input from Microcontroller. Internal Pull Down. 52 FBLDO IN/OUT LDO regulator output feedback. 53 VOUTLDO OUT LDO regulator output. 54 VINLDO SUPPLY LDO regulator power supply. 55 VBAT SUPPLY Dedicated high voltage supply for reference blocks.
56 HSD_EN OUT
Enable signal for external High Side switch (active low). Only active in microcontroller mode, high impedance in normal mode. 57 TESTMODE IN TESTMODE pin, reserved use. Connect to ground.
58 WAKEL IN Wake-up signal to enable DC/DC1 in OR internally with ENBUCK1 pin (ignored in
Normal Mode, active low in Microcontroller Mode). 59 ENLDO IN LDO regulator enable (active high). 60 PGDELAYLDO IN LDO Power good output delay time adjustable by connecting a capacitor to AGND. 61 SYNCOUT OUT External Switching clock output signal. 62 SYNCIN IN External clock input connection. Connect an external clock at SYNCIN for frequency synchronization. 63 N.C. - Not Connected.
64 PGDELAY1/
DC/DC1 Power good output delay time adjustable by connecting a capacitor from PGDELAY1 to AGND. In Microcontroller Mode, a capacitor sets the power up delay, from reset to watchdog input. L5964 Pin description DS15070 - Rev 1 page 6/49
2.2 VQFPN-48 pins description
Figure 3. VQFPN-48 pinout (bottom view) Table 2. VQFPN-48 pin list
1 PGDELAY1/
from reset to watchdog input.
2 MODE IN Working mode: pin floating sets the working Mode to Normal; shorted to AGND sets
3 PGDELAY2/
from reset to watchdog input. 4 COMP2 IN/OUT DC/DC2 Error amplifier output for compensation network connection. voltage to the internal reference voltage. 6 SWGND GROUND DC/DC analog blocks ground (Switching ground). 8 VINBUCK2 SUPPLY DC/DC2 power supply connection. 9 BS2 OUT Boot-strap capacitor connection for DC/DC2.
10 PHASE2 OUT DC/DC2 power stage output (for external inductor and boot-strap capacitor
11 ENBUCK1 IN DC/DC1 enable (active high). 12 ENBUCK2 IN DC/DC2 enable (active high). Vout; shorted to AGND sets the threshold to 85% of Vout. Vout; shorted to AGND sets the threshold to 85% of Vout. 15 PGND2 GROUND Power ground of DC/DC2. Connected to internal low-side source. 16 PGND2 GROUND Power ground of DC/DC2. Connected to internal low-side source.
N# Pin name Pin type Pin description
17 RESET OUT Reset signal to Microprocessor in Microcontroller Mode: in Normal mode is kept in high
impedance state. Open-drain output.
18 IGN_BUF OUT DC/DC1 status (ON/OFF) echo to Microprocessor in Microcontroller Mode:in Normal
Mode is kept in high impedance. Open-drain output. 19 UV2 OUT Under-voltage DC/DC2 signal. Open-drain output. 20 UV1 OUT Under-voltage DC/DC1 signal. Open-drain output. 21 PGND1 GROUND Power ground of DC/DC1. Connected to internal low-side source. 22 PGND1 GROUND Power ground of DC/DC1. Connected to internal low-side source. 23 OCPSET2 - Programmable OCP setting for DC/DC2. Pin floating sets the overcurrent threshold to
4 A; shorted to AGND sets the threshold to 2 A
24 OCPSET1 - Programmable OCP setting for DC/DC1. Pin floating sets the overcurrent threshold to 25 PGOV2 OUT Over-voltage DC/DC2 signal. Open-drain output. 26 PGOV1 OUT Over-voltage DC/DC1 signal. Open-drain output.
27 PHASE1 OUT DC/DC1 power stage output (for external inductor and boot-strap capacitor
connection). 28 BS1 OUT Boot-strap capacitor connection for DC/DC1. 29 VINBUCK1 SUPPLY DC/DC1 power supply connection. 30 FREQSET IN Programmable internal PWM frequency for DC/DC. Pin floating sets the frequency to 2M Hz; shorted to AGND sets the frequency to 250 kHz. 31 TJTEST OUT Device junction temperature information. 32 PGLDO OUT LDO regulator Power good output. Open-drain output. 33 FB1 IN/OUT DC/DC1 Output feedback. Connected to error amplifier that compares the feedback voltage to the internal reference voltage. 34 COMP1 IN/OUT DC/DC1 Error amplifier output for compensation network connection. 35 PGTHLDO IN Power good threshold setting for LDO. Pin floating sets the threshold to 95% of VOUTLDO; shorted to AGND sets the threshold to 85% of VOUTLDO. 36 AGND GROUND Device analog ground. 37 WDI IN Watchdog input from Microcontroller. Internal Pull Down. 38 FBLDO IN/OUT LDO regulator output feedback. 39 VOUTLDO OUT LDO regulator output. 40 VINLDO SUPPLY LDO regulator power supply. 41 VBAT SUPPLY Dedicated high voltage supply for reference blocks.
42 HSD_EN OUT
Enable signal for external High Side switch (active low). Only active in microcontroller mode, high impedance in normal mode. 43 TESTMODE IN TESTMODE pin, reserved use. Connect to ground.
44 WAKEL IN Wake-up signal to enable DC/DC1 in OR internally with ENBUCK1 pin (ignored in
Normal Mode, active low in Microcontroller Mode). 45 ENLDO IN LDO regulator enable (active high). 46 PGDELAYLDO IN LDO Power good output delay time adjustable by connecting a capacitor to AGND. 47 SYNCOUT OUT External Switching clock output signal. 48 SYNCIN IN External clock input connection. Connect an external clock at SYNCIN for frequency synchronization. L5964 Pin description DS15070 - Rev 1 page 8/49
3 Block diagram
Figure 4. Block diagram
4 Applications diagram
Figure 5. Application circuit (microcontroller mode)
5 Electrical specifications
5.1 Absolute maximum ratings
Table 3. Absolute maximum ratings
5.2 Operating voltage
Table 4. Operating voltage
5.3 Thermal data
Table 5. Thermal data (LQFP64) Table 6. Thermal data (VQFPN-48)
5.4 Electrical characteristics
VVBAT = 14.4 V, VINBUCK1/2 = 14.4 V, VVINLDO = 14.4 V, Tamb = 25 °C unless otherwise specified. Symbol Parameter Condition Min Typ Max Unit Battery Supply VVBAT Battery voltage operatingrange - 3.3 - 26 V ISHUTDOWN Shutdown mode powersupply current VVBAT = VVINLDO = VVINBUCK1 = VVIBUCKN2 = 14.4V VENLDO = VENBUCK1 = VENBUCKN2 = Low; VWAKEUP = High - 3 5 µA ISTANDBY_LDO LDO standby mode powersupply current VVBAT = VVINLDO = VVINBUCK1 = VVIBUCKN2 = 14.4 V = VENLDO, VENBUCK1 = VENBUCKN2 = Low; VWAKEUP = High,No Load - 35 45 µA OVVBAT, OVVNBUCK, OVVNLDO, Over voltage lockout threshold VVBAT Rising 30 32 34 V VVBAT Falling 28 30 32 V UVVBAT Under voltage lockout threshold VVBAT Rising 2.8 3 3.2 V VVBAT Falling 2.7 2.9 3.1 V Buck converters Enable Normal mode VEN1/2 ENBUCK1/2 threshold, oscillator, BUCK On VENBUCK1/2 Rising 1.5 1.7 1.9 V VENBUCK1/2 Falling 1 1.3 1.6 V IEN1/2_LEAKAGE ENBUCK1/2 leakage current VENBUCK1 = 3.3 V, VENBUCK2 = 14 V - 1 2 µA Microcontroller mode En_Tmin Highl evel duration of ENBUCK1 enable - 20 70 150 µs IEN1 ENBUCK1 leakage current - - 3.5 5 µA WAKEL VWAKEL WAKEL Threshold, BUCK1 On WAKEL Falling 0.8 1 1.3 V WAKEL Rising 1.5 1.8 2.1 V IWAKEL WAKEL Leakage Current WAKEL = 0 V - 1.5 3 µA Buck converter VVIN1/2 OVVIN1/2 Operating range - 3.3 - 26 V HYSOVVinbuck Hysteresis - - 0.4 - V UVVinbuck Under voltage lockout threshold VVINBUCK1/2 Rising @ Vout = 1.2 V 2.7 3.0 3.3 V VVINBUCK1/2 Falling @ Vout = 1.2 V 2.6 2.9 3.2 V VFB1/2_VFB1/2 Feedback voltage - 880 900 920 mV ΔVLOADR Load regulation Load = 0.3 A to 1.5 A - 0.1 - mV ΔVLINER_VFB1/2 Line regulation VVIN1/2 = 3.3 V to 26 V - 0.1 - mV ΔVFB1/2/ VFB1/2 VFB1/2 undershoot Load = 0.5 A ↔ 1.5 A, Δt = 10 µs ±5 % VVIN1/2 = 8 V ↔ 18 V, Δt = 1 ms ±5 % RonHS High side switch on resistance QFN package - 75 90 mΩLQFP package - 90 110 RonLS Low side switch on resistance QFN package - 60 80 L5964 Electrical specifications DS15070 - Rev 1 page 13/49
Symbol Parameter Condition Min Typ Max Unit RonLS Low side switch on resistance LQFP package mΩ- 70 90 ΔVFBSWx/Δt FB pin Slope at Turn- on Soft start time related - 1 2 V/ms Error amplifier gm (1) Error Amplifier Transconductance - 1 - mS Oscillator fOSC Free-run switching frequency FREQSET pin floating 2 2.2 2.4 MHz FREQSET pin connected to AGND 0.24 0.27 0.3 MHz Peak current limit IPEAK_LIMIT Switch peak current limit OCPSET1/2Floating (2) 3.7 4.5 - A OCPSET1/2Connected to Ground (3) 1.7 2 - A Power Good and Power Good Delay for BUCK1/2 THPG1/2 PGOV1/2 Threshold as FB Voltage Percentage PGTH1/2 pin connected to AGND 80 85 92 % PGTH1/2 pin Floating 90 95 99.5 % VPG1/2L PGOV1/2 Voltage Low IPGOV1/2 = 500 µA - 0.1 0.2 V IPG1/2LEAKAGE PGOV1/2 Leakage Current VPGOV1/2 = 5 V - - 1 µA tPG1/2 Delay for reporting a fault C = 0 pF on PGDELAY 1,2 pin - 1 - µs IPG_CHARGE PGDELAY1/2 Charging current 7 10 13 µA VTHPGDLY1/2 PGDELAY1/2 Threshold 1.5 1.9 2.5 V tPG1/2 Power Good Delay Time C = 100 pF on PGDELAY1,2 pin tPG1/2 = C * VTHPGDLY1/2 / IPG_CHARGE 10 20 25 µs OVand UV for BUCK1/2 output voltage THOV1/2 OV Threshold as Percentage of FB1/2 Voltage PGTH1/2 connect to ground 105 110 115 % PGTH1/2 Floating 115 120 125 % HYSOV1/2 Hysteresis on OV1/2 PGTH1/2 pin floating/connected to AGND 4 6.5 8 % tOV1/2_GLITCH Glitch filter time for OV1/2 - - 5 - µs THUV1/2 UV Threshold as Percentage of FB1/2 Voltage PGTH1/2 Connect to Ground 72 80 84 % PGTH1/2 Floating 82 90 94 % HYSUV1/2 Hysteresis on UV1/2 PGTH1/2 pin floating/connected to AGND - 2 4 % VUV1/2L UV1/2 Voltage Low IUV1/2 = 500 µA - 0.1 0.2 V IUV_LEAKAGE UV1/2 Leakage Current VUV1/2 = 5 V - - 1 µA tUV1/2_GLITCH Glitch Filter Time for UV1/2 - 5 6.5 10 µs Synchronization fSYNC Frequency Range 50% Duty-cycle Wave on SYNCIN Pin 125 - 2300 kHz - SYNCIN Low Threshold - - - 0.8 V - SYNCIN High Threshold - 2 - - V FDIVISION Pin RFDI Resistors connected to FDIVISON pin to set switching frequency of DC/DC2 60 kΩ <RFDI<80 kΩ fSWBUCK2=1*fSWBUCK1 115 kΩ < RFDI<130 kΩ fSWBUCK2=1/2*fSWBUCK1 L5964 Electrical specifications DS15070 - Rev 1 page 14/49
Symbol Parameter Condition Min Typ Max Unit RFDI Resistors connected to FDIVISON pin to set switching frequency of DC/DC2 170 kΩ < RFDI<178 kΩ fSWBUCK2=1/4*fSWBUCK1 RFDI> 250 kΩ fSWBUCK2=1/8*fSWBUCK1 Thermal Shutdown for BUCK1/2 TSDSWx Thermal shut-down temperature Temperature Rising 155 165 175 °C HysTSDSWx Hysteresis on thermal shutdown temperature - - 8 - °C Linear regulator (LDO) enable VENLDO ENLDO threshold, linear regulator on VENLDO Rising 2.1 2.35 2.6 V VENLDO Falling 0.8 1 1.2 V VENLDO ENLDO threshold in standby mode VENLDO Rising 5.0 5.5 6.0 V IENLDO ENLDO leakage current VENLDO = 14 V
4 MOhm internal pull down
2 4 6 µA Linear regulator (LDO) VVINLDO Input voltage range - 3.3 - 26 V UVVINLDO Over voltage lockout thresholdon VINLDO VVINLDO Falling 2.7 2.9 3.1 V VFBLDO Feedback Voltage Load Current = 250 mA (normal mode) 980 1000 1020 mV Load Current = 50 mA (st-by mode) 960 990 1020 mV ΔVLOADR_FBLDO Load Regulation ΔVFBLDO, Load Current = 0 mA to 50 mA, VVOUTLDO = 1.5 V, Standby Mode -2.5 -1 0 mV Load Current = 0 mA to 250 mA VVOUTLDO = 1.5 V, Normal Mode -2 -0.8 0 mV ΔVLINER_FBLDO Line regulation ΔVFBLDO, VVINLDO = 3.5 V to 18 V, Load current = 50 mA - 1 - mV ΔVFBLDO / VFBLDO Undershoot/Overshoot 5 mA ↔ 250 mA Load Transition in Δt = TBD -5 - 5 % 8↔ 18 V VVINLDO Transition in Δt = TBD -5 - 5 % Co Output capacitance - 3 - - µF ESR Output Capacitor ESR - - - 0.2 Ω VDROPOUT_LDO Drop-out Voltage VVOUTLDO = 3.3 V, Load current = 50 mA VVOUTLDO decreasing of 100 mV, Standby Mode - 0.25 0.3 V VVOUTLDO = 3.3 V, Load current = 250 mA VVOUTLDO decreasing of 100 mV, Normal Mode - 0.35 0.45 V ILIMIT_DO Short circuit current limit VOUTLDO Shorted to Ground, Standby Mode - 70 - mA VOUTLDO Shorted to Ground, Normal Mode - 380 - mA PSRRLDO Power supply rejection ratio Load Current = 50 mA, 10 Hz < f < 10 kHz 1Vacpp on VINLDO 50 - - dB tSOFT_START Soft-start Period - 150 250 350 µs Thermal shutdown for linear regulator L5964 Electrical specifications DS15070 - Rev 1 page 15/49
Symbol Parameter Condition Min Typ Max Unit TSDLDO Thermal Shut-down Temperature Temperature rising 155 165 175 °C HYSTSDLDO Hysteresis on Thermal Shutdown Temperature - - 8 - °C Power Good and Power Good Delay for linear regulator THPGLDO PGLDO threshold as percentage of FBLDO voltage PGTHLDO pin connected to AGND 83 87 91 % PGTHLDO pin floating 94 97 99.5 % VPGLDOL PGLDO voltage low IPGLDO = 500 µA - 0.1 0.2 V ILEAKAGE_PGLDO PGLDO leakage current VPGLDO = 5 V - - 1 µA TPGLDO Delay for reporting a fault C = 0 pF on PGLDO DELAY Pin - 1 2 µs TGLITCH_PGLDO Glitch Filter Time for PGLDO - 10 14 17 µs IPG_CHARGE PGDELAYLDO Charging Current - 7 10 13 µA VTHPGLDODLY PGDELAYLDO threshold - 1.5 2 2.5 V tDLYPGLDO PowerGood Delay Time C = 100 pF on PGLDO DELAY Pin tDLYPGLDO = C * VTHPGLDODLY/ IPG_CHARGE 15 20 25 µs High side driver enable Vhsd_en Output voltage low Load = 2 mA - 0.1 0.2 V Window watchdog VWDI Input high voltage - 2 - - V Inputl ow voltage - - - 0.8 V TWD WDI minimum period - - 5 - ms WDI maximum period - 35 45 55 ms WDI Glitch immunity (1) - - 100 150 ns RESET function VRESET Reset voltage IRESET = 500 µA - 0.1 0.2 V Tinternal_reset Fixed internal reset time (4) - 0.8 1 1.2 ms TDLYRESET Delay time C = 100 pF on RESET Pin 15 20 25 µs ILEAKAGE_RESET RESET leakage current VRESET = 3.3 V - - 1 µA IGNITION BUFFER (IGN_BUF PIN) IGNBUF Output leakage BUCK1 on, microcontroller mode - 0 1 µA IGNBUF Output Voltage Low BUCK1 off, microcontroller mode IIGN_BUF = 500 µA - 0.1 0.25 V 1. Guaranteed by design. 2. A 20 V, with less than 0.5 V forward voltage, and 2 A at room temperature Schottky diode to ground is required as close to the phase pin as possible, to enable > 2 A current capability 3. Guaranteed by bench validation. 4. RESET time is the sum of Tinternal_reset and Tdelay . Treset = Tinternal_reset + Tdelay L5964 Electrical specifications DS15070 - Rev 1 page 16/49
6 Functional description
6.1 Block description
6.2 Switching regulators
by an external resistor divider, at the feedback pin. 900 µs and doesn't change with operating frequency. DC/DCs can work with an external clock at the SYNCIN pin: the applied frequency is automatically adopted. shorted to ground, the FDIVISION pin is inhibited. Figure 6. PWM frequency management
6.3 Low drop out (LDO) linear regulator
(see Figure 8 for reference). power-good signal is available with 2 different selectable thresholds, which can be chosen acting on PGTHLO pin. capacitor on PGDELAYLDO pin. Figure 7. LDO diagram
Figure 8. Enable timing for LDO regulator in Normal Mode (ENLDO < 5 V) The linear regulator works as Standby Regulator when ENLDO is brought to a voltage higher than 5.5 V typ. standby regulator as soon as the battery voltage is present. resetting the latch. An under-voltage of VBAT switches off the LDO. reduce supply current consumption.
Figure 9. Enable timing for standby regulator
7 Working modes
7.1 Shutdown mode
and current consumption from supply line is very low (10 µA). Figure 10. Shutdown Mode configuration
7.2 Normal mode
internally floating (see Figure 11). Figure 11. ENBUCK2 internal block diagram
Figure 12. Output signals behavior in normal mode Table 7. Relationship between capacitor value at PGDELAY pin and delay duration Table 8. 2 presets which can be selected through PGTH12 pin UV1/2 and OV1/2 outputs are available: power-good1/2 status can be derived consequently (see Figure 13). its own power-good signal PGLDO and PGDELAYLDO, but it has no UV/OV detection. UV/OV pin; the fault is not latched.
Figure 13. OV,UV functions reference (current control mode). In case of over current in the inductor it is internally limited by control loop. stage is switched off. It is turned on automatically when temperature decreases under low shutdown threshold. Each regulator has its own thermal sense and it is independently switched off.
7.3 Microcontroller mode
power-good 1/2 signals (at PGOV1/2 pins) will show no delay. Where Ilim is the maximum current permissible in ENBUCK1 pin, 1 mA. (TWD), otherwise a watchdog fail is detected and a Reset will be issued (see Figure 14). Figure 14. ENBUCK1 internal block diagram in microcontroller mode
Figure 15. Microcontroller mode power up phase asserted the external PMOS is turned OFF. Table 9. Relationship between capacitor value at PGDELAY pin and Reset/Power Up duration: be ignored. A Reset event can reset the internal Enable latch (Watchdog fail or under voltage on DC/DC1 output).
a Reset is asserted. Fault is managed as described in Figure 18 and Figure 19. The table below resumes Fault Management for all regulators in all working modes. Table 10. Fault Management for all regulators in all working modes Vout UV No action (only detection after 10 µs (typ) of filtering time). lower than shutdown threshold (considering hysteresis). shutdown threshold (considering hysteresis). Output short Current limit to 250 mA (normal mode). Current limit to 50 mA (Standby mode). when VINLDO returns to normal value. when VBAT returns to normal value. VBAT UV LDO switched off and switched on again when VBAT returns to normal value.
Figure 20. TJTEST voltage vs junction temperature Note: Values coming from corners simulation at Ibias = 10 µA. Table 11. TJTEST voltage vs junction temperature
8 Application information
8.1 Output inductor (L)
The value of the output inductor is usually calculated to satisfy the peak-to-peak ripple current requirement. For the best compromise of cost, size and performance, it is suggested to keep the inductor current ripple between 20% and 40% of the maximum load current. For example, if a ΔIL = IRIPPLE = 0.3 x IOUT(MAX). Where, IOUT(MAX) is the maximum output current. Then, the inductor value can be estimated by the following equation: L > fSW ∆ IL VOUT (1 − VOUT V IN ( MAX ) (1) Where, fSW is the switching frequency, VIN(MAX) is the maximum input voltage. The peak current flowing in Inductor is IL(PEAK) = IOUT(MAX) + ΔIL / 2. If the Inductor value decreases, the peak current increases. The peak current has to be lower than the current limit of the device. An inductor having saturation current higher than the device current limit has to be chosen.
8.2 Output capacitors (COUT)
Output capacitors are selected to support load transients and output ripple current, as well as to get loop stability. The amount of voltage ripple can be calculated by the output ripple current flowing in the Inductor: ∆ VOUT(RIPPLE) = ∆ IL (ESR + 8fSW COUT (2) Usually the first term is dominant. However, if a ceramic capacitor (which is recommended) is adopted, the first term on the above equation can be neglected as the ESR value is very low. COUT (MIN) = ∆ IL 8fSW× (VOUT (RIPPLE) − ∆ IL × ESR) (3) For example, in case VOUT = 3.3 V, VIN = 14 V, fSW = 250 kHz, ΔIL = 0.3 x 3.5 A = 1.05 A, in order to have a ΔVOUT = 5% × VOUT = 0.165V , a capacitor bigger than 3.3 µF is needed ignoring the ESR of the capacitor. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. The ESR can be minimized by simply adding more capacitors in parallel, or by using higher quality capacitors. It is important to have a big enough output capacitor to sustain the output voltage during a load transient. The regulator usually needs time to maintain the output voltage during load transitions. Eq. (4) shows the minimum output capacitance needed in this case. This value does not take the ESR of the output capacitor into account in the output voltage change. High quality capacitors or lower ESR capacitors are recommended. The minimum output capacitance needed is also determined by the maximum energy stored in the inductor when a high current to low current transition occurs. The capacitance must be sufficient to absorb the change in inductor current as Eq. (5). ΔVOUT COUT ( MIN ) = (I ) × OUT ( MAX) − I 2.5TswOUT (MIN ) (4) COUT ( MIN ) = ΔVOUTVOUT I OUT ( MAX) 2 2− IOUT (MIN) L (5) Where: IOUT(MAX) and IOUT(MIN) refer to the worst case load in the system and ΔVOUT is the tolerance of the regulated output voltage. Generally, if the minimum output capacitance satisfies Eq. (4) and Eq. (5), it is bigger enough to meet also Eq. (3). However, the final output capacitance should be the biggest one among them. L5964
Application information
DS15070 - Rev 1 page 30/49
8.3 Input capacitors (CIN)
The input capacitors must be chosen to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitors must deliver the RMS current according to the below equation: IRMS > IOUT (MAX) √ D(1 − D) (6) Where IOUT(MAX) is the maximum DC output current and D is the duty cycle. This function has a maximum at D = 0.5 and it is equal to IOUT(MAX)/2. Ceramic capacitors can deliver quite a bit of current but their total capacitance is relatively low. Electrolytic capacitors typically offer much more capacitance than ceramic capacitors, but can typically deliver a current of 100 to 500 mArms. So a good design will employ both types of capacitor with the ceramic capacitors placed closest to the input pins of the device. As a result, ceramic capacitors which have very low ESR and inductance are the best for filtering the high frequency switching noise, and electrolytic capacitors are typically able to provide more current over extended periods of time where VIN would otherwise droop.
8.4 Bootstrap capacitor (CBS)
A bootstrap capacitor must be connected between the BSx and PHASEx pins to provide floating gate drive to the high-side MOSFET. For most applications 47 nF is sufficient. This should be a ceramic capacitor with a voltage rating of at least 6 V.
8.5 Schottky diode
When the L5964 needs to supply more than 2 A from a switching regulator, one Schottky diode has to be connected at each output of the DC-DC converter (cathode on PHASE1/PHASE2 pins, anode on PGND1/ PGND2). The Schottky diode needs to have a breakdown voltage equal or higher than PHASE pin absolute maximum ratings of 40 V, with less than 0.5 V forward voltage at 2 A forward current at room temperature 25 °C. In order to keep the voltage drop within 0.5 V, the series resistance to the diode should be minimized, keeping short and large PCB connection between the diode and the phase pin, the diode and ground. Maximum parasitic capacitance that Schottky can add is 2 nF. Parasitic capacitor will affect the snubber. Figure 21 shows simulations in 3 conditions: the red line shows the L5964 alone, the blue line shows the Schottky STPS3L40UF alone and the green line shows the parallel of L5964 and STPS3L40UF. They are the worsts case conditions for both L5964 (highest current capability versus process spread) and Schottky (lowest current capability). Comparison is made at 3 temperatures. The blue line must be always lower than the red one: higher distance means higher protection. The green line close to blue line says that almost all the current flows through the Schottky diode. L5964 DS15070 - Rev 1 page 31/49
Figure 21. Worstcase I/V characteristic of L5964, Schottky diode and L5964 protected with Schottky
8.6 Compensation network
is a transconductance amplifier with large bandwidth, which is much larger than the closed-loop one. Figure 22. Basic control loop block diagram DS15070 - Rev 1 page 32/49
Where: s is the angular frequency; VREF is the internal reference voltage, 0.9 V; VOUT is the output voltage of the converter; GMOD(s) is the transfer function of the modulator with COUT and RLOAD. GMOD(s) forms a pole and a zero by RLOAD, the output capacitor (COUT), and its ESR as expressed in below equation: G (s) =MOD gmMODR )LOAD (1 + sESR x COUT (1+sR )LOAD COUT (8) gmMOD = 3.6S R =LOAD VOUT IOUT MAX (9) The dominant pole is: ƒ =pMOD 2πCOUT ESR)(R LOAD (10) The zero is : f =zMOD 2πCOUT ESR (11) GEA(s) is the transfer function of the buck convertor from control to output. It forms two poles and a zero as expressed in the equation below: GEA(s) ≈ gmEA ro (1+ sRCCC) (1+ srO CC)(1+ sRCCF) (12) Where: gmEA is the transconductance of the error amplifier, 1mS. rO is the output resistance of error amplifier. The zero is: ƒ =zEA 2π x C x RC C (13) The option pole is: ƒ =pEA 2π x C x RF C (14) L5964 DS15070 - Rev 1 page 33/49
Figure 23. Simplified gain plot The zero fzEA set by CC and RC cancel the pole fpMOD set by RLOAD and COUT. The optional pole fpEA set by CF and RC to cancel the output capacitor ESR zero if it occurs near the crossover frequency fC, where the loop gain equals 1 (0 dB). The power modulator has a DC gain set by gmMOD x RLOAD. gmMOD is transconductance of modulator, it is about 3.6S. The following equations allow to approximate the value for the gain of the power modulator GAINMOD(DC). GAINMOD(DC) = gmMOD x RLOAD (15) The total loop gain as the product of the modulator gain, the feedback voltage-divider gain, and the error-amplifier gain at fC should be equal to 1. So: GAINMOD(fC) = GAINMOD(DC) × fpMDO fC (16) The guidelines for calculation of network: 1. Choose a value for fC,usually between fSW/5 and fSW/10. 2. Choose resistor divider R1 and R2 to set the desired VOUT. 3. Calculate the value of RC as follows: RC = VOUT gmEA × VFB × GAINMOD(fC) (17) 4. Set the error-amplifier compensation zero formed by RC and CC (fzEA) at the fpMOD. Calculate the value of CC as follows: 1CC = 2π x fpMOD Cx R (18) 5. If fzMOD is less than 5fC, add a second capacitor, CF, from COMP to GND and set the compensation pole formed by RC and CF (fpEA) at the fzMOD. Calculate the value of CF as follows: 1CF = 2π x fzMOD Cx R (19) L5964 DS15070 - Rev 1 page 34/49
8.7 Power good delay time setting
The PGDELAY1 and PGDEALY2 pins are multipurpose pin that provide a delay function of power good output when chip is out of microcontroller mode. There is an internal 10 µA current source to charge up the external delay capacitor. The delay time is set by : 2.2VTDLY CDLY = 10µA (20) Where: CDLY is the external delay capacitor.
8.8 Watch dog delay time setting
The PGDELAY1 and PGDEALY2 pins are multipurpose pins that do not provide a delay function of power good output when chip is in microcontroller mode. The PGDELAY1 set the reset duration time (TR) and PGDEALY2 set the power up delay time (TUP). 2.2VTR CDLY = 10µA (21) 2.2VTUP CDLY = 10µA (22) Where: CDLY is the external delay capacitor. L5964 DS15070 - Rev 1 page 35/49
9 Package information
To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 LQFP64 (10x10x1.4 mm exp. pad up) package information Figure 24. LQFP64 (10x10x1.4 mm exp. pad up) package outline
Package information
DS15070 - Rev 1 page 36/49
Table 12. LQFP64 (10x10x1.4 mm exp. pad up) package mechanical data
- Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusion is “0.25
- The Top package body size may be smaller than the bottom package size by much as 0.15 mm.
DS15070 - Rev 1 page 37/49
- Number, dimensions and position of shown groves are for reference only: GADG2108170827PS L5964
DS15070 - Rev 1 page 38/49
9.2 Package marking information
Figure 25. LQFP64 (10x10x1.4 mm exp. pad up) marking information engineering samples to run a qualification activity. DS15070 - Rev 1 page 39/49
9.3 VFQFPN-48 (7x7x1.0 mm - opt. D) package information Figure 26. VFQFPN-48 (7x7x1.0 mm - opt. D) package outline COPLANARITY SHALL NOT EXCEED 0.08 mm.
- ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES.
- WARPAGE SHALL NOT EXCEED 0.10 mm.
- COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
0.20 Ref
0.075 Ref
0.05 Ref
DS15070 - Rev 1 page 40/49
Table 13. VFQFPN-48 (7x7x1.0 - opt. D) package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
DS15070 - Rev 1 page 41/49
9.4 VFQFPN-48 (7x7x1.0) marking information Figure 27. VFQFPN-48 (7x7x1.0) marking information to any decision to use these engineering samples. DS15070 - Rev 1 page 42/49
Table 14. Ordering information
Ordering information
DS15070 - Rev 1 page 43/49
Revision history
Table 15. Document revision history 02-Dec-2025 1 Initial release.
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