Overview
IDT74SSTUBF32868A is listed in the Logic IC category. Available datasheets include documents from Renesas Technology Corp.
Summary
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Description
This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output.
Source title
IDT74SSTUBF32868A Datasheet(PDF) - Integrated Device Technology