HD81803

HD81803 HITACHI

Document overview

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Technical content

a ] ADPCM Transcoder Conforming to G.721 @- HITACHI Prelietinery Jan. 1990 ee] Description Features The HD81803 is a single-chip ADPCM (Adaptive + Full conformity with CCITT Recommendation Differential Pulse Code Modulation) Transcoder G.721 conforming to the CCITT Recommendation + ADPCM transcoding ensures speech data G.721. It can compress and expand voice data by accuracy ADPCM transcoding, and is suitable for high- + —64-kbits/s channel can be compressed to 32 quality voice recording and playback systems. kbits/s (Half-Duplex) Applications include ISDN services, voice mail, * Serial or parallel input/output and private broadcasting. * Parallel input/output allows digital sequence tests specified by the CCITT Converting data from PCM code to ADPCM code «Parallel input/output width can be selected as reduces the memory needed to store voice data by 4, 8, or 16 bits (suitable for a 125-, 250-, or half the size. Also, since the HD81803 conforms 500-1s microprocessor I/O cycle) to G.721, it can be used in ISDN line terminal. Through functions are available to input/output equipment. specific waveforms without ADPCM . transcoding The HD81803 can be directly connected toaPCM =. 4. Jaw or pelaw PCM can be input/output CODEC, and can convert a 64-Kbits/jt-law or A- . Direct connection to a PCM CODEC is law PCM channel to and from a 32-kbits/s possible ADPCM channel. + Built-in interface for 8- and 16-bit microprocessors + Operating mode can be controlled by i microprocessor + +5 V power supply | eee i PCM data ADPCM data Encoder Serial input Serial or parallel! output Decoder _ Serial or parallel output _Serial or parallel input (Through and test functions are not included.) i

Coding process CCITT recommendation G.721 ADPCM : ‘SamplingtrequencysiSKHZSS—S—SSC‘CS:*S Code length 4 bits : Data rate 32 kbits/sec Serial interface (1) p-law PCM CODEC (ex. HD44238C/HD44278P) (PCM CODEC interface) (2) AJaw PCM CODEC (ex. HD44237C/HD44277P) H Parallel interface (1) 8-bit microprocessor | (microprocessor interface) (2)16-bitmicroprocessor | ‘Supplementary functions -—=«(1)Serialcommunication == | (2) High-quality waveform input/output (through function) | (3) Digital sequence test (CCITT Recommendation G.721) Fabrication Process CMOS 1.3 um | Powerdissipation ss SOW) | Power supply voltage +5V | Package SAG pinpplastic DIP, 44-pin PLCC i i i i

Ground data GND (41 40[] osc Input clock Voltage level 1 vii LJ2 39 {_] SCLK Internal system clock Operating mode select 2 MODE2 [}3 38 (7) RES Reset Dis (44 37{/] VH Voltage high o7 (5 36[] SO Serial output D14 (J6 35 [|] LAW u-/A-law select De (17 34{-] REQ Data transfer request

013 LJ8 33 [_) SICK

Ds C]9 32 |-] SOEN . p12 C10 ao =| Seria VO control Parallel input/output data bus dati 30 [J SIEN D11 (}12 29{] SI Serial input D3 (413 28{"] MODE1 Operating mode select 1 O10 (414 27(-) F2 Parallel /O control b2 (j15 26 [J VL2 Voltage level 2 Do (_}16 25{) F1 01417 24{] Fo ds (418 23[] Cs Parallel /O control Do [_}19 2217] RW +5 V power supply VecL]20 aCe (Top view)

__ MODE1 RES MODE2 osc Clock REQ sick |— ADPCM r cs SIEN pelaw coding/ | | Abhe 3 RW sl |__J g Ataw| | Gocacing 3 k— e 3 } 4 2 FO to F2 5 3 sock 3 Linear 4/8/ s SOEN a lcon- L | 16-bit & L | lversior data so K lcon- KK _) Dotopis 7 | version] 7 7

Electrical Characteristics

Item Symbol Value Unit Note Power supply voltage Voc 0.3 to +7.0 Vv Input voltage Vin 0.3toVec +03 V Operating temperature Topr -20 to +75 °C Storage temperature Tsig —55 to +125, °C DC Characteristics (Vcc = 5.0 V +5%, GND = 0 V, T, = -20 to +75°C; unless otherwise specified) Item Pins Symbol Min Typ Max Unit Test Conditions Input high Osc Via 24 — Voc+03 V voltage IE, SICK, SOCK 2.4 = Voc +03 RES Vecx0.7 — Voc + 0.3 Other input pins 2.2 — Veo + 0.3 Input low osc Vit -0.3 — 04 v voltage IE, SICK, SOCK 03 — 04 RES -0.3 — 04 Other input pins 0.3 — 04 Input leakage IE, RAW, CS,FOto In| - — 10 HA Vin = 0.410 2.4V current F2, SI, SIEN, SOCK, SOEN, SICK, RES, OSC High- Do to D15, SO tIrs| - — 10 BA Vin = 0.4 to 2.4V impedance i leakage i current i (off state) : Open drain REQ, MODE1, thou! = — — 10 BA Vin = 0.4 to 2.4V current MODE2, LAW (off state) Output high DO to. D15, SO Von 2.4 - = Vo Alo = 400 pA voltage Output low D0 to D15, SO, REQ Voy - — 08 Vi lop = 1.6 mA voltage ! Input All input pins Cin — — 125 PF Vin = OV, f = 1 MHz, capacitance Ta = 25°C ! Current lec - 30 © 100 mA No load dissipation ‘on output

AC Characteristics (Voc = 5.0 V +5%, GND = 0 V, T, = -20 to +75°C unless otherwise specified) System Clock item Symbol Min Typ Max Unit Test Conditions ' Clock (OSC) period Scye 30.0 31.25 325 ns See Figure 1 ; Clock (OSC) pulse width OwH 10 - - ns Ow. 10 _- - ns Clock (OSC) rise time o - — 5 ns Clock (OSC) fall time oO ad - 5 ns Reset Timing Item Symbol = Min Typ Max Unit Test Conditions ha och LT Power-on reset time tac 20 - - ms See Figure 2 Reset pulse width tast 1.0 _- - ps Serial /O Timing Item Symbol Min Typ Max Unit Test Conditions ah kG Clock (SICK, SOCK) period Syc 0.4 — 10.0 us See Figure 3 Clock (SICK, SOCK) pulse width = Swy 100 - - ns Sw. 100 — = ns Clock (SICK, SOCK) rise time Ss, - - 20 ns i Clock (SICK, SOCK) fall time Ss; _ - 20 ns Serial input data setup time tsps 50 = = ns | Serial input data hold time tsp 50 _ - ns | Serial output data delay time tspp - - 80 ns | Enable delay time ted 50 — - ns ' Enable setup time tes 50 - - ns i j i

Item Symbol Min Typ Max Unit Test Conditions IE period eye 05 = = ys See figure 4 IE pulse width twu 210 - 5000 ns twe 2100 = ns IE rise time t - - 20 ns IE fall time i - _ 20 ns CS setup time tes 60 = = ns CS hold time ton 10 - - ns Input data setup time tosw 60 - - ns Input data hold time touw 10 - = ns Output data delay time topr _- _ 150 ns Output data hold time tour 20 = — ns Timing Diagrams % OwH or “ == Figure 1 Clock Input Waveform

(Clock input)

5.25 V ¢

4.75V fF Vec __ Vi RES Vi Vit FE Reset Reset start start Note: The 32-MHz clock must be supplied during power-on reset and tasr- Figure 2 Reset Timing Scyc St | soct a a i SOCK, N | SIEN (2.4 V) Vin | SOEN (0-4 V) Vi tsos 4. (oY i (2.4) Vin - ; sI ( » (0.4 V) Vit tspp tsop | 0.8 Vv \\ | Figure 3 Serial I/O Timing

Symbol Pin No. vo Description Power supply Veco 20 +5 V power supply GND 1 Ground : Clock osc 40 Input Input clock: Apply a 32-MHz clock signal. SCLK 39 Output Internal system clock: Outputs a 8-MHz clock except during reset. Serial VO SICK 33 Input Serial input clock: Serial data is input at the falling SICK edge. SIEN 30 Input Serial input enable: Serial data can be input when SIEN is high. SI 29 Input Serial input: Serial data must be input MSB first. SOCK 31 Input Serial output clock: Serial data is output after the rising SOCK edge. | SOEN 32 Input Serial output enable: Serial data can be output when SOEN is high. so 36 Output Serial output: Three state serial output. After SOEN goes low, SO enters a high-impedance state after the next rising SOCK edge. Parallel input FOtoF2 24,25,27 Input Parallel /O Control: Used for specifying the transfer of commands or data. cs 23 Input Chip select: While CS is low, parallel input/output (FO to F2, R/W, _ IE and DO to D15) are enabled. : RW 22 Input Read/write Control: Input for deciding the direction of transferring data, which can be output while R/W is high and input while R/W is tow. | IE 21 Input Data bus enable: Data can be input or output while IE is high. | Parallel input/output data bus j DOtoD15 41019 Input/Output Data bus: Three state bus for transferring data tofirom a i microprocessor. Use mode select pins, MODE1 and 2 to select | either 8- or 16-bit transfer, If 8-bit transfer is selected, ground D& | through D15. | _ Auxillary output REQ 34 Opendrain _ Data transfer request: Notifies the microprocessor that data is output ready for transter by the level output (low level). REQ enters a | high-impedance state after the transfer is completed. | Operating mode select i MODE1 28 Input Operating mode select pins: These can select following modes: | MODE2 3 Input MODE1 low and MODE2 low selects serial coding mode. | MODE1 low and MODE2 high selects serial decoding mode. | MODE‘1 high and MODE2 low selects byte transferring mode. | MODE1 high and MODE2 high selects word transferring mode. | LAW 35 Input p-/A-law select pin: j1-law is selected when LAW is low, and A law | is selected LAW is high. | __ Reset | RES 38 Input LSI reset input. i OO SSFSFSSSFSSeFeeseF | Other pins ! VL1,VL2 2,26 Input Voltage level 1 and 2: Test pins (connect to ground) VH 37 Input Voltage high: Test pin (connect to +5 V)

The HD81803 has two operating modes: Parallel © PCM out pin of a PCM CODEC, the SIEN enable mode is used to operate the HD81803 in _ signal is used to provide 8 kHz synchronization combination with a microprocessor (Figure 6), and the SICK clock signal is used to provide bit and; serial mode is used for stand-alone operations synchronization. For serial PCM output, SO pin is (Figure 7). The MODE] signal determines which _used can be directly connected to a PCM in pin of mode is selected. Serial mode can be used for a PCM CODEC, the SOEN and SOCK signals are either input or output ADPCM serial data. used, Physically, the HD81803 has two serial interfaces The parallel interface allows a microprocessor to and one parallel interface. One serial interface is | control the HD81803 and to send or receive for the input and the other is for the output of speech data. Parallel I/O control signals FO to F2 either PCM or ADPCM data. are used to indicate whether the data on the bus (D0 to D15) is command or speech data. The serial interface input or output can be connected directly to a PCM CODEC. For serial © Commands can be transferred at any time while PCM input, SI pin can be directly connected toa _ the HD81803 is in operation.

7 Voc

_ —_ MODE}, 2, LAW ‘Synchronizing im SICK REQ -—> Data transfer request clocks on SIEN O sl cs Serial input | RW (from PCM out pin SOCK Ie Microprocessor of PCM CODEC) SOEN Foto F2 interface fo so DotoD1I5K 7 > Serial output Bor16 (to PCM in pin : of PCM CODEC) Figure 6 Example Operation in the Parallel Mode Serial input Serial output interface HD81803 interface MODE1, 2, LAW Synchronizing { SICK SOCK } Synchronizing clocks SIEN SOEN clocks ! Serial input i) so Serial output PCM CODEC or soovsnene=one--o--3> | or PCM in pin of PCM SO pin of HD81803 CODEC i Figure 7 Example Operation in the Serial Mode | 11

Figure 8 shows the data flow for the 8-bit parallel from 64 kbits/s to 32 kbits/s. Since the data bus mode. The p-law PCM data arriving at the serial _can be 8 or 16 bits wide, one, two, or four samples input is converted to ADPCM format and output _of the coded data can be output at once. on the data bus (in this case, 8 bits at a time). The HD81803 compresses input speech data from 8-bit_ For decoding, ADPCM data is input via the codes into 4-bit codes. Since the sampling Parallel interface and converted into 1-law PCM frequency is 8 kHz, the speech data is compressed Which is output from the serial output. i , : ; ADPCM Abit Data transfer request i Wlaw coding codes x 2 (every 250 ys) ! Serial input | pelaw J Linear | PCM codes . ‘ 8 bits ADPCM code data every 125 ys Linear - data Do to D7 Jconversion 4-bit code pack i (u-law PCM CODEC, 8-bit parallel mode) (a) Coding i Linear ADPCM 8 bits Data transfer request | . decoding data (every 250 ps) | Serial output| | pelaw J ‘4-bit code J | PCM codes i) 4-bit ADPCM code data | every 125 us b-law Linear codesx2 D0 to D7 | |conversior unpat ck i (u-law PCM CODEC, 8-bit parallel mode) i (b) Decoding j Figure 8 Data Flow in the Parallel Mode i

Operating Mode Select Pins The HD81803 has three operating mode select — modes, respectively. The PCM CODECSs* used in | pins: MODE1, MODE2, and LAW (see Table 1). these examples, which contain A/D and D/A i Command 0 (see “Parallel Interface") can also be + converters with 12- or 13 bit precision, S/H | used to select the operating mode. circuitry, and filters all on a single chip, can | effectively reduce the scale and cost of an analog i TO ————————__ I/O system. To synchronize the serial interfaces . with the PCM CODEC, the serial I/O clock and | Serial Interface enable signals are supplied externally. i The serial interfaces allow the HD81803 to be . + i connected directly to a PCM CODEC. The LAW aoe enon ae chown a aure 7. Since ae eens Mine (ene Table 2) CODEC uses" ADPCM codes are 4 bits long, the serial 1/0 | 8 ° enable pulse is set to be 4 bits wide (see Figure | Figures 10 and 11 show example PCM CODEC 12). ; Figure 13 shows an example of timing | interface connections for the parallel and serial “ircuit. i Table 1 Operating Mode Selection Pins i MODE} Pin MODE2 Pin LAW Pin ! 0: Serial mode 0: Coding mode 0: p-law | 1: Decoding mode 1: A-law 1 1: Parallel mode 0: Byte transferring mode 0: p-law i 1: Word transferring mode = 1: A-law In the serial mode following a reset, the HD81803 determines its status from the MODE1, 2 and LAW i signals and starts processing. | In the parallel mode, the HD81803 will not start until a command is received. Table 2 PCM CODEC Types for Serial Interfaces | Type Code length Sampling frequency § Remarks | A-law PCM CODEC 8 bits 8 kHz LAW pin = 1 ! y-law PCM CODEC. 8 bits 8 kHz LAW pin = 0 * 44237C (A-law), 44238C (u-law), 44277P (A-law), 44278P (-law) i i

Serial I/O clock the timing for the ADPCM data interface. Figure 13 shows an example serial I/O timing circuit. In Serial I/O is performed by using synchronizing this example, serial I/O enable pulses SIEN and clocks (serial input clock SICK, serial output clock — SOEN may be 4 bits or more in width, and only SOCK, serial input enable SIEN, and serial output the enabled bits are output from SO. Thus, the enable SOEN) and input/output datas. output data might contain more bits than required (4 bits). Figure 12 (a) shows the serial I/O timing for the € PCM CODEC interface and Figure 12 (b) shows

Clock signal (160 to 2048 kHz) sook JUAN SOCK SIEN | ry 1 . — SOEN 125-ps cycle (8 kHz SYNC) 8 clock cycles SICK SOCK SIEN es SOEN bit number S| X 1X 2X 3X4 Xs X 6 X 7 X 8 X dontcare MSB . Hi-Z so (1 X2X3X4XsX eX 7X 8) (a) Interface for PCM CODEC Clock signal (160 to 2048 kHz) sock JU SOCK SIEN Tr 1 IT SOEN 125-s cycle (8 kHz SYNC) 4 clock cycles SICK : SOCK / SIEN a SOEN MSB sl X 1X 2X 3X 4 X dont care MSB Hi-Z so (1X 2 X 3 X 4 >) (b) Interface for ADPCM data Figure 12 Serial Interface Timing

4049 4049 1/10 counter (4162) 640 kHz SkHZ sien > ° > ° Clock Q1 SOEN [ aM Q2 (PCM CODEC Rising edge Q3| interface clock) i Xtal: Murata MFG. ; U Co., Lid. | aitiz soet CSB640A SOEN | (ADPCM data | > 100 p ae 100 p interface clock) | Po 160k sick | SOCK | Figure 13 Sample Serial I/O Timing Circuit i i i i i i | 18

Command and Data Transfer and transfer procedure are defined below for each command. In the parallel mode, a command transfer is needed to start the internal processing the HD81803. | When an 8-bit data bus is used, ground pins D8 After the internal processing the HD81803 has through DIS. been started, it can request the microprocessor to transfer data using REQ. Commands A command transfer involves sending 16 bits, but (1) Command overview i the high-order byte is fixed, onl: 1 eight bits are gnifican, is fixed, only the lower ter a reset, the HD81803 is initialized and waits for a command input. In this state, operations Upon receiving a data transfer request, the micro- Such as mode selection, coding, and decoding etc processor does either a read or write. Data transfer CaN be controlled by transferring a command from requests are generated after a command other than the microprocessor via the parallel interface. an initialize or idle command is issued. The Table 3 lists the commands. ( —> indicates contents to be transferred, transfer direction, Parallel I/O and —> indicates serial 1/0.) Table 3 HD81803 commands Pin level F RW Command Code"! Description Data flow

2 RW = L Initialize $0000 Sets internal MODE1,

FO =L/H command MODE2, and LAW values Fiel (equivalent to hardware F2=H reset). Idle $0001 Places the HD81803 in the command command waiting state. This command is used to ‘stop the processing of other commands. i Serial $0002 After this command is 4 coding start transferred, PCM datais POM data ADPCM data command input and coded (ADPCM) data is output. Serial $0003 After this command is 8 decoding transferred, ADPCM data Bog qatal 08: [ADPCM data start is input and decoded coding command (PCM) data is output.

Table 3 HD81803 commands (cont) Pin level Fo=UH R/W-L Parallel $0004 After this command is PCM dat: ADPCM dat: Fi=L coding transferred, coded (ADPCM) aa ata . F2=H start data will begin to be output. 4 gommand{ ____ The commands 1,2, differ Parallel $0005 according to the number of poy dat: dat: coding data bus bits (4, 8, or 16) ata ADPCM data start used to carry coded 8 command 2 (ADPCM) data. Parallel $0006 PCM data ADPCM data coding ——>} Coding start 16 command 3 Parallel $0007 After this command is PCM data! ADPCM data decoding transferred, coded (PCM) De- start data is output when coding 4 command 1 ADPCM data is input. Parallel $0008 The commands 1, 2, 3differ po Md decoding according to the number of POM data! De- ADPCM data start data bus bits (4, 8, or 16) coding 8 command 2 used to carry ADPCM data. Parallel $0009 decoding PCM data De- ADPCM data start coding 16 command 3 $000A Reserved. $000B_ Reserved. : Coding test $000C After this command is PCM data ADPCM data start transferred, the coding Coding | command test starts. 4 | — i Decoding $000D After this command is PCM dat. CM dat: ' test start transferred, the decoding atal pg. [ADPCM data command test starts. coding 4

Table 3 HD81803 commands (cont) Pin level F RW Command Code"! Description Data flow Fo=UH RWe=L Through $000E After this command is PCM datal Senal-] PCM data Fle=L output transferred, PCM data is parallel F2=H start input in serial and output Sone 16 command in parallel. Through $000F After this command is M data| Parallel-] PCI input start transferred, PCM data is PCM datal Paralel-] POM data command input in parallel and output gone 16 in serial. *1. This shows the value of data transferred on the data bus (D15—D0). In the word transferring mode, data is transferred twice using DO through D7 (starting with the upper byte). *2. For the byte transferring mode, leave FO high. In the 8-bit parallel mode, set FO low to send the high- order byte of the command, and high to send the low-order byte. Example: Transferring a parallel coding start command Word transfer; Send D15 through DO with $0005 and F2, F1, FO = 101. Byte transfer: Send D7 through DO with $00 and F2, F1, FO = 100, then D7 through Do with $05 and F2, F1, FO = 101.

(2) State transition diagram Reset ™~ Hl Serial coding Initialize (10 ys) \\ 2 1 1 1 Through input | Serial decoding 3 [\\ ° () -— | 1 | 4 a Parallel coding 1 21.57 Through output | Parallel coding 2 “3 co N D | 1 | Parallel coding 3) vy 91 | 1 Parallel 8 Parallel i decoding 1 decoding 3 | Parallel | decoding 2 | * The hexadecimal numbers in the diagram correspond to the four low-order bits of the transfer command. | 0. Initialize command | 1. Idle command | 2. Serial coding start command i 3. Serial decoding start command | 4, Parallel coding start command 1 | 5. Parallel coding start command 2 | 6. Parallel coding start command 3 H 7. Parallel decoding start command 1 i 8. Parallel decoding start command 2 | 9. Parallel decoding start command 3 | C.Coding test start command (for digital sequence tests) | D. Decoding test start command (for digital sequence tests) | E. Through output start command | F. Through input start command | + A bold line indicates that the state transition occurs automatically (i.e. the idle state is entered | automatically after initialization). | + The idle command can be issued to stop command execution. i « For the initialize and idle states, the value in parenthesis indicates the execution time. During this | period other commands cannot be executed. | 22

(3) Functional description of commands (e) Parallel coding start commands 1, 2, and 3 (a) Initialize command After this command is transferred, the HD81803 converts the PCM data received via the serial input The initialize command initializes the internal into ADPCM data. The ADPCM data is output state of the HD81803, in the same way as a from the parallel output. hardware reset. When this command is transferred via the parallel interface, the initializing of the | The ADPCM data can be read by the micro- internal state of the HD81803 will begin according processor after the data transfer request signal to the mode select inputs MODE1, MODE2, and REQ goes low. REQ goes low: for every serial LAW. After 10 ps the HD81803 enters the idle —_ input sample when parallel coding start command state. 1 is issued; for every two input samples when parallel coding start command 2 is issued; and for (b) Idle command every four input samples when parallel coding ‘ : . start command 3 is issued. Thus, for an 8-kHz The idle command terminates the execution of sampling rate, read cycles would be needed every other commands, and places the HD81803 in the 125, 250 and 500 us, respectively. idle state. . . To stop the execution of this command, issue the (©) Serial coding start command idle command. After this command is transferred, the HD81803 (fy Parallel decoding start commands 1, 2, and 3 converts the PCM data received via the serial input into ADPCM data. The ADPCM data is output —_After this command is transferred, the HD81803 from the serial output, and can be also read via the converts the ADPCM data received via the parallel parallel interface after the data transfer request _ interface into PCM data. The PCM data is output signal REQ goes low. REQ goes low for every from the serial output. serial input sample (i.e. every 125 ps). The ADPCM data can be sent by the To stop the execution of this command, issue the microprocessor after the data transfer request idle command. signal REQ goes low. REQ goes low: for every . . serial output sample when parallel decoding start (d) Serial decoding start command command 1 is issued; for every two output After this command is transferred, the HD81803SAmPles when parallel decoding start command 2 ; converts the ADPCM data received via the serial _'S issued; and for every four output samples when . . . parallel decoding start command 3 is issued. i input into PCM data. The PCM data is output " from the sezial output, and can be also read via the Thus, for an 8-kHz sampling rate, write cycles . would be needed every 125, 250 and 500 ps, parallel interface after the data transfer request tivel signal REQ goes low. REQ goes low for every “SPecuvely: serial output sample (i.¢. every 125 ps). To stop the execution of this command, issue the To stop the execution of this command, issue the idle command. idle command. | 23

(g) Coding test start command followed by a request to read PCM data. Thus, write and read requests are issued in The coding test start command is used to check the sequence. ADPCM coding process of the HD81803 (digital sequence test defined in CCITT Recommendation _To stop the execution of this command, issue the G.721) via the parallel interface. After this idle command. command is transferred, the HD81803 receives the . PCM data via the parallel interface, converts it into _(i) Through output start command ADPCM data, and outputs the ADPCM data back via the parallel interface. The through output start command causes the HD81803 to convert the PCM data received via The PCM data can be written and the ADPCM __ the serial input into parallel. The parallel PCM data can be read after the data transfer request data is output from the parallel output. signal REQ goes low. There is no limit on the response time. After this command is transferred, The parallel PCM data can be read after the data the HD81803 requests to write PCM data first. "nsfer request signal REQ goes low. One read A request to write PCM data is always followed request is needed for every two serial input by a request to read ADPCM data. Thus, write samples. Thus, for an 8-kHz sampling rate, read and read requests are issued in sequence. cycles would be needed every 250 ps. To stop the execution of this command, issue the 70 Stop the execution of this command, issue the idle command. idle command. (h) Decoding test start command (j) Through input start command The decoding test start command is used to check The through input start command causes the the ADPCM decoding process of the HD81803_ _HD81803 to convert the PCM data received via (digital sequence tests defined in CCITT the Parallel interface into serial. The serial PCM Recommendation G.721) via the parallel interface. data is output from the serial output. After this command is transferred, the HD81803 5 receives the ADPCM data via the parallel The parallel PCM data can be written after the data interface, converts it into PCM data, and outputs transfer request signal REQ goes low. One write i - el is request is needed for every two serial output : the PCM data back via the lel interface. samples. Thus, for an 8-kHz sampling rate, write The ADPCM data can be written and the PCM —_°¥¢les would be needed every 250 is. j data can be read after the data transfer request : A A ' signal REQ goes low. There is no limit on the To stop the execution of this command, issue the ! response time. After this command is transferred, idle command. the HD81803 requests to write ADPCM data first. A request to write ADPCM data is always

(2) Data input/output operations Table 4 shows the data input/output operations for the parallel interface. | Table 4 HD81803 Parallel I/O Operations | Pin level Data bus format | F R/W Operation Dis <-> D0 _ Description | Fo=L R/W-=H DATA-U READ 15 8 7 0 Reads only the high-order byte | FisH Upper data read of 16-bit data when an 8-bit bus | F2-L Undefined DATA is used. | FO=H DATA-L READ 15 4 3 0 Reads only the four low-order a = i Lower data read (1) Undefined DATA] bits when an 8-bit bus is used. i = 15 87 0 Reads 8 bits or the low-order (2) |__ Undefined DATA 8-bit bus is used. i DATA-W READ 15 0 Reads all 16 bits when a 16-bit Word data read DATA bus is used. i Fo=L R/WeL DATA-U WRITE 15 gz 0 Writes the high-order byte of Fi=H Upper data write DATA 16-bit data when an 8-bit bus is i F2=L used, i FO=H DATA-L WRITE 15 4 3 0 Writes the four low-order bits : t Lower data write (1) DATA when an 8-bit bus is used. : 15 87 © Writes 8 bits or the low-order (2) |__ don't care DATA 8-bit bus is used. | DATA-W WRITE 15 0 Writes all 16 bits when a 16-bit Word data write DATA bus is used, | eee | Examples i 1. Parallel coding start command 1 uses DATA-L READ. | 2. Parallel decoding start command 3 uses DATA-W WRITE, or DATA-U WRITE and DATA-L WRITE. i i i

(3) Data transfer request (REQ) must read or write data (except when transferring a serial coding/decoding start command). (a) REQ is an open-drain output pin which requires an external pull-up resistor. The timing between REQ and the microprocessor's . . response are given below. The microprocessor (b) REQ is used to request the microprocessor to must transfer data within 100, 200, or 400 is after transfer data to/from the HD81803 by the level REQ goes low. output. When REQ goes low, the microprocessor H081803 +V Zz a o Figure 16 Data Transfer Request Output REQ \\ / Data input/output serene" (U) (Ly (tegen access 100 ys max (4-bit data) 200 us max (8-bit data) 400 is max (16-bit data) i Figure 17 Maximum Microprocessor Response Time for REQ When Coding/Decoding (32-MHz Clock, 8-kHz Sampling Rate)

(5) Example response of a microprocessor to an _ input or output data. Examples of the I/O timing ADPCM data transfer request (REQ) on each states are given below. When REQ goes low, the microprocessor must Examples 1. 4-bit data input/output in the 8-bit parallel mode 125 ys (typ) <—> REQ cs Data Data Data Data Applicable states: Serial coding Serial decoding Parallel coding 1 Parallel decoding 1 2. 8-bit data input/output in the 8-bit parallel mode 250 us (typ) Data Data Data Applicable states: Parallel coding 2 Parallel decoding 2 — When wansferring 16 bits of data, two 250-s cycles are needed for an 8-bit bus, or one 500-s cycle for a 16-bit bus.

The Phase relationship between serial input them is unavoidable due to the system design, enable and serial output enable timing relationships should be as shown in Figure 20. The output from SO should be terminated The serial input enable (SIEN) and serial output _ before the input from SI is completed. The input enable (SOEN) signals should be basically the from SI is completed at the rising edge 16 clock i same. However, if a phase difference between _ pulses from the rising edge of SIEN. | sien_/ AN XEON ; ot 16 clock pulses i )°2 | H i i i | sick 1 2 Lp 15 16 i ee i +5 <> i tps (max)! | i ! , 3 120 ps (max) yo | H H ! i | sx LJ LJ LJ LI LI Lf | Figure 20 Timing Relation between Serial Input and Output Enable | “1: The first rising SICK edge after SIEN goes high | *2: The rising SICK edge 16 clock pulses later (The rising SIEN edge is ignored.) *3: The rising SOCK edge after SOEN goes high | *4: The rising SOCK edge after SOEN goes low | *5: The minimum is undefined. That is, as in the usual case, this value might also be negative | (*4 precedes *2). i | : i | 30

Sample System Configuration This section shows an example record/playback Specifications system consisting of the HD81803 and a host CPU HD6301 (Figure 21). — Speech data memory: HM62256 (also used as system memory) This design uses the HM62256 (256-kbit RAM) as | - CODEC: HD44238 p-law CODEC a speech data RAM to record and playback speech — Sampling frequency: 8 kHz data for 7-8 seconds. The microphone and power — Number of coding bits: 4 amplifiers are not shown in this figure, 45V 10k 47 04 LS04 __ -1->—be RES reser ° mau ose

1 REQ

5, 9 HD6303Y Hoos HCO4 So———d> i-dotr Voc 6d 64 i | #-dLOAD Q. era . eo “AiR 8 EXTAL weep & BD Bc ad ° MPo = RW 8 RW 0 fa, —fdsrey TAD tor AO 24M BA p™2 AO to A15 ye yor P>CK Gp 2 Mt6l por Ls139 8 3 bi>CSROM TW 14) 628 AIS IZATd BIB 1Y3 Pee CSROM Murata MFG. Co,, Lid. fF S.6 y PWriaibe ANS ae 13 WA 1v2Pe>CSPCM + WWizipos = a2 1244 diG_ yop CSA32.00MX040 Wt p55 Ai Bed os a ar Ne Rec °° d> Sa P20 Alara | as I > MW 231 PBZ Al ag 64 | Play f° © q eer 4554 ' — War pee As ae ' 5 RS Lyw2olpss =A movef~° 181 Peo Alaa 2) 71p8 Allgo 07 A zea Q7KXA aol AO 7 fi220ne tS240 ss vo-p-WMy221 p67 D7 12 = 8 [526 REC D diva 1a4 WW Si Pee De {pa—8 PLAY tS H¥3 1A tas pes Bsa wooo S-Wwedivi te Las BEA MODO D> cy? 1At 2G) Bee pe lbz 1 LED iG per Dilea ON ; $, Vss Vss_Voo i ay Las Do to D7 1 344 Tantalum electrolytic : capacitor +5 V | Figure 21 Example System Configuration (Microprocessor Section) i | 31

+5V v9 4069 40699 he be ¢> 47k iM | fa CLR O. +5V $3 GLOAD Qala 9 it 6-18 100 +P RG p=100p| Tolr og 4.7x2 + om Ken] YS _ REQ Murata MFG, Co., Ltd. 8 Lg CSAG40A ¥s 45V ustez “9 9 hs Ldoir a #3-LOAD Qa _ HA RES 1B Gp 5 dis ose tole = RG 081803 AO to AZ ‘CK an. ; wu ead Falbs F116 38 |nES Eipea 7) ge | REQ cs| CSPCM a7ex 30) MODE1 RWS Bw 45V +5V MODE2 47 kx8 © — HD44238C 9 pas MARE? pis

4 Diag 4

Yoo PO] y 0 VH 013} —4 = +5V 39 Dia 3-4 ry ScLK DI Wt TxSYNC ~ QIsien — ng his WF hort ¢t 334 118 AW 3 Analog An MPEREK SE tee reK OB input ly | [Tel pris ; RCV SYNC 1 * "3 1896N SIS EN Analog RCV.CLOCK Ip —* 351 80CK Dati ink so pat 4y output Rou POMin in Gaze vu Da}3—) | [ 26 | oie) | Analog AGND 26 | i> Dths-0N : ground GAI 10k GND, cc Vss__DGND To, 0 Do to D7 Hé [13 Analog ground N - 33u6 o—! Digital ground sv ‘analy Tantalum electrolytic capacitor ‘Separate the analog ground and digital grounds. Connect the analog signal lines (Aja, Ao, GA1, and GA2) as far from the digital signal lines as possible, and don't allow them to cross. Provide a bypass capacitor (3-47 uF) at the shortest connection between Voc and ground. | Figure 22 Example System Configuration (ADPCM Section)

cSROM Od cE ata [28 G WE AM bs 19) RD BqOE AN [eat] Gore AN? lea 314 ° A100) Ato fat 104 ec As les pou 8 ne i8 Ala 64 A lao 3/07 AS 2 — 3) 3| V7 As e—7) (S18 6 aa [8—4 ($-18\\vos «aaa (8 4 (a= Os Slay PSHE vos 43 a3) Yate) aC, L378] vos lo 1) (3 15| o3 ai fey sos a AB) 22 0 [199 eB voe a0 19 oi] 21 voi es _v a "ss Vv H H 33g 334 Tantalum electrolytic Tantalum electrolytic D0 to D7 capacitor capacitor Figure 23 Example System Configuration (Memory Section)

Appendix (Terminology) ADPCM modulation) is the one of methods which requires less data than PCM. In the ADPCM process, each PCM (pulse code modulation) is a process for differential between two adjacent samples is converting analog signals into digital signals. This represented by the small number of bits (as PCM), process is employed in CD players and soon which —_ while the quantization intervals (bit weight) of the can provide high-quality recording and playback = PCM signals are made adaptive according to the of speech data with enough number of bits. differentials. Thus, high-quality speech data is available in a wide dynamic range thanks to The ADPCM (adaptive differential pulse code ADPCM. ADPCM Encoder The ADPCM encoder quantizes the differential between the estimated and input values according to the quantization interval A. + Differential POM 4) ADPCM (12 to 16 bits) input (3 or 4 bits) - Change in Estimated Aa quantization value interval Integrator + oS T] Inverse quantizer 4: Quantization interval z zm: Delay ADPCM Decoder

1 The ADPCM decoder, having the same configuration as the estimator in the ADPCM encoder above,

reverses the coding procedure. + Integrator ADPCM Cpe > eM input output Change in 4 * quantization i interval Reference: K. Nakata "Onsei" J. Acoustic Society of Japan, 1977, Corona Pub. Co., Ltd, Japan

Unit: mm (inch) 52.8 (2.079) 2 Mannnewem ramen) 21/8 8 rx gé8 15.24 PTAs ats uy i ' Egle 0.2 Orsosnons 8 | ea | = | sevec | — | 1016.58(00.653 ~ En +) ee 8 aod] H2e > s| q h S| q b 4 gi p Saad b 3\\"id 5 S| ‘q 5 s| q es d h #8 5) 6d bese os 7 7 He 2s 0.74(0.029) sit s/t Hf x|S BIS q iT qs fT COMM | OUI i (0.01720.004 (0.6100.020) Hitachi Code|_CP-44 | seoec | — |

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