HD74AC

HD74AC HITACHI

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HD74AC Series Common Information September 2000 Customer Service Division Semiconductor & Integrated Circuits Hitachi, Ltd. Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

FACT Descriptions and Family Characteristics FACT Descriptions and Family Characteristics 1. Advanced CMOS FACT Logic FACT logic offers a unique combination of high speed, low power dissipation, high noise immunity, wide fanout capability, extended power supply range and high reliability. This data book describes the product line with device specifications as well as material discussing design considerations and comparing the FACT family to predecessor technologies. For direct replacement of LS, ALS and other TTL devices, HD74ACT circuits with TTL-type input thresholds are included in the FACT family. These include the more popular bus drivers/transceivers as well as many other HD74ACTXXX devices.

1.1 Characteristics

• Full logic product line
• Industry standard functions and pinouts for SSI and MSI
• Meets or exceeds JEDEC standards for HD74ACXX family
• TTL inputs on selected circuits
• High performance outputs ¾ Common output structure for standard and buffer drivers ¾ Output Sink/Source Current of 24 mA ¾ Transmission line driving 50 W guaranteed
• Operation from 2 to 6 volts guaranteed
• Temperature range –40°C to +85°C
• Improved ESD protection network
• High current latch-up immunity

1.2 Interfacing

FACT devices have a wide operating voltage range (V CC = 2 to 6 VDC) and sufficient current drive to interface with most other logic families available today. Device designators are as follows:

• HD74AC is a high-speed CMOS device with CMOS input switching levels and buffered CMOS outputs that can drive –24 mA of I OH and IOL current. Industry standard HD74AC nomenclature and pinouts are used.
• HD74ACT is a high-speed CMOS device with a TTL-to-CMOS input buffer stage. These device inputs are designed to interface with TTL outputs operating with a VCC = 5 V –0.5 V with VOH = 2.4 V and VOL = 0.4 V, but are functional over the entire FACT operating voltage range of 2.0 to 5.5 VDC. These devices have buffered outputs that will drive CMOS or TTL devices with no additional interface circuitry. HD74ACT devices have the same output structures as HD74AC devices.

FACT Descriptions and Family Characteristics

1.3 Low Power CMOS Operation

If there is one single characteristic that justifies the existence of CMOS, it is low power dissipation. In the quiescent state, FACT draws three orders of magnitude less power than the equivalent LS or ALS TTL device. This enhances system reliability; because costly regulated high current power supplies, heat sinks and fans are eliminated. FACT logic devices are ideal for portable systems such as laptop computers and backpack communications systems. Operating power is also very low for FACT logic. Power consumption of various technologies with a clock frequency of 1 MHz is shown below.

• FACT = 0.1 mW/gate
• ALS = 1.2 mW/gate
• LS = 2.0 mW/gate
• HC = 0.1 mW/gate Figure 1 illustrates the effects of I CC versus power supply voltage (VCC ) for two load capacitance values: 50 pF and stray capacitance. The clock frequency was 1 MHz for the measurements. C L = 50 pF @ 1 MHz ICC (µA) C L = Fixture Capacitance @ 1 MHz VCC (Volts) 100 200 300 400 500 Figure 1 ICC vs VCC

1.4 AC Performance

In comparison to LS, ALS and HC families, FACT devices have faster internal gate delays as well as the basic gate delays. Additionally, as the level of integration increases, FACT logic leads the way to very high-speed systems. The example below describes typical values for a HD74XX138, 3 to 8 line decoder.

• FACT = 6.0 ns @ C L = 50 pF
• ALS = 12.0 ns @ CL = 50 pF
• LS = 27.0 ns @ CL = 15 pF
• HC = 17.0 ns @ CL = 50 pF

FACT Descriptions and Family Characteristics 2.0 V VCC on all device types, the formula below can be used to determine AC performance. AC performance at 2.0 V VCC = 1.9 · AC specification at 3.3 V

1.5 Multiple Output Switching

Propagation delay is affected by the number of outputs switching simultaneously. Typically, devices with more than one output will follow the rule: for each output switching, derate the databook specification by 250 ps. This effect typically is not significant on an octal device unless more than four outputs are switching simultaneously. This derating is valid for the entire temperature range and 5.0 V – 10% V CC .

1.6 Noise Immunity

The noise immunity of a logic family is also an important equipment cost factor in terms of decoupling components, power supply dynamic resistance and regulation as well as layout rules for PC boards and signal cables. The comparisons shown describe the difference between the input threshold of a device and the output voltage, |V IL–V OL | / |VIH–V OH | at 4.5 V VCC .

• FACT = 1.25/1.25 V
• ALS = 0.4/0.7 V
• LS = 0.3/0.7 V@ 4.75 V VCC
• HC = 1.25/1.25 V

1.7 Output Characteristics

All FACT outputs are buffered to ensure consistent output voltage and current specifications across the family. Both HD74AC and HD74ACT device types have the same output structures. Two clamp diodes are internally connected to the output pin to suppress voltage overshoot and undershoot in noisy system applications witch can result from impedance mismatching. The balanced output design allows for controlled edge rates and equal rise and fall times. All devices (HD74AC or HD74ACT) are guaranteed to source and sink 24 mA. HD74AC/ACTXXX, are capable of driving 50 W transmission lines. 1.7.1 I OL /IOH Characteristics

• FACT = 24/–24 mA
• ALS = 24/–15 mA
• LS = 8/–0.4 mA @ 4.75 V VCC
• HC = 4/–4 mA

FACT Descriptions and Family Characteristics

1.7.2 Dynamic Output Drive

Traditionally, in order to predict what incident wave voltages would occur in a system, the designer was required to do an output analysis using a Bergeron diagram. Not only is this a long and time-consuming operation, but the designer needed to depend upon the accuracy and reliability of the manufacturer-supplied ‘typical’ output I/V curve. Additionally, there was no way to guarantee that any supplied device would meet these ‘typical’ performance values across the operating voltage and temperature limits. Hitachi has taken the necessary steps to guarantee incident wave switching on transmission lines with impedances as low as 50 W . Figure 2 shows a Bergerton diagram for switching both high-to-low and low-to-high. On the right side of the graph (I out > 0), are the VOH and IIH curves for FACT logic while on the left side (Iout < 0), are the curves for VOL and IIL. Although we will only discuss here the low-to-high transition, the information presented may be applied to a high-to-low transition. Current (A) 0.1 0.2–0.1–0.2 Volts (V) VOH /IOHHIGH-to-LOW LOW-to-HIGH Line 1 Slope = 50 Ω Line 2 Slope = 50 Ω VIN/IIN VOL /IOL Figure 2 Gate Driving 50 W Line Reflection Diagram Begin analysis at the VOL (quiescent) point. This is the intersection of the VOL /IOL curve for the output and the VIN/IIN curve for the input. For CMOS inputs and outputs, this point will be approximately 100 mV. Then draw a 50 W load line from this intersection to the VOH /IOH curve as shown by Line 1. This intersection is the voltage that the incident wave will have. Here it occurs at approximately 3.95 V. Then draw a line with a slope of –50 W from this first intersection point to the V IN/IIN curve as shown by Line 2. This second intersection will be the first reflection back from the input gate. Continue this process of drawing the load line from each intersection to the next. Lines terminating on the V OH /IOH curve should have positive slopes while lines terminating on the VIN/IIN curve should have negative slopes. Each intersection point predicts the voltage of each reflected wave on the transmission line. Intersection points on the VOH /IOH curve will be waves travelling from the driver to the receiver while intersection points on the VIN/IIN curve will be waves travelling from the receiver to the driver. Figure 3 and 4 show the resultant waveforms. Each division on the time scale represents the propagation delay of the transmission line.

FACT Descriptions and Family Characteristics Voltage (V) Current (mA) –0.1 0 0.1 VIN/IIN 0.2–0.2 VCC = 5.0 V, Ta = 25°C Figure 7 Input Characteristics VIN/IIN

1.8 Choice of Voltage Specifications

To obtain better performance and higher density, semiconductor technologies are reducing the vertical and horizontal dimensions of integrated device structures. Due to a number of electrical limitations in the manufacture of VLSI devices and the need for low-voltage operation in memory cards, the JEDEC committee decided to establish interface standards for devices operating at 3.3 V –0.3 V. To this end, Hitachi guarantees all of its devices operational at 3.3 V –0.3 V. Note also that AC and DC specifications V CC . Operating Voltage Ranges

• FACT = 2.0 to 6.0 V
• ALS = 5.0 V –10%
• LS = 5.0 V –5%
• HC = 2.0 to 6.0 V

1.9 FACT Replaces LS, ALS, HCMOS

The Advanced CMOS family is specifically designed to outperform the LS, ALS, and HCMOS families. Figure 8 shows the relative position of various logic families in speed/power performance. Table 1 summarizes the key performance specifications for various competitive technology logic families. Table 2 compares propagation delays.

FACT Descriptions and Family Characteristics HC FACT ALS LS FAST AS Propagation Delay (ns) Power Per Gate (mW) (Not to scale) Figure8 Propagation Delays Table 1a Logic Family Comparisons General Characteristics (All Max Ratings) FACT Characteristics Symbol LS ALS HCMOS HD74AC HD74ACT Unit Operating voltage range Operating temperature range –20 to +75 0 to +70 –40 to +85 –40 to +85 –40 to +85 °C Input voltage (limits) Output voltage (limits) Input current I IH 20 20 +1.0 +1.0 +1.0 mA Output current at V0 (limit) 0.37 –24 @ VCC – 0.7 –24 @ VCC – 0.7 mA DC noise margin low/high

FACT Descriptions and Family Characteristics Table 1b Logic Family Comparisons Speed/Power Characteristics (All Typical Ratings) FACT Characteristics Symbol LS ALS HCMOS HD74AC HD74ACT Unit Quiescent supply current/Gate IG 0.4 0.2 0.0005 0.0005 mA Power/gate (Quiescent) PG 2.0 1.2 0.0025 0.0025 mW Propagation delay tP 10 5.0 8.0 5.0 ns Speed power product — 20 6.0 0.02 0.01 pJ Clock frequency D/FF fmax 33 50 50 160 MHz Table 2 Propagation Delay Product LS ALS HCMOS FACT unit tPLH /tPHL HD74XX00 Typ 10.0 5.0 8.0 5.0 ns Max 15.0 11.0 23.0 8.5 ns tPLH /tPHL (Clock to Q) HD74XX74 Typ 25.0 12.0 14.0 8.0 ns Max 40.0 18.0 40.0 10.5 ns tPLH /tPHL (Clock to Q) HD74XX163 Typ 18.0 10.0 18.0 5.0 ns Max 27.0 17.0 40.0 10.0 ns Note: continuous: (LS) VCC = 5.0 V, CL = 15pF, 25°C; (ALS/HC/FACT) VCC = 5.0 V – 10%, CL = 50 pF, typ values at 25˚C, max values at 0 to 70˚C for ALS. –40 to +85˚C for HC/FACT.

FACT Descriptions and Family Characteristics 2. Circuit Characteristics

2.1 Power Dissipation

One advantage to using CMOS logic is its extremely low power consumption. During quiescent conditions, FACT will consume several orders of magnitude less current than its bipolar counterparts. But DC power consumption is not the whole picture. Any circuit will have AC power consumption, whether it is built with CMOS or bipolar technologies. Power consumption of a circuit can be calculated using the formula: PD = [(CL + CPD ) • VCC • VS • f] + [IQ • VCC ] where: PD = power dissipation C L = load capacitance C PD = device power capacitance V CC = power supply V S = output voltage swing f = frequency of operation I Q = quiescent current Power consumption for FACT is dependent on the supply voltage, frequency of operation, internal capacitance and load. VS will be VCC and IQ can be considered negligible for CMOS. Therefore, the simplified formula for CMOS is: PD = (CL + CPD )VCC 2 f C PD values for CMOS devices are calculated by measuring the power consumption of a device at two different frequencies. CPD is calculated in the following manner. 1. The power supply voltage is set to VCC = 5.0 VDC. 2. Signal inputs are set up so that as many outputs as possible are switching, giving a worst-case situation per JEDEC CPD conditions.

FACT Descriptions and Family Characteristics VCC SET CLR D CLK Q Q ’74 SET CLR D CLK Q Q ’74 SET CLR D CLK Q Q ’74 SET CLR D CLK Q Q ’74 E1 E2 E3 A0 A1 A2 01 02 03 04 05 06 07 08 Input ’04 Load Devices ’138 Figure 9 Power Demonstration Circuit Schematic 3. The power supply current is measure and recorded at input frequencies of 200 kHz and 1 MHz. 4. The power dissipation capacitance is calculated by solving the two simultaneous equations P1 = (CPD • VCC 2 • f1) + (ICC • VCC ) P2 = (CPD • VCC 2 • f2) + (ICC • VCC ) giving C PD = (P1 – P2)/VCC 2 (f1 – f2) or C PD = (I1 – I2)/VCC (f1 – f2) where I1 = supply current at f1 = 200 kHz. I2 = supply current at f2 = 1 MHz

FACT Descriptions and Family Characteristics On FACT device data sheets, CPD is a typical value and is given either for the package or for the individual device (i.e., gates, flip-flops, etc.) within the package. The circuit shown in Figure 9 was used to compare the power consumption of FACT versus ALS devices. Two identical circuits were built on the same board and driven from the same input. In the circuit, the input signal was driven into four D-type flip-flops which act as divide-by-2 frequency dividers. The outputs from the flip-flops were connected to the inputs of a HD74AC138/74ALS138 decoder. This generated eight non-overlapping clock pulses on the outputs of the HD74AC138/74ALS138, which were then connected to an HD74AC04/74ALS04 inverter. The input frequency was then varied and the power consumption was measured. Figure 10 illustrates the results of these measurements. Power (mW) 60 80 10040 ALS ALS Circuit Stopped Functioning FACT Frequency (MHz) 200 100 200 150 300 250 350 400 Figure 10 FACT vs ALS Circuit Power Below 40 MHz, the FACT circuit dissipates much less power than the ALS version. It is interesting to note that when the frequency went to zero, the FACT circuit’s power consumption also went to zero; the ALS circuit continued to dissipate almost 100 mW. Another advantage of FACT is its capabilities above 40 MHz. At this frequency, the first 74ALS74 D-type flip-flop ceased to operate. Once this occurred, the entire circuit stopped working and the power consumption fell to its quiescent value. The FACT device, however, continued functioning beyond the limit of the frequency generator, which was 100 MHz. This graph shows two advantages of FACT circuits (power and speed). FACT logic delivers increased performance in addition to offering the power savings of CMOS.

FACT Descriptions and Family Characteristics

2.2 Capacitive Loading Effects

In addition to temperature and power supply effects, capacitive loading effects for loads greater than 50 pF should be taken into account for propagation delays of FACT devices. Minimum delay numbers may be determined from table 3. Propagation delays are measured to the 50% point of the output waveform. Table 3 Minimum Propagation Delay Voltage(V) Parameter 3.0 4.5 5.5 Units Trise 31 22 19 ps/pF tfall 18 13 12.5 ps/pF Note: TA = 25˚C The two graphs following, figures 11 and 12, describe propagation delays on FACT devices as affected by variations in power supply voltage (VCC ) and lumped load capacitance (CL). Figures 13 and 14 show the effects of lumped load capacitance on rise and fall times for FACT devices. Delay (ns) VCC (Volts) CL = 1000 pF, t PLH CL = 1000 pF, t PHLCL = 470 pF, t PLH CL = 470 pF, t PHL C L = 220 pF, t PLH C L = 50 pF, tPHL C L = 50 pF, tPLH C L = 220 pF, tPHL Figure 11 Propagation Delay vs. VCC (HD74AC00)

FACT Descriptions and Family Characteristics 10tfall (ns) 10 20 30 40 50 Load Capacitance (pF) VCC = 5.0V Ta = 25°C Figure 14 tfall vs. Capacitance P-Channel MOS +V DD -VSS N-Channel MOS N-Substrate Output Input N-well N+ N+P+ N+ P+ P+ P-well Figure 15 CMOS Inverter Cross Section with Latch-up Circuit Schematic

2.3 Latch-up

A major problem with CMOS has been its sensitivity to latch-up, usually attributed to high parasitic gains and high input impedance (figure 15). FACT logic is guaranteed not to latch-up with dynamic currents of 100 mA forced into or out of the inputs or the outputs under worst case conditions (Ta = 85˚C and V CC = 5.5 VDC). At room temperature the parts can typically withstand dynamic currents of over 450 mA. For most designs, latch-up will not be a problem, but the designer should be aware of its causes and how to prevent it. FACT devices have been specifically designed to reduce the possibility of latch -up occurring; Hitachi accomplished this by lowering the gain of the parasitic transistors, reducing N-well and p-well resistivity to increase external drive current required to cause a parasitic to turn on, and careful design and layout to minimize the substrate-injected current coupling to other circuit areas.

FACT Descriptions and Family Characteristics

2.4 Electrostatic Discharge (ESD) Sensitivity

FACT circuits show excellent resistance to ESD-type damage. These logic devices are classified as category ‘B’ of MIL-STD-883C, test method 3015, and withstand 4000 V typically. FACT logic is guaranteed to have 2000 V ESD immunity on all inputs and outputs. FACT parts do not require any special handling procedures. However, normal handling precautions should be observed as in the case of any semiconductor device. Figure 16 shows the ESD test circuit used in the sensitivity analysis for this specification. Figure 17 is the pulse waveform required to perform the sensitivity test. The test procedure is as follows: five pulses, each of 2000 V, are applied to every combination of pins with a five second cool-down period between each pulse. The polarity is then reversed and the same procedure, pulse and pin combination used for an additional five discharges. Continue until all pins have been tested. If none of the devices from the sample population fails the DC and AC test characteristics, the device shall be classified as category B of MIL-STD-883C, TM-3015. For further specifications of TM-3015, refer to the relevant standard. The voltage is increased and the testing procedure is again performed; this entire process is repeated until all pins fail. This is done to thoroughly evaluate all pins. Regulated High Voltage Supply DC Voltmeter DUT Waveform Terminals R 1 = 800kΩ (min) 30Ω (max) R 2 = 1500Ω Charge Discharge High Voltage Relay R 3 = 1500Ω Calibrate Test C1 = 100pF Figure 16 ESD Test Circuit

FACT Descriptions and Family Characteristics 100% 90% 36.8% 10% tPEAK tRISE tDECAY tRISE ≤ 15 ns tDECAY ≤ 350 ns (R2+R 3)C1 ‡ 300 ns TIME Voltage Amptitude Figure 17 ESD Pulse Waveform

Definition of Specifications Definition of Specifications 1. Power Dissipation-Test Philosophy In an erfort to reduce confusion about measuring CPD , a JEDEC standard test procedure (7A Appendix E) has been adopted, which specifies the test setup for each type of device. This allows a device to be exercised in a consistent manner for the purpose of specification comparison. All device measurements are made with V CC = 5.0 V at 25°C, with 3-state outputs both enabled and disabled.

• Gates: Switch one input. Bias the remaining inputs such that the output switches.
• Latches: Switch the Enable and D inputs such that the latch toggles.
• Flip-Flops: Switch the clock pin while changing D (or bias J and K) such that the output (s) change each clock cycle. For parts with a common clock, exercise only one flip - flop.
• Decoders: Switch one address pin which changes two outputs.
• Multiplexers: Switch one address pin with the corresponding data inputs at opposite logic levels so that the output switches.
• Counters: Switch the clock pin with other inputs biased such that the device counts.
• Shift Registers: Switch the clock pin with other inputs biased such that the device counts.
• Transceivers: Switch one data input. For bidirectional devices enable only one direction.
• Parity Generator: Switch one input.
• Priority Encoders: Switch the lowest priority input.
• Load Capacitance: Each output which is switching should be loaded with the standard 50 pF. The equivalent load capacitance, based upon the number of outputs switching and their respective frequency, is then subtracted form the measured gross C PD number to obtain the device’s actual CPD value. If the device is tested at a high enough frequency, the static supply current can be ignored. Thus at 1 MHz, the following formula can be used to calculate CPD : C PD = ICC / (VCC ) (1 · 106) – Equivalent Load Capacitance

Definition of Specifications 2. Ratings and Specifications Table 1 Absolute Maximum Ratings*1 Parameter Symbol Limit Unit Condition Supply voltage V CC –0.5 to 7.0 V DC input Diode current or DC input voltage IIK –20 mA V I = –0.5 20 mA V I = VCC +0.5 VI –0.5 to VCC +0.5 V DC output Diode current or DC output voltage I OK –50 mA V O = –0.5 50 mA V O = VCC +0.5 VO –0.5 to VCC +0.5 V DC output source or sink current IO –50 mA DC V CC or ground current per output pin ICC or IGND –50 mA Storage temperature T STG –65 to 150 °C Note: 1. Absolute maximum ratings are those values beyond which damage to the device may occur. Obviously the databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, output/input loading variables. Hitachi does not recommend operation of FACT circuits outside databook specifications. Table 2 Recommended Operating Conditions Parameter Symbol Limit Unit Condition Supply Voltage (unless otherwise specified) AC devices V CC 2.0 to 6.0 V ACT devices 4.5 to 5.5 Input voltage V I 0 to VCC V Output voltage V O 0 to VCC V Operating temperature T A –40 to +85 °C Input rise and Fall time*1 (typical) tr, tf 150 ns/V V CC @ 3.0V (except Schmitt inputs) ’AC devices VIN from 40 ns/V V CC @ 4.5V 30% to 70% of VCC 25 ns/V V CC @ 5.5V Input rise and Fall time*1 (typical) tr, tf 10 ns/V V CC @ 4.5V (except schmitt inputs) ’ACT devices VIN from 8 ns/V V CC @ 5.5V 0.8 to 2.0 V, Vmeas from 0.8 to 2.0V Note: 1. See individual data sheets for those devices which differ from the typical input rise and fall times noted here.

Definition of Specifications Table 3 DC Characteristics for HD74AC Family Devices Ta = +25°C Ta = –40 to +85 °C Parameter Symbol V CC (V) Typ Guaranteed Limit Unit Condition Voltage 5.5 2.75 3.85 3.85 Voltage 5.5 2.75 1.65 1.65 Maximum V OH 3.0 2.99 2.9 2.9 V I OUT = –50 mA High Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.0 2.58 2.48 V V IN = VIL or VIH 4.5 3.94 3.80 –12 mA I OH –24 mA 5.5 4.94 4.80 * 1 –24 mA Maximum V OL 3.0 0.002 0.1 0.1 V I OUT = 50 m A Low Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 3.0 0.32 0.37 V V IN = VIL or VIH 4.5 0.32 0.37 12 mA I OL 24 mA 5.5 0.32 0.37 * 1 24 mA Maximum Input Leakage Current I IN 5.5 –0.1 –1.0 mAV I = VCC , GND Maximum 3-State Current I OZ 5.5 –0.5 –5.0 mAV I (OE) = VIL, VIH VI = VCC , VG ND VO = VCC , GND Minimum Dynamic Output Current * IOLD 5.5 86 mA V OLD = 1.1 V IOHD 5.5 –75 mA V OHD = 3.85 V Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0 ms, one output loaded at a time.

Definition of Specifications Table 4 DC Characteristics for HD74ACT Family Devices Ta = +25°C Ta = –40 to +85 °C Parameter Symbol V CC (V) Typ Guaranteed Limit Unit Condition Voltage Maximum Low V Voltage Maximum High V OH 4.5 4.49 4.4 4.4 V I OUT = –50 mA Level 5.5 5.49 5.4 5.4 Output Voltage 4.5 3.94 3.80 V V IN = VIL or VIH 5.5 4.94 4.80 I OH –24 mA *1 –24 mA Maximum Low V OL 4.5 0.001 0.1 0.1 V I OUT = 50 mA Level Output 5.5 0.001 0.1 0.1 Voltage 4.5 0.32 0.37 V V IN = VIL or VIH 5.5 0.32 0.37 I OL 24 mA *1 24 mA Maximum Input Current IIN 5.5 –0.1 –1.0 mAV I = VCC , GND Maximum 3- State Current IOZ 5.5 –0.5 –5.0 mAV I = VIL, VIH VO = VCC , GND Maximum ICC /Input Current ICCT 5.5 0.6 1.5 mA V I = VCC – 2.1V Minimum Dynamic Output Current * IOLD 5.5 86 mA V OLD = 1.1 V IOHD 5.5 –75 mA V OHD = 3.85 V Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0 ms, one output loaded at a time.

Definition of Specifications DUTTest Load 50pF 50Ω Scope 500Ω 450Ω OPEN 2 × VCC tZH tHZ tZL tLZ tr = 3.0 ns tf = 3.0 ns Figure 1 AC Loading Circuit 3. AC Loading and Waveforms

3.1 Loading Circuit

Figure 1 shows the AC loading circuit used in characterizing and specifying propagation delays of all FACT devices (HD74AC and HD74ACT) unless otherwise specified in the data sheet of a specific device. The use of this load, differs somewhat from previous practice provides more meaningful information and minimizes problems of instrumentation and customer correlation. In the past, +25°C propagation delays for TTL devices were specified with a load of 15 pF to ground; this required great care in building test jigs to minimize stray capacitance and implied the use of high-impedance, high-frequency scope probes. FACT circuits changed to 50 pF of capacitance, allowing more leeway in stray capacitance and also loading the device during rising or falling output transitions. This more closely resembles the inloading to be expected in average applications and thus gives the designer more useful delay figures. We have incorporated this scheme into the FACT product line. The net effect of the change in AC load is to increase the average observed propagation delay by about 1 ns. The 500 W resistor to ground can be a high-frequency passive probe for a sampling oscilloscope, which costs much less than the equivalent high-impedance probe. Alternately, the 500 W resistor to ground can simply be a 450 W resistor feeding into a 50 W coaxial cable leading to a sampling scope input connector, with the internal 50 W termination of the scope completing the path to ground. This is the preferred scheme for correlation. (See figure 1.) With this scheme there should be a matching cable from the device input pin to the other input of the sampling scope; this also serves as a 50 W termination for the pulse generator that supplies the input signal. Shown in figure 1 is a second 500 W resistor from the device output to a switch. For most measurements this switch is open; it is closed for measuring one set of the Enable/Disable parameters (low-to-off and off- to-low) of a 3-state output. With the switch closed, the pair of 500 W resistors and the 2 · V CC supply voltage establish a quiescent high level.

Definition of Specifications

3.2 Test Conditions

Figure 2 describes the input signal voltage levels to be used when testing FACT circuits. The AC test conditions follow industry convention requiring VIN to range from 0 V for a logic low to 3.0 V for a logic high for HD74ACT devices and 0 V to VCC for HD74AC devices. The DC parameters are normally tested with VIN at guaranteed input levels, that is VIH to VIL (see tables 3 and 4 for details). Care must be taken to adequately decouple these high performance parts and to protect the test signals from electrical noise. In an electrically noisy environment, (e.g., a tester and handlder not specifically designed for high-speed work), DC input levels may need to be adjusted to increase the noise margin to allow for the extra noise in the tester which would not be see in a system. Noise immunity testing is performed by raising V IN to the nominal supply voltage of 5.0 V then dropping it to a level corresponding to VIH, and then raising it again to the 5.0 V level. Noise tests can also be performed on the VIL characteristics by raising VIN from 0 V to VIL, then returning it to 0 V. Both VIH and V IL noise immunity tests should not induce a switch condition on the appropriate outputs of the FACT device. Good high-frequency wiring practices should be used in constructing test jigs. Leads on the load capacitor should be as short as possible to minimize ripples on the output waveform transitions and to minimize undershoot. Generous ground metal (preferably a ground plane) should be used for the same reasons. A V CC bypass capacitor should be provided at the test socket, also with minimum lead lengths.

3.3 Rise and Fall Times

Input signals should have rise and fall times of 3.0 ns and signal swing of 0 V to 3.0 V for HD74ACT devices or 0 V to VCC for HD74ACT devices. Rise and fall times less than or equal to 1 ns should be used for testing fmax or pulse widths. CMOS devices, including, 4000 Series CMOS, HC, HCT and FACT families, tend to oscillate when the input rise and fall times become lengthy. As a direct result of its increased performance, FACT devices can be more sensitive to slow input rise and fall times than other lower performance technologies. It is important to understand why this oscillation occurs. Consider the outputs, where the problem is initiated. Usually, CMOS outputs drive capacitive loads with low DC leakage. When the output changes from a high level to a low level, or from a low level to a high level, this capacitance has to be charged or discharged. With the present high performance technologies, this charging or discharging takes place in a very short time, typically 2-3 ns. The requirement to charge or discharge the capacitive loads quickly creates a condition where the instantaneous current change through the output structure is quite high. A voltage is generated across the V CC or ground leads inside the package due to the inductance of these leads. The internal ground of the chip will change in reference to the outside world become of this induced voltage.

Definition of Specifications Consider the input. If the internal ground changes, the input voltage level appears to change to the DUT. If the input rise time is slow enough, its level might still be in the device threshold region, or very close to it, when the output switches. If the internally-induced voltage is large enough, it is possible to shift the threshold region enough so that it re-crosses the input level. If the gain of the device is sufficient and the input rise or fall time is slow enough, then the device may go into oscillation. As device propagation delays become shorter, the inputs will have less time to rise or fall through the threshold region. As device gains increase, the outputs will swing more, creating more induced voltage. Instantaneous current change will be greater as outputs become quicker, generating more induced voltage. Package-related causes of output oscillation are not entirely to blame for problems with input rise and fall time measurements. All testers have V CC and ground leads with a finite inductance. This inductance needs to be added to the inductance in the package to determine the overall voltage which will be induced when the outputs change. As the reference for the input signals moves further away from the pin under test, the test will be more susceptible to problems caused by the inductance of the leads and stray noise. Any noise on the input signal will also cause problems. With FACT logic having gains as high as 100, it merely takes a 50 mV change in the input to generate a full 5 V swing on the output.

3.4 Propagation Delays, f

max , Set and Hold Times A 1.0 MHz square wave is recommended for most propagation delay tests (figures 3 and 4) The repetition rate must necessarily be increased for testing fmax . A 50% duty cycle should always be used when testing fmax . Two pulse generators are usually required for testing such parameters as setup time, hold time, recovery time etc. DATA IN DATA OUT tpxx tpxx Vmi Vmo Vmi = 50% VCC for HD74AC devices; 1.5 V for HD74ACT devices Vmo = 50% VCC for HD74AC/HD74ACT devices Figure 3 Waveform for Inverting and Non-Inverting Functions

Definition of Specifications CONTROL IN CLOCK tPHL tPLH Vmi Vmi Vm Vmo tw trec OUTPUT Vmi = 50% VCC for HD74AC devices; 1.5 V for HD74ACT devices Vmo = 50% VCC for HD74AC/HD74ACT devices Figure 4 Propagation Delay, Pulse Width, and trec Waveforms

3.5 Enable and Disable Times

Figures 5 and 6 show that the disable times are measured at the point where the output voltage has risen or fallen by 10% from the voltage rail level (i.e., ground for tLZ or VCC for tHZ ) . This change enhances the repeatability of measurements, reduces test time, and gives the system designer more realistic delay times to use in calculating minimum cycle times. Since the high-impedance state rising or falling waveform is RC-controlled, the first 10% of change is more linear and is less susceptible to external influences. More importantly, perhaps from the system designer’s point of view, a change in voltage of 10% is adequate to ensure that a device output has turned off. Measuring to a larger change in voltage merely exaggerates the apparent Disable time and thus penalizes system performance since the designer must use the Enable and Disable times to device worst case timing signals to ensure that the output of one device is disabled befor that of another device is enabled. OUTPUT CONTROL DATA OUT Vmi Vmo –0.3 V VCC 90% V CC tHZtZH Vmi = 50% VCC for HD74AC devices; 1.5 V for HD74ACT devices Vmo = 50% VCC for HD74AC/HD74ACT devices Figure 5 3-State Output High Enable and Disable Times

Definition of Specifications OUTPUT CONTROL DATA OUT Vmi Vmo 10% V CC Gnd tLZ tZL Vmi = 50% VCC for HD74AC devices; 1.5 V for HD74ACT devices Vmo = 50% VCC for HD74AC/HD74ACT devices Figure 6 3-State Output Low Enable and Disable Times

3.6 Electrostatic Discharge

Precautions should be taken to prevent damage to devices by electrostatic discharge. Static charge tends to accumulate on insulated surfaces such as synthetic fabrics or carpeting, plastic sheets, trays, foam, tubes or bags, and on ungrounded electrical tools or appliances. The problem is much worse in a dry atmosphere. In general, it is recommended that individuals take the precaution of touching a known ground before handling devices. More often, handling equipment that is not properly grounded, causes damage to parts. Ensure that all plastic parts of the tester, that are near the device, are conductive and connected to ground. DATA IN CONTROL INPUT MR OR CLEAR Vmi Vmi Vmi tsu tsu th trec Vmi = 50% VCC for HD74AC devices; 1.5 V for HD74ACT devices Vmo = 50% VCC for HD74AC/HD74ACT devices Figure 7 Setup Time, Hold Time and Recovery Time

Definition of Specifications 4. Symbols and Terms Defined for HD74AC Series Explanation of Symbols Used in Electrical Characteristics and Recommended Operating Conditions Table 5 DC Characteristics Symbol Term Description VIH High level input voltage High level input voltage to ensure that a logic element operates under some constraint VIL Low level input voltage Low level input voltage to ensure that a logic element operates under some constraint VOL Low level output voltage Output voltage in effect when, under the input condition for bringing the output low, the rated output current is allowed to flow to the output terminal VOH High level output voltage Output voltage in effect when, under the input condition for bringing the output high, the rated output current is allowed to flow to the output terminal Vt + Forward input threshold voltage Input voltage in effect when the operation of a logic element varies as the input is allowed to go up form a voltage level lower than the reverse input threshold voltage V t Vt - Reverse input threshold voltage Input voltage in effect when the operation of a logic element varies as the input is allowed to drop up form a voltage level higher than the forward input threshold voltage V t Vh Hysteresis voltage Difference between forward input threshold voltage Vt + and reverse threshold voltage Vt IIN Input leakage current Input current that flows in when the rated maximum input voltage is applied to the input terminal IOZ Off-state output current (high-impedance) Current that flows to the 3-state output of an element under the input condition for bringing the output to high-impedance state ICC Quiescent Supply current Current that flows to the supply therminal (VCC ) under the rated input condition IOLD Minimum Dynamic Output Current Output current that flows in when, under the condition for bringing the output low,the output terminal is tied to the rated out voltage V OLD . IOHD Output current that flows out when, under the condition for bringing the output high, the output terminal is tied to the rated out voltage V OHD . ICCT Maximum ICC /Input Current that flows to the supply terminal (VCC ) under the rated input condition

Definition of Specifications Table 6 AC Characteristics Symbol Term Description fmax Maximum clock frequency Maximum clock frequency that maintains the stable changes in output logic level in the rated sequence under the I/O condition allowing clock pulses to change the output state tTLH Rise (transient) time Rated time from low level to high level of a wavefrom during the defined transient period changing from low level to high level tTHL Fall (transient) time Rated time from high level to low level of a wavefrom during the defined transient period changing from high level to low level tPLH Output rise propagation delay time Delay time between the rated voltage levels of an I/O voltage waveform under a defined load condition, with the output changing from low level to high level tPHL Output fall propagation delay time Delay time between the rated voltage levels of an I/O voltage waveform under a defined load condition, with the output changing from high level to low level tHZ 3-state output disable time (high level) Delay time between the rated voltage levels of an I/O voltage waveform under a defined load condition, with the 3-state output changing from high level to the high-impendance state tLZ 3-state output disable time (low level) Delay time between the rated voltage levels of an I/O voltage waveform under a defined load condition, with the 3-state output changing from low level to the high-impendance state tZH 3-state output enable time (high level) Delay time between the rated voltage levels of an I/O voltage waveform under a defined load condition, with the 3-state output changing from the high-impendance state to high level tZL 3-state output enable time (low level) Delay time between the rated voltage levels of an I/O voltage waveform under a defined load condition, with the 3-state output changing from the high-impendance state to low level tw Pulse width Duration of time between the rated levels from a leading edge to a trailing edge of a pulse waveform th Hold time Time in which to hold data at the specified input terminal after a change at another related input terminal (e.g., clock input) tSU Setup time Time in which to set up and keep data at the specified input terminal before a change at another related input terminal (e.g., clock input)

Definition of Specifications Symbol Term Description trec Recovery time Time period between the time when data at the specified input terminal is released and the time when another related input terminal (e.g., clock input) can be changed C IN Input capacitance Capacitance between GND terminal and an input terminal to which 0 V is applied C PD Power Dissipation Capacitance Equivalent device power capacitance in dynamic state Table 7 Explanation of Symbols Used in Function Tables Symbol Description H High level (in steady state; written H or "H" level in sentences) L Low level (in steady state; written L or "L" level in sentences) Transition from L level to H level Transition from H level to L level X Either H or L Z 3-state output off (high impedance) a·····h Input level of steady state for each of inputs A-H Q 0 Q level immediately before the indicated input condition is established Q 0 Complement of Q0 Q n Q level immediately before the latest active change ( or ) occurs Single H level pulse Single L level pulse TOGGLE Each output is changed to the complement of the preceding state by an active input change ( or )

Today’s system designer is faced with the problem of keeping ahead when addressing system performance and reliability. Hitachi’s Advanced CMOS helps designers achieve these goals. FACT (Fairchild Advanced CMOS Technology) logic was designed to alleviate many of the drawbacks that are common to current technology logic circuits. FACT logic combines the low static power consumption and the high noise margins of CMOS with a high fan-out, low input loading, and a 50 W transmission line drive capability to offer a complete family of SSI and MSI devices. Performance features such as advanced Schottky speeds at CMOS power levels, advanced Schottky drive, excellent noise, ESD and latch-up immunity are characteristics that designers of state-of-the-art systems require. FACT logic answers all of these concerns in one family of products. To fully utilize the advantages provided by FACT, the system designer should have an understanding of the flexibility as well as the trade-offs of CMOS design. The following section discusses common design concerns relative to the performance and requirements of FACT. There are five items of interest which need to be evaluated when implementing FACT devices in new designs:

• Interfacing—interboard and technology interfaces, battery backup, and power down or live insert/ extract systems require some special thought.
• Transmission line driving—FACT has line driving capabilities superior to all CMOS families and most TTL families.
• Noise effects—As edge rates increase, the probability of crosstalk and ground bounce problems increases. The enhanced noise immunity and high threshold levels improve FACT’s resistance to crosstalk problems.
• Board layout—Prudent board layout will ensure that most noise effects are minimized.
• Power supplies and decoupling—Maximize ground and V CC traces to keep VCC /ground impedance as low as possible; full ground/VCC planes are best. Decouple any device driving a transmission line; otherwise add one capacitor for every package.

5.0V 510 T1,T2 - 2SC641 (K) D1,D2 - HP5082 - 2811 D3 - IN414 OR IN 4148 –5.2V AC ECL Figure 6 Differential Output ECL-to-HD74AC Circuit It should be understood that for FACT, as with other CMOS technologies, input levels that are between specified input values will cause both transistors in the CMOS structure to be conducting. This will cause a low resistive path from the supply rail to ground, increasing the power consumption by several orders of magnitude. It is important that CMOS inputs are always driven as close as possible to the rail.Figure 7 Crystal Oscillator Circuit Implemented with FACT HD74AC00

1. Line Driving With the available high-speed logic families, designers can reach new heights in system performance. Yet, these faster devices require a closer look at transmission line effects. Although all circuit conductors have transmission line properties, these characteristics become significant when the edge rates of the drivers are equal to or less than three times the propagation delay of the line. Significant transmission line properties may be exhibited in an example where devices have edge rates of 3 ns and lines of 8 inches or greater, assuming propagation delays of 1.7 ns/ft for an unloaded printed circuit trace. Of the many properties of transmission lines, two are of major interest to the system designer: Zoe, the effective equivalent impedance of the line, and t pde, the effective propagation delay down the line. It should be noted that the intrinsic values of line impedance and propagation delay, ZO and tpd, are geometry- dependent. Once the intrinsic values are known, the effects of gate loading can be calculated. The loaded values for Zoe and t pde can be calculated with: Z= Z

1 C / C

O t I+ t = t 1+ C / Cpde pd t I where CI = intrinsic line capacitance and Ct = additional capacitance due to gate loading. The formulas indicate that the loading of lines decreases the effective impedance of the line and increases the propagation delay. Lines that have a propagation delay greater than one third the rise time of the signal driver should be evaluated for transmission line effects. When performing transmission line analysis on a bus, only the longest, most heavily loaded and the shortest, least loaded lines need to be analyzed. All lines in a bus should be terminated equally; if one line requires termination, all lines in the bus should be terminated. This will ensure similar signals on all of the lines.

a: No Termination b: Series Termination c: Parallel Termination d: AC Parallel Termination e: Thevenin Termination Figure 8 Termination Schemes There are several termination schemes which may be used (figure 8). Included are series, parallel, AC parallel and Thevenin terminations. AC parallel and series terminations are the most useful for low power applications since they do not consume any DC power. Parallel and Thevenin terminations cause high DC power consumption.

2.1 Series Terminations

Series terminations are most useful in high-speed applications where most of the loads are at the far end of the line. Loads that are between the driver and the end of the line will receive a two-step waveform. The first wave will be the incident wave. The amplitude is dependent upon the output impedance of the driver, the value of the series resistor and the impedance of the line according to the formula VW = VCC · Zoe/(Zoe + RS + ZS) The amplitude will be one-half the voltage swing if RS (the series resistor) plus the output impedance (ZS) of the driver is equal to the line impedance. The second step of the waveform is the reflection from the end of the line and will have an amplitude equal to that of the first step. All devices on the line will receive a valid level only after the wave has propagated down the line and returned to the driver. Therefore, all inputs will see the full voltage swing within two times the delay of the line.

2.2 Parallel Termination

Parallel terminations are not generally recommended for CMOS circuits due to their power consumption, which can exceed the power consumption of the logic itself. The power consumption of parallel terminations is a function of the resistor value and the duty cycle of the signal. In addition, parallel termination tends to bias the output levels of the driver towards either V CC or ground. While this feature is not desirable for driving CMOS inputs, it can be useful for driving TTL inputs.

2.3 AC Parallel Termination

AC parallel terminations work well for applications where the delays caused by series terminations are unacceptable. The effects of AC parallel terminations are similar to the effects of standard parallel terminations. The major difference is that the capacitor blocks any DC current path and helps to reduce power consumption.

2.4 Thevenin Termination

Thevenin terminations are also not generally recommended due to their power consumption. Like parallel termination, a DC path to ground is created by the terminating resistors. The power consumption of a Thevenin termination, though, will generally not be function of the signal duty cycle. Thevenin terminations are more applicable for driving CMOS inputs because they do not bias the output levels as paralleled terminations do. It should be noted that lines with Thevenin terminations should not be left floating since this will cause the input levels to float between V CC or ground, increasing power consumption. FACT circuits have been designed to drive 50 W transmission lines over the full temperature range. This is guaranteed by the FACT family’s specified dynamic drive capability of 86 mA sink and 75 mA source current. This ensures incident wave switching on 50 W transmission lines and is consistent with the 3 ns rated edge transition time. FACT devices also feature balanced output totem pole structures to allow equal source and sink current capability. This gives rise to balanced edge rates and equal rise and fall times. Balanced drive capability and transition times eliminate both the need to calculate two different delay times for each signal path and the requirement to correct signal polarity for the shortest delay time. FACT product inputs have been created to take full advantage of high output levels to deliver the maximum noise immunity to the system designer. V IH and VIL are specified at 70% and 30% of VCC respectively. The corresponding output levels, VOH and VOL , are specified to be within 0.1 V of the rails, of which the output is sourcing or sinking 50 mA or less. These noise margins are outlined in figure 9. 70% 50% 50% 30% Input Thresholds Figure 9 Input Threshold

4.1 Crosstalk

The problem of crosstalk and how to deal with it is becoming more important as system performance and board densities increase. Crosstalk is the capacitive coupling of signals from one line to another. The amplitude of the noise generated on the inactive line is directly related to the edge rates of the signal on the active line, the proximity of the two lines and the distance that the two lines are adjacent. Crosstalk has two basic causes. Forward crosstalk, figure 11, is caused by the wavefront propagating down the printed circuit trace at two different velocities. This difference in velocities is due to the difference in the dielectric constants of air (Er = 1.0) and epoxy glass (Er = 4.7). As the wave propagates down the trace, this difference in velocities will cause one edge to reach the end before the other. this delay is the cause of forward crosstalk; it increases with longer trace length, so consequently the magnitude of forward crosstalk will increase with distance. Reverse crosstalk, figure 12, is caused by the mutual inductance and capacitance between the lines which is a transformer action. Reverse crosstalk increases linearly with distance up to a critical length. This critical length is the distance that the signal can travel during its rise or fall time. Although crosstalk cannot be totally eliminated, there are some design techniques that can reduce system problems resulting from crosstalk. FACT’s industry-leading noise margins make systems immune to crosstalk-related problems easier to design. FACT’s AC noise margins, shown in figures 13 and 14, exemplify the outstanding immunity to everyday noise which can effect system reliability. Voltage (V) Time (ns) (5.0 ns/div) Key Active Driver Forward Crosstalk Active Receiver This figure shows traces taken on a test fixture designed to exaggerate the amplitude of crosstalk pulses. Vertical Scale

1.0 V/Div

0.2 V/Div

5.0 ns/Div 5.0 ns/Div 0.0 V Figure 11 Forward Crosstalk on PCB Traces

Voltage (V) Time (ns) (5.0 ns/div) Key Active Driver Forward Crosstalk Active Receiver This figure shows traces taken on a test fixture designed to exaggerate the amplitude of crosstalk pulses. Vertical Scale 5.0 ns/Div 5.0 ns/Div 0.0 V Figure 12 Reverse Crosstalk on PCB Traces Gnd 30% VCC 0 5 10 15 20 25 Pulse Width (ns) 30 35 40 45 50

4 Volts from V

CC VCC = 5.0 V HAZARD SAFE Figure 13 High Noise Margin

70% 0 5 10 15 20 25 Pulse Width (ns) 30 35 40 45 50

3 Volts V

CC = 5.0 V HAZARD SAFE Figure 14 Low Noise Margin With over 2.0 V of noise margins, the FACT family offers better noise rejection than any other comparable technology. In any design, the distance that lines run adjacent to each other should be kept as short as possible. The best situation is when the lines are perpendicular to each other. For those situations where lines must run parallel, the effects of crosstalk can be minimized by line termination. Terminating a line in its characteristic impedance reduces the amplitude of an initial crosstalk pulse by 50%. Terminating the line will also reduce the amount of ringing (figure 15). Crosstalk problems can also be reduced by moving lines further apart or by inserting ground lines or planes between them. Signal on Active Line Noise Amplitude at A Versus RPassive Line Vn = Coupled SignalZOA R VT 100% : NO R R+Z O RV 67% : R = 2ZO 60% : R = 1.5ZO 50% : R = ZO Figure 15 Effects of Termination on Crosstalk

4.2 Ground Bounce

Ground bounce occurs as a result of the intrinsic characteristics of the leadframes and bondwires of the packages used to house CMOS devices. As edge rates and drive capability increase in advanced logic families, the effects of these intrinsic electrical characteristics become more pronounced. Figure 16 shows a simple circuit model for a device in a leadframe driving a standard test load. The inductor L1 represents the parasitic inductance in the ground lead of the package; inductor L2 represents the parasitic inductance in the power lead of the package; inductor L3 represents the parasitic inductance in the output lead of the package; the resistor R1 represents the output impedance of the device output, and the capacitor and resistor C L and RL represent the standard test load on the output of the device. I C L R L VCC Figure 16 Ground Bounce Output Model Output Voltage Output Current Inductor Voltage

The three waveforms shown in figure 16 depict how ground bounce is generated. The first waveform shows the voltage (V) across the load as it is switched from a logic high to a logic low. The output slue rate is dependent upon the characteristics of the output transistor, the inductors L1 and L3, and C L , the load capacitance. The second waveform shows the current that is generated as the capacitor discharges [I = CL • dv/dt]. The third waveform shows the voltage that is induced across the inductance in the ground lead due to the changing currents [Vgb = –L • (di/dt)]. There are many factors which affect the amplitude of the ground bounce. Included are:

• Number of outputs switching simultaneously: more outputs results in more ground bounce.
• Type of output load: capacitive loads generate two to three times more ground bounce than typical system traces. Increasing the capacitive load to approximately 60 to 70 pF increases ground bounce. Beyond 70 pF, ground bounce drops off due to the filtering effect of the load. Moving the load away from the output reduces the ground bounce.
• Location of the output pin: outputs closer to the ground pin exhibit less ground bounce than those further away.
• Voltage: lowering V CC reduces ground bounce.
• Test fixtures: standard test fixtures generate 30 to 50% more ground bounce than a typical system since they use capacitive loads which both increase the AC load and form LCR tank circuits that oscillate. Ground bounce produces several symptoms:
• Altered device states. FACT logic does not exhibit this symptom.
• Propagation delay degraduation. FACT devices are characterized not to degrade more than 250 ps per additional output switching
• Undershoot on active outputs. The worst-case undershoot will be approximately equal to the worst-case quiet output noise.
• Quiet output noise. FACT logic’s worst-case quiet output noise has been measured to be approximately 500 to 1100 mV in actual system applications. Observing either one of the following rules is sufficient to avoid running into any of the problems associated with ground bounce:
• First, use caution when driving asynchronous TTL-level inputs from CMOS octal outputs, or
• Second, use caution when running control lines (set, reset, load, clock, chip select) which are glitch- sensitive through the same devices that drive data or address lines. When it is not possible to avoid the above conditions, there are simple precautions available which can minimize ground bounce noise. These are:
• Locate these outputs as close to the ground pin as possible.
• Use the lowest VCC possible or separate the power supplies.
• Use board design practices which reduce any additive noise sources, such as crosstalk, reflections etc.

1. Design Rules The set of design rules listed below are recommended to ensure reliable system operation by providing the optimum power supply connection to the devices. Most designers will recognize these guidelines as those they have employed with advanced bipolar logic families.

• Use multi-layer boards with V CC and ground planes, with the device power pins soldered directly to the planes to insure the lowest power line impedances possible.
• Use decoupling capacitors for every device, usually 0.10 mF should be adequate. These capacitors should be located as close to the ground pin as possible.
• Avoid sockets or wirewrap boards whenever possible.
• Do not connect capacitors from the outputs directly to ground.

5.1 Decoupling Requirements

FACT, as with other high-performance, high-drive logic families, has special decoupling and printed circuit board layout requirements. Adhering to these requirements will ensure the maximum advantages are gained with FACT products. Local high frequency decoupling is required to supply power to the chip when it is transitioning from a low to a high value. This power is necessary to charge the load capacitance or drive a line impedance. Figure 17 displays various V CC and ground layout schemes along with associated impedances. For most power distribution networks, the typical impedance is between 50 and 100 W . This impedance appears in series with the load impedance and will cause a droop in the VCC at the part. This limits the available voltage swing at the local node, unless some form of decoupling is used. This drooping of rails will cause the rise and fall times to become elongated. Consider the example described in figure 18 to calculate the amount of decoupling necessary. This circuit utilizes an HD74AC240 driving a 100 W bus from a point somewhere in the middle. Being in the middle of the bus, the driver will see two 100 W loads in parallel, or an effective impedance of 50 W . To switch the line from rail to rail, a drive of 78 mA is needed; more than 624 mA will be required if all eight lines switch at once. This instantaneous current requirement will generate a voltage across the impedance of the power lines, causing the actual V CC at the chip to droop. This droop limits the voltage swing available to the driver. The net effect of the voltage droop will lengthen device rise and fall times and slow system operation. A local decoupling capacitor is required to act as a low impedance supply for the driver chip during high current conditions. It will maintain the voltage with acceptable limits and keep rise and fall times to minimum. The necessary values for decoupling capacitors can be calculated with the formula given in figure 19.

It is good practice to distribute decoupling capacitors evenly through the logic, placing one capacitor for every package.

5.2 Capacitor Types

Decoupling capacitors need to be of the high K ceramic type with low equivalent series resistance (ESR), consisting primarily of series inductance and series resistance. Capacitors using 5ZU dielectric have suitable properties and make a good choice for decoupling capacitors; they offer minimum cost and effective performance. 6. TTL-Compatible CMOS Designs Require Delta ICC Consideration The FACT product line is composed of two types of advanced CMOS circuits: HD74AC and HD74ACT devices. HD74ACT indicates an advanced CMOS device with TTL-type input thresholds for direct replacement of LS and ALS circuits. As this HD74ACT series is used to replace TTL, the Delta I CCT specification must be considered; this spec may be confusing and misleading to the engineer unfamiliar with CMOS. It is important to understand the concept of Delta I CCT and how to use it within a design. First, consider where Delta ICCT initiates. Most CMOS input structures are of the totem pole type with an n-channel transistor in a series with a p-channel transistor as illustrated in figure 20. P Channel N Channel VCC To Internal Logic Input Pad Figure 20 CMOS Input Structure These two transistors can be modeled as variable resistors with resistances varying according to the input voltage. The resistance of an on transistor is approximately 50 W while the resistance of an off transistor is generally greater than 5 MW . When the input to this structure is at either ground or VCC , one transistor will be on and one will be off. The total series resistance of this pair will be the combination of the two individual resistances, greater than 5 MW . The leakage current will then be less than 1 mA. When the input is between ground and V CC , the resistance of the on transistor will increase while the resistance of the off transistor will decrease. The net resistance will drop due to the much larger value of the off resistance. The total series resistance can be as low as 600 W . This reduction in series resistance of the input structure will cause a corresponding increase in I CC as current flows through the input structure. Figure 21 depicts typical ICC variance with input voltage for an HD74ACT device.

1.000 0.000 0.000 5.000 0.5000V/dlc VIN ICC 0.1000 mA/div Figure 21 ICC versus Input Voltage for HD74ACT Devices The Delta ICC specification is the increase in ICC . For each input at VCC -2.1 V, the Delta ICC value should be added to the quiescent supply current to arrive at the circuit’s worst-case static ICC value. Fortunately, there are several factors which tend to reduce the increase in ICC per input. Most TTL devices will be able to drive FACT inputs well beyond the TTL output specification due to FACT’s low input loading in a typical system. For example, FAST logic outputs can drive HD74ACT-type inputs down to 200 mV and up to 3.5 V. Additionally, the typical I CC increase per input will be less than the specified limit. As shown in the graph above, the ICC increase at VCC -2.1 V is less than 200 mA in the typical system. Experiments have shown that the ICC of an HD74ACT240 series device typically increases only 200 mA when all of the inputs are connected to a FAST device instead of ground or VCC . It is important when designing with FACT, as with any TTL-compatible CMOS technology, that the Delta ICC specification be considered. Designers should be aware of the spec’s significance and that the data book specification is a worst-case value; most systems will see values that are much less. 7. Testing Advanced CMOS Devices with I/O Pins There are more and more CMOS families becoming available which can replace TTL circuits. Although testing these new CMOS units with programs and fixtures which were developed for bipolar devices will yield acceptable results most of the time, there are some cases where this approach will cause the test engineer problems. Such is the case with parts that have a bidirectional pin, exemplified by the HD74AC245/HD74ACT245 octal transceiver. If the proper testing methods are not followed, these types of parts may not pass those tests for I CC and input leakage currents, even when there is no fault with the devices. CMOS circuits, unlike their bipolar counterparts, have static ICC specification orders of magnitude less than standard load currents. Most CMOS ICC specifications are usually less than 100 mA. When conducting an ICC test, greater care must be taken so that other currents will not mask the actual ICC so that other currents will not mask the actual ICC of the device. These currents are usually sourced from the inputs and outputs.

Each I/O pin is connected to both an input device and an output device. The pin can be viewed as having three states: input, output and output disabled. However, only two states actually exist. The pin is either an input or an output. When testing the ICC of the device, the pins selected as outputs by the T/R signal must either be enabled and left open or be disabled and tied to either rail. If the output device is disabled and allowed to float, the input device will also float, and an excessive amount of current will flow from V CC to ground. VCC VCC VCC Input Output IIN IOZ Clamp Diodes Figure 24 I/O Pin Internal Structure A simple rule to follow is to treat any output which is disable as an input. This will help insure the integrity of an ICC test. Another area which might precipitate problems is the measurement of the leakages on I/O pins. The I/O pin internal structure is depicted in figure 24. The pin is internally connected to both an input device and an output device; the limit for a leakage test must be the combined IIN specification of the input and the IOZ specification of the output. For FACT devices, IIN is specified at –1 mA while IOZ is specified at –5 mA. Combining these gives a limit of –6 mA for I/O pins. Usually, I/O pins will show leakages that are less than the IOZ specification of the output alone. Testing CMOS circuits is no more difficult than testing their bipolar counterparts. However, there are some areas of concern that will be new to many test engineers beginning to work with CMOS. Becoming familiar with and understanding these areas of concern prior to creating a test philosophy will avert many problems that might otherwise arise later.