HD6845SP

Hitachi Semiconductor

CRT CONTROLLER (CRTC)

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HD6845R HITACHI

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The CRTC is a LSI controller which is designed to provide an interface for microcomputers o raster scan type CRT displays. HD6845SP, HD68A45SP, HD6SB45SP The CRTC belongs to the HD6800 LSI Family and has full HD6845AP, HD68A45AP, HD68B45RP compatibility with MPU in both data lines and control lines. Its primary function is to generate timing signal which is necessary for raster scan type CRT display according to the specification \\ programmed by MPU. The CRTC is also designed as a program- ny yt mable controller, so applicable to wide-range CRT display from nyt small low-functioning character display up to raster type full yt graphic display as well as large high-functioning limited graphic 5 yet display. 1 yy Y- T @ FEATURES vv {0P-40) ‘© Number of Displayed Characters on the Screen, Vertical Dot Format of One Character, Horizontal and Vertical Sync Signal, Display Timing Signal are Programmable * 3.7 MHz High Speed Display Operation (HD6845S) © PIN ARRANGEMENT * 3.0 MHz High Speed Display Operation (HD6845R) vss Ha vsync + Line Butfer-less Refreshing baad alvswc © 14-bit Refresh Memory Address Output (16k Words max. vests [3] alan. Access) ee Ce fala. «Programmable interface/Non-intertace Scan Mode ws ey pee ‘* Built-in Cursor Control Function a En, ‘+ Programmable Cursor Height and its Blink wa. Eel jo. * Built-in Light Pen Detection Function mas jo «Paging and Scrolling Capability ome fi Bio; + TTL Compatible we ao, * Single +5V Power Supply Me po ay I] Balo, Mie Blo = SYSTEM BLOCK DIAGRAM Mas Eso. on wa Ei Eales secge acy Lal Ears - oer cus [al Binw 7 a, [wrx] Go voc Bay Balcux | (Top View) ES +4 0%, fore} Hoses care = ORDERING INFORMATION | Bho \\ | . i HD6845S 1.0 MHz — { = | yee HO6BA45S 1.5 MHz 3.7 MHz max. - HD68B45S 2.0 MHz tr so [SI HD6845R Vem Oe HD68A45R: 3,0 MHz max. | ste aes HD6aB45R ! cera @HITACHI 80 Hitachi America, Ltd. ¢ Hitachi Plaza » 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300

= ABSOLUTE MAXIMUM RATINGS ikem Unie Supply Voltage v input Vatoe vo Operating Temperature "6 Storage Temperature “

7 With respect to Veg (SYSTEM GNDT

INOTE} Permanent LS! damage may occur if maximum ratings are exceeded. Normal operation should be under recommendea operating conditions. If these Conditions ere exceeded, @ could atfect reliability of LSI, = RECOMMENDED OPERATING CONDITIONS ) Hem [symbor min Tye Tmax Unit Supply Voltage [ect 5 T8025 v a Input Voltage [Vin 20 Vee v Operating Tonowrre a SO * With respect 10 Vgg (SYSTEM GND) ® ELECTRICAL CHARACTERISTICS @ DC CHARACTERISTICS (Voc = 5V + 5%, Vss = OV, Ta = -20~+75°C, untess otherwise noted.) teem [Symboi [Test Condition |min_[typ* [max] unit Input “High” Voltage | Vin | | 20 [= 7 vee Tv input “Low Voge - Ss Input Leakage Current | tin | Vin =O~5.25V (ExceptDo~O,) | -25 | - | 25 | HA Three-State input Current fi Vin = 0.4~ 2.4V -0 | _ 10 A (off-state) rs Vee = 5.25V (Dp~ D7) | a Output “High” Volt: Vv LOAD v utp tian’ Voltaae * Tone = 100A (Other Outputs) Output “Low” Voltage Toa = 1.6 mA v \\ Vin = 0 Do ~ D> pF Input sitance Ta= 25°C Ouapit Capacance | Can | Vn =v, Ta 28°C f= t0Mae | - | - | wo | oF Powe Owain | ff |) 00 | 000 | * Ta= 28°C, Veo = 5.0V © HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 + (415) 589-8300 81

—— eS HD6845R/HD6845S eo 1068 45H 8455 * AC Characteristics (Vee = 5V + 5%, T, = -20 ~ +75°C, unless otherwise noted.) 1. TIMING OF CRTC SIGNAL T[GeckGyeetine | tee | [so [= | = [eo] | = [os 2 [one Puss wiah | Px | be f= [= [oof = T= 3 [ectow" Pune wan | Pa | bso = [= fe | = P= Tre : [=t= Tet] co 5 [=p =p [ = ms @ [ua on Sve Paso wa | Pn | [et = p= pet = [= T. 7 | Light Pen strobe [== fof = [= ff os Unc Tne ot Acceptance faye pela [=f ef 8 | Memory Adéress Delay Time | two _| [= [= foo | = [= | eo [os a bap = pe [= [Poe Te 10 | DISPTMG Delay Time Fie1 | — | [20 | — | — | 280 | ns 11 | CUDISP Delay Time tooo |= | = | 250 [ns 42 | Vertical Sync Delay Time vso [= | =_| 250 | ns 2. MPU READ TIMING Tex |___ noeeets est | Enable Cycle Time 10 | - oses| - | - | 05) - us Enable “High” Pulse Width _ [os t= 028 | - | - | o2| — Hs Enable “Low” Pulse Width j0.40 | — 028 | - | — [oa - us Enable Rise and Fall Time fT ta[ -[- 5 3 - l=) 25 | ns ‘Address Set Up Time Fig. 3 wo] - | - [ ol - | - | 7) - | - jo Data Oelay Time ge ee ee Data Hold Time 10 | = wo} = j -~ | 10 — | = | ms Address Hold Time [tan —_| “0 | = t= 10 a = ToT = [= [a Data Access Time [tace | T= [aso = =f 360 T= T=] 280 fe 3._ MPU WRITE TIMING | Test Heseess HBesaass Abseesse st EE n |Semb=t| condition [in [we [mae | win | we | max [min | wp | max | OM Enable Cycle Time Tone voT - ) - josssp- 1-05) - Enable “High” Pulse Width | PWew oas | — | - [ozs | - | - [o2) - | - | ms Enable “Low” Pulse Width | PWey joo] = | = 1028 | = | - 192 ee Enable Rise and Fail Time ter, ter p= js] =] = | me) | nw 8 “Address Set Up Time ta re oe eo ~ Data Set Up Time tosw fe ee Bata Hold Fine ra a a a ‘Address Hold Time [tan | ee ee de ee @HITACHI 82 Hitachi America, Ltd, * Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 « (415) 589-8300

20v 20v. Pwo | oav. |Aboav oav osv CuK PWew ) 2av | | oav WA-MA,, ‘ua tan! zav | o4v RA, “RA, | tRaD tran zav | | oav oiseTwG t 24v i} cuoise | tooo Teo0 zav oav sync VEvNE tHsD tHso Tov 2ov PW LPH ‘LPSTB “This Figure shows the rettion in ime between CCL signa end each ovtout gnats Outout sequence thown in Figs, 10-15. Figure 1 Time Chart of the CRTC @HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 83

(@ FUNCTION OF SIGNAL LINE * Interface Signals to CRT Display Device ‘The CRTC provides 13 interface signals to MPU and 25inter- Character Clock (CLK) face signals to CRT display. - Input Pin No. 21 * Interface Signals to MPU Bi-directional Data Bus (D9 ~D7) CLK is a standard clock input signal which defines character timing for the CRTC display operation. CLK is normally derived VO Pin No. 33~26 from the external high-speed dot timing logic. Bi-directional data bus (Dp~D7) are used for data transfer Horizontal Sync (HSYNC) between the CRTC and MPU. The data bus outputs are 3-state buffers and remain the high-impedance state except when MPU Output Pin No. 39 Performs a CRTC read operation HSYNC is an active “High” level signal which provides hori: Read/Write (R/W) zontal synchronization for display device. Input Pin No. 22 Vertical Sync (VSYNC) 2 Read/Write signal (R/W) controls the direction of data transfer Output Pin No. 40 TC vw “ ” ls between the CRTC and MEU. When RW i ai ee VSYNC is an active “ High’ level signal which provides verti- level, data of MPU is transferred to CRTC. cal synchronization for display device Chip Select (C8) Display Timing (OISPTMG) Input_Pin No. 35 Chip Select signal (CS) is used to address the CRTC. When CS DISPTMG is an active “High” level signal which defines the is at "Low level. it enables Read/Write operation to CRTC splay period in horizontal and vertical raster scanning. It is internal registers. Normally this signal is derived from decoded _‘N€CESSAFY to enable video signal only when DISPTMG is at address signal of MPU under the condition that VMA of MPU is. “High” level at “High” level. Refresh Memory Address (MAg ~MAj3) Register Select (RS) Output Pin No. 4~ 17) Input Pin No. 24 MAo~MAj are refresh memory address signals which are Register Select signal (RS) isused to select the address register Used 0 access to refresh memory is order to refresh the CRT and Igsonvol egistersofthe CRTC. When S isat“Low'level, 8 periodically. These outputs enables 16k words max. re- in addnens replat s selected and when RS is at "High" level, "88h memory access. So, for instance. these are applicable up to ccontrol registers are selected. This signal is normally a derivative 2000 characters/screen and 8-page system. Of the lowest bit (AO) of MPU address bus, Raster Address (RAg ~ RA) Enable (E) Output Pin No. 38 ~34) Input_ Pin No. 23 RAg~ RAq are raster address signals which are used to select Enable signal (E) is used as strobe signal in MPU Read/Write __ the Faster of the character generator or graphic pattern generator ‘operation with the CRTC internal registers. This signal is nor- ete. mally a derivative of the HD6800 System 9, clock. Cursor Display (CUDISP) Reset (RES) Output Pin No. 19 Input _Pin No. 2 CUDISP is an active “High” level video signal which is used RES mani display the cursor on the CRT screen. This output is inhibited Reset signal (RES) is an input signal used to reset the CRTC. (0 GSPIRY. Maal pe When RES is at “Low” level, it forces the CRTC into the While DISPTMG is at “Low” level. Normally this output is following status. mixed with video signal and provided to the CRT display device 1) All the counters in the CRTC are cleared and the device strobe stops the display operation. Light Pen Strobe (LPSTB) 3) Control registers in the CRTC are not affected and remain unchanged. LPSTB is an active “High” level input signal which accepts ‘This signal is different from other HD6800 family LSIs in the _strobe pulse detected by the light pen and control circuit. When following functions and has restrictions for usage. this signal is activated, the refresh memory address 1) RES has capability of reset function only when LPSTBisat_ (MAg~ MA\\3) which are shown in Fig. 2 are stored in the 14-bit ““Low'" level light pen register. The stored refresh memory address need to be 2) The CRTC starts the display operation immediately after _ corrected in software, taking the delay time of the display device, RES goes “High” level light pen, and light pen control circuits into account @ HITACHI Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300 87

= REGISTER DESCRIPTION Table 1 Internal Registers Assignment _ sare Ten a rove Un owe CE ARSE of [ewes] on omrome TO [es | pt tt c[leweer le femmoeneleme ee fT ~ Yertical Raster, | t t ° ooo1 yf 3 [Sync Width Horizontal: x ° ww | w2) wet) wv | wh3 | wh2| wht | whd Seats so |sloorso) 6 [vas imines | Line x [o ; | pT Vertical * ~ } if cheer [® Bae eS Ts ae o[fereee a fevereon noo ic Maximum Rarer \\ \\ efeleeees[ wm frmamme [=fe eT — > ——— = +—-+ [freee anf Tbe Tet Tt TT (NOTE) 1, The Registers marked *: (Written Value) = (Specified Valve) - 1 2. Written Value of RQ is mentioned below. Face eee Rete | (Written Value) = (Specified Value? - 1 2) Iarlace Syne 8 Video Mode {Wien Value) = (Specified Value) -2 3. CDand C1 wecty shew of CUDISP Bo ang 01 pecty sxe of OISPTMG, Binen Sn", V aperin video mode. Ssowcties the nverlace Syne Mode 4, Beatie the corse blink. Papectiey tne coor blak persed & mabtinS pecly the puns width of Vertes! Syne Sara Meno=wn3 spery tne pulse wrath of Horizona! Syne Sgn

6 Rot srinay programed to be odd member n teriae mode

® FUNCTION OF INTERNAL REGISTERS Table 2 Pulse Width of Vertical Sync Signal © Address Register (AR) 7 se 7 Pulse Width This is a S-bit register used to select 18 internal control 2 z 2 z registers (RO~R17). Its contents are the address of one of 18 0 ° ° 0 16H internal control registers. Programming the data from 18 to 31 ° ° ° 1 produces no results. Access to RO~RIT requires, first of all, to : write the address of corresponding control register into this ° ° ' ° 2 register. When RS and CS are at “Low” level, this register is ° ° 1 1 3 selected, o 1 ° o 4 © Horizontal Total Register (RO) 0 1 0 1 5 This is a register used to program total number of horizontal ° 1 1 o 6 characters per line including the retrace period. The data is 8-bit, 0 1 1 1 , 9 and its value should be programmed according to the specifi- 1 ° ° ° 8 cation of the CRT. When M is total number of characters, M-! thall be programmed to this register. When programming for 1 o 0 1 9 interlace mode, M must be even. 1 ° 1 o | 10 © Horizontal Displayed Register (R1) ' ; 5 ; Bs This is a register used to program the number of horizontal displayed characters per line. Data is 8-bit and any number that 1 1 o ’ 13 is smaller than that of horizontal total characters can be 1 ’ 1 o 4 Programmed. 1 1 1 1 18 © Horizontal Sync Position Register (R2) Hi Raster period This is a register used to program horizontal sync position as multiples of the character clock period, Data is 8-bit and any number that is lower than the horizontal total number can be programmed. When H is character number of horizontal Sync Table 3 Pulse Width of Horizontal Syne Signal Position, H-1 shall be programmed to this register. When pro- Sw grammed value of this register is increased, the display position P Fy 2 Py Pulse Width on the CRT screen is shifted to the left. When programmed value is decreased, the position is shifted to the right. Therefore, 0 0 0 0 = (Note) the optimum horizontal position can be determined by this 0 ° 0 1 1cH value 0 0 1 0 | 2 ‘© ‘Syne Width Register (R3) } This is a register used to program the horizontal sync pulse o 0 1 1 3 width and the vertical sync pulse width. The horizontal sync ° 1 ° ° 4 pulse width is programmed in the lower 4-bit as multiples of the 0 1 ° ’ 5 character clock period. “0 can't be programmed. The vertical ° 1 1 ° 1 4 sync pulse width is programmed in higher 4-bit as multiples of the raster period. When “O” is programmed in higher 4-bit, 0 1 1 1 7 16 raster period (16H) is specified 1 0 ° o 8 © Vertical Total Register (R4) ' ° ° ' 8 ‘This is a register used to program total number of lines per 1 o 1 ° 10 frame including vertical retrace period. The data is within 7-bit 1 ° ’ 1 " and its value should be programmed according to the specifica- 1 1 ° ° | 2 tion of the CRTC. When N is totat number of lines, N-1 shall 1 1 0 1 | a3 be programmed to this register. | 1 1 1 0 } 14 © Vertical Total Adjust Register (RS) 1 1 1 1 15 This is a register used to program the optimum number to Gar Character Gost period adjust total number of rasters per field. This register enables to (Note) HSW = "0" can’t be used decide the number of vertical deflection frequency more strictly. © Vertical Displayed Register (6) This is a register used to program the number of displayed character rows on the CRT screen. Data is 7-bit and any number that is smaller than that of vertical total characters can be programmed. @ HITACHI Hitachi America, Ltd. © Hitachi Plaza # 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300. 89

© Vertical Syne Position Register (R7) Skew function is used to delay the output timing of This is a register used to program the vertical sync position CUDISP and DISPTMG in LSI for the time to access refresh fn the screen as multiples of the horizontal character line peri- memory. character generator or pattern generator, and to od, Data is 7-bit and any number that is equal to or less than make the same phase with serial video signal, vertical total characters can be programmed. When V is charac- ter number of vertical sync position, V-I shall be programmed @ Maximum Raster Address Register (R9)" to this register. When programmed value of this register is in- This is a register used to program maximum raster address creased, the display position is shifted up. When programmed within S-bit. This register defines total number of rasters per value is decreased, the position is shifted down. Therefore, the character including line space. This register is programmed as optimum vertical position may be determined by this value. follows, Non-interlace Mode, Interlace Syne Mode © Interlace and Skew Register (R8) When total number of rasters is RN, RN-1 shall be pro- This is a register used to program raster scan mode and skew grammed. (delay) of CUDISP and DISPTMG. Interlace Sync & Video Mode Raster Scan Mode Program Bit (V, S) When total number of rasters is RN, RN-2 shall be pro- Raster scan mode is programmed in the V, S bit. grammed, This manual defines total number of casters in non-interlace Table 4 Raster Scan Mode (2', 2°) mode, interlace sync mode and interlace sync & video mode as follows: Vv $s Raster Scan Mode = Non-interlace Mode 0 ° } Non-interlace Mode 0 ——————_ Total Number of Rasters:5 1 0 1 ———~ Programmed Value: Nr = 4 t) 1 Interlace Syne Mode 2_—_————— {The same as displayed ) 1 1 Interlace Sync & Video Mode —_ total number of rasters “ _— , Raster Address. In the non-interlace mode, the rasiers of even number Mod field and odd number field are scanned duplicatedly. In the interlace Syne . 9 ———____ Total Number of Rasters:5 interlace sync mode, the rasters of odd number field are > r Tevctoss---= 0 Programmed Value: Nr=4 scanned in the middle of even number field. Then it is i——— I SST in the interlace sync mode, controlled to display the same character pattern in two 927-7 i 2 ‘otal number of rasters in fields. In the interlace sync & video mode, the raster scan Witter 2 gu both the even and odd fields method is the same as the interlace sync mode, but it is : 3 isten. On programming, controlled to display different character pattern in two field. #——————— the half of t indefined ee Skew Program Bit (C1, CO, D1, D0) sp Raster Address otal number of rasters. ‘UDI sna ae used to program the skew (delay) of C Intartaca Syne & Video Mode ‘Skew of these two kinds of signals are programmed 9 >--vv7waa. 1 Total Number of Rasters's separately. pL | Programmed Value: Nr= 3 pos Total number of rasters ( displayed in the even field Raster Address. and the odd field Table § DISPTMG Skew Bit (2°, 2°) DI DO DISPTMG ‘© Cursor Start Rester Register (R10) This is a register used to program the cursor start raster ° ° Non-skew address by lower 5-bit (2°~2*) and the cursor display mode by o 1 One-character skew higher 2-bit (2° , 2°). 1 tC) ‘Two-character skew 1 1 Non-output Table 7 Cursor Display Mode (2°, 2°)

8 Pp Cursor Display Mode

Table 6 CUDISP it (27, 2° able 6 cunise Seow Bit (27, 2") 1 o Blink 16 Field Period ci oo Cubise 1 1 Blink 32 Field Period oO 0 Non-skew 0 1 One-character skew Blink Period 1 0 ‘Two-character skew Lae rk S ——] 1 1 Non-output 16 of 32 Field Period *See Comparison of HD684SS and HDOESSR on page 40 @HITACHI 90 Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300

5 SNht (Non-interlace mode only)

© Start Address Register (R12, R13) ‘* In the interlace mode, pulse width is changed +44 raster time when These are used to program the first address of refresh vertical syne signal extends over two fields. memory to read out. Paging and scrolling is easily performed using this register. ‘This register can be read but the higher 2-bit (2°, 27) of R12 are Notes for Use always “0”, The method of directly using the value programmed in the internal registersof LSI for controlling the CRT is adopted. © Cursor Register (R14, R15) Consequently, the display may flicker on the screen when the These two read/write registers stores the cursor location. The | contents of the registers are changed from bus side asynchro- higher 2-bit (2°, 2”) of R14 are always “0”. nously with the display operation. Cursor Register © Light Pen Register (R16, R17) Writing into this register at frequent intervals for moving the ‘These read only registers are used to catch the detection | cursor should be performed during horizontal and vertical address of the light pen. The higher 2-bit (2°, 27) of R16 are | retrace period. always “0”. Its value needs to be corrected by software because —_| Start Address Register there is time delay from address output of the CRTC to signal Writing into the start address register at frequent intervals for input LPSTB pin of the CRTC in the process that raster is It | scrolling and paging should be performed during horizontal and after address output and light pen detects it. Moreover, delay __| vertical display period. time shown in Fig. 2 needs to be taken into account. It is desirable to avoid programming other registers during display operation. [Restriction on Programming internal Register 1) O<Nhd<Nht + 1 $256 = OPERATION OF THE CRTC 2)0<Nvd < Nv +] S128 3) 0 SNhsp SNht © Time Chart of CRT Interface Signals 4) 0S Nvsp SNute The following example shows the display operation in which 5) 0S Ncstart SNCEND $ Nr (Non-interlace, Interlace sync | values of Table 8 ate programmed to the CRTC internal mode) registers. Fig. 7 shows the CRT screen format. Fig. 10 shows the OS Ncstart © NceNp © Nr + I (Interlace sync & video time chart of signals output from the CRTC. mode) (7 Maer of Hosizontat Total Characters (nt # 1)—————————_ | Number of Horizontal Displayed Characters (Nhd) ——— | 22 SaaS Se iii it ec f El 3 2 3 a 3 3 = 3 7 34 32 2 3) 35 Display Periog 5| 3 = € S| 2 pve || Vertical Total Adjust (Ned) Figure 7 CRT Screen Format @HITACHI itachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 » (415) 589-8300 91

Table 8 Programmed Values into the Registers Register [| _Reaister Name | Value Resister_|_ResisterName | Value RO Horizontal Total Nhe i) Max Raster Address Nr Rk Horizontal Displayed Nhd | R10 Cursor Start Raster R2 Horizontal Sync Position Nhsp au Cursor End Raster R3—— | Syne Width Nvsw, Nhsw RI2 Start Address (H) ° RA Vertical Total Net R13 Start Address (L) 0 RS Vertical Total Adjust Nadi [ RI Cursor (H) RE Vertical Displayed Nvd | R15 Cursor (L) R7 Vertical Sync Position Nvsp j R16 Light Pen (H) RS lnterlace & Skew [av Light Pen (L) TNOTET NhacNnt, Nac The relation between values of Refresh Memory Address In non-interlace mode, each field 1s scanned duplicatedly. (MAo~MAj3 ) and Raster Address (RAg~RAg) and the display The values of raster addresses (RAg~RAs) are counted up one position on the screen is shown in Fig. 16. Fig. 16 shows the from 0. case where the value of Start Address is 0. Interlace Syne Mode Control In the interlace sync mode, raster addressed in the even field © Intertace Control and the odd field are the same as addressed in the non-interlace Fig. 8 shows an example where the same character is mode. One character pattern is displayed mutually and its dis- displayed in the non-interlace mode, interlace sync mode, and _played position in the odd field is set at 1/2 raster space down interlace sync & video mode, from that in the even field. Non-interlace Mode Control tee ee 3-2 Ee Saeeennes od : ~ po Seeeeeeeee Sry eaaeenne SARIS + SESE SSS s- beer Soeeemeneees St) 8-2 Se °° * pee ceeeerreree St] Non-interlace Mode Interlace Syne Mode Sees oe SSe0 00S |e oo ‘SBieee--0- $5 |line #0 Qo tg 8] st ie Interiace Sync & Video Mode Interiace Sync & Video Mode {Total aumber of rasters ina tine is even.) (Total number of ratters ina line it odd.) Figure 8 Example of Raster Scan Display @ HITACHI 92 Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

Interlace Sync & Video Mode Control In interlace sync & video mode, the output raster address when the number of rasters is even is different from that when. ° ° the number of rasters is odd. 1 tf 1 1. Table 9 The Output of Raster Address in 3 Coro 2 CCC Interlace Sync & Video Mode ase sry Toul co Sco Number of Odd Field eto ett Rasters in 2 Line aaa to — mee fo ine* Ls ire s ove [Even bine Even Address_| Odd Address Soper eet oyeeeees Odd Line* Odd Address Even Address + tnternal line address begins from 0. Cursor Start Address = 9 Cursor Start Address = 9 Cursor End Andress = 9 ‘Cursor End Address = 10 1) Total number of rasters in a line is even; When number of rasters is programmed to be even, even , raster address is output in the even field and odd raster address 0. is output in the odd field. 16644494 2) Total number of rasters in a line is odd; 2-6O5O906 When total number of rasters is programmed to be odd, odd 396556546 and even addresses are reversed according to the odd and even 1-6$65904 lines in each field. In this case, the difference in numbers of dots 5O$o5504 displayed between even field and odd field is usually smaller the pahaeaea: case of 1), Then interlace can be displayed more stably. 7. [NOTE] The wide disparity of dots between number of dots ete between even field and odd field influences beam ett current of CRT. CRT, which has a stable high-voltage ot tae part, can make interlace display normal. On the con- trary, CRT, which has unstable high-voltage part, Cursor Start Address = 1 moves deflection angle of beam current and also dots Cursor End Address = § displayed in the even and odd fields may be shifted, Characters appears distroting on a border of the Figure 9 Cursor Control screen. So 2) programming has an effect to decrease such evil influences as mentioned above. Fig. 13 shows fine chart in each mode when interlace is performed © Cursor Control Fig. 9 shows the display patterns where each value is programmed to the cursor start raster register and the cursor end raster register. Programmed values to the cursor start raster register and the cursor end raster register need to be under the following condition. Cursor Start Raster Register SCursor End Raster Register © Maximum Raster Address Register. Time chart of CUDISP is shown in Fig. 14 and Fig. 15. @ HITACHI Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 93

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a HD6845R/HD6845S —~idi TE a 5 i i! Ar ° 3 4 = Hye HU ; r [| g Ff] 3 | § i —-| a | ian i if | : HLL HITACHI Hitachi America, Ltd. « Hitachi Plaza « wee Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 97

~~ -i]—li-ili-i] (eel — HEHE meet deli ili) ¢ aL 1a 1 3 r ml | matte) HHH | ii 53 } & ; Fyn) yt i 2 = hci] — JHA) Pil? Ine — IH i is @HITACHI 98 Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

s7elo1 224567801 2345 67 8 lo vorer-p Q,. Loao pis REG-N cner-# (eux) Character Tome Figure 19 Time Chart of Dot Counter = INTERFACE TO DISPLAY CONTROL UNIT Fig. 21 shows detailed block diagram of display control unit. Fig. 20 shows the interface between the CRTC and display This shows how to use CUDISP and DISPTMG. CUDISP and control unit. Display control unit is mainly composed of DISPTMG should be used being latched at least one time Refresh Memory, Character Generator, and Video Control at external flip-flop F! and F2. Flip-flop Fl and F2 function circuit. For refresh memory, 14 Memory Address line to make one-character delay time so as to synchronize them (0~16383) max are provided and for character generator, 5 with video signal from parallel-serial converter. High-speed Raster Address line (0~31) max are provided. For video control —_D type flip-flop as TTL is used for this purpose. After being circuit, DISPTMG, CUDISP, HSYNC, and VSYNC are sent delayed at Fl and F2 DISPTMG is AND-ed with character out. DISPTMG is used to control the blank period of video video signal, and CUDISP is Or-ed with output from AND signal. CUDISP is used as video signal to display the cursor on _ gate, By using this circuitry, blanking of horizontal and vertical the CRT screen. Moreover, HSYNC and VSYNC are used as retrace time is controlled. And cursor video is mixed with drive signals respectively for CRT horizontal and vertical deflec- character video signal. tion circuits. Fig. 21 shows the example in the case that both refresh Outputs from video control circuit, (video signals and sync memory and Character Generator can be accessed for horizontal signals) are provided to CRT display unit to control the one character time. Time chart for this case is shown in Fig. 24 deflection and brightness of CRT, thus characters are displayed This method is used when a few character needed to be dis- ‘on the screen. played in horizontal direction on the screen. @HITACHI 100 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300

When many characters are displayed in horizontal direction _there are some troubles about delay time of MA during hori- ‘on the screen, and horizontal one-character time is so short zontal one-character time on high-speed display operation, that both refresh memory and Character Generator cannot be system shown in Fig, 23 is adopted. The time chart in this case accessed, the circuitry shown in Fig. 22 should be used. In this _is shown in Fig. 26, Character video signal is delayed for two- case refresh memory output shall be latched and Character character time because each MA outputs and refresh memory Generator shall be accessed at the next cycle. The time chart outputs are latched, and they are made to be in phase with in this case is shown in Fig. 25. CUDISP and DISPTMG should CUDISP and DISPTMG by delaying for two-character time. be provided after being delayed by one-character time by using Table 10 shows the circuitry selection standard of display units. skew bit of interlace & skew register (RB). Moreover, when Table 10 Circuitry Standard of Display Control Unit Block Interlace & Skew Register Case Relation among tcy Refresh Memory and Character Generator Diagram Bit Programming rey | or |e —1_| ten > RM Access +06 Access +twao [Finzi | o [| o | o | o 2 | RM Access + CG Access + twp 2 ten > RM Access + tran Z oft

3 RM Access + tan 2 ton > RM Access 1 0

Ten CHOP Period, tag MA Delay RM: Refresh Memory CG: Character Generator FY cupise oar cHoP.N r OISPTMG Cf care DP xc Retresh Cheracter | __ cu cHere (ox ] Figure 22 Display Control Unit (2) cuoise on Homme F om) ew Ceo [osc] Figure 23 Display Control Unit (For high-speed display operation) (3) @HITACHI 102 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 # (415) 589-8300

ma (ie XX XXX) cupise \\ | / aw 71 20 \\ | faked i i A i ! f \\ mou XK XK 2 XK OTK 2 KK NT baton) ED GED GHD GHD GED GEE, ) fl I esouT XOX FOX FOC OOK FXO OKT) t * vioco | | T i \\ erro | vocores Figure 26 Time Chart of Display Unit (3) Table 10A Parameter of Display [_________] Specification of CRT monitor CRTC iniernal Register Character Dot Size (Horizontal) fT External ircuit | Character Dot Size (Vertical) [Oe [ Horizontal owl PO OSC*T Horizontal Displayed [a Horizontal Sync Position a <a GO| Horizontal Sync Width <a Ca | [ Vertical Total Vertical Displayed | | Werical Syne Wieth | Interface mode | Skew oe | Cursor Size i010 [ SatAddress es Cursor Address [Oa Fis 4 This parameter is decided by specification of CRT monitor. @HITACHI 104 Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 * (415) 589-8300

Number of Horizontal Displayed Characters cal retrace period and the relation between number of vertical Number of horizontal displayed characters is programmed to displayed character and total number of rasters on a screen is horizontal displayed register (RI) of the CRTC. Programmed as mentioned above, CRT which is suitable for desired screen value is based on screen format. Horizontal display period, format should be selected, which is given by specification of horizontal deflection fre- For optimum screen format, it is necessary to adjust number quency and horizontal retrace period of CRT display unit, of rasters per line, number of vertical displayed characters, and determines horizontal character time, being divided by number total adjust raster (Nadj) within specification of vertical of horizontal displayed characters. Moreover, its cycle time and deflection frequency. access time which are necessary for CRT display system are Scan Mode determined by horizontal character time. The CRTC can program three-scan modes shown in Table 11 Number of Vertical Displayed Characters to interlace mode register (R8). An exampl: of character display Number of vertical displayed characters is programmed to _in each scan mode is shown in Fig. 8 vertical displayed register (R6). Programmed value is based on screen format, As specification of vertical deflection frequency of CRT determines number of total rasters (Rt) including verti- , ) Monona Detection Perad y= Horizontal Display Period Horizontal Reteace Period tt Number of Horizontal Displayed Characters te vivon sme « Horizontal Dspioy Period He wal Character Ti ‘Number of Horizontal Dispiayed Characters: Figure 31 Number of Horizontal Displayed Characters Table 11 Program of Scan Mode (R10, R11) enable programming the display modes shown in T Table 7 and display patterns shown in Fig. 9, Therefore, it is V__S_| Scan Mode Main Usage possible to change the method of cursor display dynamically o 0} \\ ‘Normal Display of Characters according to the system conditions as well as to realize the 1g | Nomintertace | tures cursor display that meets the system requirements. 0 1 | tnterlace Syne | Pine Display of Characters Start address resisters (R12. R13) give an offset to the _ & Figures, address of refresh memory to read out. This enables paging and ———TBisplay of Many Characters S« Tooling easily interlace Syne | D'IaY of Many Characters Pi ei V1) Video & Figures Without Using Cursor registers (R14, R15) enable programming the cursor High-resolution CRT display position on the screen. As for cursor address. it is not X, Y address but linear address that is programmed. [NOTE] In the interlace mode, the number of times per = Applications of the CRTC sec. in raster scanning on one spot on the screen is half as many as that in non-interlace mode. @ Monochrome Character Display Therefore, when persistence of luminescence is Fig, 32 shows a system of monochrome character display. short, flickering may happen. It is necessary to Character clock signal (CLK) is provided to the CRTC through select optimum scan mode for the system, taking OSC and dot counter. It is used as basic clock which drives characteristics of CRT, raster scan speed, and internal control circuits. MPU is connected with the CRTC by number of displayed characters and figures into standard bus and controls the CRTC initialization and read/ account. write of internal registers. Refresh memory is composed of RAM which has capacity of Curtor Display Method ‘one frame at least and the data to be displayed is coded and Cursor start raster cegister and cursor end raster register stored. The data to refresh memory is changed through MPU @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 107

, Ain Ay meee ne es Kel : = contro. | Sicwat [oo] Figure 32 Monochrome Character Display bus, while refresh memory is read out successively by the CRTC CUDISP, HSYNC, and VSYNC are provided to video control to display a static pattern on the screen. Refresh memory is circuit. It controis blanking for output of parallel-serial con- accessed by both MPU and the CRTC, so it needs to change its verter, mixes these signals with cursor video signal, and gene- address selectively by multiplexer. The CRTC has 14 MA rates sync signals for an interface to monitor. (Memory Address output), but in fact some of them that are needed are used according to capacity of refresh memory. © Color Character Display Code output of refresh memory is provided to character Fig. 33 shows a system of color character display. In this generator. Character generator generates a dot pattem of a example, a 3-bit color control bit (R, G, B) is added to refresh Specified raster of a specified character in parallel according to memory in parallel with character code and provided to video code output from refresh memory and RA (Raster Address control circuit. Video control circuit controls coloring as well output) from the CRTC. Parallelserial converter is normally as blanking and provides three primary color video signals (R, composed of shift register to convert output of character G, B signals) to CRT display device to display characters in generator into a serial dot pattern. Moreover, DISPTMG, seven kinds of color on the screen. @ HITACHI 108 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300

a 5R/HD6845S ry... Ays~Ay “Teal I - er, Lex [sus oniven] TER a Configuration ofthe Retresh Memory REFRESH MEMORY bing iam) Color __Bbit ate 1T word aCe BR Oana word — end Tigh order Low Srer cuanacten “ | I COLOR BIT (R, G, 8) o1seTMs A. vioeo SYNC Vivo conTROL vane —_— SYNC SIGHAT Figure 33 Color Character Display © Color limited Graphic Display coded output of refresh memory Limited graphic display is to display simple figures as well as In this example, graphic pattern generator adopts ROM, so character display by combination of picture element which only the combination of picture elements which are program- are defined in unit of one character med to it is used for this graphic display system. Adopting RAM 'As shown in Fig. 34, graphic pattern generator is set up in instead of ROM enables dynamically writable symbols in any parallel with character generator and output of these gener- combination on one display by changing the contents of them, ators are wire-ORed, Which generator is accessed depends on @ HITACHI Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 109

~ Pees | oe | | COLOR BIT IR, G, 8) lnsvue | W19EO.CONFROL. oa Figure 34 Color Limited Graphic Display @HITACHI 110 Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300

‘© Monochrome Full Graphic Display refresh memory is dot memory that stores all the dot patterns, Fig. 35 shows a system of monochrome full graphic display. so its output is directly provided to parallelserial converter to ‘While simple graphic display is figure display by combination of be displayed. Dot memory address to refresh the screen is set picture elements in unit of 1 picture elements, full graphic dis- up by combination of MA and RA of CRTC. play is display of any figures in unit of 1 dot. In this case tT b.-0,

007 J cux ma

TER RA } ~ | IserMG 2c0 “oe sve Co vemc_| conrnor [sionat' [oo | vsyne Figure 35 Monochrome Full Graphic Display @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 111

Fig. 36 shows an example of access to refresh memory tween dot on the CRT screen and refresh memory address is by combination of MA and RA. Fig. 36 shows a refresh memory shown in Fig. 37. address method for full graphic display. Correspondence be- aa, a =] RA, r 4 care | MA Tt mn wap TT ma wap TT ma, wasp — TT ma, a be ma 8) | petri Memory ma, mee | Rai, wa mm wa m me, me, Figure 36 Refresh Memory Address Method for Full Graphic Display

32 Charcters x8 dot = 286 dou

a LC A | Tevatens Hadron Csi2 | 63 [as Value of ma Figure 37 Memory Address and Dot Display Position on the Screen for Full Graphic Display @ HITACHI 112 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

© Color Full Graphic Display their output is provided to three parallel-serial converters. Then Fig. 38 shows a system of color full graphic display by 7- video control circuit adds the blanking control to output of color display. -Refresh memory is composed of three dot these converters and provides it to CRT display device as red, memories which are respectively used for red, green, and blue. green, and blue video signals with sync signals. These dot memories are read out in parallel at one time and a hunks fe | cux —_ river) 2 ren =— s | vor MEMORY (nam CRTC | | [usvnc | weve | coyrnor | Mieco |] SYNC SIGNAL Figure 38 Color Full Graphic Display @HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 113

a CED B4ER/HDGSAES © Cluster Control of CRT Display circuit separately, but these are controlled together by the The CRTC enables cluster contro) that is to control CRT CRTC, display of plural devices by one CRTC, Fig. 39 shows a system In this system, it is possible for plural CRT display devices to of cluster control. Each display control unit has refresh memory, —_ have their own display separately. character generator, parallelserial converter, and video control E 7 co <@ fy ge ke bie s8 32 SE | [Se* a8 38 ) | } ' . \\ | | BE Fi 8 e wy! aj oc of ig oO

2 SEP 32 ss r

eed $5 58 £ Este] 5 zl al of 8 Ka, 2k i al gig = 3c 8 9] =) = = 3 3) 3) 2] | é 8] | es Q 2 cse 3B Fo | | 5|| a rT s a < | 38e @HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza « 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 # (415) 589-8300 115

"EXAMPLES OF APPLIED CIRCUIT OF THE CRTC Table 12. Moreover, specification of CRT display unit is shown Fig. 41 shows an example of application of the CRTC (o in Table 13 and initializing values for the CRTC are shown in monochrome character display. Its specification is shown in Table 14. Table 12 Specification of Applied Circuit Item Specification “Character Format | «SB x7 Dot SO __ Character Space 1 Horizontal : 3 Dot Vertical - § Dot “One Character Time Tus — —_ "Number of Displayed Characters | 40 characters = 16 lines = 640 characters __ ‘Access Method to Refresh Memory Snychronous Method (DISPTMG Read) Refresh Memory 6408 OO Fr ee ee ee [Reem 9 9 ooo os Tt j CRTC Address Map Address 0 001 00> «© w» we» we» © 6 ee 0 Register | CRTC Control 0 001008... eee wat Register nsssdon'teate, #.::00r1 Synchronization Method _———_—_~| HVSYNC Method ~ Oo Table 13 Specification of Character Display tem Specification Scan Mode Non: interlace Horizontal Deflection Frequency 15.625 kHz Vertical Deflection Frequency 60.1 Hz Dot Frequency | 8MHz © Character Dot (Horizontal x Vertical) Z (8x 12 (Character Font 5 » 7) Number of Dislayed Characters (Row sine) 406 HSYNC Width aus VSYNC Width 3H ; — Cursor Display Raster 9~ 10, Blink 16 Field Period Paging, Scrolling _ Not used © HITACHI 116 Hitachi America, Ltd. « Hitachi Plaza « 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300

a EEE Eee Table 14 Initializing Values for Character Display Register Name Symbol ae eae no [Horizontal Tow! Nt 3F (63) a Horizontal Displayed [nna | 240) Ra Horizontal Sync Position Nhsp Ea (62) f3 SyneWidth 00 Nw, sw a Ra Vertical Total _ dt Net 14 (20) RS | Vertical Total Adjust Nadj 08 (8) ——_F5__| Vertical Total Adjuse 0 RE Vertical Displayed Nw 10 (16) a [Vertical SynePosiion | Ne 13 (9) Re Interlace & Skew __t 00 Ro Maximum Raster Address _ Ne 08 ay R10 Cursor Start Rastee 8, P, NcstanT 49 _ Ri | Gursor End Raster _ Neeno | OA (10) R12 Start Address (H) | C7 (0) a ot ala Cursor (HY | 00 7) RIS Cursor (L Lsiészd 00 (0 te tas lasessst 10123.4567101234567101234567 -——— + — Ra }—— Fa }——— ee }——— ST aan seescces! iseesssest———— HH js a See en BEEnaS! cuner Figure 40 Non-interlace Display (Example) @HITACHI Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 117

es | | We = Pr it 7

——SSSSSSSSSSSSSMMMses = ANOMALOUS OPERATIONS IN HD6845S CAUSED BY REWRITING REGISTERS DURING THE DISPLAY OPERATION® . Register Nome those Operations OK or NG ar | Horizontal Displayed There are some cases where the width of DISPTMG becomes shorter than the [e} @) Woreonial Tere ace some cases where HSYNC is place on the postion ifferent from x 3" “Syne With ~~~ When a rewrite operation i performed at a "High’” level on HSVNC pulse or VSYNC ry Ra) Vertical Total When a rewrite operation is performed during the last raster period in the line, there is 3 RS Vertical Total When a rewrite operation is performed in the last character time of the raster period. cy ‘ava there are tame cars where tre uber oF Adu Raster speed Wy prema aoe mot ade. (Only Guing the ast rene pero! fahioted. However he slay according to the Brogremmed waves performed Vosivan| ___progremmedvatueortne none woutput sen nemontondltieent em me |X Ro me Maximum Raster ‘The internal operation will be disordered by @ rewrite operation. x R10 ‘Cursor Start Raster When a rewrite operation is performed in the last character time of the raster ry ‘ Period, there are some Cases where the jitter Occurs on the cursor raster or the cursor - _—____temporatly shorter than usual, ee RN Cursor End Raster When a rewrite operation 1s performed in the last character time of the raster period, ry is not displayed correctly, Moreover, there are also some cases where the blink rate | RI2 ‘Start Address (H} R12 and R13 are used in the last raster period of the field. A rewrite operation can ° enamel Ge performed encept during ht pelea, However, when R12 ond As oe vowriten in RI3 | Start Address (L) temporally by programming sequence, wil! be performed. fe} | ‘rewrite operation should be peorted Goring the Rercontal/veriea delay | — sores, = Ria Cursor (H) When @ rewrite operation is performed during the display period, there are some [o} i ______ Gatti inere'the curser trnporlly Seplaved tthe adsceor steer ems she en ~~ programmed value, A rewrite operation should be performed during the horizontal/ RIS | Cursor IL) vertical retrace period, Also, when R14 and RIS are rewritten in each held separately. ° the LSI pertormy the spenled davioyeperanon trom the moet ee fo} A rewrite operation is possibie without affecting the screen in the display so much, x When a rewrite operation is performed, there are some cates where 2 Wicker and 30 0n occur temporal @ HITACHI 120 Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300

——— SSSSSSSSSSSSSSSSSSSeSSSSSSSSSSSSSSSSSSSSSSessSsSsSesesseses tides = COMPARISON BETWEEN HD6845S AND HD6845R. © Comparison of function between HD6845S and HD6845R: We. | Functional Oiference [| ———SSCDBUS SBS 1] intertece [Programming Character line address [Character line address Syne | Method |i ee (aie emi ae | of ABO roaramming lola B.C cogrameing Video Mode | Number of unit for number! unit for number | | —_ | nena | oe —. | a a | | in 406845, number of characters is vertically pro: In HO6B45S, number of characters is vertically pro- Srammed im Unit of two lines. at slustrated above grammed nn of one ine a un ated above Number of vertical total characters, Number of {Number of vertical total characters, Number of { artical displayed characters, Vertical Syne Pos verical daploye carats, Vets! Syne Po | ton! tion Programmed number into Vertical Duplaved | Programmed number into Vertical Displayed | Reguter™'s i: |_Reguter™= 10, Number of Only even number can be specified. Both even number and odd number can be specified. | Bases Pe Character line adcress Character line adress a | BE | feels Hf) | 4 4 0 «See ° | | Sigeee rom twesdren © | org eeeen) 1gSS8E-| | 1 | 8 Beeo ka o-Seeo 7 1 Peg ‘Number of raster = 10 scan line (specified) | When number of raster When number of raster ‘However, number which is programmed into re- | per character line is per character line is | ters calculated at follows | EVEN we SO tater | | Programmed number (Ne) |= 10 scan fine 9 scan line | | SiNumber specitied) = 1 | pect ispecited! However, number which is progrommed into register | | iscalculated as follows. | | Proprammes numbe (Nt | | | “number specified) -2 Dupiay fl fala | | | 26S SS—| —EVEN number iit EVEN number pores \\ 4 6=S-SS-S SF ——EVEN number | EB BSSIF even number a | go 2559-8893 +—ODD number $tiee 5 889-3 ——000 number 2-889-600-5000 number | EREERRTS 000 number 6? [rere] | 8 = | Ps wots | >, | z c=! = EVEN number BEE SEs —000 mumver 8 sE (to be continued) @ HITACHI Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 ¢ (415) 589-8300. 121

[ne | Fanon ounce or) — 2 | Vertieat Syne Fixed at 16 raster can eycle (16H) Programmable (1 ~ 16 raster seen cycle) | Paive Width ‘Specified by | [Eins aie | | high order {VSYNC output) sean cycle ! Abitof RE vsync_ ; vsyne [4 i j Attached bits | Noted Horizontal Syne Wicth Vertical Syne Horizontal Syne | | Width Width 3. | SKEW Function ‘Not includes ‘SKEW function is newly included in OISPTMG, | | CUDISP signals | ‘Attached byte | faZZ77 7700) ne {oO MFAvTS) (AMMA a, | Example of DISPTMG output | IT Not shewed a character skew = Two character skew { 1 character time i Sa charater ime RESET Signal (RES) MA, ~ MA,, Output | MAg ~ MA Ourou) | Omer oupute Asynchronous eset | Omer Outputs Output signals of MAy ~ MA.,, RAy ~ RAs, | Output signals of MAs ~ MA.,, RA, ~ RAs and synchronizing with DLK "Low level go to others go t0.""Low”” seve! immediately after RES ‘Low’ leva, after RES has gone to "Low | hasgone to “Low” level Osher outputs go to Low’ immediately after RES has gone to “‘Low” level | = COMPATIBILITY OF HD6845S AND HD6845R feanengea direction need to Non-interlace mode control ct . }: Fully compatible with HD6845R° * The functions added to HD6845S utilize undefined bits of the Interlace syne mode control !” HD684SR can be directly replaced Control Register in HD6845R. If “0” is programmed to the by HD6845S in these modes. undefined bits in the initial set, it is possible to replace Interlace sync & Video mode control HD6845R with HD6845S without changing the parameters. Not compatible with HD6845R_ Note) The restriction on programming of HD6845S and HD6845R. in regard to programming and should be taken into consideration. @ HITACHI 122 Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 © (415) 589-8300

Selected Specification

Hitachi Semiconductor HD6845SP overview.

Summary

CRT CONTROLLER (CRTC)

Description

CRT CONTROLLER (CRTC)

Source title HD6845SP Datasheet(PDF) - Hitachi Semiconductor

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