HD68000

Hitachi Semiconductor

MPU(MICRO PROCESSING UNIT)

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HD68000 HITACHI

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MPU (Micro Processing Unit) — H1D68000 — "The HD68000 is the first in a family of advanced micropro- _ pggq00-8, HD6B000-70, HDBBOO-t2 cessors from Hitachi, Utilizing VLSI technology, the HD68000 | 44 . . isa fully-implemented 16-bit microprocessor with 32-bit }D6BHCO00-8, HOGBHCO00-10, HOGBHCO00-12 registers, a rich basic instruction set, and versatile addressing modes. "The HD68000 possesses an asynchronous bus structure with 24-bit address bus and a 16-bit data bus.

FEATURES

© 32-Bit Data and Address Registers © 16 Megabyte Direct Addressing Range © 56 Powerful Instruction Types (0C-64) © Operations of Five Main Data Types @ Memory Mapped, 1/O HD68000Y-8, HD68000Y-10, HDG8000Y-12 © 14 Addressing Modes HD68HCOO0Y-8, HD68HCOOOY-10, HD68HCOO0Y-12 — HD6BHCO00 — “The HD68HC000 is a 16-bit microprocessor of HD68000 family, which is exactly compatible with the conventional HD68000. ‘The HD68HCOOO is a complete CMOS device and the power t dissipation is extremely low. \\?7 “cl FEATURES (PGA88) © Instruction Compatible with NMOS 068000 HDe8000P-8 ‘© Pin Compatible with NMOS HD68000 HD68HCOOOP-8, HD68HCOOOP-10, HDB8HCOOOP-12 ‘© AC Timing Compatible with NMOS HD68000 . ' © Low Power Dissipation (icc typ = 20 mA, loc max =35 mA at f= 12.5 MHz) (DP-64) HD68000PS-8 HO68HCOO0PS-8, HD6BHCOOOPS-10, HD68HCOOOPS- 12 (0P-648) HD68000CP-8 HD68HCOOOCP-8, HD68HCOOOCP-10, HD68HCOOOCP-12 {cP-68) | | @HITACHI Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 907 .

® TYPE OF PRODUCTS Clock Frequency Torna | rene |r| Pen 1H068000-8 | #H069000-10 [oo] HDee000E [80] HD88000¥40 [too] POA 68 HD68000¥42 aS H68000R8 [80 | ora 6800098 [80 _|_DP.eas HD68000CRE [80 |S cP-68 HOBsHC000-8 [20] HOB8HCIO0-10, [0 HD6BHG000-12 [25°08 HO6sHCODO¥S a HD68HCO00Y-10 [100 | PGA68 HOSBHCOOOYA2 HO6BHCOOORS [ 80 HO68HCOOOP10 [100] oPe4 HDSBHCOOORIZ [25] HOBsHCo00rae [80] HDEBHCOOOPS10 [10.0] oP.64s HDBsHCOOOPSIZ [25] HD68HCO00CRS: [80 HD68HCOOOCR1O [100 | cPé6s HDBBHCOOOCRIZ [725 (Mote) 1068000 rater to the NMOS version 68000, and HOSBHCOOD ‘afer to the CMOS version 88000, 88000 stendr for NMOS end M08 version @ HITACHI 908 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300 .

= PIN ARRANGEMENT © DC-64, DP-64, DP-64S © PGA-68 1PIN by a BOs ees © SISISISISISISIOISISN Os] EADe SISISIOIOLCISICISIO) oe G] aD, pig o1O1) EDs Eo 10) oe x OO, 50) DofB} EID> OIOm roto) soy F910 Soy io) USE] BaD: Si TOIO) Tos EAD: oisioveiciajeictele R/WE Zon GOOOOOOOO9O BACK EG = an Eapis (Top View) (Bottom View) BGACK F} Bass oR Fa Ax [Penne Benenon [Pane | Frson [a ho [ ncn Print| Fercin] Vee EAze es a cLK Bq A: [a [ora | w | wc [| «| as | ss [Ay | = Ean a Mss & EaVee cs [sv | FAT EG Ea A20 a Oa A FES fw EFAs a a = eC vwAGS Eg Are a Bg Ega:> ee vena FA ave [ewe [ay fe ef y ES a BERR Eq EB Ais [a [ref [oy fa we ff mo Be SseSeeeee seaesrs WU Bg Eva's Ae oe a Pika Faas ae Fe: By EGA: a a = Fc; By BS Aio FCo Ba B7)As A Bg Ba As © CP68 A: Ba BaAr As Gi B4 Ag aed Faas "Bbeessssssaseaaa eeteteleitalste Leeds PUELCUPUSEPEPUR PEA Pi (Top View) ony pay roe Eston. Ears Faw vel = cote] Eee, vali] Exaan vat Fete, wet Em ACL Fes foes ne vaxiz] Fama fra Emm, vary Ema. arcs Ex, wood Emma. OCR] Fans WHERE BEREEEEES SPEVEEE FEET EEE PEI SI IE 12] 515] 315) Beggs ef2277iizeeeF (Top View) @ HITACHI Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 « (415) 589-8300 909

© ABSOLUTE MAXIMUM RATINGS Symbol HD68HC000 =0.3~ +70 03~ +65 [input Voltage Mn 070 0s | Operating Temperature Range [Top TO HO [_Storage Temperature Toy ee Heo es 180 with rewect to Veg (SYSTEM GND) (NOTE) Permanent LSI damage may occur it maximum ratings ae exceeded, Normal operation should be under recommended operating conltion It tees conditions are excoeded, could afec ralislty of CSI Since the HDG2HCO00 is MOS device, users are expected 10 be cautious on “letchup” problem caused by voltage frecturation. ™ RECOMMENDED OPERATING CONDITIONS [_____ Ho68000 TH 68H1c000 [min [ye [max [min [ye | max | [_Supply Vottage | Moo” 478 | 80 | 5.26 [are [80 [82s Tv | vie Veo be f= fp ve yy Input Voltage [Other Inputs | VH © [20 [= 1 vec | [Ailinputs — [ vau* [-03 | - | os [-o3 [=~ Tos Tv | [Operating Temperature Tor =| of 5s | mo To Ts fT Tc |

7 With rewpect to Vgg (SYSTEM GND)

@ HITACHI | 910 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300

——— HD68000/HD68HC000 © AC CHARACTERISTICS (Voc = SV + 5%, Veg = OV, Ta = 0 ~ +70°C, unless otherwise noted.) CLOCK TIMING Pe eee TT | | reewneretoowavon |_| [+0] 20] 40] rool 20] v5] me | [ cycie time | tere | | 126 | 260 | 100 | 260] "60 | 250 [ns | ee Boe eaed feye aov oav wore) Timing mesturemants are referenced 0 from # low voltage of 0.8 volt and high a voltage of 2.0 volts, unles otherwise note Tre voage swing tough hi range shoul ser ute end pe trough the ane such at thei wl be ian Bane 8 vat voit Figure 2 Clock input Timing @HITACHI 912 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 .

a Bi 001D5BFIOS READ AND WRITE CYCLES: [me rt ent anf ae ae Condition] min[ max] min] max] min | max] a oe CEs a [5 Becca rigs ee] ae fan as sf a [a8 | [4 | Goce Fai tine ter [| tof =] wf =] 5] m | seek heehee) eS of Se ix Bocctionoroveig [reves] = [= 70] [oo] — | ea | [7 [Sane ice | eouse] | -| | -| m| - | wo] o | ‘High Impedance (Maximum) bet pete pete te] [5 escrito Arn, FT IT eas | Feta mato betel ot slo fest | Spee fo EC he FS Low (Write) Tavs Pee lom| Lal -| wl -| wl -| 2 | Po Pees] ees, Ce lp al Lml o| [Hi Geek tone AS, Oi | Dena [ 14? | AS, BS width Low (Read)/AS Low (Write) | wi_| [240] - [195] - [160] — | as | Last[tewamioetiee ee) Ls = fos ool [| Le peetewontn te) mol = Teel = Pal = | [ie [Socio Comaitana imine [ioc] =o] [ro] [aol | Le [Retin aagr Red [toe] = Dad) = [aot = | val — [| Lis Lancrgrishig ewe] «= C0 70) 0 [ol 0 [ool | Hi Satneniceme pee) (bel pel-fafn| [ioat[ aitowe nares twee) we] | Pept of | aoe | a [pase veg nitow win [we] = aol [of [ol - [os Laat [fevsiaionaftor wie [wom] (Poo) =| sol — | a0] — | | [aot [aiitoniebs tonite [mee] Doo = | sof - | ool | | [as [onctowte ne Gurvaiein ——Twwoe] = P= [0] [sl — [es | [ae TRS oigebrwosrinats we Tyme] Lat = paol= [ asl = [| Lat baaivcdektowuptimes fad! wea} — (15| =|] [vol - | ae [287 | AS,0S High to DTACK Hin | tsuoa| [0 [245] 0 | 190] 0 | 160] ne | teem tee elele fetal Lo ee bet=pep=pet— te Let Sueliscomesstm [ese] [-lel-lw] [alm [ae [ Rat ang EET put Tantion Tine [wet] (C2 | 000 [00] 0 [200] | ae feewtinei@toe mee) = Pep off f= ool | Lacfeaeestua Tew] [=f »t=fel=felm 90 80 70 Pelee fee|_felselile aoa @ HITACHI Hitachi America, Ltd. © Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 913 ;

READ AND WRITE CYCLES (CONTINUED) Test [@MHe [10 MHz [12.5 MHz | Srmbe' |condition | in| max | min] max | min] max | [a [eatin Yen) |e) 89) Se] Fre saws lenin [mbm el» | BG Low to Control, Address, Data Bus High Impedance (AS High) toiz [39 | BG width ih | pus] - [ssf - [8] — fonre| | 40 | Ciock LowtoVMA Low | tcuv | | =| wo -| wf [7] ns | | 41 | Clock Low tot Transition | tcuer_} [=| vol - | es[ | as] os | | 42 | Eoutput Riseand Fal Time | tere | [| 2] — | as] | 25] os | [44 [AS.OSHigh to VPA High | tenon | [0 | ol of sf of 70] ms | E Low to Control, Address Bus Invalid (Address Hold Time) [ 46 [BGACKWiathtow | tat | pus] = [sl = [as] = fonmer| [478 | Asynchronous input Setup Time | tags _| [ 2of = | 2of Tao] — | os _| | 49° | AS.DSHigntoELow | tae | | =0] 70 | -s5| 66 [-45] 45] ns _| oe ewan ee ee [61_| EWidth Low [700] - | s60| - |ao] — [ns _| So |_84 | € tow to Data Out invalid expo | en ee |_88 | RWto Date Bus Driven | tau 080 | [sol - | 20) - | tof — | os | [set | RACTAESET ue wan [mew] [10] | 10] - | 10] — [oar [se [etm oconeitwonen Powe] [ss] [vs] [vs] — four Notes: 1. For loading capecitance of as than or equl to 0 picotarad, subtract nanoutcondt from the value given in the maximum column. 2. Actual value depends on clock period. 3. 11 #47 is satisfied for both DTACK and BEAR, #48 may be 0 nanoseconds. 4. For power up, the MPU must be held in RES state for 100 ms to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the system. 8. if the arynchronous setup time (#47) requirements are satisfied, the OTACK loweto-date setup time (#31) requirement canbe ignored ST deta must only satisfy the dete-in clock low setop time (#27) forthe folloming cycle 6. When AS and R/W are equally loeded (220%), subtrect 10 nenoseconds from the values given in these columns. 7. The processor will negate BG and begin driving the bus again if external arbitration logic negates BA before asserting BGACK. 8. The minimum value must be met to guarentee proper operation. If the maximum value is exceeded, BG may be reasserted. 9. The falling edge of $6 triggers both the negation of the strobes (AS and xDS) and the fling edge of E, Either of thee events can occur {ist dopending upon te ouding on vech nant. Sonciicaion #4B inccats the absolute manitum skew the wil occur between the Taig edge of the nroben and te fling edge of the & lock @ HITACHI 914 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 ;

‘edge-to-edge measurement of the timing specifications. They _their related diagrams for device operation. 1, Setup time for the synchronous inputs BGACK, iPLo.. and VPA guarantees their recognition at the next falling edge of the clock.

BR need fall at this time only in order to insure being recognized at the end of this bus cycle.
Timing measurements are referenced to and from s low voltage of 0.8 volt and a high voltage 2.0 volts, unless otherwise noted.

Figure 3. Read Cycle Timing a

a HD68000/HD68HC000 These waveforms should only be referenced in regard to the signals. Refer to other functional descriptions and their related edge-to-edge measurement of the timing specifications. They are diagrams for device operation. not intended as a functional description of the input and output so st s2 83 Ss s6& S86 s7 @® ® eux a reorcs TT [TT TTT arte AH] jy ae =F AP ad Gree +g eel O ® Pier | cosaDs | of @\\—-@ os fokat e aw l @ es e fe lo-fi es e® ® 8 te ble Dew out ia: _ @ @ SERR/ER @. (Note 2) @ a @ pa ‘HACT/RESET Aaynchronous © Inputs (ore) notes: * Thevalaee ig trou hs ronge tou var utnde end be ough range ooh ts fal ba aban Da vcitane ZO soe 2. Because of loading variations, R/W may be valid after KS even though both are initiated by the rising edge of S2 (Specification 20A). Figure 4, Write Cycle Timing @ HITACHI ) 916 Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

‘the strobes and the falling edge of the E clock. NOTE: This timing diagram is included for those who wish to design their own circuit to generate VMIA. It shown the best case possibly attsinabie. Figure 5. HD6800 Timing—Best Case

8 Hl 8

Figure 6. HD8800 Timing—Worst Caso

The processor will negate BG and begin driving the bus agsin it external arbitration logic negates BA betore asserting BGACK.
The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be ressserted.

for a complete discussion of bus arbitration. Figure 7. Bus Arbitration Timing Diagram — Idie Bus Case

= INTRODUCTION Programming Mode! ‘As shown in the programming model, the 68000 offers seven- Py 1615 a? ° teen 32-bit registers in addition to the 32-bit program counter 100 and a 16-bit status register. The first eight registers (DO ~ D7) lot are used as data registers for byte (8-bit), word (16-bit), and b2 Jong word (32-bit) data operations. The second set of seven los Ewe registers (AO ~ A6) and the system stack pointer may be used Dew as software stack pointers and base address registers. In addi- 04 Rogesters tion, these registers may be used for word and long word jos address operations. All 17 registers may be used as index regis- Jos ters. Jo? ‘The status register contains the interrupt mask (eight levels FT 1615 2 available) as well as the condition codes; extend (X), negative Jao N), zero (Z), overflow (V), and carry (C). Additional status lat bits indicate that the processor is in a trace (T) mode and/or JA2 Seven in a supervisor (S) state, Aedes A> Registers Status Register ae as ‘System Byte (Condition Code Register) aaa oT | Sa 1 ee eC < 4 10,98 43 210 tL ‘Supervisor Stack Pointer H Powers CNERSUEERSE PETS ed a ~~ ieee ee eed Counter ‘Trace Mode Extend 15, ry ° copenior | Mean aon State Interrupt Zero leoitor * Overflow Table 1 Addressing Modes Carry Unused, read as zero. Mode Generation Register Direct Addressing Date Regifter Direct EA=On © DATA TYPES AND ADDRESSING MODES Address Register Direct EA*An Five basic data types are supported. These data types are: “Absolute Duta Addressing () Bits Absolute Short EA = (Next Word) (2) BCD Digits (4 bits) Absolute Long EA = (Next Two Words) 3) Bytes (8 bits) Program Counter Relative Addressing (4) Word (16 bits) Relative with Offset | EA= (PC) + die (5) Long Words (32 bits) Relative with Index and Offset EA= (PC) + (Xn) +44 In addition, operations on other data types such as memory ‘Ropieter Indirect Addressing address, status word data, etc., are provided for in the instruc- Register indirect EA= (An) tion set. Postinerement Register Indirect EA= (AN), An cAn +N The 14 addressing modes, shown in Table 1, includes six Predecrement Register Indirect ‘An © An ~N,EA= (An) basic types: Register indirect with Offtet EA=IAn) + die (1). Register Direct Indexed Register Indirect with Otfset_| EA (An) + (Xn) + dy (2) Register Indirect Immediate Data Addressing @) Absolute Immediate DATA = Next Word(s) (4) Immediate Quick immediate Inherent Data (5) Program Counter Relative Implied Addressing (6) Implied Implied Register EA = SR, USP, SP, PC Included in the register indirect addressing modes is the capa- (NOTES) bility to do postincrementing, predecrementing, offsetting and EA = Effective Address due Sixteen-bit Offset indexing. Program counter relative mode can also be modified An = Address Register (displacement) via indexing and offsetting, On = Data Register N = 1 for Byte, 2 for Xn = Address or Date Register used Words and 4 for Long ne Index Register Words. If Anis the stack SR = Status Rogister pointer and the operand PC = Program Counter fize is byte, Ne=2 to keep ( }= Contents of the sree peunrer on da = Eight-bit Offset word boundary. (displacement) + + Reptaces @HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 921

© INSTRUCTION SET OVERVIEW instructions can use any of the 14 addressing modes. Combining ‘The 68000 instruction set is shown in Table 2. Some addi- instruction types, data types, and addressing modes, over 1000 tional instructions are variations, or subsets, of these and they useful instructions are provided. These instructions include appear in Table 3. Special emphasis has been given to the in- _ signed and unsigned multiply and divide, “quick” arithmetic struction set's support of structured high-level languages to facil operations, BCD arithmetic and expanded operations (through itate ease of programming. Each instruction, with few excep- traps). tions, operates on bytes, words, and long words and most Table 2 Instruction Set Minemonie Description Mnemonic Deseription Moemonie Description "ABC "Add Decimal with Extend OR Exclusive Or PEA Push Etfective Address ‘0 ‘Add EXG Exchange Registers AND Logical And ext Sign Extend Pee Peortbeprierhooneaiie Ast ‘Arithmetic Sift Left aMP ume ROR Fotate Right without Extend ASR Arithenetic Shift Right sn Jump to Subroutine ROXL Rotate Left with Extend Bec Branch Conditionally LEA ‘Losd Ettective Address ROXR —_| Rotate Right with Extend acre Bit Test and Change Link, Link Stack RTE Return from Exception acur Bit Test and Clear tse Logical Shift Lett are Return and Restore ora Seach Atay tse Lopes! Shite Right ATs Return trom Subroutine it Feet " MOVE Move ‘sBcD ‘Subtract Decimal with Extend BSR Branch to Subroutine MOVEM — | Move Multiple Registers See Set Conditional erst Bit Tost mover ‘Move Peripheral Data sTOP Stop ‘CHK Check Register Against Bounds = MULS. Signed Multiply sus Subtract cLR Clear Operand MULU Unsigned Multiply SWAP Swap Date Register Halves cue Compare, NBCD Negate Decimal with Extend TAS ‘Test and Set Operand OBce Test Condition, Decrement and NEG Neseee Thar ee Branch Noe ‘No Operation TRAPV | Trap on Overflow olvs Signed Divide NOT One's Complement TST Test oivu Untigned Divide OR Logical Or UNLK Uniink Table 3 Variations of Instruction Types aa Veration Deseription trarueton ] variation | Description

700 AOD Thea wove wove Move

ADDA | Ass ras MOVEA Move Addeess ‘00a ‘Add Quick Movea Move Quick Apo! | Ad immediate MOVE from SR | Move from Status Register | aoox ‘Add with Extend MOVE 10 SR | Move to Status Register rr) rr Logical And MOVE 10 CCR. | Move to Condition Coder No! ‘And Immediate MOVE USP __ | Move Uter Stack Pointer ANDI te. CCR | And Immediate to NEG Neoete ANDI 16S} And Inmedit to on OR Logical Or ont Or Immediate cme cwr | Compare ORI t0.CCR | Or Immediate to omen Compare Address Condition Codes \\omem | Compace Memory ORI 10 SR Or immediate to MPI ___| Compare immediate _ _ Status Register OR | EOR Exclusive Or ‘sus ‘suB Subtract | Eon Exclusive Or immediate SUBA Subtract Address EORI to CCR | Exclusive Or Immediate sue! Subtract Immediate | to Condition Codes susa Subtract Quick J EOR!toSR | Exclusive Or Immediate suex ‘Subtract with Extend i to Status Regier @HITACHI 922 Hitachi America, Ltd. © Hitachi Ptaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 .

a HD68000/HD68HCO000 hhc ® REGISTER DESCRIPTION AND DATA ORGANIZATION ADDRESS REGISTERS The following paragraphs describe the registers and data Each address register and the stack pointer is 32 bits wide organization of the 68000. and holds a full 32 bit address. Address registers do not support byte sized operands. Therefore, when an address register is used © OPERAND SIZE as a source operand, either the low order word or the entire Operand sizes are defined as follows: a byte equals 8 bits, long word operand is used depending upon the operation size. a word equals 16 bits, and a long word equals 32 bits. The When an address register is used as the destination operand, the operand size for each instruction is either explicitly encoded entire register is affected regardless of the operation size. If the in the instruction or implicitly defined by the instruction ‘operation size is word, any other operands are sign extended operation. Implict instructions support some subset of all three to 32 bits before the operation is performed. sizes. ® DATA ORGANIZATION IN MEMORY @ DATA ORGANIZATION IN REGISTERS Bytes are individually addressable with the high order byte The eight data registers support data operands of 1, 8, 16, having an even address the same as the word, as shown in ‘or 32 bits, The seven address’ registers together with the active Figure 10. The low order byte has an odd address that is one stack pointer support address operands of 32 bits. ‘count higher than the word address. Instructions and multibyte data are accessed only on word (even byte) boundaries. If a DATA REGISTERS long word datum is located at address n (n even), then the Each data register is 32 bits wide. Byte operands occupy second word of that datum is located at address n + 2. the low order 8 bits, word operands the low order 16 bits. and ‘The data types supported by the 68000 are: bit data, integer long word operands the entire 32 bits, The least significant bit data of 8, 16, or 32 bits, 32-bit addresses and binary coded is addressed as bit zero: the most significant bit is addressed decimal data. Each of these data types is put in memory, as as bit 31 shown in Figure 11. The numbers indicate the order in which ‘When a data register is used as cither a source of destination the data would be accessed from the processor. ‘operand, only the appropriate low-order portion is changed the remaining high-order portion is neither used nor changed. is 4 13 2 1 9 8 7 6 5 4 3 2 09001 [00007 byte 000008 aye FFEFFE Bye FFrEEE Figure 10 Word Organization in Memory @HITACHI Hitachi America, Ltd. # Hitachi Plaza 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300 923 .

vayte = Baits pos 5's 32 1 0 Invager Onta Oye eon is 4 9 2 1 0 9 8 7 6 a3 19

1 Word « 16 Bis

is 1312 1 10 9 8 7 s 4 3 2 1 0

1 Long Word = 22 Bits

is 4 2 1 9 8 7 6s 4 9 2 1 Oo 0 fase ish Order net a+ LongWord 0 === = = ener nnn ene m2 Low Order tse} 9° a -Long Word 1--= === 22-222 eee een =e 6 a7 “8 a0 = = LongWord 22= = = = 22-2 2 ween -- ee nv10 nent Address 1 address 32 Bis is 4 3 2 1 oe 7 6 § 4 39 2 Oo n [MSB High Order net =a addres 0— nn Ol m2 Low Order sal 2 m4 a8 a a6 ov ove 8 ee av10 nent SB Mon Significant Bi tSe 2 Coan Sgmiicane Bt ecimal Dota

2 Binary Coded Decimer Digits = 1 Byte

54 18 2 “ 10 n fas . a CS MSD= Mos Sgnitiant Dio USO = Laon Sniicant Dat Figure 11 Data Organization in Memory @HITACHI 924 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300 .

——— HD68000/HD68HCO000 REGISTER DIRECT MODES Date Register Direct These effective addressing modes specify that the operand The operand is in the data register specified by the effective is in one of the 16 multifunction registers. address register field. examre comments MPU MEMORY *EA=Dn soorroo| Saco | PE) sein tt coe Move 0, $1F00 2011 90011100 0000 wee i. Word Reg #0 eis a Snort a as Regster om. [3100] _ Move 00,8100 ow «2 treo] a Address Register Direct ‘The operand is in the address register specified by the effec- tive address register field. EXAMPLE COMMENTS seat an wou memory i aa | szoroo0]* 7254] achine Level Costing 011 9911_1100_1100 a | |e Word Abroluie —— tone Rares om aac | Reoser cows. + 2[ 0020 | Oweet MOWENG S7010% ome +4{ 1000] a as @HITACHI 926 Hitachi America, Ltd. # Hitachi Plaza 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300 .

EXAMPLE COMMENTS: seas An Pu MEMORY © Address Register Sign Extended:

1 Machine Lave Codon

KK -—— MOVE $201000, a4 (@oo0T34) ae i es ott om pnnt_son aa] a= Lone or acre egater — Breet om[__sa | Move s201000,aa OWL +2[__ 0020 om. +4[ 1000 | a J a MEMORY ADDRESS MODES Address Register Indirect ‘These effective addressing modes specify that the operand ‘The address of the operand is in the address register specified is in memory and provide the specific address of the operand. by the register field. The reference is classified as a data refer- ence with the exception of the jump and jump to subroutine instructions. EXAMPLE comments wu wewonv # EAs (An) K = 001000] 234] ee eee —— MOVE (40), 00 0011 0000_0001 a0 Wes | baw | Reger —— Direct om [210] eo a in MOVE (A0), 00 C4 Tndirect as Pd a @HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza # 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 + (415) 589-8300 927 .

——— HD68000/HD68HCO000 Address Register Indirect With Postincrement address register is the stack pointer and the operand size is ‘The address of the operand is in the address register specified byte, the address is incremented by two rather than one to by the register field. After the operand address is used, it is keep the stack pointer on a word boundary. The reference is incremented by one, two, or four depending upon whether classified as a data reference. the size of the operand is byte, word, or long word. If the EXAMPLE COMMENTS © A= (An): An ¢ Men weu MEMORY Were Asoo Address Repter woheees [~~ byeWord, or Byte Nord. or ro s100[ aera Long Word EEA mecine nt Ean olsen ——_J MOVE (AA) +, $2000 Cc = 0011 9001 _1101_1100 sooo[ are i ea a) Wows Word Absolute a Short Karan om [sie _| Increment MOVE (AA) +,$2000 omrz| zee a a Address Register indirect With Predecrement. register is the stack pointer and the operand size is byte, the The address of the operand is in the address register specified address is decremented by two rather than one to keep the by the register field. Before the operand address is used, it is stack pointer on a word boundary. The reference is classified decremented by one, two, or four depending upon whether asa data reference. the operand size is byte, word, or long word. If the address EXAMPLE COMMENTS tan Mean: €& = (An) meu MEMORY Where An Adare Heiter wierd oN {Bapending Whether Byte Wore. or (95000759) soore| 1234 Long Word) a sorool ‘© Machine Level Coding [D00000F E) J MOVE — (A3), $4000 Cc -— 11 90011110, 0918 $4000 [1234 =} arr -—~__J Move with — Wore Rowaite frei om| aves Foo +2[ 4000] MOVE — (A3),$4000 Ome 2) -_ a as @HITACHI 928 Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300 .

Address Register Indirect With Displacement register and the sign-extended 16-bit displacement integer in ‘This address mode requires one word of extension. The ad- the extension word. The reference is classified as a data refer- dress of the operand is the sum of the address in ‘the address ence with the exception of the jump to subroutine instructions. EXAMPLE COMMENTS # EAs An * die meu MEMORY Where An “= Pointer Register diz > 16-B1 Duplacerent # dys Displacement it Sign Extended (Jt Macnine Level Coxing a0 ‘$1100 / 2 MOVE $100(A0). $3000 0011 0011110 1 -=—~ eg Cc Sons | ea tO s9000[_ABco Wore mar Wors with —w. Displacement pd MOVE $1001A0),$3000 Gy [seg] apoasss +2[-_o100 | CALCULATION: OWL +2 ‘AO = 00001000 owt +4 {73000 ‘00001 100 —) Address Register Indirect With Index eight bits of the extension word, and the contents of the index ‘This address mode requires one word of extension. The register. The reference is classified as a data reference with the address of the operand is the sum of the address in the address exception of the jump and jump to subroutine instructions. register, the sign-extended displacement integer in the low order EXAMPLE COMMENTS SEA Ane Re ody meu MEMORY Where Ax —= Designated Index Register.

7 Tether Aare eter

08 srooo[ 2345 4, —a 8.81 Displacement (59907806) 00 © RX & de are Sign Extended LD) Saat ve wore or Lone Word (5007000) A0 es Long Word may be Designated with Rx.L ‘¢ Mechie Level Coding saseo[ 254 _ a Absolute Reg #0 Word Short tn 100 ApoRESS ow. +4[ 1000 | ain CALCULATION Cd om Word t ‘AO = 00002000 | jeg #0 ynstant Zeros: 80 = oooo260c “8 = 00000004 ——) ‘0000480 @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 929 .

a HD68000/HD68HCO000 HDGSOOOIIDEBHCOOD ‘The special address modes use the effective address register This address mode requires one word of extension. The ad- field to specify the special addressing mode instead of a register dress of the operand is the extension word. The 16-bit address number. is sign extended before it is used. The reference is classified as a data reference with the exception of the jump and jump to subroutine instructions. exaurce comments oem en Word neu memory Ties Were Son extended oT. $2000 — 01000110 10111000 $2000 02 [tw if aT) Nortanveion OE NoT.L $2000 ow. | 4608] examrie comments oem (Newt Word) neu memory 258i Wor Sion Extonced ie Move $1000, $2000 Cc ~~}, seoof ae 011 000111111000 E———_ae adam | Word Shon oo _—— Shor ow [sire] wove sion smo 40m | 8 a @®HITACHI 930 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 (415) 589-8300 .

Absolute Long Address first extension word; the low-order part of the address is the ‘This address mode requires two words of extension. The second extension word. The reference is classified as a data address of the operand is developed by the concatenation of reference with the exception of the jump and jump to sub- the extension words. The high-order part of the address is the routine instructions. ExaMPLe coMmeNTs sea Next Two Words) weu memory a. ec s014000 e100 0100 9111 “Pe we oT Instruction Long om [aa | ves so14000 ow. +2 [7 0001} owe +4 [4000] a a Program Counter With Displacement the extension word. The value in the program counter is the ad- This address mode requires one word of extension. The dress of the extension word. The reference is classified as a pro- address of the operand is the sum of the address in the program gram reference. counter and the sign-extended 16-bit displacement integer in EXAMPLE ‘COMMENTS seas cl td weu Memory 3 dee Son Extends

2 Sethe a Cong

WOVE (LABEL), 09 20 14 0000, 111010 + rieter Displacement s2002 [1000 | wore ect a MOVE (LABEL), 00 -—— aponens a eatcucarion: PS coaoago2 Ls Sr 4+ 00001000 < ager >s8002 | ABCD | @ HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 931

Program Counter With Index This address mode requires one word of extension. This address is the sum of the address in the program counter, the sign-extended displacement integer in the lower eight bits of the extension word, and the contents of the index register. The value in the program counter is the address of the extension word. This reference is classified as a program reference. EA= (PC) + (Rx) # du — iwore) Pc vatve | —Tonrueton — | | Extension Word L— 15 14 19 1211 10-9 pes a4 ° . cS Bra reviwer [wrfoTo ToT — oicenent intowr | Rene’: | rc +s. OIA Ons Rr =, Aas Rei = Bate Table Regiter Index Register Number oa W/L: Sign-extanted low order Word inteper Dested Ont8 pc dy oe Table in index Regier = © Pskatlon in Tabie | PC * ds long Word in Index Reiser = 1 EXAMPLE COMMENTS SEA (PC) (RK + ds eu memory ‘te Pe = Current Progam Counter Fix== Designed Indes Regater | wine ee esos aoe, (KKB Oo e000 [3038 gy Sng 9 2.8it Displacement saoo2| soo | ‘# Rx may be Word or Long Word 20601570 Cong Word i Designed with Rx. (Geeerera} a0 a mT eo <uasen> ES MOVE (LABEL) (A0), 00 Le-sgor2| oon 111011 C—O ore Index — al ——— ones MOVE (LABEL) (A0), D0 | al a ApoRess son|—= sae] aes ‘1 Oaplacement CALCULATIONS: | Register Fe = 00000002 Regater | Contant Zerot Ao = 099010%0 — Nome 9. = 00000010 goowonye a) x Length @HITACHI 932 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 :

a _ HD68000/HD68HC000 Immediate Data Extension Word ‘This address mode requires either one or two words of ex- tension depending on the size of the operation. Byte operation — operand is low order byte of extension 00000000) Byte word or Long word operation — operand is in the two extension words, high-order 16 bits are in the first extension word, 1 or 0 Jow-order 16 bits are in the second extension word. High Order oe dows a Le Word Aer co Ovect om XK 307c | Lid Cd EXAMPLE ‘COMMENTS: (00500054) 03 MOVEQ #$5A, 03 oon tks [Ld wos Zero Data [ Quick owe Tt td @HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 # (415) 589-8300 933 .

Condition Codes or Status Register A selected set of instructions may reference the status regis- ter by means of the effective address field. These are: ‘ANDI to CCR ANDI to SR EORI to CCR EORI to SR EXAMPLE COMMENTS: ORI teceR © EA = (Next Word) to MPU MEMORY © Note: This Example it » Privileged ORI to SR Inetruction MOVE 10 CCR MOVE 10 SR —— ‘¢ Machine Levat Coding MOVE from SR stozo| 010) MOVE $1020, SR Giase — 0100 0110 14111000 (ward) Short ow.[ “aera | move sio20,sn OWL 2 — as a © EFFECTIVE ADDRESS ENCODING SUMMARY stack pointer (SSP), the user stack pointer (USP), or the status Table 4 is a summary of the effective addressing modes dis- register (SR). cussed in the previous paragraphs. SYSTEM STACK ‘The system stack is used implicitly by many instructions; Table 4 Effective Address Encoding Summary user stacks and queues may be created and maintained through the addressing modes. Address register seven (A7) is the system Addressing Mode Mode Register stack pointer (SP). The system stack pointer is either the super- “Data Register Direct __| 000 [register number visor stack pointer (SSP) or the user stack pointer (USP), de- Address Register Direct 001 | register number Bending on the state of the S-bit in the status register. If the “Address Regier indirect {01 number it indicates supervisor state, SSP is the active system stack Address Register Indirect O10 _| register number pointer, and the USP cannot be referenced as an address re- Address Register Indirect with 914 | register number _—_—gister. If the S-bit indicates user state, the USP is the active __Postincrement — system stack pointer, and the SSP cannot be referenced. Each Address Register Indirect with | 109 | register number _#YStem tack fils from high memory to low memory. ' ister Indirect with | eat Aarrotaeeenet incirectwith 101 | register number SYSTEM STACK POINTERS ee —— User Stack Supervisor Steck Address Register Indirect with | 10 register number Ar AT TRowouteShot SSS Absolute Long . wm 001 | Program Counter with Displacement mm o10 | Program Counter with Index| 111 On use. | ssr . Immediate nt 100 ‘© Accessed when § = 0 © Accened whan S = 1 © PC is Stacked on © PC is Stacked on © IMPLICIT REFERENCE trerseare Supervor sian Some instructions make implicit reference to the program 1 Used for Exception counter (PC), the system stack pointer (SP), the supervisor * Increasing Addresses Processing ®HITACHI 934 Hitachi America, Ltd, » Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 # (415) 589-8300 :

a _ HD68000/HD68HC000 ‘The address mode SP @- creates a new item on the active system stack, and the address mode SP @+ deletes an item from low memory the active system stack. ‘The program counter is saved on the active system stack on subroutine calls, and restored from the active system stack on returns. On the other hand, both the program counter and the status register are saved on the supervisor stack during the processing of traps and interrupts. Thus, the correct execution Processing of {Penton tte behavior ‘of user code and user programs may use the user stack pointer oie mf me | In order to keep data on the system stack aligned properly, data entry on the stack is restricted so that data is always put high memory jin the stack on a word boundary. Thus byte data is pushed on ‘or pulled from the system stack in the high order half of the word; the lower half is unchanged. QUEUES User queues can be implemented and manipulated with the USER STACKS address register indirect with postincrement or predecrement ‘User stacks can be implemented and manipulated by employ- addressing modes. Using a pair of address registers (two of AO ing the address register indirect with postincrement and pre- through A6), the user may implement queues which are filled decrement addressing modes. Using an address register (on of either from high memory to low memory, or vice versa. Because ‘AO through A6), the user may implement stacks which are filled queues are pushed from one end and pulled from the other, two either from high memory to low memory, or vice versa. The _registers are used: the put and get pointers. important things to remember are ‘Queue growth from low to high memory is implemented with — using predecrement, the register is decremented before its ‘Aput@+ to put data into the queue, contents are used as the pointer into the stack, ‘Aget@+ to get data from the queue. — using postincrement, the register is incremented after its After a put operation, the put address register points to the contents are used as the pointer into the stack, next available space in the queue and the unchanged get address — byte data must be put on the stack in pairs when mixed register points to the next item to remove from the queue. with word or long data so that the stack will not get After a get operation, the get address register points (o the next misaligned when the data is retrieved. Word and long item to remove from the queue and the unchanged put address ‘accesses must be on word boundary (even) addresses. register points to the next available space in the queue. This is Stack growth from high to low memory is implemented with illustrated as: ‘An@- to push data on the stack, ‘An@+ to pull data from the stack. After eigher a push or a pull operation, register An points to low memory the last (top) item on the stack. This is illustrated as: | lon mary ene soe | woetnee | ps fi 4 ad eT coon wax wenn wo awnoy If the queue is to be implemented as a circular buffer. the address register should be checked and, if necessary, adjusted Stack growth from low to high memory is implemented with before the put or get operation is performed. The address regis- ‘An@+ to push data on the stack, ter is adjusted by subtracting the buffer length (in bytes). An@- to pull data from the stack. Queue growth from high to low memory is implemented with After either a push or a pull operation, register An points to ‘Aput@- to put data into the queue, the next available space on the stack. This is illustrated as Aget@ - to get data from the queue. After a put operation, the put address register points to the last item put in the queue, and the unchanged get address register points to the last item removed from the queue. After a get operation, the get address register points to the last item removed from the queue and the unchanged put address register points to the last item put in the queue. This is illustrated as: @HITACHI Hitachi America, Ltd. « Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 935 .

—. SSS HD68000/HD68HCO000 link stack (LINK), unlink stack (UNLK), and move quick ow memory (MOVEQ). Table S is a summary of the data movement put [moe Table 5 Data Movement Operations Instruction | Operand Size _| Operation exe Rx > Ry iN ‘An-+— (SP) a Lestat ree) ee a (Sra high memory MOVE 816,32 | (EA)s> EAd (EA) > An, Dn _MOvEM 16, 32 An, Dn-+ EA, If the queuc is to be implemented as a circular buffer. the MOVEP | 2 | one get or put operation should be performed first. and then the in Ei address register should be checked and. if necessary. adjusted Moveo [8 | #xxx>Dn The address register is adjusted by adding the buffer length PEA [32 ea +18?) (on bytes swap [32 | ontat:t6) = nit6:0) SINSTRUCTION SET SUMMARY UNLK | - | Cen The following paragraphs contain an overview of the form and structure of the 68000 instruction set. The instructions (Noes) form a set of tools that include all the machine functions to ssource —(_) = indirect with predecrement, perform the following operations: = daestinstion (1 += ingieeet with portinerement Data Movement {J +bit numbers # immediate data Integer Arithmetic " © INTEGER ARITHMETIC OPERATIONS Logie pote The arithmetic operations include the four basic operations Bit Manipulation of add (ADD), subtract (SUB), multiply (MUL), and divide Binary Coded Decimal (DIV) as well as arithmetic compare (CMP), clear (CLR), and Program Control negate (NEG). The add and subtract instructions are available System Control for both address and data operations, with data operations The complete range of instruction capabilities combined accepting all operand sizes. Address operations are limited with the flexible addressing modes described previously pro- to legal address size operands (16 or 32 bits). Data, address, vide a very flexible base for program development and memory compare operations are also available. The clear and negate instructions may be used on all sizes of data oper- © DATAMOVEMENT OPERATIONS ands. The basic method of data acquisition (transfer and storage) The multiply and divide operations are available for signed is provided by the move (MOVE) instruction. The move instruc- and unsigned operands using word multiply to produce a long tion and the effective addressing modes allow both address word product, and a long word dividend with word divisor to and data manipulation. Data move instructions allow byte, Produce a word quotien with a word remainder. word, and long word operands to be transferred from memory Multiprecision and mixed size arithmetic can be accomplish- to memory, memory to register, register to memory, and regis- ed ‘using a set of extended instructions. These instructions are. ter to memory, and register to register. Address move instruc- add extended (ADDX), subtract extended (SUBX), sign extend tions allow word and long word operand transfers and ensure (EXT), and negate binary with extend (NEGX). that only legal address manipulations are executed. In addition A test operand (TST) instruction that will set the condition to the general move instruction there are several special data codes as a result of a compare of the operand with zero is also movement instructions: move multiple registers (MOVEM), available. Test and set (TAS) is a synchronization instruction move peripheral data (MOVEP), exchange registers (EXG), useful in multiprocessor systems. Table 6 is a summary of load effective address (LEA), push effective address (PEA), the integer arithmetic operations. @ HITACHI 936 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 :

a HD68000/HD68HC000 Table 6 Integer Arithmetic Operations shift and rotate operations can be performed in either registers : or memory. Register shifts and rotates support all operand Instruction ‘Operation sizes and allow a shift count specified in the instruction of Br (EAI = De ‘one to eight bits. or 0 to 63 specified in a data register. apo teale bors EA Memory shifts and rotates are for word operands only and AN+ (EA) An allow only single-bit shifts or rotates. Table 8 is a summary Ox + Dy +X Dx of the shift and rotate operations. anox | Sata? | Sia Ps Tanta cr TEA) MPU Table 8 Shift and Rotate Operations On-(eA) vaslon - he Toavcton [operand Sie] Ooeraton area ers Divs | 32716 On={EA)= Da t ivy fae 16 | “OnHEAI=On A 8.16.32 co muis | texte =32_| “OnxlEA) = On usr a ——— MULU | 161692 | OnxiEAl>Dn = NEGX | 6,16.32 | 0-(EA)-X-EA SSSI R fons ——_ 16, 32 An - (EA) > An noxa es ce ‘suex 8. 16,32 1x) ~ — (Ay) ~ X= (Ax) TAS [e _|_ (A) -0, 1 EAl7) qt | 8.16.32 | (eA)-0 © BIT MANIPULATION OPERATIONS (NOTE) | 1 = bit number Bit manipulation operations are accomplished using the =) = indireet with predecrerent following instructions: bit test (BTST). bit test and set (BSET), (C+ = ingirect with postinerement bit test and clear (BCLR). and bit test and change (BCHG). # = immediate date Table 9 is a summary of the bit manipulation operations. (Bit 2 of the status register is Z.) @ LOGICAL OPERATIONS Logical operation instructions AND, OR. EOR, and NOT ure available for all sizes of integer data operands. A similar Table 9 Bit Manipulation Operations set of immediate instructions (ANDI, ORI, and EORI) provide ; Looman] these logical operations with all sizes of immediate data, Table jnstrustion. Operation is a summary of the logical operations. srt 8.32 = bit of (EA) =Z = it of (EA) 2s ser ce | Goitoes Table 7 Logical Operations BcLR 8.32 '~ bit of (EA) = 2; Instruction | _Operand Suze ‘Operation 7 ~ bit of (EA) = 2, | naTEA)~ On Bene 5.92 (- pit of (a) = bit of EA ano | 8.16.92 (EAI Do = EA Swe | (EAD a oxxx = EA Wore) " en ee On v (EA) = On © BINARY CODED DECIMAL OPERATIONS oR {816.92 | ‘ear en Multiprecision arithmetic operations on binary coded deci- Ce ae, T (ea mal numbers are accomplished using the following instructions: €or 8.16.92 | EAR Een add decimal with extend (ABCD), subtract decimal with extend ye a OS —_(ESOC), and negate decimal with extend (NBCD). Table 10 is 36. a summary of the binary coded decimal operations. TNOTET ~ = invert eee ee Table 10 Binary Coded Decimal Operations ‘A= logical AND @ = exclusive OR Tenvuction | operand Sae_| Operation @ SHIFT AND ROTATE OPERATIONS a lAxde += (Aye +X (Ax Shift operations in both directions are provided by the yeco re | Dry Ova -X = Ox arithmetic instructions ASR and ASL and logical shift instruc- 7 Arhie ~~ (Avie =X (Ax) tions LSR and LSL. The rotate instructions (with and without waco | 8 __—*| O- IEA), -X ~ EA extend) available are ROXR, ROXL, ROR, and ROL. All TTF indirect with predecrement @HITACHI Hitachi America, Ltd, Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 937

The conditional instructions provide setting and branching summarized in Table 12. Table 11. Program Control Operations EOR! to SR Logical EOR to status register

1 IF Offset = O then Word Offre is Used

RELATIVE, BACKWARD REFERENCE 8-BIT OFFSET EXAMPLE ‘COMMENTS: S Oftaet Contained in 8 LSB wpu MEMORY ot Op Word « Otter 4 Complement Number

2 Gino = Other ord

«Machine Lvs! Coding BNE NEXT ‘Oyo ojo 101 uw ~~ Bracch Oar $4000 [Next OF Code_] Lay a L—~ J [ese | $4020, eve next [td roa ee ae 7000 as a ———. RELATIVE, FORWARD REFERENCE, 16-B1T OFFSET EXAMPLE COMMENTS © Otten Next Word Meu Memory $B Oftet Fed =0 SE Complement Ort $ Machine Lrvel Coding Bcc NEXT (e=0) o110 0100 9000 oc meh s4o0e | e460 | uy ier s4002| i000] 5002 [Went OF Cove _| ce NEXT d= + 1000 002 | @ HITACHI Hitachi America, Ltd, © Hitachi Plaza # 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 939 .

" SIGNAL AND BUS OPERATION DESCRIPTION Read Mrite (RAV) The following paragraphs contain a brief description of the This signal defines the data bus transfer as a read or write input and output signals. A discussion of bus operation during cycle. The R/W signal also works in conjunction with the upper the various machine cycles and operations is also given and lower data strobes as explained in the following paragraph, (NOTE) The terms assertion and negation will be used extensively ‘Upper and Lower Data Strobes (UDS, LDS) sings Cone fo Sxaid confusion when dealing with # mixture These signals control the data on the data bus, as shown of “activelow™ and “activehigh" signals The term assert of th Stiertion i used to indicate that a Signal isactie or tue i) Table 13. When the R/W line is high, the processor will read dependent of whether that voltage is low or high. The term from the data bus as indicated. When the R/W line is low, the negate or negation is used to indicate that a signals inactive or processor will write to the data bus as shown false © SIGNAL DESCRIPTION Table 13 Data Strobe Control of Data Bus The input and output signals can be functionally organized _ into the groups shown in Figure 14. The following paragraphs wos RW Ds ~ Dis Do ~ Dy provide a brief description of the signals and also a reference High | High | ~ | No valid data) No valid data (if applicable) to other paragraphs that contain more detail — 1 Valid date bi lid data bits about the function being performed. Low i Low | High | Valig date bits | Valid data bits acnaieen eons mince Vee (2) cares | Lew 1h Valid data bits eet PSN ama, High | bo | High No atid ata on? ah ira) 0,0 Low | High High | VAIS! 9812 5 No valid data Low Low Low | Valid data bits | Valid data bits Rw B8~15 O~7 Fc, Be | Asynchronous i + + ~ 18 O~7 __ Processor 68000 Foe Bus High | Low | Low Valid data bits | Valid data bits sts TFC Meromrocenol 5 rAGe | Control tH o~7 on? | Valid data bits Valid data bits mm bos Low | High | Low oS B18" ‘06900 Pa: r . Control A ‘Controt appear on future devices. System { ee Te } Interrupt Comet \\ aa Conurol Data Transfer Acknowledge (DTACK) This input indicates that the data transfer is completed. Figure 14 Input and Output Signals When the provessor recognizes DTACK during # read cycle, . data is latched and the bus cycle terminated. When DTACK 1s recugnized during a write cycle, the bus cycle is terminated. ADDRESS BUS (A: through Azs} (Refer to ASYNCHRONOUS VERSUS SYNCHRONOUS OP- This 23-bit, unidirectional, three-state bus is capable of | ERATION) addressing 8 megawords of data. It provides the address for bus ‘operation during all cycles except interrupt cycles. During interrupt cycles, address lines Ar, Az, and Aa. Provide infor. BUS ARBITRATION CONTROL mation about what level interrupt is being serviced while address These three signals form a bus arbitration circuit to deter- lines Ae through Aas are ail set to a logic high ‘mine which device will be the bus master device. Bus Request (BR) DATA BUS (Do through Dis) This input is wire ORed with all other devices that could This 16-bit, bidirectional, threestate bus is the general be bus masters. This input indicates to the processor that Purpose data path. It can transfer and accept data in either some other device desires to become the bus master word or byte length. During an interrupt acknowledge cycle, an external device supplies the vector number on data lines Bus Grant (BG) Do through Dy. This output indicates to all other potential bus master ASYNCHRONOUS BUS CONTROL devices that the processor will release bus control at the end Asynchronous data transfer are handled using the following of the current bus cycle. control signals: address strobe, read/write, upper and lower data strobes, and data transfer acknowledge. These signals Bus Grand Acknowledge (BGACK) are explained in the following paragraphs. This input indicates that some other device has become the bus master. This signal cannot be asserted until the following Address Strobe (AS) four conditions are met. This signal indicates that there is a valid address on the (1) A Bus Grant has been received address bus. (2) Address Strobe is inactive which indicates that the microprocessor is not using the bus (3) Data Transfer Acknowledge is inactive which indicates @HITACHI 940 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 :

a HD68000/HD68HC000 that neither memory nor peripherals are using the bus Enable (E) (4) Bus Grant Acknowledge is inactive which indicates that This signal is the standard enable signal common to all no other device is still claiming bus mastership H1D6800 type peripheral devices. The period for this output is ten 68000 clock periods (six clocks low; four clocks high). En- INTERRUPT CONTROL (IPLy,iPL,, iPL;) able is generated by an internal ring counter which may come These input pins indicate the encoded priority lével of the up in any state (i.e., at power on, it is impossible to guarantee device requesting an interrupt. Level seven is the highest priority phase relationship of E to CLK), E is a free-running clock and while level zero indicates that no interrupts are requested. runs regardless of the state of the bus on the MPU. Level seven can not be masked, The least significant bit is given in TPLo and the most significant bit is contained in is Valid Peripheral Address (VPA) These lines must remain stable until the processor signals inter- This input indicates that the device or region addressed is a rupt acknowledge (FCo ~ FC2 are all high) to insure that the HD6800 family device and that data transfer should be syn- interrupt is recognized. chronized with the enable (E) signal. This input also indicates that the processor should use automatic vectoring for an inter- SYSTEM CONTROL rupt. Refer to INTERFACE WITH HD6800 PERIPHERALS. The system control inputs are used to either reset or halt ALS. the processor and to indicate to the processor that bus errors. have occurred. The three system control inputs are explained Valid Memory Address (VMA) in the following paragraphs. This output is used to indicate to HD6800 peripheral devices that there isa valid address on the address bus and the processor Bus Error (BERR) is synchronized to enable. This signal only responds to a valid "This input informs the processor that there is a problem —_peripheral address (VPA) input which indicates that the periph- with the cycle currently being executed. Problems may be a eral is a HD6800 family device. result of (1) Nonresponding devices PROCESSOR STATUS (FCo, FC,, FC2) (2) Interrupt vector number acquisition failure These function code outputs indicate the state (user or (3) Hilegal access request as determined by a memory man- supervisor) and the cycle type currently being executed, as agement unit shown in Table14, The information indicated by the function (4) Other application dependent errors. code outputs is valid whenever address strobe (AS) is active. The bus error signal interacts with the halt signal to deter- mine if exception processing should be performed or if the Table 14 Function Code Outputs current bus cycle should be retried. Refer to BUS ERROR AND HALT OPERATION paragraph Fe; | Fe, | FC. | Cycle Type for additional information about the interaction of the bus __ tow Low | Low | (Undefined, Reserved) error and halt signals. tow | Low | High User Data This bidirectional signal line acts to reset (initiate a system Low | High | High (Undefined, Reserved) initialization sequence) the processor in response to an external High | Low | Low | (Undefined, Reserved) reset signal, An internally generated reset (result of a RESET High | tow | High | _ Superviser Data instruction) causes all external devices to be reset and the = —jigh™ vom 1 ——Sanervisor Program imternal state of the processor is not affected. A total system —High | High _| Low | __Supervisor Program _ reset (processor and external devices) is the result of external High High | High Interrupt Acknowledge HALT and RESET signals applied at the same time. Refer to RESET OPERATION paragraph for additional information CLOCK (CLK) about reset operation. The clock input is a TTL-compatible signal that is internally buffered for development of the internal clocks needed by the Halt (HALT) processor. The clock input should not be gated off at any time, ‘When this bidirectional line is driven by an external device, and the clock signal must conform to minimum and maximum it will cause the processor to stop at the completion of the pulse width time, current bus cycle. When the processor has been halted using this input, all control signals are inactive and all three-state lines. SIGNAL. SUMMARY. ‘are put in their high-impedance state. Refer to BUS ERROR Table 15 is a summary of all the signals discussed in the [AND HALT OPERATION paragraph for additional information _previous paragraphs. ‘about the interaction between the halt and bus error signals. When the processor has stopped executing instructions, such asin a double bus fault condition, the hat lin is driven by the © BUS OPERATION, 1 signal and processor to indicate to external devices that the processor has The following paragraphs explain. control signal ant Os stopped. operation during data transfer operations, bus arbitration, bus error and halt conditions, and reset operation. HMCS6800 PERIPHERAL CONTROL ‘These control signals are used to allow the interfacing of syn- chronous HD6800 peripheral devices with the asynchronous 68000, These signals are explained in the following paragraphs. @HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 941

Signat Name Input/Output [os Race [on RRC ‘Address Bus output ves | ves Data Bus inputioutput _ [yes [ves ‘Address Strobe output no read Reed/Write RAT outa witli | 0 Upper and Lower Data Strobes THOS Tos output tow | yes | te Date Traneter Acknowledge [TACK input | low [no | no Bus Request [Rint tow nor Bus Grant ac “output Tow a Bus Grant Acknowledge BGACK input ___low [no | no {Interrupt Priority Level input low [no | n0 Bus Error [BERR Tint | tow [no [ne Reset input/output __ low ae Halt input/output _ low [_no* [| no” Enebie ee ee high [ro [no Valid Memory Address | VAT output tow ves [ne Valid Peripheral Addeess 2 = Function Code Output Fo, FCy, FC output _ high ves, | ne Clock CLK input high [no | 0 Power input [Tee inpat Ground [Ves inp * Open drain DATA TRANSFER OPERATIONS read cycle flow chart is given in Figure 16. Read cycle timing is Transfer of data between devices involve the following leads: given in Figure 17. Figure 18 details word and byte read cycle (1) Address Bus A, through A2y operations, Refer to these illustrations during the following (2) Data Bus Do through Dis detailed (3) Control Signals At state zero (SO) in the read cycle, the address bus (A, The address and data buses are separate parallel buses used through Azy) is in the high impedance state. A function code to transfer data using an asynchronous bus structure. In all is asserted on the function code output line (FCy through FC;). eycies, the bus master assumes responsibility for deskewing The read/write (R/W) signal is switched high to indicate a read all signals it issues at both the start and end of a cycle. In cycle. One half clock cycle later, at state 1, the address bus is addition, the bus master is responsible for deskewing the ac- released from the high impedance state. The function code knowledge and data signals from the slave device ‘outputs indicate which address space that this cycle will operate The following paragraphs explain the read, write, and read- on. modify-write cycles. The indivisible read-modify-write cycle In state 2, the address strobe (AS) is asserted to indicate that is the method used by the 68000 for interlocked multiprocessor _ there is a valid address on the address bus and the upper and communications. lower data strobe (UDS, LDS) is asserted as required. The mem- ory of peripheral device uses the address bus and the address Read Cycle strobe to determine if it has been selected. The selected device During a read cycle, the processor receives data from memo- _uses the read/write signal and the data strobe to place its infor- ry of a peripheral device. The processor reads bytes of data mation on the data bus. Concurrent with placing data on the in all cases. If the instruction specifies a word (or double word) _—_ data bus, the selected device asserts data transfer acknowledge operation, the processor reads both upper and tower bytes (TACK). simultaneously by asserting both upper and lower data strobes. Data transfer acknowledge must be present at the processor When the instruction specifies byte operation, the processor _at the start of state 5 or the processor will substitute wait states uses an internal Ao bit to determine which byte to read and _ for states $ and 6. State S starts the synchronization of the then issues the data strobe required for that byte. For bytes returning data transfer acknowledge. At the end of state 6 ‘operations, when the Ao bit equals zero, the upper data strobe (beginning of state 7) incoming data is latched into an internal is issued. When the Ao bit equals one, the lower data strobe is data bus holding register. issued, When the data is received, the processor correctly posi During state 7, address strobe and the upper and/or lower tions it internally data strobes are negated. The address bus is held valid through ‘A word read cycle flow chart is given in Figure 15. A byte state 7 to allow for static memory operation and signal skew. @ HITACHI 942 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 .

80 51 S2 $3 S4 85 $6 S7 SO SI S2 §3 S485 $6 S7 SO SI S753 SA 55 56 57 ox SUVS LS LS LL LS L$ Rae At | | xs TT ,- f~ — ws lS /—— aw 26-01, 26-0. FO > i i a, <i Ct “internal Signal Only fo == =~ Word Read ~~ -=f+--~ -Odd Byte Read- ~ ele -— Even Byte Read — a] Figure 18 Word and Byte Read Cycle Timing Diagram The read/write signal and the function code outputs also remain One half clock later, at state 1, the address bus is released valid through state 7 to ensure a correct transfer operation. The from the high impedance state. The function code outputs slave device keeps its data asserted until it detects the negation indicate which address space that this cycle will operate on. of either the address strobe or the upper and/or lower data In state 2, the address strobe (AS) is asserted to indicate strobe. The slave device must remove its data and data transfer that there is a valid address on the address bus. The memory acknowledge within one clock period of recognizing the nega- _or peripheral device uses the address bus and the address strobe tion of the address or data strobes. Note that the data bus might _to determine if it has been selected. During state 2, the read/ not become free and data transfer acknowledge might not be write signal is switched low to indicate a write cycle. When removed until state 0 or 1. external processor data bus buffers are required, the read/write When address strobe is negated, the slave device is released. _line provides sufficient directional control. Data is not asserted Note that a slave device must remain selected as long as address during this state to allow sufficient turn around time for ex- strobe is asserted to ensure the correct functioning of the read- ternal data buffers (if used). Data is asserted onto the data bus modify-write cycle during state 3. In state 4, the data strobes are asserted as required to indi- ; cate that the data bus is stable. The selected device uses the Write Cycle read/write signal and the data strobes to take its information During a wnite cycle. the processor sends data to memory from the data bus. The selected device asserts data transfer or a peripheral device, The processor writes bytes of data in seknowledge (DTACK) when it has successfully stored the date, all cases. If the instruction specifies a word operation, the pro- Data transfer acknowledge must be presen: at the procter cessor writes both bytes. When the instruction specifies 4 byt ay the start of state § or the processor will sbstitute Wan sree jperation. the processor uses an internal Ay bit to determine for states § and 6. State 8 ears the synchronization of the which byte to write and then issues the dats strobe required returning data transfer acknowledge for that byte. For byte operations, when the Ao bit equals zero, During state 7, address strobe and the upper and/or lower the upper data strobe is issued. When the Ao bit equals ome, garg strobes are negated, The addiess and deve beret are held the lower data strobe is asued. A word write cycle low chart ®Jak4 through state 7 to allow for static memo operttion and eee in Figure 1 socle pda hia yl ee JA signal skew. The read/write signal and the function code outputs details word and byte write cycle operation. Refer to these 20, ation The dave dette bee le dan agit sonster ee ane ary ia the wane avale, sha advess bus (A, #8etted until it detects the negation of ether the addres strobe , 2 ig oF the upper and/or lower data strobe. The slave devi asserted on the function code output line (FCo through FC2). after recognizing the negation of the address or data strobes. _ Note that the processor releases the data bus at the end of state (NOTE) Tre Lelie SEW) leral coral WU wot ete 2. PN; 7 but that data transfer acknowledge might not be removed pot driven untibatate 3. until state O or 1. When address strobe is negated, the slave device is released. @ HITACHI 944 Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 * (415) 589-8300

a HD68000/HD68HC000 aus MASTER stave BUSMASTER SLAVE ‘Adress Device ress Device 1) Place Function Code on Fx ~ FC: Asse Device 2) Place Adaret on A ~ Any 1) pee Function Cade on FCs = FC: 3) wert Adore Sivobe (8) 2 eon on Ay “ 4) Set RIW to Write ssert Address strobe (AS) Seen ot ~ 0, or By ~ Das t 2) amet Acca | Pag Batson Br ~ Oo Dy Dr acrdig 5) Place Data on De ~ 0, . "ue 6) Assert Upper Data Strobe (UDS) or Lower 8) Auert Upper Date Strobe (TDS) and ate Strobe (COS fbted on As) Inout Oats tnput Osta 1) Decode Address “on 1) Decode Address

3 Oecoge Acaeem 2 Store Dota on Dy ~ Ds 4 CDSs anetes

3 Anart Dats Tremter Acknawted _. Store Data on Dy ~ Dis if UDS is asserted \\OTACK) wedge 3) Assert Data Transfer Acknowledge (DTACR) Terminate Output Tanster , ‘Terminate Output Tanster Terminate Oviput Teansfer 3) Negate GDS and COS 1) Negate UBS and COS 3) Remove Dats tram Oy ~ Out 3 Marve Daa om Os ~Ds or Ds =D 4) Set RIM to Rand 4) Set RIW to Read . ° " Terminate Cycle Terminate Cycle 1) Negate TACK 1) Negate BTACR ‘Start Next Cycle ‘Start Next Cycle Figure 19 Word Write Cycle Flow Chart Figure 20 Byte Write Cycle Flow Chart S0 $1 s2 52 54 55 96 57 50 S1 52 S2 S455 56 57 50 S1 52 59 S455 86 S7 ox PLELE LL LLL LL LS SL on CD 3 CD CD op a es cy \\ { \\ { \\ f Oos \\ A — ma f- ios \\ / \\ { nw / \\ / \\ A \\ / orack OSC fT YC NY 2.-06 >—{ 0-0) 2&— internal Signal Only Jo = — = Word Write — -— =f — - Odd yte Write ~ - —=Le- — -Even Byte Write- ~ -->| Figure 21 Word and Byte Write Cycle Timing Diagram iagr @ HITACHI Hitachi America, Ltd, « Hitachi Ptaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94006-1819 « (415) 589-8300 945

Read-Modify Write Cycle that the data bus is stable. The selected device uses the read/ The read-modify-write cycle performs a read, modifies the _write signal and the data strobe to take its information from the data in the arithmetic-logic unit, and writes the data back tothe data bus. The selected device asserts data transfer acknowledge same address. In the 68000 this cycle is indivisible in that (DTACK) when it has successfully stored its data. the address strobe is asserted throughout the entire cycle. The Data transfer acknowledge must be present at the processor test and set (TAS) instruction uses this cycle to provide mean- at the start of state 17 or the processor will substitute wait ingful communication between processors in a multiple pro- states for states 17 and 18. State 17 starts the synchronization cessor environment. This instruction is the only instruction that of the returning data transfer acknowledge for the write portion uses the read-modify-write cycle and since the test and set in- of the cycle. The bus interface circuitry issues requests for struction only operates on bytes, all read-modify-write cycles subsequent internal cycles during state 18, are byte operations. A read-modify-write cycle flow chart is During state 19, address strobe and the upper or lower data given in Figure 22 and a timing diagram is given in Figure 23. strobe is negated. The address and data buses are held valid Refer to these illustrations during the following detailed discus- through state 19 to allow for static memory operation and - | . signal skew. The read/write signal and the function code outputs AAt state zero (SO) in the read-modify-write cycle, the address 55 remain valid through state 19 to ensure a correct tranefer bus (A: through A2s) is in the high impedance state. A function operation. The slave device keeps its data transfer acknowledge code is asserted on the function code output line (FCo through asserted until it detects the negation of either the address strobe FC,). The read/write (R/W) signal is switched high to indicate gy the upper or lower data strobe. The slave device must remove a read cycle. One half clock cycle later, at state 1) the address its data transfer acknowledge within once clock period after bus is released from the high impedance state. The function recognizing the negation of the address or data strobes, Note code outputs indicate which address space that this cycle will that the processor releases the data bus at the end of state 19 operate on. | | but that data transfer acknowledge might not be removed until In state 2, the address strobe (AS) is asserted to indicate that state Q or 1 When addrest strobe is negated the slave device is there is a valid address on the address bus and the upper oF released lower data strobe (UDS, LDS) is asserted as required. The mem- cory or peripheral device uses the address bus and the address strobe to determine if it has been selected. The selected device uses the read/write signal and the data strobe to place its infor- BUS ARBITRATION mation on the data bus. Concurrent with placing data on the Bus arbitration is a technique used by muster-type devices data bus, the selected device asserts data transfer acknowledge to request, be granted, and acknowledge bus mastership. In its ——(DTACK). simplest form, it consists of: Data transfer acknowledge must be present at the processor (1) Asserting a bus mastership request at the start of state 5 or the processor will substitute wait states (2) Receiving a grant that the bus is available at the end of for states 5 and 6. State 5 starts the synchronization of the the current cycle returning data transfer acknowledge. At the end of state 6 (3) Acknowledging that mastership has been assumed. (beginning of state 7) incoming data is latched into an internal Figure 24 is a flow chart showing the detail involved in a data bus holding register. request from a single device. Figure 25 is a timing diagram for During state 7, the upper or lower data strobe is negated. the same operations. This technique allows processing of bus The address bus, address strobe, read/write signal, and function _requests during data transfer cycles. code outputs remain as they were in preparation for the write The timing diagram shows that the bus request is negated portion of the cycle. The slave device keeps its data asserted at the time that an acknowledge is asserted. This type of oper- until it detects the negation of the upper or lower data strobe. ation would be true for a system consisting of the processor The slave device must remove its data and data transfer ac- and one device capable of bus mastership. In systems having knowledge within one clock period of recognizing the negation _a number of devices capable of bus mastership, the bus request of the data strobes. Internal modification of data may occur __line from each device is wire ORed to the processor. In this from state 8 to state 11. system, it is easy to see that there could be more than one bus (NOTE) The read/write signal remains high until state 14 to prevent bus Fequest being made, The timing diagram shows that the bus conflicts with the preceding read portion of the cycle andthe grant signal is negated a few clock cycles after the transition data bus is not asserted by the processor until state 15. of the acknowledge (BGACK) signal In state 14, the read/write signal is switched low to indicate However, if the bus requests are still pending, the provessor a write cycle, When external processor data bus buffers are will assert another bus grant within a few clock cycles after required, the read/write line provides sufficient directional it was negated. This additional assertion of bus grant allows control. Data is not asserted during this state to allow sufficient external arbitration circuitry to select the next bus master turn around time for external data buffers (if used). Data is before the current bus master has completed its requirements, asserted onto the data bus during state 15. The following paragraphs provide additional information about In state 16, the data strobe is asserted as required to indicate _the three steps in the arbitration process. @ HITACHI 946 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300

transfer acknowledge might not enter into this function. Gen- been met (see Figure 27). The input signal is sampled on the eral purpose devices would then be connected such that they falling edge of the clock and is valid internally after the next were only dependent on address strobe. When bus grant ac- _ falling edge. knowledge is issued the device is bus master until it negates As shown in Figure 26, input signals labeled R and A are bus grant acknowledge. Bus grant acknowledge should not be internally synchronized on the bus request and bus grant negated until after the bus cycle(s) is (are) completed. Bus acknowledge pins respectively. The bus grant output is lebeled mastership is terminated at the negation of bus grant acknowl G and the internal three-state control signal T. If T is true, the edge. address, data, function code line, and control buses are placed ‘The bus request from the granted device should be drop- in a high-impedance state when AS is negated. All signals are ped after bus grant acknowledge is asserted. If a bus request shown in positive logic (active high) regardless of their true is still pending, another bus grant will be asserted within a few active voltage level. clocks of the negation of bus grant. Refer to Bus Arbitration State changes (valid outputs) occur on the next rising edge Control section. Note that the processor does not perform after the internal signal is valid. any external bus cycles before it re-asserts bus grant. ‘A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in Figure 28. The bus arbitration BUS ARBITRATION CONTROL sequence while the bus is inactive (i... executing internal ‘The bus arbitration control unit in the 68000 is implemented ‘operations such as a multiply instruction) is shown in Figure 29. with a finite state machine. A state diagram of this machine is If a bus request is made at a time when the MPU has already shown in Figure 26. All asynchronous signals to the 68000 are begun a bus cycle but AS has not been asserted (bus state $0), synchronized before being used internally. This synchronization __BG will not be asserted on the next rising edge. Instead, BG will is accomplished in a maximum of one cycle of the system clock, be delayed until the second rising edge following it’s internal ‘assuming that the asynchronous input setup time (#47) has assertion. This sequence is shown in Figure 30. RA ( morn Spat Va External i ee : Seo So Set Rat “y cux . BR (External) xx ax yn a RA C7, A Figure 27 Timing Relationship of External Asynchronous Inputs to Internal Signals f= Bus Requert Internal {A= Bun Grene Acknowledge Internal G =u Grant $ = Thre State Contre o Bus Control Logies* x= bowt care + state machine will not chongo state if bus isin SO. Refer 10 BUS SRETRATION CONTROL tor aduitiont information 0+ Fea autor bus ol be peed nthe Bigh mpecance state iT it asserted and AS is negated, Figure 26 State Diagram of 68000 Bus Arbitration Unit @HITACHI Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 949

BG asserted Processor starts next bus cycle.

3 D*Ee Fr

BG asserted and bus three stated. Figure 28. Bus Arbitration with Bus inactive

RESET OPERATION registers are affected by the reset sequence The reset signal is a bidirectional signal that allows either the When a RESET instruction is executed, the processor drives processor or an external signal to reset the system. Figure 35 _the reset pin for 124 clock periods. In this case, the processor is a timing diagram for the reset operations. Both the halt and is trying to reset the rest of the system. Therefore, there is reset lines must be asserted to ensure total reset of the pro- no effect on the internal state of the processor. All of the cessor rocessor’s internal registers and the status register are un- When the reset and halt lines are driven by an external _ affected by the execution of a RESET instruction. All external Gevice, it is recognized as an entire system reset, including devices connected to the reset line should be reset at the com- the processor. The processor responds by reading the reset _letion of the RESET instruction, vector table entry (vector unumber zero, address $000000) Asserting the Reset and Halt pins for 10 clock cycles will and loads it into the supervisor stack pointer (SSP), Vector cause @ processor reset, except when Voc is initially applied table entry number one at address $000004 is read next and to the processor. In this case, an external reset must be applied loaded into the program counter. The processor initializes for 100 milliseconds. the status register to an interrupt level of seven. No other Plus 5 Volts~ a Vee feet > 100 Mutiseconds emf AES Ca bh—s ica eines rie ie le ee (woTes) 1) Internal start-up time 4) PC High rea in nace fu State Unknown: XXXXXX 2} SSP High aad in are PC Low en innare 11) Contot Signals ins SSP Low readin hee 6) First instruction fetchea here. ‘As Control Signals nace,” Figure 35 Reset Operation Timing Diagram THE RELATIONSHIP OF DTACK, SERR, ANO HALT (cases 6 and 7); HALT must be held at In order to properly control termination of a bus cycle for a east one cycle after BERR. Case 5 in- rerun or a bus error condition, DTACK, BERR, and HALT dicates BERR may precede HALT should be asserted and negated on the rising edge of the which allows fully asynchronous asser- 68000 clock. This will assure that when two signals are asserted tion. simultaneously, the required setup time (9#47) for both of them Table 16 details the resulting bus cycle termination under will be met during the same bus state. various combinations of control signal sequences. The nega- This, or some equivalent precaution, should be designed tion of these same control signals under several conditions is external to the 68000. Parameter #48 is intended to ensure this shown in Table 17 (DTACK is assumed to be negated normal- operation in a totally asynchronous system, and may be ignored ly in all cases; for best results, both DTACK ‘and BERR should if the above conditions are met. be negated when address strobe is negated.) The preferred bus cycle terminations, may be summarized Example A: A system uses a watch-dog timer to terminate as follows (case numbers refer to Table 16): accesses to un-populated address space, The timer asserts Normal Termination: DTACK occurs first (case 1). DTACK and BERR simultaneously after time-out. (case 4) Halt Termination: HALT is asserted at the same time or Example B: A system uses error detection on RAM con- before DTACK and BERR remains tents. Designer may (a) delay DTACK until data verified, and negated (cases 2 and 3), return ‘nd HALT simultaneously to rerun error cycle Bus Error Termination: BERR is asserted in lieu of, at the same (cae 6), or if valid, return DTACK; (b) delay DTACK until time, or before DTACK (case 4); BERR data verified. and return BERR at same time as DTACK if is negated at the same time or after _ data in error (case 4); (c) return DTACK prior to data verifica- DIACK. tion, as described in previous section. If data invalid, BERR is Re-Run Termination: HALT and BERR are asserted in lieu asserted (case 1) in next cycle. Error-handling software must of, at the same time, or before DTACK know how to recover error cycle. @HITACHI 954 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300

Table 16 OTACK, BERR, HALT Assertion Results Asserted on Rising | Case No. | Control Signal; Edge of State | Result | N N+2 \\DTACK A s 1 | BERR NA x Normal cycle terminate and continue. _watr | NA KO DTACK A s 2 | BERR NA | Xx Normal cycle terminate and halt. Continue when HALT removed. , DTACK NA A 3 | BERR NA | NA Normal cycle terminate and halt. Continue when HALT removed. {| HAUT _ AL Sf DTACK x x t 4 BERRA s Terminate and take bus error trap. _ HALT | NA NA DTACK NA x 5 BERA LA s Terminate and re-run. HALT + _NA a OTACK x x a 6 BERR A s Terminate and re-run when HALT removed. HALT A s DTACK x 7 BERR A Terminate and re-run when HALT removed. HALT s gens N' — The number of the curtent even bus state (e.9., $4, $6, et.) A Signal i asserted in this but state NA — Signal is not asserted in this state X= Don't care $= Signal was asserted in previous state and remains asserted in this state Table 17 BERR and HALT Negation Results Conditions of Negated on Rising Termination in| Control Signal Edge of State Results — Next Cycle Table A wwe] Bus Error pad 2 8 Takes bus error trap. Rerun BERR $7 INlegal sequence; usually traps to vector number 0. Rerun BERR . . Re-runs the bus cycle. Normal Eat ft oa May lengthen next cycle. ‘ASYNCHRO! HALT, NOUS VERSUS SYNCHRONOUS OPERATION cori; the BERR, or BERR and HALT, signal to abort or Asynchronous Operation re-run the bus cycle. To achieve clock frequency independence at a system level, The DTACK signal is allowed to be asserted before the data the 68000 can be used in an asynchronous manner. This from a slave device is valid on a read cycle. The length of entails using only the bus handshake lines (AS, UDS, LDS, time that DIACK may precede data is given as parameter #31 DTACK, BERR, HALT, and VPA) to contro} the data transfer. and it must be met in any asynchronous system to insure that Using this method, AS signals the start of a bus cycle and the valid data is latched into the processor. Notice that there is no data strobes are used as a condition for valid data on a write maximum time specified from the assertion of AS to the asser- cycle. The slave device (memory or peripheral) then responds by _ tion of DTACK. This is because the MPU will insert wait cycles placing the requested data on the data bus for a read cycle of one clock period each until DTACK is recognized. or latching data on a write cycle and asserting the data transfer ‘The BERK signal is allowed to be asserted after the DTACR acknowledge signal (DTACK) to terminate the bus cycle. If signal is asserted. BERR must be asserted within the time given no slave responds or the access is invalid, external control logic as parameter #48 after DTACK is asserted in any asynchronous @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 (415) 589-8300 955

system to insure proper operation. If this maximum delay time assumes that the system is unusable and halts. Only an external is violated, the processor may exhibit erratic behavior. reset can restart a halted processor. Note that a processor in the stopped state is not in the halted state, nor vice versa. Synchronous Operation To allow for those systems which use the system clock as a signal to generate DTACK and other asynchronous inputs, PROCESSING STATES the asynchronous input setup time is given as parameter #47. If this setup is met on an input, such as DTACK, the processor is INSTRUCTION guaranteed to recognize that signal on the next falling edge of NORMAL EXECUTION the system clock. However, the converse is not true — if the (INCLUDING STOP) input signal does not meet the setup time it is not guaranteed | . not to be recognized. In addition, if DTACK is recognized exception | rampgeres on a falling edge, valid data will be latched into the processor TRACING ETC. (on a read cycle) on the next falling edge provided that the data —-———— eee meets the setup time given as parameter #27. Given this, para- HALTED Double Bus FAULT meter #31 may be ignored. Note that if DTACK is asserted, TATED | bouste sus raver with the required setup time, before the falling edge of S4, no wait status will be incurred and the bus cycle will run at its maximum speed of four clock periods. In order to assure proper operation in a synchronous system © PRIVILEGE STATES when BERR is asserted after DTACK, BERR must meet the The processor operates in one of two states of privilege: setup time parameter #27A prior to the falling edge of the clock the “user state or the “supervisor” state. The privilege state one clock cycle after DTACK was recognized. This setup time determines which operations are legal, are used to choose is critical 10 proper operation, and the HD68000 may exhibit _ between the supervisor stack pointer and the user stack pointer erratic behavior if it is violated, in instruction references, and may be used by an external memory management device to control and translate accesses. (note) The privileges state is a mechanism for providing security 4 VPA and BERR in 4 computer system. Programs should access only their own ore falling he or Aree cence, savoted code und data areas, and ought to be restricted from accessing DTACK is sampled on every falling. edge of the clock information which they do not need and must not modify starting with $4 and data is latched on the falling edge of ane privilege mechanism provides security ‘by allowing S6 during a read. The bus cycle will then be terminated most programs to execute in user state. In this state, the ac in $7 except when BERR is asserted in the absence of cesses are controlled, and the effects on other parts of the DTACK, in which case it will terminate one clock cycle system are limited. The operating system executes in the super~ later in $9 visor state, has access to all resources, and performs the over- head tasks for the user state programs. = PROCESSING STATES SUPERVISOR STATE This section describes the actions the 68000 which are out- The supervisor state is the higher state of privilege. For side the normal processing associated with the execution of instruction execution, the supervisor state is determined by instructions. The functions of the bits in the supervisor portion _the S.bit of the status register, if the S-bit is asserted (high), of the status register are covered: the supervisor/user bit, the the processor is in the supervisor state. All instructions can be trace enable bit, and the processor interrupt priority mask. executed in the supervisor state. The bus cycles generated by Finally, the sequence of memory references and actions taken instructions executed in the supervisor state are classified as by the processor on exception conditions is detailed. supervisor references, While the processor is in the supervisor The 68000 is always in one of three processing states: privilege state, those instructions which use either the system normal, exception, or halted. The normal processing state is stack pointer implicitly or address register seven explicitly that associated with instruction execution: the memory tef- access the supervisor stack pointer. erences are to fetch instructions and operands. and to store All exception processing is done in the supervisor state, results. A special case of the normal state is the stopped state regardless of the setting of the S-bit. The bus cycles generated which the processor enters when a STOP instruction is exe- during exception processing are classified as supervisor refer- cuted. In this state, no further memory references are made ences. All stacking operations during exception processing use The exception processing state is associated with interrupts, the supervisor stack pointer. trap instructions, tracing and other exceptional conditions. The exception may be internally generated by an instruction USER STATE ‘or by an unusual condition arising during the execution of The user state is the lower state of privilege. For instruction an instruction, Externally, exception processing can be forced execution, the user state is determined by the S-bit of the status. by an interrupt. by a bus error, or by a reset. Exception process- register; if the S-bit is negated (low), the processor is executing ing is designed to provide an efficient context switch so that instructions in the user state. the processor may handle unusual conditions. Most instructions execute the same in user state as in the The halted processing state is an indication of catastrophic _ supervisor state. However, some instructions which have im- hardware failure. For example. if during the exception pro- portant system effects are made privileged. User programs cessing of a bus error another bus error occurs, the processor are not permitted to execute the STOP instruction, or the @ HITACHI 956 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

RESET instruction. To ensure that a user program cannot © EXCEPTION PROCESSING enter the supervisor state except in a controlled manner, the Before discussing the details of interrupts, traps, and tracing, instructions which modify the whole status register are privi a general description of exception processing is in order. The leged. To aid in debugging programs which are to be used as processing of an exception occurs in four steps, with variations operating systems, the move to user stack pointer (MOVE for different exception causes. During the first step, a tem- to USP) and move from user stack pointer (MOVE from USP) porary copy of the status register is made, and the status register instructions are also privileged. is set for exception processing. In the second step the exception ‘The bus cycles generated by an instruction executed in vector is determined, and the third step is the saving of the user state are classified as user state references. This allows current processor context. In the fourth step a new context is an external memory management device to translate the ad- obtained, and the processor switches to instruction processing. dress and to control access to protected portions of the address space. While the processor is in the user privilege state, those EXCEPTION VECTORS instructions which use either the system stack pointer im- Exception vectors are memory locations from which the plicitly, or address register seven explicitly, access the use stack processor fetches the address of a routine which will handle pointer. that exception. All exception vectors are two words in length (Figure 36), except for the reset vector, which is four words. PRIVILEGE STATE CHANGES All exception vectors lie in the supervisor data space, except ‘Once the processor is in the user state and executing instruc for the reset vector which is in the supervisor program space tions, only exception processing can change the privilege state. A vector number is an eight-bit number which, when multiplied During exception processing, the current setting of the Sit by four, gives the address of an exception vector. Vector num of the status register is saved and the Sit is asserted, putting bers are generated internally or externally depending on the the processing in the supervisor state. Therefore, when instruc- cause of the exception. In the case of interrupts, during the tion execution resumes at the address specified to process the _ interrupt acknowledge bus cycle. a peripheral provides an 8:bit exception, the processor is in the supervisor privilege state vector number (Figure 37) to the processor on data bus lines Do through Dz. The processor translates the vector number into a full 24-bit address, as shown in Figure 38, The memory layout USER/SUPERVISOR MODES for exception vectors is given in Table 19. ‘As shown in Table 19,the memory layout is 512 words Re en PROCESSING long (1024 bytes). It starts at address 0 and proceeds through address 1023. This provides 255 unique vectors; some of these are reserved for TRAPS and other system functions. Of the 285, there are 192 reserved for user interrupt vectors. However, super there is no protection on the first 64 entries, so user interrupt at vectors may overlap at the discretion of the systems designer. KINDS OF EXCEPTIONS . Exceptions can be generated by either internal or external TRANSITION MAY BE MADE BY: causes, The externally generated exceptions are the interrupts ATE; MOVE, ANDI, EOR! TO STATUS WORD Sd the bus error and reset requests. The interrupts are requests from peripheral devices for processor action while the bus error and reset inputs are used for access control and processor REFERENCE CLASSIFICATION restart. The internally generated exceptions come from instruc- ‘When the processor makes a reference, it classifies the kind tions, or from address error or tracing. The trap (TRAP), trap of reference being made, using the encoding on the three func- on overflow (TRAPV), check register against bounds (CHK) tion code output ines. This allows external translation of ad- and divide (DIV) instructions all can generate exceptions as dresses, control of access, and differentiation of special pro- part of their instruction execution. In addition, illegal instruc- cessor states, such as interrupt acknowledge. Table 18 lists the tions, word fetches from odd addresses and privilege violations classification of references. cause exceptions. Tracing behaves like a very high priority, internally generated interrupt after each instruction execution. Table 18 Reference Classification EXCEPTION PROCESSING SEQUENCE Function Code Output Reterence Class Exception processing occurs in four identifiable steps. In FC, ie the first step, an internal copy is made of the status register. After the copy is made, the S-bit is asserted, putting the pro- of 0 {oT Wrassignes) ‘cessor into the supervisor privilege state. Also, the T-bit is o [| o | 1 | User date negated which will allow the exception handler to execute o {| t | 0 | User Program unhindered by tracing. For the reset and interrupt exceptions, Oo [| 1 | Wnassigned) the interrupt priority mask is also updated.

7 In the second step, the vector number of the exception is

1 [0 [0 [Unassigned determined. For interrupts, the vector number is obtained by 7 {| 0 | 1 | Supervisor Data a processor fetch, classified as an interrupt acknowledge. For 1 [1 | 0 | Supervisor Program all other exceptions, internal logic provides the vector number. This vector number is then used to generate the address of

1 TT] tnerrupt Accnowiesee _ the exception vector

MULTIPLE EXCEPTIONS RECOGNITION TIMES OF EXCEPTIONS, These paragraphs describe the processing which occurs HALT, AND BUS ARBITRATION when multiple exceptions arise simultaneously. Exceptions can be grouped according to their occurrence and priority. The END OF # CLOCK CYCLE Group 0 exceptions are reset, bus error, and address error. eno or A Bus CYCLE These exceptions cause the instruction currently being executed "ADDRESS ERROR to be aborted, and the exeception processing to commence BUS ERROR : as the privil illegal instruc- tions. These exceptions allow the current instruction to execute ENO OE A NENS ton ON CVE to completion, but preempt the execution of the next instruc INTERRUPT EXCEPTIONS tion by forcing exception processing to occur (privilege viola- Hee tere tions and illegal instructions are detected when they are the PRIVILEGE VIOLATION next instruction to be executed). The Group 2 exceptions WITHIN AN INSTRUCTION CYCLE ‘occur as part of the normal processing of instructions. The TRAP, TRAP. TRAP, TRAPV, CHK, and zero divide exceptions are in this cue ZERO DIVIDE group. For these exceptions. the normal execution of an instruc- tion may lead to exception processing, Group 0 exceptions have highest priority, while Group 2 ‘exceptions have lowest priority. Within Group 0, reset has © EXCEPTION PROCESSING DETAILED DISCUSSION highest priority, followed by address error and then bus error. Exceptions have a number of sources, and each exception Within Group 1, trace has priority over external interrupts, has processing which is peculiar to it. The following paragraphs which in turn takes priority over illegal instruction and privi- detail the sources of exceptions, how each arises, and how each lege violation. Since only one instruction can be executed at is processed a time, there is no priority relation within Group 2 The priority relation between two exceptions determines RESET which is taken, or taken first, if the conditions for both arise The reset input provides the highest exception level. The simultaneously. Therefore, if a bus error occurs during a TRAP processing of the reset signal is designed for system initiation, instruction, the bus error takes precedence, and the TRAP and recovery from catastrophic failure. Any processing in pro- instruction. processing is aborted. In another example, if an gress.at the time of the reset is aborted and cannot be recovered interrupt request occurs during the execution of an instruction The processor is forced into the supervisor state, and the trace while the T-bit is asserted, the trace exception has priority, state is forced off. The processor interrupt priority mask is set and is processed first. Before instruction processing resumes, at level seven. The vector number is internally generated to however, the interrupt exception is also processed, and instruc- reference the reset exception vector at location 0 in the super- tion processing commences finally in the interrupt handler visor program space. Because no assumptions can be made about routine. A summary of exception grouping and priority is given the validity of register contents, in particular the supervisor in Table 20 stack pointer, neither the program counter nor the status register is saved. The address contained in the first two words of the reset exception vector is fetched as the initial supervisor Table 20 Exception Grouping and Priority stack pointer, and the address in the last two words of the reset exception vector is fetched as the initial program counter. Group |_Exceotion | Processing Finally, instruction execution is started at the address in the | Reset ception processing begin program counter. The power-up/restart code should be pointed 0 | Adaress Error | CThintwo cock eves, to by the inital program counter. —__| Bus Error_ — a The RESET instruction does not cause loading of the reset Trace vector, but does assert the reset line to reset external devices 1 | Interrupt Exception processing begins This allows the software to reset the system to a known state | tiege! before the next instruction and then continue processing with the next instruction. rivilege 2 lone APY Exception processing is started by SH ide | ofmal instruction execution @ HITACHI 960 Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300

oo, EG BOOOIDGBECOOO Mask Bit +7 Fatch Baars. ves Double Vector No.0 Steck Pornter Le | Error or Gus Eror Vector No. Soe ere Error or No No Figure 41 Reset Exception Processing INTERRUPTS but are made pending. Pending interrupts are detected between Seven levels of interrupt priorities are provided. Devices instruction executions. If the priority of the pending interrupt may be chained externally within interrupt priority levels, is lower than or equal to the current processor priority, exe- allowing an unlimited number of peripheral devices to inter- cution continues with the next instruction and the interrupt rupt the processor. Interrupt priority levels are numbered exception processing is postponed. (The recognition of level from one to seven, with level seven being the highest priority. seven is slightly different, as explained in a following paragraph.) The status register contains a three-bit mask which indicates the If the priority of the pending interrupt is greater than the current processor priority, and interrupts are inhibited for current processor priority, the exception processing sequence all priority levels less than or equal to the current processor _is started. First a copy of the status register is saved, and the priority. privilege state is set to supervisor, tracing is suppressed, and ‘An interrupt request is made to the processor by encoding the processor priority level is set to the level of the interrupt the interrupt request level on the interrupt request lines; a being acknowledged. The processor fetches the vector number zero indicates no interrupt request. Interrupt requests arriving from the interrupting device, classifying the reference as an at the processor do not force immediate exception processing, interrupt acknowledge and displaying the level number of @HITACHI Hitachi America, Ltd, « Hitachi Ptaza © 2000 Sierra Point Pkwy, » Brisbane, CA 94005-1819 » (415) 589-8300 961 ;

Figure 44. Interrupt Exception Timing Sequence may still be caused by the level comparison if the request level instructions in software. processor then proceeds with the usual exception processing. instructions while in the user state will cause an exception. normal behavior is trapping. or a subscript out of bounds. gram under test. Hitachi America, Ltd. « Hitachi Plaza # 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 (415) 589-8300 963 .

error, or address error exception. If the instruction is indeed ex- more detailed. To save more of this context, additional infor- ecuted and an interrupt is pending on completion, the trace mation is saved on the supervisor stack. The program counter exception is processed before the interrupt exception. If, during _and the copy of the status register are of course saved. The value the execution of the instruction, an exception is forced by that __saved for the program counter is advanced by some amount, instruction, the forced exception is processed before the trace one to five words beyond the address of the first word of the exception. instruction which made the reference causing the bus error. If ‘As an extreme illustration of the above rules, consider the _the bus error occurred during the fetch of the next instruction, arrival of an interrupt during the execution of a TRAP instruc- the saved program counter has a value in the vicinity of the tion while tracing is enabled. First the trap exception is pro- current instruction, even if the current instruction is a branch, cessed, then the trace exception, and finally the interrupt ex- a jump, or a return instruction. Besides the usual information, ception. Instruction execution resumes in the interrupt handler _the processor saves its internal copy of the first word of the routine instruction being processed, and the address which was being accessed by the aborted bus cycle. Specific information about iete1 TRACE MODE the access is also saved: whether it was a read or a write, wheth- ‘er the processor was processing an instruction or not, and the STATUS REGISTER. classification displayed on the function code outputs when the bus error occurred. The processor is processing an instruc- tion if it is in the normal state or processing a Group 2 excep- tion; the processor is not processing an instruction if it is pro- ASAE casings Grovp O ort Greup | ekepton Pyar as dusters how this information is organized on the supervisor stack. RETURN TO Although this information is not sufficient in general to effect EXecUTE full recovery from the bus error, it does allow software diag- Me hucTION nosis. Finally, the processor commences instruction processing at the address contained in the vector. It is the responsibility PRomvecrorTaece | PROGRAM Shane rror handler routine to clean up the stack and determine If a bus error occurs during the exception processing for a 1. HH, upon completion of an insteuetion, T = 1 bus error, address error, or reset, the processor is halted, and 96 to wace exception processing all processing cases. This simplifies the detection of catastrophic 2. Execute race exception sequence system failure, since the processor removes itself from the Sree Rothe ossine, execute system rather than destroy all memory contents. Only the ‘etuen from exception (RTE! RES pin can restart a halted processor. ADDRESS ERROR BUS ERROR ‘Address error exceptions occur when the processor attempts Bus error exceptions occur when the external logic requests. to access a word or a long word operand or an instruction at that a bus error be processed by an exception. The current bus. an odd address. The effect is much like an internally generated cycle which the processor is making is then aborted. Whether bus error, so that the bus cycle is aborted, and the processor the processor was doing instruction or exception processing, ceases whatever processing it is currently doing and begins that processing is terminated, and the processor immediately exception processing. After exception processing commences, begins exception processing. the sequence is the same as that for bus error including the Exception processing for bus error follows the usual se- information that is stacked, except that the vector number quence of steps. The status register is copied, the supervisor refers to the address error vector instead. Likewise, if an address state is entered, and the trace state is turned off. The vector error oceurs during the exception processing for a bus error, number is generated to refer to the bus error vector. Since the address error, or reset, the processor is halted. As shown in Processor was not between instructions when the bus error Figure 46, an address error will execute a short bus cycle follow- exception request was made, the context of the processor is ed by exception processing. @ HITACHI 964 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 © (415) 589-8300 .

Do ~D» lor Ds ~ Dis? _ ee CT ‘Decode fr 8800 pan Address en b—a a B eS 68000 rR woeeeo Devices vA Ss a Figure 47 Connection of HD6800 Peripherals the read/write (R/W) signal is switched to low (write) during PROCESSOR SLAVE state 2. One half clock later, in state 3, the write data is placed Initiate Cycle con the data bus, and in state 4 the data strobes are issued to 1) The procestr starts 2 normal Read or indicate valid data on the data bus. The processor now inserts Write cycle wait states until it recognizes the assertion of VPA. ‘The VPA input signals the processor that the address on the bus is the address of an HD6800 device (or an area reserved for peti Hes00 Cycle H1D6800 devices) and that the bus should conform to the ¢, er ee LE here transfer characteristics of the HD6800 bus. Valid peripheral asec (UPR) address is derived by decoding the address bus, conditioned by address strobe. Chip select for the HD6800 peripherals should be derived by decoding the address bus conditioned by VMA. After the recognition of VPA, the processor assures that the Enable (E) is low, by waiting if necessary, and subsequently Synchronize With Enable asserts VMA. Valid memory address is then used as part of the 1) The procestor monitors Enable (E) until its chip select equation of the peripheral. This ensures that the tow (Phase 1) HD6800 peripherals are selected and deselected at the correct, 21 Te erpeessor asserts Valid Memory Aagress time. The peripheral now runs in cycle during the high portion of the E signal. Figures 49 and 50 depict the best and worst case HDD6800 cycle timing. This cycle length is dependent strictly upon when VPA is asserted in relationship to the E clock. dependent strictly upon when VPA is asserted in relationship Transter Data, to the E clock. 1) The peripheral waits until E i active and If we assume that external circuitry asserts VPA as soon as then transfers the date possible after the assertion of AS, then VPA will be recognized as being asserted on the falling edge of $4, In this case, no “extra” wait cycles will be inserted prior to the recognition of VPA asserted and only the wait cycles inserted to synchronize with the E clock will determine the total length of the cycle. ‘Terminate Cycle, In any case. the synchronization delay will be some integral y Fens cree me gees anu gone a . number of clock cycles within the following two extremes: fw ineernaity) 1. Best Case — VPA is recognized as being asserted on the 21 The procestor negates VA falling edge three clock cycles before E rises (or three 13) The procestor negates AS, UDS, ond COS clock cycles after E falls). 2. Worst Case -- VPA is recognized as being asserted on the falling edge two clock cycles before E rises(or four clock cycles after E falls) Start Next Cycle During a read cycle, the processor latches the peripheral Sen Ment Cycle data in state 6. For all cycles, the processor negates the address and data strobes one half clock cycle later in state 7, and the Enable signal goes low at this time. Another half clock later, Figure 48 HD6800 Interface Flow Chart the address bus is put in the high-impedance state. During a write cycle, the data bus is put in the high-impedance state @HITACHI 966 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 .

a HD68000/HD68HCO00 i a i es i _ oe Te MT =a 2 § HL Ears 8 ee ——— & pS 4 g im | A i LJ Ty z [a Sao i EE ed 8 bet & I cy ile Tey EH dA mo UL i ie: Li | AN ee q | ny @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 369 .

© CONDITION CODE REGISTER NOTATION X (extend) transparent to data movement. When affect- In the instruction set details, the description of the effect on ed, it is set the same as the C-bit. the condition codes is given in the following form: ‘The notational convention that appears in the representation Condition Codes: x nN oz vic of the condition code registers is: CLIII] ‘* set according to the result of the operation ‘Where — not affected by the operation N (negative) set if the most significant bit of the result 0 cleared is set. Cleared otherwise. 1 set Z (zero) set if the result equals zero. Cleared otherwise. U undefined after the operation V (overflow) set if there was an arithmetic overflow. This implies that the result is not representable ®@ CONDITION CODE COMPUTATION in the operand size. Cleared otherwise Most operations take a source operand and a destination C (carry) ‘set if a carry is generated out of the most ‘operand, compute, and store the result in the destination significant bit of the operands for an addition. location. Unary operations take a destination operand, com- Also set if a borrow is generated in a subtrac- pute, and store the result in the destination location. Table 22 tion. Cleared otherwise. details how each instruction sets the condition codes. Table 22 Condition Code Computations Operon [x Tw Tz Tv fe | Special Definition aco = Decimal Ca eRe "ADD, ADDI. Vem: Om: Rm» Sa Om: Rm Fae ‘ADOX “Te ? Ve Sm+ Om- Rm + Sm- Bm + Rm i 28RD Ri: me Sm- Am “AND. ANDI, - |) * 0 €0R-EOR!. | Moved, Move. On.ont | eta ext. NOT. TAS. TST ee sue, subi ag VoSR: Oa: fin Sm: Bm Am aa Oe a ec ‘suex Te | V= Sm Dm: Am Sm: Om> Rm EISDLBR Le! Bm sm: fim _ 2=Z- Rim: ..- AO CP, = VSR: Om: Ri +Sm: BR: Am MPM ("| C= Sm: Dm+ Rm: Bm+ Sms Am Divs, DIVU -{* [| 0 | V= Division Overtiow wuts. muwo |) - {= oe fo | a 2c, NBCO © = Decal Boro NEG ‘ I V=Om- Rm,C=Om+ Rm Necx oi Y= Bm Rm: C= bm + Am Z=2- Fim: = RO a BIST, CHG, rts 2205 mee [-T- ii | a ASL . ? V=Dm = (ny +. Oma) + DM + (Om.r ++ Omar) ASL =O) Te SL, ROXL [to] = Omae UR) | | Se ROXL (r= 0) =) cx oo Tro. set fe] Colmar _—— TAS. LSR, ROXR eo, ‘ASR. LSR (r =O) 4 of] ~ ROKR =O ex nonveo [-j~t*lele Theta * Gent Com n= See apron mont nica © Gravina xe m= Dennen cowed ran nant ¥ Cine te Seca Deon Ahm Fin= Renn ot mon eon se Pam batseren

7 Line

© CONDITIONAL TESTS 1, the condition succeeds, or is true. If the formula evaluates to Table 23 lists the condition names, encodings, and tests 0, the condition is unsuccessful, or false. For example, the T for the conditional branch and set instructions. The test associ- condition always succeeds, while the EQ condition succeeds ated with each condition is a logical formula based on the only if the Z bit is currently set in the condition codes. current state of the condition codes. If this formula evaluates to Table 23 Conditional Tests Mnemonic [Condition [Encoding | Test —t | we T0000 F | fase Toor Hi | high Toto ts C+z CS | carry set or | ic EQ equal ony z ve v vs overflow set 1001 Vv PL | plus. 1010 N ce | greater orequal | 1100 Nevin V, tT less than 101 | ON: V+NeV GT _weaterthan | 1110 N-V-Z+N-V-Z LE Jess or equal wit Z+N:V+Nev "= INSTRUCTION SET memory or data alterable. The former refers to those address- The following paragraphs provide information about the ing modes which are both alterable and memory addresses, and addressing categories and instruction set of the 68000. the latter refers to addressing modes which are both data and alterable. @ ADDRESSING CATEGORIES Effective address modes may be categorized by the ways ® INSTRUCTION PRE-FETCH in which they may used. The following classifications will The 68000 uses a 2-word tightly-coupled instruction prefetch be used in the instruction definitions. mechanism to enhance performance. This mechanism is described Data If an effective address mode may be used to refer in terms of the microcode operations involved. If the execution to data operands, it is considered a data address- of an instruction is defined to begin when the microroutine for ing effective address mode. that instruction is entered, some features of the prefetch Memory If an effective address mode may be used torrefer mechanism can be described. to memory operands, it is considered a memory 1) When execution of an instruction begins, the operation addressing effective address mode. word and the word following have already been fetched. Alterable If an effective address mode may be used to refer The operation word is in the instruction decoder. to alterable (writeable) operands, it is considered 2) In the case of multi-word instructions, as each addi- an alterable addressing effective address mode. tional word of the instruction is used internally, a fetch Control If an effective address mode may be used to refer is made to the instruction stream to replace it. to memory operands without an associated size, it 3) The last fetch from the instruction stream is made when is considered a control addressing effective address the operation word is discarded and decoding is started mode. on the next instruction. Table 24 shows the various categories to which each of the 4) If the instruction is a single-word instruction causing a effective address modes belong. Table 25 is the instruction set branch, the second word is not used. But because this summary. word is fetched by the preceding instruction, it ia im- The status register addressing mode is not permitted unless possible to avoid this superfluous fetch. In the case of it is explicitly mentioned as a legal addressing mode. an interrupt or trace exception, both words are not used. These categories may be combined so that additional, more 5) The program counter usually points to the last word restrictive, classifications may be defined. For example, the fetched from the instruction stream. instruction descriptions use such classifications as alterable @HITACHI 972 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 * (415) 589-8300 .

Table 24 Effective Addressing Mode Categories Effective Addressing Categories jn Modes [Memory | Control | Alterable On 000 | register number | = = x An 001 register number - - - x Ane 010 | register number | x x x x An@+ on register number x x - x An@ - 100 register number x x - x An@(d) 101 register number x x x } x An@(d, ix) register number x x x x ox. We 000 x x x x rook 001 x x | x | x ced) 010 x x x | = PCO, ix} on x x x - HxXX 100 x x - - ‘The following example illustrates many of the features of instruction prefetch. The contents of memory are assumed to be as illustrated in Figure 55 one DEFINE RESTART VECTOR oc.t—_INISSP INITIAL SYSTEM STACK POINTER OC\\L RESTART RESTART SYSTEM ENTRY POINT ORG —INTVECTOR DEFINE AN INTERRUPT VECTOR Dc.L__INTHANOLER HANOLER ADDRESS FOR THIS VECTOR ons SYSTEM RESTART CODE RESTART Nor NO OPERATION EXAMPLE BRAS LABEL SHORT BRANCH ADD.W 00,01 {ADD REGISTER TO REGISTER Laset SUB.W —_DISPIAO), At SUBTRACT REGISTER INDIRECT WITH OFFSET cMP.W 02,03 COMPARE REGISTER TO REGISTER SGE8 07 See TO REGISTER INTHANDLER: MOVE. LONGADAI, LONGADR2 MOVE WORD FROM AND TO LONG ADDRESS NOP NO OPERATION SWAP.W REGISTER SWAP Figure 55 Instruction Prefetch Example, Memory Contents The sequence we shall illustrate consists of the power-up The order of operations described within each microroutine is reset, the execution of NOP, BRA, SUB, the taking of an not exact, but is intended for illustrative purpose only. interrupt, and the execution of the MOVE.W xxx. to yyy.L. @HITACHI Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 89-8300 973

Er PRR em emPe Pree etmmmm inset i i : f | ® ES Peer pet esate a _ OniTach ; oe

HD68000/HD68HCO00 _ __ SET beer er ee bere ad — [SL BP AM merece retest ole Senko ae} (Hatpstetainerteryenayy Hf | sommes. (sc @ HITACHI 976 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300

AE MUARIMHEHREERERSHRSIBEIEEE S| = RBar ER POIATTEHITRI RMT HT HET TES io PHT TEL PET BEET SRPRRR EC TCTECTI ESTP beereree TLL Lea eerie | peso) RRR TET RET rE RET TE RETIN

2 TERETE FE

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——SSSSSSSSSSSSSSSSS HD68000/HD68HC000 —_ee = INSTRUCTION FORMAT SUMMARY instructions according to the op-code map. ‘This provides a summary of the first word in each instruction where, Size; Byte = 00 Sz; Word =0 of the instruction set. Table 26 is an operation code (op-code) Word = 01 Long Word = 1 map which illustrates how bits 15 through 12 are used to Long Word = 10 specify the operations. The remaining paragraph groups the Table 26 Operation Code Map Bits _ 16 thru 12 Operation 0000 | _Bit Manipulation/MOVEP/Immediate ‘0001 Move Byte 0010 | ~ Move Long

011 Move Word _

0100 Miscellaneous

0101 ADDQ/SUBO/Scc/DBec

0110 Bec

oi | MOvEQ ~ 1000 | “onvoiviseco 1oor | sue/suex 110 (Unassigned)

1011 CMP/EOR

1100 AND/MUL/ABCD/EXG

1101 ADD/ADDX

___1110 | Shift/Rotate it (Unassigned) (1) BIT MANIPULATION, MOVE PERIPHERAL, IMMEDIATE INSTRUCTIONS Dynamic Bit 4 1 2 1 9 8 7 6 &§ 4 3 2 3 (eTe To fo [esse Ts [tye] ettctwe Adare] Static Bit io 3 2 1) 9 8 7 6 5s 8 3 2 Cole le[e[+[o]e[o] tw | fase] Bit Type Codes: TST = 00, CHG = 01, CLR = 10,SET=11 MOVEP i 4 3 2 1 te 8 8 7 6 8 4 3 2 [eo Lo [o |] Revi Opatode [0 To [+ | Reviter ‘Op Mode; Word 0 Req 100, Long to Reg = 101, Word to Mem = 110, Long to Mam = 177 OR Immediate 3 4 3 2 1 to 8 8 7 6 6 4 2 Lo fe [ole fo]oTo fo] sa [ ~ eiiecivenssom | AND Immediate is 9 2 1 0 8 8 7 6 5 4 3 2 0 (eTe Telefe lol fe] am | eaienaiea —] @HITACHI 978 Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 + (415) 589-8300 | .

‘SUB immediate wow 2 1 wo 9 8 7 6 5 4 3 2 1 0 CofelelTe lel: [ole] sm [Teresi nsces J ADD immediate ow 9 2 1 1 9 8 7 8 8 4 3 2 1 0 CeoTefeTole[+[+]o] s= [ etetwaseen EOR Immediate i wom 27 nw 6 8 7 6 6 # 3 2 1 CofeToleo{+[e[+ Jo] sm [ ttecieaseen | CMP Immediate wow a 2 nw 8 6 7 6 6 4 3 2 1 0 [eofTeTolo[+[+[oJo] sm | tteciveaswen | (2) MOVE BYTE INSTRUCTION MOVE Byte we ouon wm nw 9 8 7 6 8 4 3 27 1 a er an Regier Mode Mode _ Regiater (3) MOVE LONG INSTRUCTION MOVE Long www 2 nw 8 8 7 6 6 4 3 2 1 O Source ee (4) MOVE WORD INSTRUCTION MOVE Word wou oa 2 to 8 8 7 6 8 # 3 2 1 Destination Source ee {6) MISCELLANEOUS INSTRUCTIONS NEGX ow 1 4 1 © 9 8 7 6 6 4 3 2 4 0 Ce[+Tefololelolo] sm | ememasm | MOVE from SR 6 4 «130 «92 1 0 D8 8 7 6 & 4 3 2 1 o Cef+TeTe[olo[olo]+][+] erences | cLR 1% 14 13) 12: «1 0 8 8 7 6 iJ 4 3 2 1 ° Cots TeTeyole|+l[o] sm» | ttenieasien | @ HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 979

HD68000/HD68HC000 _ - - NEG woo 2 nw 9 8 7 6 6 4 3 2 4 0 (ote Te [oo [i To [oe] sxe [ettectve aces] MOVE to CCR wou ono nw 8 8 7 6 5 4 3 2 1 0 (eq + Jeyofofs fo fos Ts [ etecive nade] NOT Mo 4 nw 9 8 7 6 5 4 3 2 4 0 feT: fo Too fs [To] sie [eee dace] MOVE to SR wo 4 3 2 1 w 8 8 7 6 5 4 a 2 4 0 [ofr fofofo]+ fs [oft [1] ~ eecive rsdn) NBCD 4 a Hw 9 8 7 6 5 4 3 2 4 0 Cel: To[ol:]olojololo | eae sare ~~] PEA Mom 2 1 we 8 8 7 6 5s 4 9 2 3 0 Cots tejo}:fofofo]o]s [ erecivenasen — —] SWAP Mon a 1 0 9 8 7 6 5 4 3 2 1 @ fe[+]el[o{s]ofe[ojo]: [eo lo] ei —] MOVEM Registers to EA woo 1 nw 8 8 7 6 5 4 3 2 1 0 (oT: Telos fololols lm] tiem rss EXTW Mon nw 8 8 7 6 5 4 3 2 4 0 (eT: [eTe[sfoTofo fr ]oTo fo] o [Rate] EXTL mo we 9 6 7 6 8 4 3 2 1 0 Cols [oTo[+Jofofols]sJTofo lo] evs | TsT 4 3 2 nw 8 8 7 6 5 4 9 2 4 0 Colt To fo]:[o[s [eo] sw | etetive adden] TAS: Mo 2 nw 6 8 7 6 5 4 3 2 4 0 Cots Tofo]s Jo]: Joly fs] ttectiveaaaen | @HITACHI 980 Hitachi America, Ltd. Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

wou on won we 8 7 6 6 4 3 2 1 0 Ces ToTo[+ [+ [olo[s [se] eteciwnsine | ‘TRAP 1% 4 19 12 1 1 9 8 7 6 $ 4 3 2 1 O Cet: tefol+[+[+]Jolo ls ]o To] vem J LINK wow ow 2 nw 9 8 7 6 6 4 3 2 1 0 (ete TeToT+ [+f Tole [+ [eo]. To] tes] UNLK is wow 2 nw 9 8 7 6 6 4 3 2 1 0 CoT+[olo[s]+{+lofeo[+lo]s [+] few] MOVE to USP wow 2 nw 6 6 7 6 8 4 3 2 1 0 CotrleTot+[:[+Jolo[+]:][o]lo] Few —] MOVE from USP ow om 2 nw 8 @ 7 6 6 4 3 2 1 © Cet+Totot+ [+t tele fs [slo ls [tev RESET ws wo 2 ww 9 8 7 6 6 4 3 2 1 Co[stefet+ +] Jelo[+ [1 [+ ]JoJofeole NOP wou on 2 nw 9 8 7 6 8 4 3 2 1 Cot: tolo[+]+{*lJelo[+ [++ Jel[oto [*) ‘sTOP wow 1 2 nw 9 8 7 6 6 # 3 2 1 0 Cofeteolet+[*1+[oJel* +I" Telet Te] RTE wow ow 2 Ww 9 8 7 6 6 4 3 2 1 0 Ce[+Tetet+ [+ [+ Jollet T+ T+ Tole ts] ) ats wow 3 2 ww 6 8 7 6 6 4 3 2 1 0 Cots Tojej[+|*[*lelol+{+{ Jol sto]s] TRAPV 1 “oa 2 yw 9 8 7 6 6 6 3 2 1 © Cet: tofol+[+[+lelol* J+ T+ Te[+ T+ Te} @HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300 981

i 4 1 2 1 1 9 8 7 6 5 4 3 2 1 0 JSR is 4 3 2 1 1 9 8 7 6 5 4 3 2 1 0 fet [olto[:[+[:Jo[+][o] theiwadren | ame i 4 3 12 «4 10 9 8 7 6 5 4 3 2 1 0 Co[s]o fos] rT Jo [at [a [erection ascress CHK bow om 2 nw 9 8 7 6 5 # 3 2 4 LEA 3 3 2 1 10 9 8 7 6 5 4 3 2 1 0 (eT Te To] revise [Ta Ts | Ettective Adres (6) ADD QUICK, SUBTRACT QUICK, SET CONDITIONALLY, DECREMENT INSTRUCTIONS ADDQ i Mo mm 8 8 7 6 58 4 3 2 1 felt [eli [ om [o] sw | tiecweAaaes suBQ 4 3 2 9 8 7 6 5 4 3 2 1 0 oT To [st [one Ty [sie [ete Aare] Sce om 9 2 1 w@ 8 8 7 6 5 4 3 2 1 0 ots Teqry OBee i 4 3 2 nw 9 8 7 6 8 4 3 2 4 0 [+ [+ To To fs J pesiser (7) BRANCH CONDITIONALLY, BRANCH TO SUBROUTINE INSTRUCTION Bee i 13 2 1 1 8 8 7 6 5 4 39 2 1 0 BSR i 4 3 2 1 w@ 9 8 7 6 5 4 3 2 4 0 Lel+ T+ [oTeTofo[s [ eeicoisicemn (8) MOVE QUICK INSTRUCTION MOVEQ 3 4 13 12 1 m0 9 8 7 6 5 kt (ole ys fe] Aes fo] One @ HITACHI 982 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300 .

{9) OR, DIVIDE, SUBTRACT DECIMAL INSTRUCTIONS oR 6% 4 13012 4 0 8 8 7 6 & 4 3 2 1 © CoTe Lo To [seer Toner [em strn —_] [ete ate —_] ewe 080 01 of0 On V-EA->0n too for $10 EV On=eA DivU 168 14 13 12) «14 wo 8 8 7 J 5 4 3 2 1 o (Te To To] tee To Ts [3 Etiectiva Adress Olvs wow mw 2 1 0 9 8 7 6 6 *& 3 2 1 0 ‘sBcD ow mw 2 m1 9 8 7 6 6 #4 3 2 1 0 [ToT fe] mmr Ts Le Lo Lo [o Jom] seer | RIMM (register /memory): register — register = 0, memory — memory = 1 (10) SUBTRACT, SUBTRACT EXTENDED INSTRUCTIONS sus 6 4 #13 12) ~«1 wo 9 8 7 6 Ss 43 2 1 © CeTe Te [eT regen Op-Mode ~_Etective Adaione 1] ‘Op-Mode awe 060 001 O10 On—EA-r0n foo for 110 EA-Dn eA Ot Mt An=EA= An ‘SUBX 1% 4 13° 12 «11 10 LJ J 7 6 & 4 3 2 1 ° RUM (register/memory): register — register = 0, memory — memory = 1 (11) COMPARE, EXCLUSIVE OR INSTRUCTIONS cMP 1% 4 #13) «120 «1 0 iJ eo7 6 s a3 2 1 iJ (Te Ts [3 [resi Te ose Ettective Address Op-Mode. ewe 000 001 O10 On-EA mo Sty AnceA cMPM 6% #4 13° «92:~«1 10) 8 8 7 6 5 4 3 2 1 o Ce Tete Tt Toomer Ts [sie To To Ts [reer J EOR i wo 2 1 1 9 8 7 6 5 4 3 2? 1 © Cee Ts Lt [eine Tt [see [etter Aarne (12) AND, MULTIPLY, ADD DECIMAL, EXCHANGE INSTRUCTIONS AND 6 4 #13) «12 «1 1 D8 8 7 J iJ 4 3 2 1 o CTs Te [eo [rain [comes [etecve aoe Op Mode ew 900 001 010 On AEA+Dn Soo for fie EA ADn eA @ HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 983 .

1% 4 13 2 1 0 9 8 7 6 Fh 8 2 0 CL Te [oe] few [Lo [ef] eteciwe aasien | MuLS [a ) Ci treteT— ABCO a RIM (register/memory): register — register = 0, memory — memory = 1 EXGD Se eS) EXGA 13413 12 1 te 8 GS kt EXGM 1 4013 12) 8 bk kt + [+ [0 [0 | datareaser | 1 [+ | © | 0 | 0 | 1 | Addve Register (13) ADD, ADD EXTENDED INSTRUCTIONS ADD is 4 3 2 tt to 7 8 Op Mode eow ot 000 001 010 Dn + EA-+0n 100 101 110 EA+ On eA ~ ON Mt An + EAs An ADOX CC ) | ‘T Destination RIM (register/memory): register ~ register = 0, memory — memory = 1 (14) SHIFT/ROTATE INSTRUCTIONS Data Register Shifts Ce ) (2 [+ [4 [eo J counumesister [| sie | i | Type Register Memory Shifts 1 4 13 12 «1 1 9 8 7 6 § 4 3 2 1 0 COT tee me Dele DD wie aaa) Shift Type Codes: AS = 00, LS = 01, ROX = 10, RO= 11 d (direction): Right = 0, Left = 1 i/r (count source): Immediate Count = 0, Register Count = 1 @ HITACHI 984 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 ¢ (415) 589-8300 .

by a longer memory cycle must be added to the total instrue- tion where indicated. w is the number of write cycles. © EFFECTIVE ADDRESS OPERAND CALCULATION bus read and write cycles is shown in parenthesis as: (r/w). pute an instruction’s effective address. It includes fetching address calculation where indicated. no write cycles involved in processing the effective address. code register, and SR = status register. Table 27. Effective Address Calculation Timing

The size of the index register (ix) does not affect execution time.

Table 29. Move Long Instruction Clock Periods

The size ofthe index cegister (1x) does not atfect execution time.

patterns in the 17-bit source; ie, worst case happens when the source ie $5555. 986 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 .

Table 31 Immediation Instruction Clock Periods Trstruction | Swe [| op#,0n | op#An | op#M | op #,CCR/SR [Byte Word [giz f= y2t2/t) + = ADD! Se car Aan

200 Fong Tso) f= porary)

‘Appa Byte, Word | 4(1/0) | BtV/Oy" |e _ Ape [ie “face, arto wana | = 1 ef comet Byte, Word ai2/0) | (2/0) | 812/0)+ = FOR! Byte,Word | 12/0) | | tata 20(3/0) MOVEQ _j_bong “t 4(1/0) | - i = - oR! Byte, Word 8(2/0) =f 42+ 2013/0) = 20(3/2) + = Byte, Word 8(2/0) - 12(2/1) + - susa Byte, Word “avy | ao | Bae PO 4 edd effective address calculation time * word only Table 32 Single Operand Instruction Clock Periods Tratruetion [Size | Resister__ [Memory CLR Byte, Word ao), TS _ Long 6/0) | 112+ NCD, Byte =| S/O) a Byte, Word 4(1/0) BI) + NEG 12102) + Byte, Word 4(1/0) B11/1) + NEGK Long 6(1/0) 1201/2) + Byte, Word 4(1/0) BI) + N Byte, Word | - a Nr tong | 09 yaq7a)+ Se Byte, False) 41/0) _ 8+ im Byte, True (1/0) (1/1) + TAS [eye | ation toni + st 4(1/0) + 4 edd tfective addres calculation time © SHIFT/ROTATE INSTRUCTION CLOCK PERIODS @ BIT MANIPULATION INSTRUCTION CLOCK PERIODS Table 33 indicates the number of clock periods for the shift Table 34 indicates the number of clock periods required for and rotate instructions. The number of bus read and write the bit manipulation instructions. The number of bus read and cycles is shown in parenthesis as: (r/w). The number of clock write cycles is shown in parenthesis as: (r/w). The number of periods and the number of read and write cycles must be added clock periods and the number of read and write cycles must be respectively to those of the effective address calculation where added respectively to those of the effective address calculation indicated. where indicated. @HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-6300 987

© CONDITIONAL INSTRUCTION CLOCK PERIODS © MP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK Table 35 indicates the number of clock periods required for PERIODS the conditional instructions. The number of bus read and write Table 36 indicates the number of clock periods required for cycles is indicated in parenthesis as: (r/w). The number of clock _the jump, jump to subroutine, load effective address, push effec- periods and the number of read and write cycles must be added —_tive address, and move multiple registers instructions. The num- respectively to those of the effective address calculation where _ber of bus read and write cycles is shown in parenthesis as: (r/w). indicated. Table 33 Shift/Rotate Instruction Clock Periods lostruction [Size [Register| Memory Byte, Word | 6+ 2ntvoy | avis ASR, ASL Long B+ ani) = ‘SIS 8+ ant) = ROR, ROL e+ Fn) = RON ROM [tera Ts zn = Table 34 Bit Manipulation Instruction Clock Periods en ee State [Register [Memory |" Register| Memory BcHe [eve [= [ane T= Teens bong [aivoyy T= t2ay* T= BCLR Bye | - | ane | — | 1202s [tong | roivor* [| - | saa" [ eset | 12(2/1) + ee Long | 811/0)* | = BIST Bye | - | ‘B(2/0) + tone [ewvo) [= | vorenoy = + dd effective address calculation time * indicates maximum value Table 35 Conditional Instruction Clock Periods A [bye tz) (1/0) iad [Word 10270) 1212/00 i a BSA Byte [ _veiaray_ = | Word [satay | = | GC 20270) oF ee | ect tora) 141370) CHK ee ee ee 10(1/0) + tar |= ier a a ET + add effective address calculation time * indeates maximum value @HITACHI 988 Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300 .

Table 36 JMP, JSR, LEA, PEA, MOMEM Instruction Clock Periods Tray | Sie | An@ | An@+ | Ane@- | Avera) [An@(a,in)"[ vox.w [ vox. | pceta [ Pcetd, x) me | - | emt — | = | ror] tara [ror | iaia | ro12/0) | 1413/0) tea} =] ato eizro)| 12/0 | sare) | vata) | aca/ | 1220) MOVEM 12+4n 12+4n 16+4n 18+4n 16+4n | 20+4n i 16+4n 18+4n MoR 12+8n | 1248n | 16+8n 18+8n | 1648n | 20+8n | 16+8n 18+8n 8+4n - Bt+4n 12+4n 14+4n 12+4n 16+4n | - - MoveM | wore | (i) | (ain) | md] md | ied |) | = = R=-M Lor 8+8n 12+8n 14480 12+8n 16+8n | - - nie the number of registers to move * ig the size ofthe index register (ix) does not affect the instruction’s execution time ‘© MULTIPRECISION INSTRUCTION CLOCK PERIODS the results, and read the next instructions. The number of read Table 37 indicates the number of clock periods for the multi- and write cycles is shown in parenthesis as: (r/w). precision instructions. The number of clock periods includes In Table 37, the headings have the following meanings: Dn = the time to fetch both operands, perform the operations, store data register operand and M = memory operand. Table 37 Multi-Precision Instruction Clock Periods Instruction [Size op0n,0n | opM.M 4(1/0) 18(3/1) _AOPK [tong j ati/o) | 9005/2) Byte, Word = t 12(3/0) MPM - ——_ a beng | 20060) suex Byte,Word | 4(1/0) 18(3/1) ano) | sows ABCD Byte 6(1/0) } 18(3/1) © MISCELLANEOUS INSTRUCTION CLOCK PERIODS © EXCEPTION PROCESSING CLOCK PERIODS Table 38 indicates the number of clock periods for the fol- Table 39 indicates the number of clock periods for exception lowing miscellaneous instructions. The number of bus read and processing. The number of clock periods includes the time for write cycles is shown in parenthesis as: (r/w). The number of all stacking, the vector fetch, and the fetch of the first instruc- clock periods plus the number of read and write cycles must be _tion of the handler routine. The number of bus read and write ‘added to those of the effective address calculation where indi- cycles is shown in parenthesis as: (r/w). cated. @HITACHI Hitachi America, Ltd. © Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 989 :

Table 38 Miscellaneous Instruction Clock Periods Instruction [Size [Register [Memory Register+ Memory |" Memory > Register WOvEromsR [| - | em | aims | id = MOVE to CCR ee 7 = MOVE t0 SR [=f t2ray s2aoye = [Worst 1614/0) Mover a EXG a a | = EXT [Word 4) = [kong favo) = LINK [ = | tere) = MOVE fromusp [= Tato) = Moverouse | Tay PT = NOP. [aio = RESET [= satya = RTE [= 200670) = RTA a A = ATS [= tea = STOP a | = SWAP a = UNLK [= aso) = + wd ttective addrans calelation time Table 39 Exception Processing Clock Periods © MASK VERSION Exception Periods Type No. Mask version Rewt* 38.5 (6/0) 40680008 ‘Address Error 5014/7) HD68000-10 Bus Error 6014/7) 11D68000-12 6800081 Interrupt 4416/3)" HDesooo¥s Ilegal Instruction 34(4/3) HD68000%-10 Privileged Violation 34(4/3) HD6B000Y-12, ‘Trace 34(4/3) : 7 HD68000R8 Tosa sete bu yl aoa 06900098 e000 ‘The difference of function between mask version 68000S! ‘and 68000U is only as following (Figure 59). The function of HD68HCOOO is as same as mask version 68000U. @ HITACHI 990 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 .

sO $1 $2 83 $4 55 S6 S7 SO SI S253 54 55 56 57 so S182 83 S455 axSLI1 LILI 1 LS | PL a ld \\ / \\ Broken line: mask version 6B000U end HOBSHCOOO. Figure 59 Address Error Timing ® NOTE FOR USE © Power Supply Circuit When designing Voc and Vsg pattern of the circuit board, the capacitors need to be located nearest to Voc and Vs as shown in the Figure 60. gfe B aq ® S| 7 | + a ves 8 a 5 fa vss vec fi a B BIS1SISISISISTOISIS) Fe B > GAGOO GS Qo’ ia vssEo pe i age ers FF a vee vs B 4 i Se Ea) oy “SS vec g ota) fo1Q) F = id B ae foto) B a alot) « GOO a Ee

4 E cisiosicieiaieigis FS y

q fz DODOOOOOSGS ” GWaEHERRREWABEEE (Top View) {Bottom View) {Top View) (a) DIP (b) PGA {c) PLCC 1yF/35V Tantalum Capacitor (2 pairs) Figure 60 Power Supply Circuit @ HITACHI Hitachi America, Ltd. © Hitachi Plaza ® 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 991

Selected Specification

Hitachi Semiconductor HD68000 overview.

Summary

MPU(MICRO PROCESSING UNIT)

Description

MPU(MICRO PROCESSING UNIT)

Source title HD68000 Datasheet(PDF) - Hitachi Semiconductor

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