HD66766R HITACHI
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 97
Technical content
Features
- 132RGB x 176-dot graphics display LCD controller/driver for 65K STN colors
- low voltage drive and flickerless PWM grayscale drive
- 16-/8-bit high-speed bus interface and Clock Synchronized Serial Interface ( SPI )
- High-speed burst-RAM write function
- Writing to a window-RAM address area by using a window-address function
- Bit-operation functions for graphics processing: - Write-data mask function in bit units. - Logical operation in pixel unit and conditional write function.
HD66766R Rev. 1.0-1 / September 2002
- Various color-display control functions - 65K out of 140K possible colors can be displayed at the same time (grayscale palette incorporated) - Vertical scroll display function in raster-row units - Partial LCD drive of two screens in any position
- Low-power operation supports: - Vcc = 2.2 to 3.6 V (low-voltage) - Common driving voltage = 8 to 44 V - Segment driving voltage = 2 to 4 V - VOUT power voltage = 4.0V to 5.75 V - Power-save functions such as the standby mode and sleep mode - Internal power supply circuit - Programmable drive duty ratios (1/8–1/176) and bias values (1/2–1/13) displayed on LCD - Maximum 12-times step-up circuit for liquid crystal drives voltage and voltage inverting circuit - 128-step contrast adjuster and voltage followers to decrease direct current flow in the LCD drive bleeder-resistors
- Internal RAM capacity: 46,464 bytes
- 396-segment × 176-common liquid crystal display driver
- n-raster-row AC liquid-crystal drive (C-pattern waveform drive)
- Internal oscillation and hardware reset
- Shift change of segment and common drivers
- COM positioned on both sides in one chip for COG Type Name Types External Dimensions HCD667A66RBP Au-bumped chip straight bump HCD667B66RBP Au-bumped chip laced bump Difference between HCD667x66R and HCD667x66 Difference HCD667x66R HCD667x66 Pad No. Pad Name Pad No. Pad Name
63 Vcc 63 Vcc
64 Vcc 64 Vcc
66 Vcc 66 Vcc
67 AVcc 67 Vcc
68 AVcc 68 Vcc
69 AVcc 69 Vcc
70 AVcc 70 Vcc
HD66766R Rev. 1.0-1 / September 2002 g HD66766R PAD Arrangement (Straight Output Arrangement) nChip size: 18.65mm×2.63mm nChip thickness: 400um (typ.) nPad coordinate: Pad center nCoordinate origin: Chip center nAu bump size: (1) 80µm × 80µm DUMMY1, DUMMY2, RESET1*~ ∼RESET3*, DUMMY10, DUMMY11 DUMMY12, DUMMY13 (2) 23µm × 140µm COM1 ~ COM176 SEG1 ~ SEG396 nAu bump pitch: Refer to pad coordinate nAu bump hight: 15µm(typ.) n Numbers in the figure corresponds to the number of pad coordinate. n Alignment mark (1) Arrangement: Two places @@ Coordinate (X, Y) = (±9000, -1121) 30 40 30 30 40 30 100µm 100µm (2-a) Coordinate (X, Y) = (-9094, 1145) (2-b) Coordinate (X, Y) = (9094, 1145) (3-a) Coordinate (X, Y) = (-9004, 1145) (3-b) Coordinate (X, Y) = (9004, 1145) 50µm 20 50µm 10 25 25 10 10 25 25 10 5 5 70µm 70µm 80µm 80µm 10 25 25 10 10 25 25 10 70µm 70µm COMP COM3 COM5 COM7 COM99 COM101 COM103 COM105 DUMMY2 COM107 RESET1* COM109 CEP COM111 CEP COM113 CEM CEM VCL VCL VCL VCL VCH VCH VCH VCH C24+ C24+ C24- COM169 C24- COM171 C23+ COM173 C23+ COM175 C23- SEG1 C23- SEG2 C22+ SEG3 C22+ SEG4 C22- C22- C21+ C21+ C21- C21- VCI2 VCI2 VCI2 VCI2 GNDDUM1 NO.1 NO.666 HD667A66R TypeCode GNDDUM4 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 GNDDUM5 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI GNDDUM6 RW/RD* E/WR*/SCL GNDDUM7 RS CS* VCC VCC VCC VCC AVCC AVCC AVCC AVCC AGND AGND GND GND GND GND AGND AGND RESET2* OSC2 OSC1 GNDDUM8 IM2 VCCDUM1 IM1 GNDDUM9 IM0/ID VCCDUM2 TEST2 TEST1 GNDDUM10 DUMMY3 DUMMY9 VREFL VREFL BIASC BIASC VREFM VREFM VM HD667A66R Straight (Top View) Y X C12- SEG393 C12- SEG394 C12- SEG395 C12- SEG396 C11+ COM176 C11+ COM174 C11+ COM172 C11+ COM170 C11- C11- C11- C11- VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCCDUM3 COM114 VCCDUM4 COM112 RESET3* COM110 DUMMY10 COM108 COM2 COM4 COM6 COM8 COM100 COM102 COM104 COM106 NO.145 NO.199 Figure 1 PAD arrangement (Straight)
HD66766R Rev. 1.0-1 / September 2002 Table 2 HD66766R PAD Coordinate (Straight)(No.1)
1 DUMMY1 -9193 -1168 81 OSC1 1284 -1168 161 COM32 9155 -411 241 SEG390 7296 1145 321 SEG310 4256 1145
2 DUMMY2 -8835 -1168 82 GNDDUM8 1440 -1168 162 COM34 9155 -373 242 SEG389 7258 1145 322 SEG309 4218 1145
3 RESET1* -8678 -1168 83 IM2 1597 -1168 163 COM36 9155 -335 243 SEG388 7220 1145 323 SEG308 4180 1145
4 CEP -8498 -1168 84 VCCDUM1 1754 -1168 164 COM38 9155 -297 244 SEG387 7182 1145 324 SEG307 4142 1145
5 CEP -8398 -1168 85 IM1 1910 -1168 165 COM40 9155 -259 245 SEG386 7144 1145 325 SEG306 4104 1145
6 CEM -8298 -1168 86 GNDDUM9 2067 -1168 166 COM42 9155 -221 246 SEG385 7106 1145 326 SEG305 4066 1145
7 CEM -8198 -1168 87 IM0/ID 2223 -1168 167 COM44 9155 -183 247 SEG384 7068 1145 327 SEG304 4028 1145
8 VCL -8018 -1168 88 VCCDUM2 2380 -1168 168 COM46 9155 -145 248 SEG383 7030 1145 328 SEG303 3990 1145
9 VCL -7918 -1168 89 TEST2 2537 -1168 169 COM48 9155 -107 249 SEG382 6992 1145 329 SEG302 3952 1145
10 VCL -7818 -1168 90 TEST1 2693 -1168 170 COM50 9155 -69 250 SEG381 6954 1145 330 SEG301 3914 1145
11 VCL -7718 -1168 91 GNDDUM10 2850 -1168 171 COM52 9155 -31 251 SEG380 6916 1145 331 SEG300 3876 1145
12 VCH -7538 -1168 92 DUMMY3 3030 -1168 172 COM54 9155 7 252 SEG379 6878 1145 332 SEG299 3838 1145
13 VCH -7438 -1168 93 DUMMY4 3130 -1168 173 COM56 9155 45 253 SEG378 6840 1145 333 SEG298 3800 1145
14 VCH -7338 -1168 94 DUMMY5 3230 -1168 174 COM58 9155 83 254 SEG377 6802 1145 334 SEG297 3762 1145
15 VCH -7237 -1168 95 DUMMY6 3330 -1168 175 COM60 9155 121 255 SEG376 6764 1145 335 SEG296 3724 1145
16 C24+ -7057 -1168 96 DUMMY7 3430 -1168 176 COM62 9155 159 256 SEG375 6726 1145 336 SEG295 3686 1145
17 C24+ -6957 -1168 97 DUMMY8 3530 -1168 177 COM64 9155 197 257 SEG374 6688 1145 337 SEG294 3648 1145
18 C24- -6857 -1168 98 DUMMY9 3630 -1168 178 COM66 9155 235 258 SEG373 6650 1145 338 SEG293 3610 1145
19 C24- -6757 -1168 99 VREFL 3810 -1168 179 COM68 9155 273 259 SEG372 6612 1145 339 SEG292 3572 1145
20 C23+ -6657 -1168 100 VREFL 3910 -1168 180 COM70 9155 311 260 SEG371 6574 1145 340 SEG291 3534 1145
21 C23+ -6557 -1168 101 BIASC 4010 -1168 181 COM72 9155 349 261 SEG370 6536 1145 341 SEG290 3496 1145
22 C23- -6457 -1168 102 BIASC 4110 -1168 182 COM74 9155 387 262 SEG369 6498 1145 342 SEG289 3458 1145
23 C23- -6357 -1168 103 VREFM 4211 -1168 183 COM76 9155 425 263 SEG368 6460 1145 343 SEG288 3420 1145
24 C22+ -6257 -1168 104 VREFM 4311 -1168 184 COM78 9155 463 264 SEG367 6422 1145 344 SEG287 3382 1145
25 C22+ -6157 -1168 105 VM 4411 -1168 185 COM80 9155 501 265 SEG366 6384 1145 345 SEG286 3344 1145
26 C22- -6057 -1168 106 VM 4511 -1168 186 COM82 9155 539 266 SEG365 6346 1145 346 SEG285 3306 1145
27 C22- -5957 -1168 107 VM 4611 -1168 187 COM84 9155 577 267 SEG364 6308 1145 347 SEG284 3268 1145
28 C21+ -5856 -1168 108 VM 4711 -1168 188 COM86 9155 615 268 SEG363 6270 1145 348 SEG283 3230 1145
29 C21+ -5756 -1168 109 VSH 4811 -1168 189 COM88 9155 653 269 SEG362 6232 1145 349 SEG282 3192 1145
30 C21- -5576 -1168 110 VSH 4911 -1168 190 COM90 9155 691 270 SEG361 6194 1145 350 SEG281 3154 1145
31 C21- -5476 -1168 111 VSH 5011 -1168 191 COM92 9155 729 271 SEG360 6156 1145 351 SEG280 3116 1145
32 VCI2 -5376 -1168 112 VSH 5111 -1168 192 COM94 9155 767 272 SEG359 6118 1145 352 SEG279 3078 1145
33 VCI2 -5276 -1168 113 VOUT 5291 -1168 193 COM96 9155 805 273 SEG358 6080 1145 353 SEG278 3040 1145
34 VCI2 -5176 -1168 114 VOUT 5391 -1168 194 COM98 9155 843 274 SEG357 6042 1145 354 SEG277 3002 1145
35 VCI2 -5076 -1168 115 VOUT 5491 -1168 195 COM100 9155 881 275 SEG356 6004 1145 355 SEG276 2964 1145
36 GNDDUM1 -4896 -1168 116 VOUT 5592 -1168 196 COM102 9155 919 276 SEG355 5966 1145 356 SEG275 2926 1145
37 GNDDUM2 -4796 -1168 117 C12+ 5772 -1168 197 COM104 9155 957 277 SEG354 5928 1145 357 SEG274 2888 1145
38 GNDDUM3 -4696 -1168 118 C12+ 5872 -1168 198 COM106 9155 995 278 SEG353 5890 1145 358 SEG273 2850 1145
39 GNDDUM4 -4596 -1168 119 C12+ 5972 -1168 199 DUMMY12 9193 1183 279 SEG352 5852 1145 359 SEG272 2812 1145
40 DB15 -4416 -1168 120 C12+ 6072 -1168 200 COM108 8892 1145 280 SEG351 5814 1145 360 SEG271 2774 1145
41 DB14 -4259 -1168 121 C12- 6172 -1168 201 COM110 8854 1145 281 SEG350 5776 1145 361 SEG270 2736 1145
42 DB13 -4103 -1168 122 C12- 6272 -1168 202 COM112 8816 1145 282 SEG349 5738 1145 362 SEG269 2698 1145
43 DB12 -3946 -1168 123 C12- 6372 -1168 203 COM114 8778 1145 283 SEG348 5700 1145 363 SEG268 2660 1145
44 DB11 -3789 -1168 124 C12- 6472 -1168 204 COM116 8740 1145 284 SEG347 5662 1145 364 SEG267 2622 1145
45 DB10 -3633 -1168 125 C11+ 6572 -1168 205 COM118 8702 1145 285 SEG346 5624 1145 365 SEG266 2584 1145
46 DB9 -3476 -1168 126 C11+ 6672 -1168 206 COM120 8664 1145 286 SEG345 5586 1145 366 SEG265 2546 1145
47 DB8 -3320 -1168 127 C11+ 6772 -1168 207 COM122 8626 1145 287 SEG344 5548 1145 367 SEG264 2508 1145
48 GNDDUM5 -3163 -1168 128 C11+ 6872 -1168 208 COM124 8588 1145 288 SEG343 5510 1145 368 SEG263 2470 1145
49 DB7 -3006 -1168 129 C11- 6972 -1168 209 COM126 8550 1145 289 SEG342 5472 1145 369 SEG262 2432 1145
50 DB6 -2850 -1168 130 C11- 7073 -1168 210 COM128 8512 1145 290 SEG341 5434 1145 370 SEG261 2394 1145
51 DB5 -2693 -1168 131 C11- 7173 -1168 211 COM130 8474 1145 291 SEG340 5396 1145 371 SEG260 2356 1145
52 DB4 -2537 -1168 132 C11- 7273 -1168 212 COM132 8436 1145 292 SEG339 5358 1145 372 SEG259 2318 1145
53 DB3 -2380 -1168 133 VCIOUT 7453 -1168 213 COM134 8398 1145 293 SEG338 5320 1145 373 SEG258 2280 1145
54 DB2 -2223 -1168 134 VCIOUT 7553 -1168 214 COM136 8360 1145 294 SEG337 5282 1145 374 SEG257 2242 1145
55 DB1/SDO -2067 -1168 135 VCIOUT 7653 -1168 215 COM138 8322 1145 295 SEG336 5244 1145 375 SEG256 2204 1145 56 DB0/SDI -1910 -1168 136 VCIOUT 7753 -1168 216 COM140 8284 1145 296 SEG335 5206 1145 376 SEG255 2166 1145 57 GNDDUM6 -1754 -1168 137 VCI1 7933 -1168 217 COM142 8246 1145 297 SEG334 5168 1145 377 SEG254 2128 1145
58 RW/RD* -1597 -1168 138 VCI1 8033 -1168 218 COM144 8208 1145 298 SEG333 5130 1145 378 SEG253 2090 1145
59 E/WR*/SCL -1440 -1168 139 VCI1 8133 -1168 219 COM146 8170 1145 299 SEG332 5092 1145 379 SEG252 2052 1145 60 GNDDUM7 -1284 -1168 140 VCI1 8233 -1168 220 COM148 8132 1145 300 SEG331 5054 1145 380 SEG251 2014 1145
61 RS -1127 -1168 141 VCCDUM3 8413 -1168 221 COM150 8094 1145 301 SEG330 5016 1145 381 SEG250 1976 1145
62 CS* -971 -1168 142 VCCDUM4 8513 -1168 222 COM152 8056 1145 302 SEG329 4978 1145 382 SEG249 1938 1145
63 VCC -791 -1168 143 RESET3* 8693 -1168 223 COM154 8018 1145 303 SEG328 4940 1145 383 SEG248 1900 1145
64 VCC -690 -1168 144 DUMMY10 8850 -1168 224 COM156 7980 1145 304 SEG327 4902 1145 384 SEG247 1862 1145
65 VCC -590 -1168 145 DUMMY11 9193 -1168 225 COM158 7942 1145 305 SEG326 4864 1145 385 SEG246 1824 1145
66 VCC -490 -1168 146 COM2 9155 -981 226 COM160 7904 1145 306 SEG325 4826 1145 386 SEG245 1786 1145
67 AVCC -390 -1168 147 COM4 9155 -943 227 COM162 7866 1145 307 SEG324 4788 1145 387 SEG244 1748 1145
68 AVCC -290 -1168 148 COM6 9155 -905 228 COM164 7828 1145 308 SEG323 4750 1145 388 SEG243 1710 1145
69 AVCC -190 -1168 149 COM8 9155 -867 229 COM166 7790 1145 309 SEG322 4712 1145 389 SEG242 1672 1145
70 AVCC -90 -1168 150 COM10 9155 -829 230 COM168 7752 1145 310 SEG321 4674 1145 390 SEG241 1634 1145
71 AGND 90 -1168 151 COM12 9155 -791 231 COM170 7714 1145 311 SEG320 4636 1145 391 SEG240 1596 1145
72 AGND 190 -1168 152 COM14 9155 -753 232 COM172 7676 1145 312 SEG319 4598 1145 392 SEG239 1558 1145
73 GND 290 -1168 153 COM16 9155 -715 233 COM174 7638 1145 313 SEG318 4560 1145 393 SEG238 1520 1145
74 GND 390 -1168 154 COM18 9155 -677 234 COM176 7600 1145 314 SEG317 4522 1145 394 SEG237 1482 1145
75 GND 490 -1168 155 COM20 9155 -639 235 SEG396 7524 1145 315 SEG316 4484 1145 395 SEG236 1444 1145
76 GND 590 -1168 156 COM22 9155 -601 236 SEG395 7486 1145 316 SEG315 4446 1145 396 SEG235 1406 1145
77 AGND 690 -1168 157 COM24 9155 -563 237 SEG394 7448 1145 317 SEG314 4408 1145 397 SEG234 1368 1145
78 AGND 791 -1168 158 COM26 9155 -525 238 SEG393 7410 1145 318 SEG313 4370 1145 398 SEG233 1330 1145
79 RESET2* 971 -1168 159 COM28 9155 -487 239 SEG392 7372 1145 319 SEG312 4332 1145 399 SEG232 1292 1145
80 OSC2 1127 -1168 160 COM30 9155 -449 240 SEG391 7334 1145 320 SEG311 4294 1145 400 SEG231 1254 1145
HD66766R Rev. 1.0-1 / September 2002 Table 2 cont. HD66766R PAD Coordinate iStraightj(No.2) No. pad name X Y No. pad name X Y No. pad name X Y No. pad name X Y X Y
401 SEG230 1216 1145 481 SEG150 -1862 1145 561 SEG70 -4902 1145 641 COM155 -7980 1145 -9000 -1121
402 SEG229 1178 1145 482 SEG149 -1900 1145 562 SEG69 -4940 1145 642 COM153 -8018 1145 9000 -1121
403 SEG228 1140 1145 483 SEG148 -1938 1145 563 SEG68 -4978 1145 643 COM151 -8056 1145 -9094 1145
404 SEG227 1102 1145 484 SEG147 -1976 1145 564 SEG67 -5016 1145 644 COM149 -8094 1145 9094 1145
405 SEG226 1064 1145 485 SEG146 -2014 1145 565 SEG66 -5054 1145 645 COM147 -8132 1145 -9004 1145
406 SEG225 1026 1145 486 SEG145 -2052 1145 566 SEG65 -5092 1145 646 COM145 -8170 1145 9004 1145
407 SEG224 988 1145 487 SEG144 -2090 1145 567 SEG64 -5130 1145 647 COM143 -8208 1145
408 SEG223 950 1145 488 SEG143 -2128 1145 568 SEG63 -5168 1145 648 COM141 -8246 1145
409 SEG222 912 1145 489 SEG142 -2166 1145 569 SEG62 -5206 1145 649 COM139 -8284 1145
410 SEG221 874 1145 490 SEG141 -2204 1145 570 SEG61 -5244 1145 650 COM137 -8322 1145
411 SEG220 836 1145 491 SEG140 -2242 1145 571 SEG60 -5282 1145 651 COM135 -8360 1145
412 SEG219 798 1145 492 SEG139 -2280 1145 572 SEG59 -5320 1145 652 COM133 -8398 1145
413 SEG218 760 1145 493 SEG138 -2318 1145 573 SEG58 -5358 1145 653 COM131 -8436 1145
414 SEG217 722 1145 494 SEG137 -2356 1145 574 SEG57 -5396 1145 654 COM129 -8474 1145
415 SEG216 684 1145 495 SEG136 -2394 1145 575 SEG56 -5434 1145 655 COM127 -8512 1145
416 SEG215 646 1145 496 SEG135 -2432 1145 576 SEG55 -5472 1145 656 COM125 -8550 1145
417 SEG214 608 1145 497 SEG134 -2470 1145 577 SEG54 -5510 1145 657 COM123 -8588 1145
418 SEG213 570 1145 498 SEG133 -2508 1145 578 SEG53 -5548 1145 658 COM121 -8626 1145
419 SEG212 532 1145 499 SEG132 -2546 1145 579 SEG52 -5586 1145 659 COM119 -8664 1145
420 SEG211 494 1145 500 SEG131 -2584 1145 580 SEG51 -5624 1145 660 COM117 -8702 1145
421 SEG210 456 1145 501 SEG130 -2622 1145 581 SEG50 -5662 1145 661 COM115 -8740 1145
422 SEG209 418 1145 502 SEG129 -2660 1145 582 SEG49 -5700 1145 662 COM113 -8778 1145
423 SEG208 380 1145 503 SEG128 -2698 1145 583 SEG48 -5738 1145 663 COM111 -8816 1145
424 SEG207 342 1145 504 SEG127 -2736 1145 584 SEG47 -5776 1145 664 COM109 -8854 1145
425 SEG206 304 1145 505 SEG126 -2774 1145 585 SEG46 -5814 1145 665 COM107 -8892 1145
426 SEG205 266 1145 506 SEG125 -2812 1145 586 SEG45 -5852 1145 666 DUMMY13 -9193 1183
L (Positive) L (Negative) Circle(Negative) Circle(Positive) Cross Alignment mark
427 SEG204 228 1145 507 SEG124 -2850 1145 587 SEG44 -5890 1145 667 COM105 -9155 995
428 SEG203 190 1145 508 SEG123 -2888 1145 588 SEG43 -5928 1145 668 COM103 -9155 957
429 SEG202 152 1145 509 SEG122 -2926 1145 589 SEG42 -5966 1145 669 COM101 -9155 919
430 SEG201 114 1145 510 SEG121 -2964 1145 590 SEG41 -6004 1145 670 COM99 -9155 881
431 SEG200 76 1145 511 SEG120 -3002 1145 591 SEG40 -6042 1145 671 COM97 -9155 843
432 SEG199 38 1145 512 SEG119 -3040 1145 592 SEG39 -6080 1145 672 COM95 -9155 805
433 SEG198 -38 1145 513 SEG118 -3078 1145 593 SEG38 -6118 1145 673 COM93 -9155 767
434 SEG197 -76 1145 514 SEG117 -3116 1145 594 SEG37 -6156 1145 674 COM91 -9155 729
435 SEG196 -114 1145 515 SEG116 -3154 1145 595 SEG36 -6194 1145 675 COM89 -9155 691
436 SEG195 -152 1145 516 SEG115 -3192 1145 596 SEG35 -6232 1145 676 COM87 -9155 653
437 SEG194 -190 1145 517 SEG114 -3230 1145 597 SEG34 -6270 1145 677 COM85 -9155 615
438 SEG193 -228 1145 518 SEG113 -3268 1145 598 SEG33 -6308 1145 678 COM83 -9155 577
439 SEG192 -266 1145 519 SEG112 -3306 1145 599 SEG32 -6346 1145 679 COM81 -9155 539
440 SEG191 -304 1145 520 SEG111 -3344 1145 600 SEG31 -6384 1145 680 COM79 -9155 501
441 SEG190 -342 1145 521 SEG110 -3382 1145 601 SEG30 -6422 1145 681 COM77 -9155 463
442 SEG189 -380 1145 522 SEG109 -3420 1145 602 SEG29 -6460 1145 682 COM75 -9155 425
443 SEG188 -418 1145 523 SEG108 -3458 1145 603 SEG28 -6498 1145 683 COM73 -9155 387
444 SEG187 -456 1145 524 SEG107 -3496 1145 604 SEG27 -6536 1145 684 COM71 -9155 349
445 SEG186 -494 1145 525 SEG106 -3534 1145 605 SEG26 -6574 1145 685 COM69 -9155 311
446 SEG185 -532 1145 526 SEG105 -3572 1145 606 SEG25 -6612 1145 686 COM67 -9155 273
447 SEG184 -570 1145 527 SEG104 -3610 1145 607 SEG24 -6650 1145 687 COM65 -9155 235
448 SEG183 -608 1145 528 SEG103 -3648 1145 608 SEG23 -6688 1145 688 COM63 -9155 197
449 SEG182 -646 1145 529 SEG102 -3686 1145 609 SEG22 -6726 1145 689 COM61 -9155 159
450 SEG181 -684 1145 530 SEG101 -3724 1145 610 SEG21 -6764 1145 690 COM59 -9155 121
451 SEG180 -722 1145 531 SEG100 -3762 1145 611 SEG20 -6802 1145 691 COM57 -9155 83
452 SEG179 -760 1145 532 SEG99 -3800 1145 612 SEG19 -6840 1145 692 COM55 -9155 45
453 SEG178 -798 1145 533 SEG98 -3838 1145 613 SEG18 -6878 1145 693 COM53 -9155 7
454 SEG177 -836 1145 534 SEG97 -3876 1145 614 SEG17 -6916 1145 694 COM51 -9155 -31
455 SEG176 -874 1145 535 SEG96 -3914 1145 615 SEG16 -6954 1145 695 COM49 -9155 -69
456 SEG175 -912 1145 536 SEG95 -3952 1145 616 SEG15 -6992 1145 696 COM47 -9155 -107
457 SEG174 -950 1145 537 SEG94 -3990 1145 617 SEG14 -7030 1145 697 COM45 -9155 -145
458 SEG173 -988 1145 538 SEG93 -4028 1145 618 SEG13 -7068 1145 698 COM43 -9155 -183
459 SEG172 -1026 1145 539 SEG92 -4066 1145 619 SEG12 -7106 1145 699 COM41 -9155 -221
460 SEG171 -1064 1145 540 SEG91 -4104 1145 620 SEG11 -7144 1145 700 COM39 -9155 -259
461 SEG170 -1102 1145 541 SEG90 -4142 1145 621 SEG10 -7182 1145 701 COM37 -9155 -297
462 SEG169 -1140 1145 542 SEG89 -4180 1145 622 SEG9 -7220 1145 702 COM35 -9155 -335
463 SEG168 -1178 1145 543 SEG88 -4218 1145 623 SEG8 -7258 1145 703 COM33 -9155 -373
464 SEG167 -1216 1145 544 SEG87 -4256 1145 624 SEG7 -7296 1145 704 COM31 -9155 -411
465 SEG166 -1254 1145 545 SEG86 -4294 1145 625 SEG6 -7334 1145 705 COM29 -9155 -449
466 SEG165 -1292 1145 546 SEG85 -4332 1145 626 SEG5 -7372 1145 706 COM27 -9155 -487
467 SEG164 -1330 1145 547 SEG84 -4370 1145 627 SEG4 -7410 1145 707 COM25 -9155 -525
468 SEG163 -1368 1145 548 SEG83 -4408 1145 628 SEG3 -7448 1145 708 COM23 -9155 -563
469 SEG162 -1406 1145 549 SEG82 -4446 1145 629 SEG2 -7486 1145 709 COM21 -9155 -601
470 SEG161 -1444 1145 550 SEG81 -4484 1145 630 SEG1 -7524 1145 710 COM19 -9155 -639
471 SEG160 -1482 1145 551 SEG80 -4522 1145 631 COM175 -7600 1145 711 COM17 -9155 -677
472 SEG159 -1520 1145 552 SEG79 -4560 1145 632 COM173 -7638 1145 712 COM15 -9155 -715
473 SEG158 -1558 1145 553 SEG78 -4598 1145 633 COM171 -7676 1145 713 COM13 -9155 -753
474 SEG157 -1596 1145 554 SEG77 -4636 1145 634 COM169 -7714 1145 714 COM11 -9155 -791
475 SEG156 -1634 1145 555 SEG76 -4674 1145 635 COM167 -7752 1145 715 COM9 -9155 -829
476 SEG155 -1672 1145 556 SEG75 -4712 1145 636 COM165 -7790 1145 716 COM7 -9155 -867
477 SEG154 -1710 1145 557 SEG74 -4750 1145 637 COM163 -7828 1145 717 COM5 -9155 -905
478 SEG153 -1748 1145 558 SEG73 -4788 1145 638 COM161 -7866 1145 718 COM3 -9155 -943
479 SEG152 -1786 1145 559 SEG72 -4826 1145 639 COM159 -7904 1145 719 COM1 -9155 -981
480 SEG151 -1824 1145 560 SEG71 -4864 1145 640 COM157 -7942 1145
HD66766R Rev. 1.0-1 / September 2002 g HD66766R PAD Arrangement (LacedOutput Arrangement) n Chip size: 18.65mm×2.63mm n Chip thickness: 400µm (typ.) n Pad coordinate: Pad center n Coordinate origin: Chip center n Au bump size: (1) 80µm×80µm DUMMY1, DUMMY2, RESET1*~ ∼RESET3*, DUMMY10, DUMMY11 DUMMY12, DUMMY13 (2) 38µm×63µm COM1~COM176 SEG1~SEG396 n Au bump pitch: Refer to pad coordinate n Au bump hight: 15µm(typ.) n Numbers in the figure correspond to the number of pad coordinate. n Alignment mark (1) Arrangement: Two places @@Coordinate (X, Y) = (±9000, -1121) 30 40 30 30 40 30 100µm 100µm (2-a) Coordinate (X, Y) = (-9094, 1145) (2-b) Coordinate (X, Y) = (9094, 1145) (3-a) Coordinate (X, Y) = (-9004, 1145) (3-b) Coordinate (X, Y) = (9004, 1145) 50µm 20 50µm 10 25 25 10 10 25 25 10 5 5 70µm 70µm 80µm 80µm 10 25 25 10 10 25 25 10 70µm 70µm COMP COM3 COM5 COM7 COM99 COM101 COM103 COM105 DUMMY2 COM107 RESET1* COM109 CEP COM111 CEP COM113 CEM CEM VCL VCL VCL VCL VCH VCH VCH VCH C24+ C24+ C24- COM169 C24- COM171 C23+ COM173 C23+ COM175 C23- SEG1 C23- SEG2 C22+ SEG3 C22+ SEG4 C22- C22- C21+ C21+ C21- C21- VCI2 VCI2 VCI2 VCI2 GNDDUM1 GNDDUM4 DB15 NO.1 NO.666 HD667B66R TypeCode DB14 DB13 DB12 DB11 DB10 DB9 DB8 GNDDUM5 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI GNDDUM6 RW/RD* E/WR*/SCL GNDDUM7 RS CS* VCC VCC VCC VCC AVCC AVCC AVCC AVCC AGND AGND GND GND GND GND AGND AGND RESET2* HD667B66R Laced (Top View) Y X OSC2 OSC1 GNDDUM8 IM2 VCCDUM1 IM1 GNDDUM9 IM0/ID VCCDUM2 TEST2 TEST1 GNDDUM10 DUMMY3 DUMMY9 VREFL VREFL BIASC BIASC VREFM VREFM VM VM VM VM VSH VSH VSH VSH VOUT VOUT VOUT VOUT OSC0 OSC1 GNDDUM9 C12+ C12- SEG393 C12- SEG394 C12- SEG395 C12- SEG396 C11+ COM176 C11+ COM174 C11+ COM172 C11+ COM170 C11- C11- C11- C11- VCIOUT VCIOUT VCIOUT VCIOUT VCI1 VCI1 VCI1 VCI1 VCCDUM3 COM114 VCCDUM4 COM112 RESET3* COM110 DUMMY10 COM108 COM2 COM4 COM6 COM8 COM100 COM102 COM104 COM106 NO.145 NO.199 Figure 2 PAD arrangement (Laced)
HD66766R Rev. 1.0-1 / September 2002 Table 3 HD66766R PAD Coordinate (Laced)(No.1)
1 DUMMY1 -9193-1168 81OSC1 1284-1168 161COM32 9108-411 241SEG390 72961098 321SEG310 4256 1098
2DUMMY2 -8835-1168 82GNDDUM8 1440 -1168 162COM34 9201-373 242SEG389 72581191 322SEG309 4218 1191 3RESET1* -8678-1168 83IM2 1597-1168 163COM36 9108-335 243SEG388 72201098 323SEG308 4180 1098
4 CEP -8498-1168 84VCCDUM1 1754 -1168 164COM38 9201-297 244SEG387 71821191 324SEG307 4142 1191
5CEP -8398-1168 85IM1 1910-1168 165COM40 9108-259 245SEG386 7144 1098 325SEG306 4104 1098 6CEM -8298-1168 86GNDDUM9 2067-1168 166COM42 9201-221 246SEG385 71061191 326SEG305 4066 1191 7CEM -8198-1168 87IM0/ID 2223-1168 167COM44 9108-183 247SEG384 70681098 327SEG304 4028 1098 8VCL -8018-1168 88VCCDUM2 2380-1168 168COM46 9201-145 248SEG383 70301191 328SEG303 3990 1191 9VCL -7918-1168 89TEST2 2537-1168 169COM48 9108-107 249SEG382 69921098 329SEG302 3952 1098 10VCL -7818-1168 90TEST1 2693-1168 170COM50 9201 -69 250SEG381 69541191 330SEG301 3914 1191 11VCL -7718-1168 91GNDDUM10 2850-1168 171COM52 9108 -31 251SEG380 69161098 331SEG300 3876 1098 12VCH -7538-1168 92DUMMY3 3030-1168 172COM54 9201 7 252SEG379 68781191 332SEG299 3838 1191 13VCH -7438-1168 93DUMMY4 3130-1168 173COM56 9108 45 253SEG378 68401098 333SEG298 38001098
14 VCH -7338-1168 94DUMMY5 3230-1168 174COM58 9201 83 254SEG377 68021191 334SEG297 3762 1191
15VCH -7237-1168 95DUMMY6 3330-1168 175COM60 9108 121 255SEG376 67641098 335SEG296 3724 1098 16C24+ -7057-1168 96DUMMY7 3430-1168 176COM62 9201 159 256SEG375 67261191 336SEG295 3686 1191 17C24+ -6957-1168 97DUMMY8 3530-1168 177COM64 9108 197 257SEG374 66881098 337SEG294 3648 1098 18C24- -6857-1168 98DUMMY9 3630-1168 178COM66 9201 235 258SEG373 66501191 338SEG293 3610 1191 19C24- -6757-1168 99VREFL 3810-1168 179COM68 9108 273 259SEG372 66121098 339SEG292 3572 1098 20C23+ -6657-1168 100VREFL 3910-1168 180COM70 9201 311 260SEG371 65741191 340SEG291 3534 1191 21C23+ -6557-1168 101BIASC 4010-1168 181COM72 9108 349 261SEG370 65361098 341SEG290 3496 1098 22C23- -6457-1168 102BIASC 4110 -1168 182COM74 9201 387 262SEG369 64981191 342SEG289 3458 1191 23C23- -6357-1168 103VREFM 4211 -1168 183COM76 9108 425 263SEG368 64601098 343SEG288 3420 1098 24C22+ -6257-1168 104VREFM 4311 -1168 184COM78 9201 463 264SEG367 64221191 344SEG287 3382 1191 25C22+ -6157-1168 105VM 4411 -1168 185COM80 9108 501 265SEG366 63841098 345SEG286 3344 1098 26C22- -6057-1168 106VM 4511 -1168 186COM82 9201 539 266SEG365 63461191 346SEG285 3306 1191 27C22- -5957-1168 107VM 4611 -1168 187COM84 9108 577 267SEG364 63081098 347SEG284 3268 1098 28C21+ -5856-1168 108VM 4711 -1168 188COM86 9201 615 268SEG363 62701191 348SEG283 3230 1191 29C21+ -5756-1168 109VSH 4811-1168 189COM88 9108 653 269SEG362 62321098 349SEG282 3192 1098 30C21- -5576-1168 110VSH 4911 -1168 190COM90 9201 691 270SEG361 6194 1191 350SEG281 3154 1191 31C21- -5476-1168 111VSH 5011-1168 191COM92 9108 729 271SEG360 61561098 351SEG280 3116 1098 32VCI2 -5376-1168 112VSH 5111 -1168 192COM94 9201 767 272SEG359 61181191 352SEG279 3078 1191 33VCI2 -5276-1168 113VOUT 5291-1168 193COM96 9108 805 273SEG358 60801098 353SEG278 3040 1098
34 VCI2 -5176-1168 114VOUT 5391 -1168 194COM98 9201 843 274SEG357 60421191 354SEG277 3002 1191
35VCI2 -5076-1168 115VOUT 5491 -1168 195COM100 9108 881 275SEG356 60041098 355SEG276 2964 1098 36GNDDUM1 -4896-1168 116VOUT 5592-1168 196COM102 9201 919 276SEG355 59661191 356SEG275 2926 1191 37GNDDUM2 -4796-1168 117C12+ 5772-1168 197COM104 9108 957 277SEG354 59281098 357SEG274 28881098 38GNDDUM3 -4696-1168 118C12+ 5872-1168 198COM106 9201 995 278SEG353 58901191 358SEG273 28501191 39GNDDUM4 -4596-1168 119C12+ 5972-1168 199DUMMY12 91931183 279SEG352 58521098 359SEG272 2812 1098 40DB15 -4416 -1168 120C12+ 6072-1168 200COM108 88921191 280SEG351 58141191 360SEG271 2774 1191
41 DB14 -4259-1168 121C12- 6172-1168 201COM110 88541098 281SEG350 57761098 361SEG270 2736 1098
42DB13 -4103-1168 122C12- 6272-1168 202COM112 88161191 282SEG349 57381191 362SEG269 2698 1191
43 DB12 -3946-1168 123C12- 6372-1168 203COM114 87781098 283SEG348 57001098 363SEG268 2660 1098
44 DB11 -3789-1168 124C12- 6472-1168 204COM116 87401191 284SEG347 56621191 364SEG267 2622 1191
45DB10 -3633-1168 125C11+ 6572-1168 205COM118 87021098 285SEG346 56241098 365SEG266 2584 1098 46DB9 -3476-1168 126C11+ 6672-1168 206COM120 86641191 286SEG345 55861191 366SEG265 2546 1191 47DB8 -3320-1168 127C11+ 6772-1168 207COM122 86261098 287SEG344 55481098 367SEG264 25081098 48GNDDUM5 -3163-1168 128C11+ 6872-1168 208COM124 85881191 288SEG343 55101191 368SEG263 2470 1191 49DB7 -3006-1168 129C11- 6972-1168 209COM126 85501098 289SEG342 54721098 369SEG262 2432 1098 50DB6 -2850-1168 130C11- 7073-1168 210COM128 85121191 290SEG341 5434 1191 370SEG261 2394 1191 51DB5 -2693-1168 131C11- 7173-1168 211COM130 84741098 291SEG340 53961098 371SEG260 2356 1098 52DB4 -2537-1168 132C11- 7273-1168 212COM132 84361191 292SEG339 53581191 372SEG259 2318 1191 53DB3 -2380-1168 133VCIOUT 7453 -1168 213COM134 83981098 293SEG338 53201098 373SEG258 22801098 54DB2 -2223-1168 134VCIOUT 7553-1168 214COM136 83601191 294SEG337 52821191 374SEG257 2242 1191 55DB1/SDO -2067-1168 135VCIOUT 7653-1168 215COM138 83221098 295SEG336 5244 1098 375SEG256 2204 1098 56DB0/SDI -1910-1168 136VCIOUT 7753-1168 216COM140 82841191 296SEG335 52061191 376SEG255 2166 1191 57GNDDUM6 -1754 -1168 137VCI1 7933-1168 217COM142 82461098 297SEG334 51681098 377SEG254 2128 1098 58RW/RD* -1597-1168 138VCI1 8033-1168 218COM144 82081191 298SEG333 51301191 378SEG253 2090 1191 59E/WR*/SCL -1440 -1168 139VCI1 8133-1168 219COM146 81701098 299SEG332 50921098 379SEG252 2052 1098 60GNDDUM7 -1284-1168 140VCI1 8233-1168 220COM148 81321191 300SEG331 50541191 380SEG251 2014 1191 61RS -1127-1168 141VCCDUM3 8413-1168 221COM150 80941098 301SEG330 50161098 381SEG250 1976 1098 62CS* -971 -1168 142VCCDUM4 8513-1168 222COM152 80561191 302SEG329 49781191 382SEG249 1938 1191 63VCC -791 -1168 143RESET3* 8693-1168 223COM154 80181098 303SEG328 4940 1098 383SEG248 1900 1098 64VCC -690-1168 144 DUMMY10 8850-1168 224COM156 79801191 304SEG327 49021191 384SEG247 1862 1191 65VCC -590-1168 145DUMMY11 9193-1168 225COM158 79421098 305SEG326 48641098 385SEG246 1824 1098 66VCC -490-1168 146COM2 9201 -981 226COM160 79041191 306SEG325 48261191 386SEG245 1786 1191 67AVCC -390-1168 147COM4 9108 -943 227COM162 78661098 307SEG324 47881098 387SEG244 1748 1098 68AVCC -290-1168 148COM6 9201 -905 228COM164 78281191 308SEG323 47501191 388SEG243 1710 1191 69AVCC -190-1168 149COM8 9108 -867 229COM166 77901098 309SEG322 47121098 389SEG242 1672 1098 70AVCC -90-1168 150COM10 9201 -829 230COM168 77521191 310SEG321 4674 1191 390SEG241 1634 1191 71AGND 90 -1168 151COM12 9108 -791 231COM170 7714 1098 311SEG320 46361098 391SEG240 1596 1098 72AGND 190-1168 152COM14 9201 -753 232COM172 76761191 312SEG319 45981191 392SEG239 1558 1191 73GND 290-1168 153COM16 9108 -715 233COM174 76381098 313SEG318 45601098 393SEG238 1520 1098 74GND 390-1168 154COM18 9201 -677 234COM176 76001191 314SEG317 45221191 394SEG237 1482 1191 75GND 490 -1168 155COM20 9108 -639 235SEG396 75241098 315SEG316 4484 1098 395SEG236 1444 1098 76GND 590-1168 156COM22 9201 -601 236SEG395 74861191 316SEG315 4446 1191 396SEG235 1406 1191 77AGND 690-1168 157COM24 9108 -563 237SEG394 74481098 317SEG314 44081098 397SEG234 1368 1098 78AGND 791 -1168 158COM26 9201 -525 238SEG393 74101191 318SEG313 43701191 398SEG233 1330 1191 79RESET2* 971 -1168 159COM28 9108 -487 239SEG392 73721098 319SEG312 43321098 399SEG232 1292 1098 80OSC2 1127-1168 160COM30 9201 -449 240SEG391 7334 1191 320SEG311 4294 1191 400SEG231 1254 1191
HD66766R Rev. 1.0-1 / September 2002 Table 3 cont. HD66766R PAD Coordinate (Lacedj(No.2) No. pad nameX Y No. pad nameX Y No.pad nameX Y No.pad nameX Y X Y 401SEG230 1216 1098 481SEG150 -1862 1098 561SEG70 -49021098 641COM155 -79801191 -9000-1121 402SEG229 1178 1191 482SEG149 -1900 1191 562SEG69 -49401191 642COM153 -80181098 9000-1121 403SEG228 1140 1098 483SEG148 -1938 1098 563SEG68 -49781098 643COM151 -80561191 -9094 1145 404SEG227 1102 1191 484SEG147 -1976 1191 564SEG67 -50161191 644COM149 -80941098 9094 1145 405SEG226 1064 1098 485SEG146 -2014 1098 565SEG66 -50541098 645COM147 -81321191 -9004 1145 406SEG225 1026 1191 486SEG145 -2052 1191 566SEG65 -50921191 646COM145 -81701098 9004 1145 407SEG224 988 1098 487SEG144 -20901098 567SEG64 -51301098 647COM143 -82081191 408SEG223 950 1191 488SEG143 -21281191 568SEG63 -51681191 648COM141 -82461098 409SEG222 912 1098 489SEG142 -2166 1098 569SEG62 -52061098 649COM139 -82841191 410SEG221 874 1191 490SEG141 -2204 1191 570SEG61 -5244 1191 650COM137 -83221098
411 SEG220 836 1098 491SEG140 -2242 1098 571SEG60 -52821098 651COM135 -83601191
412SEG219 798 1191 492SEG139 -22801191 572SEG59 -53201191 652COM133 -83981098 413SEG218 760 1098 493SEG138 -2318 1098 573SEG58 -53581098 653COM131 -84361191
414 SEG217 722 1191 494SEG137 -2356 1191 574SEG57 -53961191 654COM129 -84741098
415SEG216 684 1098 495SEG136 -2394 1098 575SEG56 -5434 1098 655COM127 -85121191 416SEG215 646 1191 496SEG135 -2432 1191 576SEG55 -54721191 656COM125 -85501098 417SEG214 608 1098 497SEG134 -2470 1098 577SEG54 -55101098 657COM123 -85881191 418SEG213 570 1191 498SEG133 -25081191 578SEG53 -55481191 658COM121 -86261098 419SEG212 532 1098 499SEG132 -2546 1098 579SEG52 -55861098 659COM119 -86641191 420SEG211 494 1191 500SEG131 -2584 1191 580SEG51 -56241191 660COM117 -87021098 421SEG210 456 1098 501SEG130 -26221098 581SEG50 -56621098 661COM115 -87401191 422SEG209 418 1191 502SEG129 -2660 1191 582SEG49 -57001191 662COM113 -87781098 423SEG208 380 1098 503SEG128 -26981098 583SEG48 -57381098 663COM111 -88161191 424SEG207 342 1191 504SEG127 -2736 1191 584SEG47 -57761191 664COM109 -88541098 425SEG206 304 1098 505SEG126 -2774 1098 585SEG46 -58141098 665COM107 -88921191 426SEG205 266 1191 506SEG125 -28121191 586SEG45 -58521191 666DUMMY13 -91931183 427SEG204 228 1098 507SEG124 -28501098 587SEG44 -58901098 667COM105 -9201 995 428SEG203 190 1191 508SEG123 -28881191 588SEG43 -59281191 668COM103 -9108 957 429SEG202 152 1098 509SEG122 -2926 1098 589SEG42 -59661098 669COM101 -9201 919 430SEG201 114 1191 510SEG121 -2964 1191 590SEG41 -60041191 670COM99 -9108 881 431SEG200 76 1098 511SEG120 -3002 1098 591SEG40 -60421098 671COM97 -9201 843 432SEG199 38 1191 512SEG119 -3040 1191 592SEG39 -60801191 672COM95 -9108 805 433SEG198 -38 1098 513SEG118 -3078 1098 593SEG38 -61181098 673COM93 -9201 767
434 SEG197 -76 1191 514SEG117 -3116 1191 594SEG37 -61561191 674COM91 -9108 729
435SEG196 -114 1098 515SEG116 -3154 1098 595SEG36 -61941098 675COM89 -9201 691 436SEG195 -152 1191 516SEG115 -3192 1191 596SEG35 -62321191 676COM87 -9108 653 437SEG194 -190 1098 517SEG114 -3230 1098 597SEG34 -62701098 677COM85 -9201 615 438SEG193 -228 1191 518SEG113 -32681191 598SEG33 -63081191 678COM83 -9108 577 439SEG192 -266 1098 519SEG112 -3306 1098 599SEG32 -63461098 679COM81 -9201 539 440SEG191 -304 1191 520SEG111 -3344 1191 600SEG31 -63841191 680COM79 -9108 501
441 SEG190 -342 1098 521SEG110 -3382 1098 601SEG30 -64221098 681COM77 -9201 463
442SEG189 -380 1191 522SEG109 -3420 1191 602SEG29 -64601191 682COM75 -9108 425
443 SEG188 -418 1098 523SEG108 -3458 1098 603SEG28 -64981098 683COM73 -9201 387
444 SEG187 -456 1191 524SEG107 -3496 1191 604SEG27 -65361191 684COM71 -9108 349
445SEG186 -494 1098 525SEG106 -3534 1098 605SEG26 -65741098 685COM69 -9201 311 446SEG185 -532 1191 526SEG105 -3572 1191 606SEG25 -66121191 686COM67 -9108 273 447SEG184 -570 1098 527SEG104 -3610 1098 607SEG24 -66501098 687COM65 -9201 235 448SEG183 -608 1191 528SEG103 -3648 1191 608SEG23 -66881191 688COM63 -9108 197 449SEG182 -646 1098 529SEG102 -3686 1098 609SEG22 -67261098 689COM61 -9201 159 Alignment mark L (Negative) Cross Circle(Positive) Circle(Negative) L (Positive) 450SEG181 -684 1191 530SEG101 -3724 1191 610SEG21 -67641191 690COM59 -9108 121 451SEG180 -722 1098 531SEG100 -3762 1098 611SEG20 -68021098 691COM57 -9201 83 452SEG179 -760 1191 532SEG99 -38001191 612SEG19 -68401191 692COM55 -9108 45 453SEG178 -798 1098 533SEG98 -38381098 613SEG18 -68781098 693COM53 -9201 7 454SEG177 -836 1191 534SEG97 -3876 1191 614SEG17 -69161191 694COM51 -9108 -31 455SEG176 -874 1098 535SEG96 -3914 1098 615SEG16 -69541098 695COM49 -9201 -69 456SEG175 -912 1191 536SEG95 -3952 1191 616SEG15 -69921191 696COM47 -9108-107 457SEG174 -950 1098 537SEG94 -3990 1098 617SEG14 -70301098 697COM45 -9201-145 458SEG173 -988 1191 538SEG93 -4028 1191 618SEG13 -70681191 698COM43 -9108-183 459SEG172 -1026 1098 539SEG92 -4066 1098 619SEG12 -71061098 699COM41 -9201-221 460SEG171 -1064 1191 540SEG91 -4104 1191 620SEG11 -7144 1191 700COM39 -9108-259 461SEG170 -1102 1098 541SEG90 -4142 1098 621SEG10 -71821098 701COM37 -9201-297 462SEG169 -1140 1191 542SEG89 -4180 1191 622SEG9 -72201191 702COM35 -9108-335 463SEG168 -1178 1098 543SEG88 -4218 1098 623SEG8 -72581098 703COM33 -9201-373 464SEG167 -1216 1191 544SEG87 -4256 1191 624SEG7 -72961191 704COM31 -9108-411 465SEG166 -1254 1098 545SEG86 -4294 1098 625SEG6 -7334 1098 705COM29 -9201-449 466SEG165 -1292 1191 546SEG85 -4332 1191 626SEG5 -73721191 706COM27 -9108-487 467SEG164 -1330 1098 547SEG84 -4370 1098 627SEG4 -74101098 707COM25 -9201-525 468SEG163 -1368 1191 548SEG83 -4408 1191 628SEG3 -74481191 708COM23 -9108-563 469SEG162 -1406 1098 549SEG82 -4446 1098 629SEG2 -74861098 709COM21 -9201-601 470SEG161 -1444 1191 550SEG81 -4484 1191 630SEG1 -75241191 710COM19 -9108-639 471SEG160 -1482 1098 551SEG80 -4522 1098 631COM175 -76001191 711COM17 -9201-677 472SEG159 -1520 1191 552SEG79 -4560 1191 632COM173 -76381098 712COM15 -9108-715 473SEG158 -1558 1098 553SEG78 -4598 1098 633COM171 -76761191 713COM13 -9201-753 474SEG157 -1596 1191 554SEG77 -4636 1191 634COM169 -7714 1098 714COM11 -9108-791 475SEG156 -1634 1098 555SEG76 -4674 1098 635COM167 -77521191 715COM9 -9201-829 476SEG155 -1672 1191 556SEG75 -4712 1191 636COM165 -77901098 716COM7 -9108-867 477SEG154 -1710 1098 557SEG74 -4750 1098 637COM163 -78281191 717COM5 -9201-905 478SEG153 -1748 1191 558SEG73 -4788 1191 638COM161 -78661098 718COM3 -9108-943 479SEG152 -1786 1098 559SEG72 -4826 1098 639COM159 -79041191 719COM1 -9201-981 480SEG151 -1824 1191 560SEG71 -4864 1191 640COM157 -79421098
HD66766R Rev. 1.0-1 / September 2002 HD66766R Block Diagram Description Figure 3 HD66766R Block Diagram Description SEG1 to SEG396 RS RW/RD * E/WR*/SCL Vcc IM2-1, IM0/ID DB0/SDI, DB1/SDO, to DB15 CS* OSC1 OSC2 RESET * TEST1 COM1 to COM176 Timinig generator VSL GND Segment drivers TEST2 Index Register (IR) Control Register (CR) Address Counter ( AC ) Palette Register (RK, GK, BK) PWM Grayscale Circuit Bit Operation System Interface - 16 bit - 8 bit - Clock synchoronized - serial Read data latch Write data latch Latch Circuit Graphic RAM (GRAM) 46,464 bytes LCD drive power supply circuit Common driver Grayscale selector circuit Latch Circuit CPG Scan data generator circuit C11+ to C12+ C21+ to C24+ VSH VREFM CE+ CE- Vci2 VciOUT VM VCL BIASC VREFL C11- to C12- VOUT C21- to C24- VCH Vci1 AVcc
HD66766R Rev. 1.0-1 / September 2002 Pin Functions Table 4 Pin Functional Description Signals Number of Pins I/O Connected to Functions IM2-1, IM0/ID
3 I GND or VCC Selects the MPU interface mode:
IM2 IM1 IM0/ID0 MPU Interface mode GND GND GND 68 system 16-bit bus interface GND GND Vcc 68 system 8-bit bus interface GND Vcc GND 80 system 16-bit bus interface GND Vcc Vcc 80 system 8-bit bus interface Vcc GND ID Clock synchronized serial interface When a serial interface is selected, the IM0 pin is used as the ID setting for a device code. CS* 1 I MPU Selects the HD66766R: Low: HD66766R is selected and can be accessed High: HD66766R is not selected and cannot be accessed Must be fixed at GND level when not in use. RS 1 I MPU Selects the register. Low: Index/status High: Control For a register or a synchronous clock interface, fixed to the Vcc or GND level. E/WR*/SCL 1 I MPU For a 68-system bus interface, serves as an enable signal to activate data read/write operation. For an 80-system bus interface, serves as a write strobe signal and writes data at the low level. For a synchronous clock interface, serves as the synchronous clock signal. RW/RD* 1 I MPU For a 68-system bus interface, serves as a signal to select data read/write operation. Low: Write High: Read For an 80-system bus interface, serves as a read strobe signal and reads data at the low level. For a synchronous clock interface, fixed to the Vcc or GND level. DB0/SDI 1 I/O MPU Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the Vcc or GND level. For a clock-synchronous serial interface, serves as the serial data input pin (SDI). The input level is read on the rising edge of the SCL signal. DB1/SDO 1 I/O MPU Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the Vcc or GND level. For a clock-synchronous serial interface, serves as a serial data output pin (SDO). Successive bit values are output on the falling edge of the SCL signal.
HD66766R Rev. 1.0-1 / September 2002 Table 4 cont. Signals Number of Pins I/O Connected to Functions DB2-DB15 14 I/O MPU Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the Vcc or GND level. For a synchronous clock interface or unused pins, fixed to the Vcc or GND level. SEG1– SEG396 396 O LCD Output signals for segment drive. In the display-off period (D1–0 = 00, 01) or standby mode (STB = 1), all pins output GND level. The SGS bit can change the shift direction of the segment signal. For example, if SGS = 0, RAM address 0000 is output from SEG1. If SGS = 1, it is output from SEG396. SEG1, SEG4, SEG7, ... display red (R), SEG2, SEG5, display blue (B) (SGS = 0). COM1– COM176 176 O LCD Output signals for common drive. In the display-off period (D1–0 = 00, 01) sleep mode (SLP = 1) or standby mode (STB = 1), all pins output GND level. The CMS bit can change the shift direction of the common signal. For example, if CMS = 0, driver outputs from COM1 to COM176. If CMS = 1, driver outputs COM176 to COM1. Note that start position of the common driver output is changed by screen diving position function. VCH, VCL 2 — Capacitor for stabilization, shot key barrier diode or external power supply Selection level for the common signal. When internal power supply is used, connect the capacitors for stabilization to VCH AND VCL, and shot key barrier diode to VCL. When internal power supply is not used, supply external voltage. VM 1 — Capacitor for stabilization or external power supply Non-selection level for the common signal. When internal operational amplifier is used, it is output of the internal operational amplifier and connect the capacitors for stabilization. When internal operational amplifier is not used, supply external voltage. VSH 1 — Capacitor for stabilization or external power supply Selection level for the segment signal. When internal operational amplifier is used, it is output of the internal operational amplifier and connect the capacitors for stabilization. When internal operational amplifier is not used, supply external voltage. VciOUT 1 — Vci1 and capacitor for stabilization or open Outputs a regulated voltage derived from Vcc. Connect a capacitor for stabilization. When this pin is not used, leave it open. Vci1 1 — VciOUT or power supply Voltage-input pin for step-up circuit 1. When the Vci adjuster is used, input the power supply from VciOUT. When not used, input the external power supply. Vci2 1 — Capacitor for stabilization or open Connect capacitor for stabilization. When the internal power supply circuit is not used, leave this pin open. VOUT 1 — Step-up capacitance A voltage that doubles or triples the voltage between Vci1 and GND is output here. The step-up factor can be set in an internal register. C11+, C11- 2 — Step-up capacitance When step-up circuit is used, connect a step-up capacitor.
HD66766R Rev. 1.0-1 / September 2002 Table 4 cont. Signals Number of Pins I/O Connected to Functions C12+, C12- 2 — Step-up capacitance When step-up circuit is used, connect a step-up capacitor. C21+, C21- 2 — Step-up capacitance When step-up circuit is used, connect a step-up capacitor. C22+, C22- 2 — Step-up capacitance When step-up circuit is used, connect a step-up capacitor. C23+, C23- 2 — Step-up capacitance When step-up circuit is used, connect a step-up capacitor. C24+, C24- 2 — Step-up capacitance When step-up circuit is used, connect a step-up capacitor. CEP, CEM 2 — Step-up capacitance or open Connect a step-up capacitor to generate VCL level by VCH and VM. When step-up circuit is not used, leave this pin open. VREFL 1 — VCC or external power supply Inputs reference voltage for LCD drives power supply. Input lower level than Vcc. Since input current does not run, level input, which is divided by resistors, is also possible. VREFM 1 — Capacitor for stabilization or external power supply Connect capacitor for stabilization for internal power supply. When internal operational amplifier is not used, supply external voltage. BIASC 1 — Capacitor for stabilization or open Connect capacitor for stabilization for internal power supply. VCC, GND 2 — Power supply VCC: + 2.2 V to + 3.6 V; GND (logic): 0 V AVCC 1 — — VCC for power supply circuit. Input the same level of voltage as VCC. AGND 1 — — GND for power supply circuit. OSC1, OSC2 2 I/O Oscillation-resistor Connect an external resistor for R-C oscillation. When providing clocks from outside, input clock to OCS1 and leave OSC2 open. RESET* 1 I MPU or external R-C circuit Open unused pins Reset pin. Initializes the LSI when low. Must be reset after power-on. Since HCD66766RBP has three RESET pins, use one pin and open unused two pins. VccDUM 1 O Input pins Outputs the internal VCC level; shorting this pin sets the adjacent input pin to the VCC level. GNDDUM 1 O Input pins Outputs the internal GND level; shorting this pin sets the adjacent input pin to the GND level. Dummy 1 — — Dummy pad. Must be left disconnected. TEST1, TEST 2 2 I GND Test pin. Must be fixed at GND level.
HD66766R Rev. 1.0-1 / September 2002 Block Function Description System Interface The HD66766R has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16- bit/8-bit bus, and a Clock synchronized serial interface. The IM2-0 pins select the interface mode. The HD66766R has three 16-bit registers: an index register (IR), a write data register (WDR), and a read data register (RDR). The IR stores index information from the control registers and the GRAM. The WDR temporarily stores data to be written into control registers and the GRAM, and the RDR temporarily stores data read from the GRAM. Data written into the GRAM from the MPU is first written into the WDR and then is automatically written into the GRAM by internal operation. Data is read through the RDR when reading from the GRAM, and the first read data is invalid and the second and the following data are normal. Execution time for instruction excluding oscillation start is 0-clock cycle and instructions can be written in succession. Table 5 Register Selection (8/16 Parallel Interface) 80-series Bus 68-series Bus WR RD R/W RS Operations 0 1 0 0 Writes indexes into IR 1 0 1 0 Reads internal status 0 1 0 1 Writes into control registers and GRAM through WDR 1 0 1 1 Reads from GRAM through RDR Table 6 Register Selection (Clock synchronized Serial Interface) Start bytes R/W Bit RS Bit Operations 0 0 Writes indexes into IR 1 0 Reads internal status 0 1 Writes into control registers and GRAM through WDR 1 1 Reads from GRAM through RDR Bit Operation The HD66766R supports the following functions. A write data mask function that selects data into the GRAM in bit units, and a logic operation function that performs logic operations or conditional determination on the display data set in the GRAM and writes into the GRAM. With the 16-bit bus interface, these functions can greatly reduce the processing lord of the MPU graphics software the display data in the GRAM at high speed. For details, see the Graphics Operation Function section. Address Counter (AC) The address counter (AC) assigns address to the GRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing into the GRAM, the AC is automatically incremented by 1 (or decrement by 1). After reading from the GRAM, the AC is not updated.
HD66766R Rev. 1.0-1 / September 2002 Graphics RAM (GRAM) The graphics RAM (GRAM) has twelve bits/pixel and stores the bit-pattern data of 132 x 176 bytes. PWM Grayscale Palette Circuit The grayscale palette generates a PWM signal, which corresponds to specified grayscale level. Any 65K out of the 140K possible colors can be displayed at the same time. Grayscale Control Circuit The grayscale control circuit performs 16-grayscale control with the pulse width modulation (PWM) method for grayscale display for each color. Timing Generator The timing generator generates timing signals for the operation of internal circuits such as the GRAM. The RAM read timing for display and internal operation timing by MPU access is generated separately to avoid interference with one another. Oscillation Circuit (OSC) The HD66766R can provide R-C oscillation simply through the addition of an external oscillation-resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be reduced. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 176 common signal drivers (COM1 to COM176) and 396 segment signal drivers (SEG1 to SEG396). Display pattern data from GRAM is latched to the 396-bit latch circuit. The latched data then enables the segment signal drivers to generate drive waveform outputs. The common driver outputs one of the VCH, VM or VCL voltage level. The SGS bit can change the shift direction of 396-bit data for the segment. The CMS bit can also change the shift direction for the common by selecting an appropriate direction for the device-mounting configuration. When display is off, or during the standby or sleep mode, all the above common and segment signal drivers output the GND level, halting the display. LCD drive power supply circuit LCD drive power supply circuit generates VCH, VSH, VM and VCL voltage level to drive LCD panel.
HD66766R Rev. 1.0-1 / September 2002 GRAM ADDRESS DIAGRAM (HD66766R) Table 7 Relationship between GRAM address and display position (SGS = “0”) Table 8 Relationship between GRAM data and output pin GRAM DATA DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Selected palette PK palette PK palette + FRC PK palette Output pin SEG (3n+1) SEG (3n+2) SEG (3n+3) Note: n = Lower 8 bits address (0 to 131) SEG/COM pins DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB "A803"H "A903"H "AA03"H "AB03"H "AC03"H "AD03"H "AE03"H "AF03"H "A881"H "A981"H "AA81"H "AB81"H "AC81"H "AD81"H "AE81"H "AF81"H "A880"H "A980"H "AA80"H "AB80"H "AC80"H "AD80"H "AE80"H "AF80"H "A882"H "A982"H "AA82"H "AB82"H "AC82"H "AD82"H "AE82"H "AF82"H "A883"H "A983"H "AA83"H "AB83"H "AC83"H "AD83"H "AE83"H "AF83"H COM169 COM170 COM171 COM172 COM173 COM174 COM175 COM176 "AF00"H "A800"H "A900"H "AA00"H "AB00"H "AC00"H "AD00"H "AE00"H "A801"H "A901"H "AA01"H "AB01"H "AC01"H "AD01"H "AE01"H "AF01"H "A802"H "AA02"H "AB02"H "AC02"H "AD02"H "AE02"H "AF02"H "A902"HCOM7 COM6 COM5 COM4 COM3 COM2 COM1 COM8 "0081"H "0181"H "0281"H "0381"H "0481"H "0581"H "0681"H "0781"H "0881"H "0981"H "0A81"H "0B81"H "0C81"H "0D81"H "0E81"H "0F81"H "1081"H "1181"H "1281"H "1381"H "0080"H "0180"H "0280"H "0380"H "0480"H "0580"H "0680"H "0780"H "0880"H "0980"H "0A80"H "0B80"H "0C80"H "0D80"H "0E80"H "0F80"H "1080"H "1180"H "1280"H "1380"H CMS=1 COM176 COM175 COM174 COM173 COM172 COM171 COM170 COM169 COM168 COM167 COM166 COM165 COM164 COM163 COM162 COM161 COM160 COM159 COM157 COM158 "0000"H "0100"H "0200"H "0300"H "0400"H "0500"H "0700"H "0800"H "0600"H "0900"H "0A00"H "0B00"H "0C00"H "0D00"H "0E00"H "0F00"H "1000"H "1100"H "1200"H "1300"H "0101"H "0201"H "0401"H "0501"H "0901"H "0A01"H "0B01"H "0C01"H "0D01"H "0E01"H "1101"H "1201"H "1301"H "0001"H "0301"H "0601"H "0701"H "0801"H "0F01"H "1001"H "0602"H "0702"H "0802"H "0902"H "0A02"H "0B02"H "0C02"H "0D02"H "0E02"H "0F02"H "1002"H "1102"H "1202"H "1302"H "0002"H "0102"H "0202"H "0302"H "0402"H "0502"H "0003"H "0103"H "0303"H "0403"H "0503"H "0603"H "0703"H "0803"H "0903"H "0A03"H "0B03"H "0C03"H "0D03"H "0E03"H "0F03"H "1003"H "1103"H "1203"H "1303"H "0203"H "0082"H "0182"H "0282"H "0382"H "0482"H "0582"H "0682"H "0782"H "0882"H "0A82"H "0B82"H "0C82"H "0D82"H "0E82"H "0F82"H "0982"H "1082"H "1182"H "1282"H "1382"H "1383"H "0183"H "0283"H "0383"H "0483"H "0583"H "0683"H "0783"H "0883"H "0983"H "0A83"H "0B83"H "0C83"H "0D83"H "0E83"H "0F83"H "1083"H "1183"H "1283"H "0083"H COM3 CMS=0 COM1 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM2 S10 S11 S12 S385 S386 S387 S388 S389 S390 S391 S392 S393 S394 S395 S396
HD66766R Rev. 1.0-1 / September 2002 Table 9 Relationship between GRAM address and display position (SGS = “1”) Table 10 Relationship between GRAM data and output pin GRAM DATA DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Selected palette PK palette PK palette + FRC PK palette Output pin SEG (396-3n) SEG (395-3n) SEG (394-3n) Note: n = Lower 8 bits address (0 to 131) CMS=1 COM176 COM175 COM174 COM173 COM172 COM171 COM170 COM169 COM168 COM167 COM166 COM165 COM164 COM163 COM162 COM161 COM160 COM159 COM157 COM158 DB DB "0083"H "0183"H "0283"H "0383"H "0483"H "0583"H "0783"H "0883"H "0683"H "0983"H "0A83"H "0B83"H "0C83"H "0D83"H "0E83"H "0F83"H "1083"H "1183"H "1283"H "1383"H "0182"H "0282"H "0482"H "0582"H "0982"H "0A82"H "0B82"H "0C82"H "0D82"H "0E82"H "1182"H "1282"H "1382"H "0082"H "0382"H "0682"H "0782"H "0882"H "0F82"H "1082"H "0681"H "0781"H "0881"H "0981"H "0A81"H "0B81"H "0C81"H "0D81"H "0E81"H "0F81"H "1081"H "1181"H "1281"H "1381"H "0081"H "0181"H "0281"H "0381"H "0481"H "0581"H "0080"H "0180"H "0380"H "0480"H "0580"H "0680"H "0780"H "0880"H "0980"H "0A80"H "0B80"H "0C80"H "0D80"H "0E80"H "0F80"H "1080"H "1180"H "1280"H "1380"H "0280"H SEG/COM pins S10 S11 S12 S385 S386 S387 S388 S389 S390 S391 S392 S393 S394 S395 S396 "0003"H "0103"H "0203"H "0303"H "0403"H "0503"H "0603"H "0703"H "08030"H "0903"H "0A03"H "0B03"H "0C03"H "0D03"H "0E03"H "0F03"H "1003"H "1103"H "1203"H "1303"H "0002"H "0102"H "0202"H "0302"H "0402"H "0502"H "0602"H "0702"H "0802"H "0902"H "0A02"H "0B02"H "0C02"H "0D02"H "0E02"H "0F02"H "1002"H "1102"H "1202"H "1302"H "0001"H "0101"H "0201"H "0301"H "0401"H "0501"H "0601"H "0701"H "0801"H "0A01"H "0B01"H "0C01"H "0D01"H "0E01"H "0F01"H "0901"H "1001"H "1101"H "1201"H "1301"H "0100"H "0200"H "0300"H "0400"H "0500"H "0600"H "0700"H "0800"H "0900"H "0A00"H "0B00"H "0C00"H "0D00"H "0E00"H "0F00"H "1000"H "1100"H "1200"H "1300"H "0000"H CMS=0 COM1 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM2 "A880"H "A980"H "AA80"H "AB80"H "AC80"H "AD80"H "AE80"H "AF80"H "A802"H "A902"H "AA02"H "AB02"H "AC02"H "AD02"H "AE02"H "AF02"H "A803"H "A903"H "AA03"H "AB03"H "AC03"H "AD03"H "AE03"H "AF03"H "A801"H "A901"H "AA01"H "AB01"H "AC01"H "AD01"H "AE01"H "AF01"H "A800"H "A900"H "AA00"H "AB00"H "AC00"H "AD00"H "AE00"H "AF00"H COM169 COM170 COM171 COM172 COM173 COM174 COM175 COM176 "AF83"H "A883"H "A983"H "AA83"H "AB83"H "AC83"H "AD83"H "AE83"H "A882"H "A982"H "AA82"H "AB82"H "AC82"H "AD82"H "AE82"H "AF82"H "A881"H "AA81"H "AB81"H "AC81"H "AD81"H "AE81"H "AF81"H "A981"HCOM7 COM6 COM5 COM4 COM3 COM2 COM1 COM8 DB DB 150 DB DB 150 DB DB 150 DB DB 15 0 DB DB 150 DB DB 150 DB DB
HD66766R Rev. 1.0-1 / September 2002 Instructions Outline The HD66766R uses the 16-bit bus architecture. Before the internal operation of the HD66766R starts, control information is temporarily stored in the registers described below to allow high-speed interfacing with a high-performance microcomputer. The internal operation of the HD66766R is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signals (DB15 to DB0), make up the HD66766R instructions.
- There are eight categories of instructions that:
- Specify the index
- Read the status
- Control the display
- Control power management
- Process the graphics data
- Set internal GRAM addresses
- Transfer data to and from the internal GRAM
- Set grayscale level for the internal grayscale palette table Normally, instructions that write data are used the most. However, an auto-update of internal GRAM addresses after each data write can lighten the microcomputer program load. Because instructions are executed in 0 cycles, they can be written in succession.
HD66766R Rev. 1.0-1 / September 2002 Instruction Descriptions Index: IR The index instruction specifies the RAM control indexes (R00h to R3Fh). It sets the register number in the range of 000000 to 111001 in binary form. However, R40 to R44 are disabled since they are test registers. Figure 4 Index Instruction Status Read: SR The status read instruction reads the internal status of the HD66766R. L7–0: Indicate the driving raster-row position where the liquid crystal display is being driven. C6–0: Read the contrast setting values (CT6-0) Figure 5 Status Read Instruction Start Oscillation (R00h) The start oscillation instruction restarts the oscillator from the halt state in the standby mode. After issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (See the Standby Mode section.) If this register is read forcibly, “0766”H is read. Figure 6 Start Oscillation Instruction W 0 * * * * * * * * ID6 ID4 ID3 ID2 ID1 ID0 R/W RS DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15 * ID5 R R/W RS DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15
0 L6 L3 L2 L1 L0 0 C5 C3 C2 C1 C0L7 C6L5 L4 C4
R/W RS DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15 R 1 0 0 0 0 0 0 00 1 1 1 01 11 1
HD66766R Rev. 1.0-1 / September 2002 Driver Output Control (R01h) Figure 7 Driver Output Control Instruction CMS: Selects the output shift direction of a common driver. When CMS = 0, COM1 shifts to COM176. When CMS = 1, COM176 shifts to COM1. SGS: Selects the output shift direction of the segment driver. When SGS = 0, data are output SEG1 to SEG396. When SGS = 1, data are output SEG396 to SEG1. When SGS = 0, SEG1 pin assigns the color display to <R><G><B>. When S GS = 1, SEG396 pin assigns <R><G><B>. Re-write to the RAM when intending to change the SGS bit. NL4-0: Specify the LCD drive duty ratio. The duty ratio can be adjusted for every eight raster-rows. GRAM address mapping does not depend on the setting value of the drive duty ratio. w 1 0 R/W RS DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15 00 000 0 CMS SGS 0 0 NL4 NL3 NL2 NL1 NL0
HD66766R Rev. 1.0-1 / September 2002 Table 11 NL Bits and Drive Duty NL1 0 1 1 0 1 1 NL2 0 01 0 11 1 01 1 11 0 00 NL3 Display Size 0 101 NL4 1 0010 1 1010 0 0110 0 1110 1 0110 1 1110 0 0001 001 1 1 10 0 0 00 0 0 0 0 0 0 NL0 0 0 0 0 396 x 16 dots 396 x 24 dots 396 x 32 dots 396 x 40 dots 396 x 48 dots 396 x 56 dots 396 x 64 dots 396 x 72 dots 396 x 80 dots 396 x 88 dots 396 x 96 dots 396 x 104 dots 396 x 112 dots 396 x 120 dots 396 x 128 dots 396 x 136 dots 396 x 144 dots 396 x 152 dots 396 x 160 dots 396 x 168 dots 396 x 176 dots 1/16 Duty 1/24 Duty 1/32 Duty 1/40 Duty 1/48 Duty 1/56 Duty 1/64 Duty 1/72 Duty 1/80 Duty 1/88 Duty 1/96 Duty 1/104 Duty 1/112 Duty 1/120 Duty 1/128 Duty 1/136 Duty 1/144 Duty 1/152 Duty 1/160 Duty 1/168 Duty 1/176 Duty Common driver used CMS="0" CMS="1" 1/8 Duty 396 x 8 dots LCD drive duty cycle Com1 - Com8 Com1 - Com16 Com1 - Com24 Com1 - Com32 Com1 - Com40 Com1 - Com48 Com1 - Com56 Com1 - Com64 Com1 - Com72 Com1 - Com80 Com1 - Com88 Com1 - Com96 Com1 - Com104 Com1 - Com112 Com1 - Com120 Com1 - Com128 Com1 - Com136 Com1 - Com144 Com1 - Com152 Com1 - Com160 Com1 - Com168 Com1 - Com176 Com176 - Com169 Com176 - Com161 Com176 - Com153 Com176 - Com145 Com176 - Com137 Com176 - Com129 Com176 - Com121 Com176 - Com113 Com176 - Com105 Com176 - Com97 Com176 - Com89 Com176 - Com81 Com176 - Com73 Com176 - Com65 Com176 - Com57 Com176 - Com49 Com176 - Com41 Com176 - Com33 Com176 - Com25 Com176 - Com17 Com176 - Com9 Com176 - Com1
HD66766R Rev. 1.0-1 / September 2002 DC2-0: The operating frequency in the step-up circuit is selected. When the step-up operating frequency is high, the driving ability of the step-up circuit becomes high, but the current consumption is increased. Adjust the frequency considering the step-up ability and the current consumption. AP1–0: The amount of fixed current from the fixed current source in the operational amplifier for the LCD is adjusted. When the amount of fixed current is large, the LCD driving ability and the display quality become high, but the current consumption is increased. Adjust the fixed current considering the display quality and the current consumption. During no display, when AP1-0 = “00”, the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. VC2-0: Set an adjustment factor for the Vci1 voltage (VC2-0). SLP: When SLP = 1, the HD66766R enters the sleep mode, where the internal display operations are halted except for the R-C oscillator, thus reducing current consumption. Only the following instructions can be executed during the sleep mode. Power control (BS2–0, BT3-0, DC2–0, AP1–0, SLP, STB) During the sleep mode, the other GRAM data and instructions cannot be updated although they are retained. STB: When STB = 1, the HD66766R enters the standby mode, where display operation completely stops, halting all the internal operations including the internal R-C oscillator. Further, no external clock pulses are supplied. For details, see the Standby Mode section. Only the following instructions can be executed during the standby mode. a. Standby mode cancel (STB = “0”) b. Start oscillation During the standby mode, the GRAM data and instructions may be lost. To prevent this, they must be set again after the standby mode is canceled. The VSH voltage should be controlled to be less than supply voltage or device proof voltage level since VCH voltage level is generated by bias amplifier ratio corresponding to LCD driving bias value and boosting ratio of the step-up circuit 2.
HD66766R Rev. 1.0-1 / September 2002 Table 12 Display bias setting table Determine the LCD drive bias according to its display duty, and select combination of boosting ratio of the step-up circuit 2 and bias amplifier ratio so as not to exceed voltage control of Vci2 and VCH. See the LCD Voltage Generation Circuit regarding how to determine the LCD drive bias, VCH voltage and contrast adjustment for the following settings. LCD driving bias Booster ratio of the step-up circuit 2 (ND2) BS3 BS2 BS1 BS0 Bias ratio (NB) Vci2 (Vci2≤VOU T-0.5V) VCH (VCH≤22V) x 2 0 0 0 0 0.75 1.50 x VM Vci2 x 2 x 2 0 1 0 0 1.25 2.50 x VM Vci2 x 2 x 3 0 0 0 1 0.825 1.75 x VM Vci2 x 31/4 x 2 1 0 1 1 1.75 3.50 x VM Vci2 x 2 x 3 0 0 1 1 1.165 2.33 x VM Vci2 x 31/6 x 3 1 0 0 0 1.50 3.00 x VM Vci2 x 31/8 x 4 0 0 1 0 1.125 2.25 x VM Vci2 x 4 x 3 1 0 1 0 1.675 3.35 x VM Vci2 x 31/9 x 4 0 1 0 0 1.25 2.50 x VM Vci2 x 4 x 3 1 1 0 0 1.825 3.65 x VM Vci2 x 31/10 x 4 0 1 1 0 1.375 2.75 x VM Vci2 x 4 x 3 1 1 0 1 2.00 4.00 x VM Vci2 x 31/11 x 4 1 0 0 0 1.50 3.00 x VM Vci2 x 4 x 4 1 0 0 1 1.625 3.25 x VM Vci2 x 41/12 x 5 0 1 0 1 1.3 2.60 x VM Vci2 x 5 x 4 1 0 1 1 1.75 3.45 x VM Vci2 x 41/13 x 5 0 1 1 1 1.4 2.80 x VM Vci2 x 5
HD66766R Rev. 1.0-1 / September 2002 Table 13 Display bias setting table VC2 VC1 VC0 Vci1 control range 0 0 0 0.92 x Vcc 0 0 1 0.87 x Vcc 0 1 0 0.83 x Vcc 0 1 1 0.8 x Vcc 1 0 0 0.76 x Vcc 1 0 1 0.73 x Vcc 1 1 0 0.68 x Vcc 1 1 1 Vc i1 control amplifier suspends. (Vci1 can be supplied externally.) Table 14 AP bits and amount of fixed current AP1 AP0 Amount of fixed current in the operational amplifier 0 0 Operational amplifier and booster do not operate. 0 1 Small 1 0 Middle 1 1 Large Table 15 Output voltage ratio of the booster 1 and 2 BT2 BT1 BT0 VOUT output of the booster 1 (Use VOUT within the range of 4.0 to 5.75V.) VCH output of the booster 2 (Set VCH lower than 22.0V.) 0 0 0 2 x Vci1 2 x Vci2 0 0 1 3 x Vci1 2 x Vci2 0 1 0 2 x Vci1 3 x Vci2 0 1 1 3 x Vci1 3 x Vci2 1 0 0 2 x Vci1 4 x Vci2 1 0 1 3 x Vci1 4 x Vci2 1 1 0 2 x Vci1 5 x Vci2 1 1 1 3 x Vci1 5 x Vci2 Set the factor of the booster 2 according to voltage of Vci2 and VCH. When the factor is set low, current consumption can be lowered.
HD66766R Rev. 1.0-1 / September 2002 Table 16 Operating clock frequency of the Booster 1 and 2 DC2 DC1 DC0 Operating clock frequency in the booster 1 Operating clock frequency in the voltage inverting circuit and the booster 2 0 0 0 32-divided clock 32-divided clock 0 0 1 64-divided clock 32-divided clock 0 1 0 32-divided clock 64-divided clock 0 1 1 64-divided clock 64-divided clock 1 0 0 32-divided clock 96-divided clock 1 0 1 64-divided clock 96-divided clock 1 1 0 32-divided clock 128-divided clock 1 1 1 64-divided clock 128-divided clock Operation of voltage inverting circuit Table 17 BT3 VCL output of the voltage inverting circuit (Set VCL no lower than –22.0V.)
0 Halt boosting
1 Output voltage between VCH and VM by inverting
Set activation of voltage inverting circuit with output of the booster 2 stable. *See the Power-on/off Sequence section. DB 15 Contrast Control (R04h) Figure 10 Contrast Control Instruction CT6–0: These bits control the LCD drive voltage to adjust 128-step contrast. Table 18 Contrast control CT6 CT5 CT4 CT3 CT2 CT1 CT0 Contrast 0 0 0 0 0 0 0 1.016R (Minimum) 0 0 0 0 0 0 1 1.008R 0 0 0 0 0 1 0 1.000R 0 0 0 0 0 1 1 0.992R 0 0 0 0 1 0 0 0.984R : : : : : : : : : : : : : : : 1 1 1 1 1 1 0 0.008R 1 1 1 1 1 1 1 0.000R (Maximum) R/W RS DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15 W 1 0 CT1 CT0CT2CT3CT4CT50 0 0 0 CT60 VR0VR1VR2
HD66766R Rev. 1.0-1 / September 2002 VR2–0: These bits amplifies 1.1 to 3.4 times the VREFL as output voltage VREFM of LCD drive reference voltage generation circuit. The VREFM should be smaller than VOUT level. Table 19 Contrast control VR2 VR1 VR0 VREFM voltage 0 0 0 VREFL x 1.1 0 0 1 VREFL x 1.3 0 1 0 VREFL x 1.4 0 1 1 VREFL x 1.5 1 0 0 VREFL x 1.7 1 0 1 VREFL x 1.8 1 1 0 VREFL x 3.4
HD66766R Rev. 1.0-1 / September 2002 LG2-0: Compare the data read from the GRAM by the microcomputer with the compare resisters (CP15- 0) by a compare/logical operation and writes the results to GRAM. For details, see the Logical/Compare Operation Function. CP15-0: Set the compare resister for the compare operation with the data read from the GRAM or written by the microcomputer. Figure 13 Logical/Compare Operation for the GRAM Write data mask (WM15-0) GRAM Logical/compare operation (LG2 - 0) Write data mask * (WM15 - 0) DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15 0 0 0 1 1 1 0 0 1 1 1 00000Write data sent from the microcomputer (DB15-0) Logical operation (with compare resister) LG2-0 = "110”: Replacement of matched write data LG2-0 = "111”: Replacement of unmatched writes data Note: The write data mask ( WM15-0 ) is set by the resister in the (20) RAM Write Data Mask section.
HD66766R R ev. 1.0-1 / September 2002 Display Control (R07h) Figure 14 Display Control VLE2–1: When VLE1 = 1, a vertical scroll is performed in the 1st screen. When VLE2 = “1”, a vertical scroll is performed in the 2nd screen. Vertical scrolling on the two screens can be independently controlled. SPT: When SPT = 1, the 2-division LCD drive is performed. For details, see the Screen-division Driving Function section. B/W: When B/W = “1”, displayed data can be “all” or “all off” regardless GRAM contents. (B/W = “1”, REV = “0”: all pixel on, B/W = “1”, REV = “1”: all pixel off) When B/W = “1”, grayscale palette has to be default value. REV: Displays all character and graphics display sections with reversal when REV = 1. For details, see the Reversed Display Function section. Since the grayscale level can be reversed, display of the same data is enabled on normally-white and normally-black panels. D1–0: Display is on when D1 = “1” and off when D1 = 0. When off, the display data remains in the GRAM, and can be displayed instantly by setting D1 = “1”. When D1 is “0”, the display is off with all of the SEG/COM pin outputs set to the GND level. Because of this, the HD66766 R can control the charging current for the LCD with AC driving. When D1–0 = “01”, the internal display of the HD66766R is performed although the display is off. When D1-0 = “00”, the internal display operation halts and the display is off. Table 20 D Bits and Operation D1 D0 SEG/COM Output HD66766R Internal Display Operation 0 0 GND Halt 0 1 GND Operate 1 0 Unlit display Operate 1 1 Display Operate Notes: 1. Writing from the microcomputer to the GRAM is independent from the state of D1–0. 2. In the sleep and standby modes, D1–0 = 00. However, the register contents of D1 –0 are not modified. R/W RS DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15 W 1 D0VLE200000 REVVLE1 0 0 0 B/WSPT D10
HD66766R R ev. 1.0-1 / September 2002 Frame Cycle Control (R0Bh) Figure 15 RTN3-0: Set the line retrace period (RTN3-0) to be added to raster-row cycles. The raster-row cycle becomes long according to the number of clocks set at RTN3-0. DIV1-0: Set the division ratio of clocks for internal operation (DIV1-0). Internal operations are driven by clocks which are frequency divided according to the DIV1-0 setting . Frame frequency can be adjusted along with the line retrace period (RTN3-0). When changing the drive-duty, adjust the frame frequency. For details, see the Frame Frequency Adjustment Function section. Table 21 RTN Bits and Clock Cycles Table 22 DIV Bits and Clock Frequency Formula for the frame frequency R/W RS DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15 W 1 RTN0RTN1RTN2RTN30000000000 DIV0DIV1 DIV1 DIV0 Division ratio 0 1 2 1 0 4 1 1 8 fosc / 1 fosc / 2 fosc / 4 fosc / 8 * fosc=R-C oscillation frequency Internal Operation Clock Frequency Frame frequency = fosc Clock cycles per raster-row xdivision ratio x 1/duty cycle [Hz] fosc: RC oscillation frequency Duty: Drive duty (NL bit) Division ratio: DI V bit Clock cycles per raster-row: (RTN+26) clock RTN2 RTN1 RTN1 0 0 0 clock 26 clock 0 0 1 1 clock 27 clock 0 1 0 2 clock 28 clock 0 1 1 3 clock 29 clock 1 1 0 14 clock 40 clock 1 1 1 15 clock 41 clock Line retrace period (Clock Cycles) Clock Cycles per one raster-row RTN3 : : : : : :
HD66766R R ev. 1.0-1 / September 2002 Vertical Scroll Control (R11h) Figure 16 Vertical Scroll Control Instruction VL17-10: Specify the display-start raster-row at the 1st screen display for vertical smooth scrolling. Any raster-row from the first to 176 th can be selected. After the 176 th raster-row is displayed, the display restarts from the first raster-row. The display-start raster-row (VL17-10) is valid only when VLE1 = “1”. The raster-row display is fixed when VLE1 = “0”. (VLE1 is the 1 st-screen vertical-scroll enable bit.) VL27-20: Specify the display-start raster-row at the 2 nd screen display. The display-start raster-row (VL27-20) is valid only when VLE2 = “1”. The raster-row display is fixed when VLE2 = “0”. (VLE2 is the 1st-screen vertical-scroll enable bit.) Table 23 R/W RS DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15 W 1 VL11 VL10VL12VL16 VL15 VL14 VL13VL21 VL20VL22VL26 VL25 VL24 VL23VL27 VL17 VL11 VL10 Display start line 0 0 1'st raster - row 0 1 1 0 VL12 1 0 1 1 VL13 VL14 VL15 VL16 VL21 VL20VL22VL23VL24VL25VL26 VL17 VL27 Note: Do not set over the 176th ("AF"H ) raster - row 2'nd raster - row 3'rd raster - row 175'th raster - row176'th raster - row : : : : : : : : :
HD66766R R ev. 1.0-1 / September 2002 Table 25 GRAM data setting R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 Grayscale palette 0 0 0 0 0 0 PK05 PK04 PK03 PK02 PK01 PK00 0 0 0 0 1 0 PK15 PK14 PK13 PK12 PK11 PK10 0 0 0 1 0 0 PK25 PK24 PK23 PK22 PK21 PK20 0 0 0 1 1 0 PK35 PK34 PK33 PK32 PK31 PK30 0 0 1 0 0 0 PK45 PK44 PK43 PK42 PK41 PK40 0 0 1 0 1 0 PK55 PK54 PK53 PK52 PK51 PK50 0 0 1 1 0 0 PK65 PK64 PK63 PK62 PK61 PK60 0 0 1 1 1 0 PK75 PK74 PK73 PK72 PK71 PK70 0 1 0 0 0 0 PK85 PK84 PK83 PK82 PK81 PK80 0 1 0 0 1 0 PK95 PK94 PK93 PK92 PK91 PK90 0 1 0 1 0 0 PK105 PK104 PK103 PK102 PK101 PK100 0 1 0 1 1 0 PK115 PK114 PK113 PK112 PK111 PK110 0 1 1 0 0 0 PK125 PK124 PK123 PK122 PK121 PK120 0 1 1 0 1 0 PK135 PK134 PK133 PK132 PK131 PK130 0 1 1 1 0 0 PK145 PK144 PK143 PK142 PK141 PK140 0 1 1 1 1 0 PK155 PK154 PK153 PK152 PK151 PK150 1 0 0 0 0 0 PK165 PK164 PK163 PK162 PK161 PK160 1 0 0 0 1 0 PK175 PK174 PK173 PK172 PK171 PK170 1 0 0 1 0 0 PK185 PK184 PK183 PK182 PK181 PK180 1 0 0 1 1 0 PK195 PK194 PK193 PK192 PK191 PK190 1 0 1 0 0 0 PK205 PK204 PK203 PK202 PK201 PK200 1 0 1 0 1 0 PK215 PK214 PK213 PK212 PK211 PK210 1 0 1 1 0 0 PK225 PK224 PK223 PK222 PK221 PK220 1 0 1 1 1 0 PK235 PK234 PK233 PK232 PK231 PK230 1 1 0 0 0 0 PK245 PK244 PK243 PK242 PK241 PK240 1 1 0 0 1 0 PK255 PK254 PK253 PK252 PK251 PK250 1 1 0 1 0 0 PK265 PK264 PK263 PK262 PK261 PK260 1 1 0 1 1 0 PK275 PK274 PK273 PK272 PK271 PK270 1 1 1 0 0 0 PK285 PK284 PK283 PK282 PK281 PK280 1 1 1 0 1 0 PK295 PK294 PK293 PK292 PK291 PK290 1 1 1 1 0 0 PK305 PK304 PK303 PK302 PK301 PK300 1 1 1 1 1 0 PK315 PK314 PK313 PK312 PK311 PK310 Note: When G0 = 1, selective grayscale for G pixel is the middle grayscale between the upper grayscale and the selective grayscale.
HD66766R Rev. 1.0-1 / September 2002 Gray Scale Palette Control (R30h to R3Fh) Table 26 Grayscale Palette Control Instruction PK31–0: Specify the grayscale level for thirty-two palettes from the 52-grayscale level. For details, see the Grayscale Palette and the Grayscale Palette Table sections. R/W RS DB7 DB0DB6 DB5 DB4 DB3 DB2 DB1DB8DB9DB10DB11DB12DB13DB14DB15 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R3A R3B R3C R3D R3E R3F PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK 112 PK 111 PK 110 PK 102 PK 101 PK 100 PK 113 PK 103 PK 114 PK 104 PK 115 PK 105 PK 132 PK 131 PK 130 PK 122 PK 121 PK 120 PK 133 PK 123 PK 134 PK 124 PK 135 PK 125 PK 152 PK 151 PK 150 PK 142 PK 141 PK 140 PK 153 PK 143 PK 154 PK 144 PK 155 PK 145 PK 172 PK 171 PK 170 PK 162 PK 161 PK 160 PK 173 PK 163 PK 174 PK 164 PK 175 PK 165 PK 192 PK 191 PK 190 PK 182 PK 181 PK 180 PK 193 PK 183 PK 194 PK 184 PK 195 PK 185 PK 212 PK 211 PK 210 PK 202 PK 201 PK 200 PK 213 PK 203 PK 214 PK 204 PK 215 PK 205 PK 232 PK 231 PK 230 PK 222 PK 221 PK 220 PK 233 PK 223 PK 234 PK 224 PK 235 PK 225 PK 252 PK 251 PK 250 PK 242 PK 241 PK 240 PK 253 PK 243 PK 254 PK 244 PK 255 PK 245 PK 272 PK 271 PK 270 PK 262 PK 261 PK 260 PK 273 PK 263 PK 274 PK 264 PK 275 PK 265 PK 292 PK 291 PK 290 PK 282 PK 281 PK 280 PK 293 PK 283 PK 294 PK 284 PK 295 PK 285 PK 312 PK 311 PK 310 PK 302 PK 301 PK 300 PK 313 PK 303 PK 314 PK 304 PK 315 PK 305 PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK PK 150 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 0 0 0 0W 1 PK PK PK PK PK PK PK PK PK PK PK PK
HD66766R Rev. 1.0-1 / September 2002 Instruction List (HD66766R) Table 27 Upper Code Lower Code Reg. No. Register Name R/ W RS DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
0 Description
IR Index 0 0 * * * * * * * * * ID6 ID5 ID4 ID3 ID2 ID1 ID0 Sets the index register value. 0 Note1 SR Status read 1 0 L7 L6 L5 L4 L3 L2 L1 L0 0 C6 C5 C4 C3 C2 C1 C0 Reads the driving raster-row position (L7–0) and contrast setting (C6–0). R00h Start oscillation ms Note1 Device code read 1 1 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 Reads 0766H. 0 R01h Driver output control 0 1 0 0 0 0 0 0 CM S SGS 0 0 0 NL4 NL3 NL2 NL1 NL0 Sets the common driver shift direction (CMS), segment driver shift direction (SGS) and driving duty ratio (NL4–0). R02h LCD- driving- waveform control 0 1 0 0 0 0 0 RST B/C EOR 0 0 NW NW NW NW NW NW Sets LCD drive AC waveform (B/C), and EOR output (EOR) or the number of n-raster-rows (NW5–0) at C-pattern AC drive. R03h Power control 1 0 1 BS3 BS2 BS1 BS0 BT3 BT2 BT1 BT0 0 DC2 DC1 DC0 AP1 AP0 SLP STB Sets the sleep mode (SLP), standby mode (STB), LCD power on (AP1– 0), boosting cycle (DC2–0), boosting output multiplying factor (BT2–0), operation of voltage inverting circuit (BT3) and LCD drive bias value (BS3–0). R04h Contrast control 0 1 0 0 0 0 0 VR2 VR1 VR0 0 CT6 CT5 CT4 CT3 CT2 CT1 CT0 Sets the regulator adjustment (VR2– 0) and contrast adjustment (CT6–0). R05h Entry mode 0 1 SPR 0 0 0 0 0 HWM 0 0 0 I/D1 I/D0 AM LG2 LG1 LG0 Specifies AC counter mode (AM), increment/decrement mode (I/D1– 0), high-speed write mode (HWM).
0 Note2
CP9 CP8 CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0 Specifies the compare resister (CP15-0), R07h Display control 0 1 0 0 0 0 0 VLE2 VLE1 SPT 0 0 0 0 B/W REV D1 D0 Specifies display on (D1-0), black- and-white reversed display (REV), pixel on/off mode (ALB), screen division driving (SPT) and vertical scroll .(VLE2-1) R0Bh Frame frequency control 0 1 0 0 0 0 0 0 DIV DIV 0 0 0 0 RTN RTN RTN RTN Specifies the line retrace period (RTN3–0) and operating clock frequency division ratio (DIV1–0). R0Ch Power control 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 VC2 VC1 VC0 Sets the adjustment factor for the Vci voltage (VC2–0). R11h Vertical scroll control 0 1 VL2 VL2 VL2 VL2 VL2 VL2 VL2 VL2 VL1 VL1 VL1 VL1 VL1 VL1 VL1 VL1 Sets the 1st screen display start raster- row (VL17-10) and 2nd screen display start raster-row (VL27-20). R14h 1st screen driving position 0 1 SE SE SE SE SE SE SE SE SS SS SS SS SS SS SS SS Sets the 1st screen driving start position (SS17–10) and 1st screen driving end position (SE17–10). R15h 2nd screen driving position 0 1 SE SE SE SE SE SE SE SE SS SS SS SS SS SS SS SS Sets 2nd screen driving start position (SS27–20) and 2nd screen driving end position (SE27–20). R16h Horizontal RAM address position 0 1 HE HEA HEA HEA HEA HEA HEA HEA HSA HSA HSA HSA HSA HSA HSA HSA Sets start (HSA7–0) and end (HEA7–0) of the horizontal RAM address range. R17h Vertical RAM address position 0 1 VEA VEA VEA VEA VEA VEA VEA VEA VSA VSA VSA VSA VSA VSA VSA VSA Sets start (VSA7–0) and end (VEA7–0) of the vertical RAM address range. R20h RAM write data mask 0 1 WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM Specifies write data mask (WM15– 0) at RAM write.
HD66766R Rev. 1.0-1 / September 2002 Instruction List (cont.) Upper Code Lower Code Reg. No. Register Name R/ W RS DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 0 1 AD15–8 (upper) AD6–0 (lower) Initially set the RAM address to the address counter (AC). R22 RAM data write 0 1 Write data (upper) Write data (lower) Writes data to the RAM. 0 RAM data read 1 1 Read data (upper) Read data (lower) Reads data from the RAM. 0 R30h Grayscale palette control (1) 0 1 0 0 PK15 PK14 PK13 PK12 PK11 PK10 0 0 PK05 PK04 PK03 PK02 PK01 PK00 Specifies the grayscale palette. 0R31h Grayscale palette control (2) 0 1 0 0 PK35 PK34 PK33 PK32 PK31 PK30 0 0 PK25 PK24 PK23 PK22 PK21 PK20 Specifies the grayscale palette. 0 R32h Grayscale palette control (3) 0 1 0 0 PK55 PK54 PK53 PK52 PK51 PK50 0 0 PK45 PK44 PK43 PK42 PK41 PK40 Specifies the grayscale palette. 0 R33h Grayscale palette control (4) 0 1 0 0 PK75 PK74 PK73 PK72 PK71 PK70 0 0 PK65 PK64 PK63 PK62 PK61 PK60 Specifies the grayscale palette. 0 R34h Grayscale palette control (5) 0 1 0 0 PK95 PK94 PK93 PK92 PK91 PK90 0 0 PK85 PK84 PK83 PK82 PK81 PK80 Specifies the grayscale palette. 0R35h Grayscale palette control (6) 0 1 0 0 PK 115 PK 114 PK 113 PK 112 PK 111 PK 110 0 0 PK 105 PK 104 PK 103 PK 102 PK 101 PK 100 Specifies the grayscale palette. 0R36h Grayscale palette control (7) 0 1 0 0 PK 135 PK 134 PK 133 PK 132 PK 131 PK 130 0 0 PK 125 PK 124 PK 123 PK 122 PK 121 PK 120 Specifies the grayscale palette. 0R37h Grayscale palette control (8) 0 1 0 0 PK 155 PK 154 PK 153 PK 152 PK 151 PK 150 0 0 PK 145 PK 144 PK 143 PK 142 PK 141 PK 140 Specifies the grayscale palette. 0 R38h Grayscale palette control (9) 0 1 0 0 PK 175 PK 174 PK 173 PK 172 PK 171 PK 170 0 0 PK 165 PK 164 PK 163 PK 162 PK 161 PK 160 Specifies the grayscale palette. 0R39h Grayscale palette control (10) 0 1 0 0 PK 195 PK 194 PK 193 PK 192 PK 191 PK 190 0 0 PK 185 PK 184 PK 183 PK 182 PK 181 PK 180 Specifies the grayscale palette. 0R3Ah Grayscale palette control (11) 0 1 0 0 PK 215 PK 214 PK 213 PK 212 PK 211 PK 210 0 0 PK 205 PK 204 PK 203 PK 202 PK 201 PK 200 Specifies the grayscale palette. 0R3Bh Grayscale palette control (12) 0 1 0 0 PK 235 PK 234 PK 233 PK 232 PK 231 PK 230 0 0 PK 225 PK 224 PK 223 PK 222 PK 221 PK 220 Specifies the grayscale palette. 0 R3Ch Grayscale palette control (13) 0 1 0 0 PK 255 PK 254 PK 253 PK 252 PK 251 PK 250 0 0 PK 255 PK 244 PK 243 PK 242 PK 241 PK 240 Specifies the grayscale palette. 0 R3Dh Grayscale palette control (14) 0 1 0 0 PK 275 PK 274 PK 273 PK 272 PK 271 PK 270 0 0 PK 265 PK 264 PK 263 PK 262 PK 261 PK 260 Specifies the grayscale palette. 0R3Eh Grayscale palette control (15) 0 1 0 0 PK 295 PK 294 PK 293 PK 292 PK 291 PK 290 0 0 PK 285 PK 284 PK 283 PK 282 PK 281 PK 280 Specifies the grayscale palette. 0R3Fh Grayscale palette control (16) 0 1 0 0 PK 315 PK 314 PK 313 PK 312 PK 311 PK 310 0 0 PK 305 PK 304 PK 303 PK 302 PK 301 PK 300 Specifies the grayscale palette. 0Note: 1. “*” means doesn’t matter. 2. High-speed write mode is available only for the RAM writing.
HD66766R Rev. 1.0-1 / September 2002 Reset Function The HD66766R is internally initialized by RESET input. Reset the gate driver/Power supply IC as its settings are not automatically reinitialized when the HD66766R is reset. The reset input must be held for at least 200 ms. Do not access the GRAM or initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10 ms). Instruction Set Initialization: 1. Start oscillation executed 2. Driver output control (NL4–0 = “10101”, SGS = “0”, CMS = “0”) 3. B-pattern waveform AC drive (B/C = “0”, EOR = “0”, NW5–0 = “000000”) 4. Power control 1 (DC2–0 = “000”, AP1–0 = “00”: LCD power off, STB = “0”: Standby mode off, 5. Contrast control (Weak contrast VR3-0 = “0000”, CT6-0 = “0000000”) 6. Entry mode set ( SPR= “0” , HWM = “0”, I/D1-0 = “11”: Increment by 1, AM = “0”: Horizontal move, LG2-0=”000”:Replace mode ) 7. Compare resister : (CP15-0 = “0000000000000000” 8. Display control (VLE2–1 = “00”: No vertical scroll, SPT = “0”, REV = “0”, D1–0 = “00”: Display off) 9. Frame cycle control (DIV1-0 = “00”: 1-divided clock, RTN3-0: No line retrace period) 10. Power control 2 (VC2-0 = “000”) 11. Vertical scroll (VL27–20 = “00000000”, VL17–10 = “00000000”) 12. 1st screen division (SE17-10 = “11111111”, SS17-10 = “00000000”) 13. 2nd screen division (SE27-20 = “11111111”, SS27-20 = “00000000”) 14. Horizontal RAM address position (HEA7-0 = “10000011”, HSA7-0 = “00000000”) 15. Vertical RAM address position (VEA7-0 = “10101111”, VSA7-0 = “00000000”) 16. RAM write data mask (WM11–0 = “000”H: No mask) 17. RAM address set (AD15–0 = “0000”H) 18. Grayscale Palette PK16 = “011000”, PK17= “011001”, PK18= “011010”, PK19= “011011”, PK24= “100010”, PK25= “100100”, PK26= “100110”, PK27= “101000” , GRAM Data Initialization: This is not automatically initialized by reset input but must be initialized by software while display is off (D1–0 = “00”). Output Pin Initialization: 1. LCD driver output pins (SEG/COM): Output GND level 2. Oscillator output pin (OSC2): Output oscillation signal
HD66766R Rev. 1.0-1 / September 2002 Note: Transfer synchronization function for an 8-bit bus interface The HD667 66R supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a “00”H instruction four times. The next transfer starts from the upper eight bits. Executing synchronization function periodically can recover any runaway in the display system Figure 28 8-bit Transfer Synchronization RS R / W E DB15 to DB8 Upper Lower 8-bit transfer synchronization (1) (2) (3) (4) Upper or lower
HD66766R Rev. 1.0-1 / September 2002 Serial Data Transfer Setting the IM 2 pin to the “Vcc” level and the IM 1 pin to the “GND” level allows standard clock- synchronized serial data transfer, using the chip select line (CS*), serial transfer clock line (SCL), serial input data line (SDI), and serial output data line (SDO). For a serial interface, the IM0/ID pin function uses an ID pin. If the chip is set up for serial interface, the DB15-2 pins which are not used must be fixed at “Vcc” or “GND”. The HD66766R initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It ends serial data transfer at the rising edge of CS* input. The HD66766R is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the HD6676 6R. The HD6676 6R, when selected, receives the subsequent data string. The least significant bit of the identification code can be determined by the ID pin. The five upper bits must be “01110”. Two different chip addresses must be assigned to a single HD6676 6R because the seventh bit of the start byte is used as a register select bit (RS): that is, when RS = “0”, data can be written to the index register or status can be read, and when RS = “1”, an instruction can be issued or data can be written to or read from RAM. Read or write is selected according to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is “0”, and is transmitted when the R/W bit is “1”. After receiving the start byte, the HD66766 R receives or transmits the subsequent data byte-by-byte. The data is transferred with the MSB first. All HD66766R instructions are 16 bits. Two bytes are received with the MSB first (DB15 to 0), then the instructions are internally executed. After the start byte has been received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is fetched internally as the lower eight bits of the instruction. Five bytes of RAM read data after the start byte are invalid. The HD66766R starts to read correct RAM data from the sixth byte. Table 28 Start Byte Format Transfer Bit S 1 2 3 4 5 6 7 8 Device ID code Start byte format Transfer start 0 1 1 1 0 ID RS R/W Note: The IM0/ID pin selects ID bit. Table 29 RS and R/W Bit Function RS R/W Function 0 0 Sets index register 0 1 Reads status 1 0 Writes instruction or RAM data 1 1 Reads RAM data
HD66766R Rev. 1.0-1 / September 2002 Note the following when using high-speed RAM write mode. Notes: 1. The logical and compare operation cannot be used. 2. Data is written to RAM each four words. When an address is set, the lower two bits in the address must be set to the following values. *When I/D0=0, the lower two bits in the address must be set to “11” and be written to RAM. *When I/D0=1, the lower two bits in the address must be set to “00” and be written to RAM. 3. Data is written to RAM each four words. If less than four words of data is written to RAM, the last data will not be written to RAM. 4. When the index registe r and RAM data write ( “22”H) have been selected, the data is always written first. RAM cannot be written to and read from at the same time. HWM must be set to “0” while RAM is being read. 5. High-speed and normal RAM write operations cannot be executed at the same time. The mode must be switched and the address must then be set. 6. When high-speed RAM write is used with a window address-range specified, dummy write operation may be required to suit the window address range-specification. Refer to the High- Speed RAM Write in the Window Address section. Table 30 Comparison between Normal and High-Speed RAM Write Operations Normal RAM Write (HWM=0) High-Speed RAM Write (HWM=1) Logical operation function Can be used Cannot be used Compare operation function Can be used Cannot be used Write mask function Can be used Can be used RAM address set Can be specified by word ID0 bit=0: Set the lower two bits to 11 ID0 bit=1: Set the lower two bits to 00 RAM read Can be read by word Cannot be used RAM write Can be written by word Dummy write operations may have to be inserted according to a window address- range specification Window address Can be set by word Can be set by four words
HD66766R Rev. 1.0-1 / September 2002 High-Speed RAM Write in the Window Address When a window address range is specified, RAM data which is in an optional window area can be rewritten consecutively and quickly by inserting dummy write operations so that RAM access counts become 4N as shown in the tables below. Dummy write operations may have to be inserted as the first or last operations for a row of data, depending on the horizontal window-address range specification bits (HSA1 to 0, HEA1 to 0). The number of dummy write operations of a row must be 4N. Table 31 Number of Dummy Write Operations in High-Speed RAM Write (HSA Bits) HSA1 HSA0 Number of Dummy Write Operations to be Inserted at the Start of a Row 0 0 0 0 1 1 1 0 2 1 1 3 Table 32 Number of Dummy Write Operations in High-Speed RAM Write (HEA Bits) HEA1 HEA0 Number of Dummy Write Operations to be Inserted at the End of a Row 0 0 3 0 1 2 1 0 1 1 1 0 Each row of access must consist of 4 x N operations, including the dummy writes. Horizontal access count = first dummy write count + write data count + last dummy write count = 4 x N
HD66766R Rev. 1.0-1 / September 2002 An example of high-speed RAM write with a window address-range specified is shown below. The window address-range can be rewritten to consecutively and quickly by inserting two dummy writes at the start of a row and three dummy writes at the end of a row, as determined by using the window address-range specification bits (HSA1 to 0= “10”, HEA1 to 0= “00”). Figure 35 Example of the High-Speed RAM write with a window address-range specification Note1) The address set for the high-speed RAM write must be 00 or 11 according to the value of I/D0 bit. Only RAM in the speicfied window address-range will be overwritten. h0000 hAF83 GRAM address map hA030 Window address-range setting HSA=h12, HEA=h30 VSA=h08, VEA=hA0 High-speed RAM write mode setting HWM=1 Address set AD=h0810 Note 1) Dummy RAM write x 2 RAM write x 31 Dummy RAM write x 3 x 152 h0812 Window address-range specification (rewrite area) Writing in the horizontal direction AM=0, I/D0=1 Window address-range setting HSA=h12, HEA=h30 VSA=h08, VEA=hA0
HD66766R Rev. 1.0-1 / September 2002 Window Address Function When data is written to the on-chip GRAM, a window address-range which is specified by the horizontal address register (start: HSA7-0, end: HEA7-0) or the vertical address register (start: VSA7-0, end: VEA7- 0) can be written to consecutively. Data is written to addresses in the direction specified by the AM bit (increment/decrement). When image data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this. The window must be specified to be within the GRAM address area described below. Addresses must be set within the window address. [Restriction on window address-range settings] (horizontal direction) “00”H ≤ HSA7-0 ≤ HEA7-0 ≤ “83”H (vertical direction) “00”H ≤ VSA7-0 ≤ VEA7-0 ≤ “AF”H [Restriction on address settings during the window address] (RAM address) HSA7-0 ≤ AD7-0 ≤ HEA7-0 VSA7-0 ≤ AD15-8 ≤ VEA7-0 Note: In high-speed RAM-write mode, the lower two bits of the address must be set as shown below according to the value of the ID0 bit. ID0 =0: The lower two bits of the address must be set to “11”. ID0 =1: The lower two bits of the address must be set to “00” AF00H AF83H 0000H 0083H 202FH 5F10H 5F2FH 2110H GRAM address map I/D0=1 (increment) AM=0 (horizontal writing) Window address area 2010H 212FH Window address-range specification area HSA5-0=10H, HSE5-0=2FH VSA7-0=20H, VEA7-0=5FH Figure 36 Example of Address Operation in the Window Address Specification
HD66766R Rev. 1.0-1 / September 2002 Graphic Operation Function The HD66766R can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and internal graphics-bit operation function. This function supports the following: 1. A write data mask function that selectively rewrites some of the bits in the 16-bit write data. 2. A conditional write function that compares the write data and compare-bit data and writes the data sent from the microcomputer only when the conditions match. Even if the display size is large, the display data in the graphics RAM ( GRAM ) can be quickly rewritten. The graphics bit operation can be controlled by combining the entry mode resister. The bit set value of the RAM-write –data mask resister, and the write from the microcomputer. Table 33 Graphics operation Figure 37 Graphics Operation flow +1/-1 Microcomputer Write data latch Logical / compare operation (LG2 - 0:) 000: replaceme nt bit. Only RAM in the110: replacement with matched write, 111: replacement with unmatched write Write bit mask Graphic RAM ( GRAM ) Logical operation bit ( LG2 - 0 ) Compare bit ( CP7 - 0 ) Write mask register ( WM15 - 0 ) Address counter ( AC ) + 256 Bit Setting I/D AM LG2-0 Operation and UsageOperation Mode Write mode 1 Horizontal data replacement, horizontal - border drawing Write mode 2 Write mode 3 Write mode 4 Vertical data replacement, vertical - border drawing Conditional horizontal data replacement, horisontal - border drawing Conditional vertical data replacement, vertical - border drawing 000 110,111 110,111
HD66766R Rev. 1.0-1 / September 2002 Write-data Mask Function The HD66766R has a bit-wise write-data mask function that controls writing the 1 6-bit data from the microcomputer to the GRAM. Bits that are “0” in the write-data mask register (WM1 5–0) cause the corresponding DB bit to be written to the GRAM. Bits that are “1” prevent writing to the corresponding GRAM bit to the GRAM; the data in the GRAM is retained. This function can be used when only one- pixel data is rewritten or the particular display color is selectively rewritten. Figure 38 Write-data Mask Function Operation Data written by the microcomputer DB15 Write data mask WM15 WMO DB11 DB0 GRAM data DB0 R02 R01 R00R03 G00 B02 B01 B00B03R04 G02 G01G03G04G05 B04 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 * * * * * G05 G04 G03 G02 G01 * * * B02 B01 B00
HD66766R Rev. 1.0-1 / September 2002 Graphics Operation Processing 1. Write mode 1: AM = 0, LG2-0 = “000” This mode is used when the data is horizontally written at high speed. It can also be used to initialize the graphics RAM ( GRAM ) or to draw borders. The write-data mask function ( WM15-0 ) are also enabled in these operations. After writing, the address counter ( AC ) automatically increments by 1 ( I/D = 1 ) or decrements by 1 ( I/D = 0 ) , and automatically jumps to the counter edge one-raster below after it has reached the left or right edge of the GRAM. Figure 39 Writing Operation of Write Mode 1 Write data mask: WM15 WM0 "Write mask for plane G and B. Write data (1) : DB15 DB0 Write data (2) : "0000"H "0001"H Write data (1) Write data (2) GRAM "0002"H Note: The bits in the GRAM indicated by (*) are not changed. Operation Examples: 2) WM15-0 = "07FF"H 3) AC = "0000"H 0 0 0 0 0 1 1 1 1 1 1 1 1 11 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0
HD66766R Rev. 1.0-1 / September 2002 2. Write mode 2: AM = 1, LG2-0 = “000” This mode is used when the data is vertically written at high speed. It can also be used to initialize the GRAM, develop the font pattern in the vertical direction, or draw borders. The write-data mask function ( WM15-0 ) are also enabled in these operations. After writing, the address counter ( AC ) automatically increments by 256, and automatically jumps to the upper-right edge ( I/D =1 ) or upper- left egde ( I/D = 0 ) following the I/D bit after it has reached the lower edge of the GRAM. Figure 40 Operation of Write Mode 2 WM15 WM0 Write- data mask: Write data (1): Write data (2): Write data (3): DB15 DB0 "0000"H "0100"H "0200"H Write data (1) Write data (2) Write data (3) GRAM Notes: 1. The bit area data in the GRAM indicated by (*) is not changed. 2. After writing to address " AF00"H the AC jumps to "0001"H. Operation Examples: 2) WM15-0 = "07FF"H 3) AC = "0000"H 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1
HD66766R Rev. 1.0-1 / September 2002 3. Write mode 3: AM = 0, LG2-0 = 110/111 This mode is used when the data is holizontally written by comparing the write data and the set value of the compare resister ( CP7-0 ). When the result of the comparison in a byte unit satisfies the condition write-data mask function ( WM15-0 ) are also enabled. After writing , the address counter ( AC ) automatically increments by 1 ( I/D =1 ) or decrements by 1 ( I/D = 0 ), and automatically jumps to the counter edge one-raster-raw below after it has reached the left or right edge of the GRAM. Figure 41 Operation of Write Mode 3 WM15 WM0 0 0 0 0 0 0 0 0 0 0 0 0 DB15 DB0 "0000"H "0001"H GRAM 0 0 0 0 1 1 1 1 0 0 0 0 Compare operation CP15 CP0 0 1 0 1 0 0 1 1 Replacement C R (Matched) Conditional replacement 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 00000 * * * * 0 1 0 1 0 0 1 1 0 0 0 00000 * * * * Operation Examples: 1) I/D = "1", AM = "0" , LG2-0 = "110" ( Matched write ) 3) AC = "0000"H Write - data mask : Compare register : Conditional replacement R Compare operation Write data (1) : Write data (2) : Matched replacement of write data (1) C
HD66766R Rev. 1.0-1 / September 2002 4. Write mode 4: AM = 1, LG2-0 = 110/111 This mode is used when a vertical comparison is performed between the write data and the set value of the compare resister ( CP15-0 ) to write the data . When the result by the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the GRAM. In this operation, write data mask function ( WM15-0 ) are also enabled. After writing, the address counter ( AC ) automatically increments by 256, and automatically jumps to the upper-right edge ( I/D = 1) or upper-left edge ( I/D = 0 ) following the I/D bit after it has reached the lower edge of the GRAM. Figure 42 Writing Operation of Write Mode 4 Operation Examples: 1) I/D = "1", AM = "1" , LG2-0 = "111" ( Unmatched write ) 3) AC = "0000"H WM15 WM0 0 0 0 0 0 0 0 0 0 0 0 0 DB15 1 0 0 1 1 0 0 1 CP15 CP0 0 0 1 0 1 0 0 0 C C R R ( Unmatched ) ( Unmatched ) 1 0 0 1 1 0 0 1 GRAM "0000"H "0100"H "AF00"H "0000"H "0001"H 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 * * * * Write - data mask : Compare register : Write data (1) : Write data (2) : Compare operation Conditional replacement Conditional replacement Compare operation Notes: 1. The bit area data in the GRAM indicated by (*) is not changed. 2. After writing to address "AF00"H the AC jumps to "0001"H. Write data (1) Write data (2) DB0
HD66766R Rev. 1.0-1 / September 2002 4096 colors Display Function HD66766R is equipped with 4096 colors display function. When setting SPR bit = 1, it operates 4096 color display function, and uses 16 bits instead of 12 bits. Upper 4 bits are invalid when operating 4096 colors display function. While operating 4096 colors display function, write mode 3 and 4 in graphic operation are not usable. Table 34 4,096 color R, G, B data and selective grayscale palette R, G, B data Selective grayscale palette R, G, B data Selective grayscale palette
0000 PK0 1000 PK17
0001 PK2 1001 PK19
0010 PK4 1010 PK21
0011 PK6 1011 PK23
0100 PK8 1100 PK25
0101 PK10 1101 PK27
0110 PK12 1110 PK29
0111 PK14 1111 K31
46,464 byte Write data 4096 color format RAM write data 65k format RAM write DB15 DB0 DB0DB15 0 0 R30 0 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 R3 R2 R1 R0 G3 G 2G 1G0 B3 B2 B1 B0B4R4 G 4G5 Read data 4096 color format RAM read data 65k format RAM read DB15 DB0 DB0DB15 0 0 R30 0 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1B4R4 G4G5 Figure 43 4096 color display data write and read format
HD66766R Rev. 1.0-1 / September 2002 Grayscale Palette The HD66766R incorporates a grayscale palette to simultaneously display 65K of the 140,608 possible colors. The grayscales consist of 32 6-bit palettes. The 52-stage grayscale levels can be selected from the 6-bit palette data. For the display data, the four-bit data in the GRAM written from the microcomputer is used. In this palette, a pulse-width control system (PWM) is used to eliminate flicker in the LCD display. The time over which the LCDs are switched on is adjusted according to the level and grayscales are displayed so that flicker is reduced and grayscales are clearly displayed. Figure 44 Grayscale Palette Control Display data MSB LSB Graphic RAM ( GRAM ) R2 R1 R0R3R4 G2 G1 G0G3G4G5 B1 B0B3 B2B4 6 5 52 gray scale control <R> 52 gray scale control <G> LCD Driver R G B LCD 32 ¨64 gray scale 3232 52 gray scale control <B> LCD Driver LCD Driver <RGB> Palette Palette register Initialized value PK0 (5\0) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0000 0 0 1 0 0 0 0 0 1 0 1 0 0 01 10 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 "00000" "00001" "00010" "00011" "00100" "00101" "00110" "00111" "01000" "01001" "01010" 0 1 0 0 01 PK1 (5\0) PK2 (5\0) PK3 (5\0) PK4 (5\0) PK5 (5\0) PK6(5\0) PK7 (5\0) PK8 (5\0) PK9 (5\0) PK10 (5\0) 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 0 0 00 1 1 0 00 1 1 1 00 1 1 0 1 00 1 1 1 10 1 1 0 0 10 1 1 0 1 PK11 (5\0) "01100" "01011" "01110" "01111" "10000" "10001" "10010" "10011" "10100" "10101" "01101" 0 1 0 1 0 0 PK12 (5\0) PK13 (5\0) PK14 (5\0) PK15 (5\0) PK16 (5\0) PK17(5\0) PK18 (5\0) PK19 (5\0) PK20 (5\0) PK21 (5\0) 01 1 1 1 0 0 01 1 1 0 01 1 0 0 0 01 1 0 1 1 1 1 0 0 0 1 1 1 0 0 01 10 1 1 1 0 0 0 0 0 01 0 0 01 1 0 "11101" "11010" "11011" "11100" "11110" "11111" "10110" "10111" "11000" "11001" 1 0 010 0 PK22 (5\0) PK23 (5\0) PK24 (5\0) PK25 (5\0) PK26 (5\0) PK27 (5\0) PK28(5\0) PK29 (5\0) PK30 (5\0) PK31 (5\0)
HD66766R Rev. 1.0-1 / September 2002 Grayscale Palette Table The grayscale register that is set for each palette register (PK) can be set to any level. 52-grayscale lighting levels can be set according to palette values (“000000” to “110100”). Table 35 Grayscale Control Level Palette Register Value (PK) Grayscale Control Level 0 0 0 0 0 0 Unlit level*1 0 0 0 0 0 1 1/52level 0 0 0 0 1 0 2/52level 0 0 0 0 1 1 3/52level 0 0 0 1 0 0 4/52level 0 0 0 1 0 1 5/52level 0 0 0 1 1 0 6/52level 0 0 0 1 1 1 7/52level 0 0 1 0 0 0 8/52level 0 0 1 0 0 1 9/52level 0 0 1 0 1 0 10/52level 0 0 1 0 1 1 11/52level 0 0 1 1 0 0 12/52level 0 0 1 1 0 1 13/52level 0 0 1 1 1 0 14/52level 0 0 1 1 1 1 15/52level 0 1 0 0 0 0 16/52level 0 1 0 0 0 1 17/52level 0 1 0 0 1 0 18/52level 0 1 0 0 1 1 19/52level 0 1 0 1 0 0 20/52level 0 1 0 1 0 1 21/52level 0 1 0 1 1 0 22/52level 0 1 0 1 1 1 23/52level 0 1 1 0 0 0 24/52level 0 1 1 0 0 1 25/52level 0 1 1 0 1 0 26/52level 0 1 1 0 1 1 27/52level 0 1 1 1 0 0 28/52level 0 1 1 1 0 1 29/52level 0 1 1 1 1 0 30/52level 0 1 1 1 1 1 31/52level 1 0 0 0 0 0 32/52level à Next Page continued
HD66766R Rev. 1.0-1 / September 2002 1 0 0 0 0 1 33/52level 1 0 0 0 1 0 34/52level 1 0 0 0 1 1 35/52level 1 0 0 1 0 0 36/52level 1 0 0 1 0 1 37/52level 1 0 0 1 1 0 38/52level 1 0 0 1 1 1 39/52level 1 0 1 0 0 0 40/52level 1 0 1 0 0 1 41/52level 1 0 1 0 1 0 42/52level 1 0 1 0 1 1 43/52level 1 0 1 1 0 0 44/52level 1 0 1 1 0 1 45/52level 1 0 1 1 1 0 46/52level 1 0 1 1 1 1 47/52level 1 1 0 0 0 0 48/52level 1 1 0 0 0 1 49/52level 1 1 0 0 1 0 50/52level 1 1 0 0 1 1 51/52level 1 1 0 1 0 0 All lit level*2 Notes: 1. The unlit level corresponds to a black display when a normally-black color-LCD panel is used, and a white display when a normally-white color-LCD panel is used. 2. The all-lit level correspon ds to a white display when a normally-black color-LCD panel is used, and a black display when a normally-white color-LCD panel is used
HD66766R Rev. 1.0-1 / September 2002 RGB pixel data and Grayscale level Table 36 G pixel data and output level G pixel data Output level G pixel data Output level
000000 PK0 100000 PK16
000001 (PK0+PK1)/2 100001 (PK16+PK17)/2
000010 PK1 100010 PK17
000011 (PK1+PK2)/2 100011 (PK17+PK18)/2
000100 PK2 100100 PK18
000101 (PK2+PK3)/2 100101 (PK18+PK19)/2
000110 PK3 10110 PK19
0000111 (PK3+PK4)/2 100111 (PK19+PK20)/2
001000 PK4 101000 PK20
001001 (PK4+PK5)/2 101001 (PK20+PK21)/2
001010 PK5 101010 PK21
001011 (PK5+PK6)/2 101011 (PK21+PK22)/2
001100 PK6 101100 PK22
001101 (PK6+PK7)/2 101101 (PK22+PK23)/2
001110 PK7 101110 PK23
001111 (PK7+PK8)/2 101111 (PK23+PK24)/2
010000 PK8 110000 PK24
0100001 (PK8+PK9)/2 110001 (PK24+PK25)/2
010010 PK9 110010 PK25
010011 (PK9+PK10)/2 110011 (PK25+PK26)/2
010100 PK10 110100 PK26
010101 (PK10+PK11)/2 110101 (PK26+PK27)/2
010110 PK11 110110 PK27
010111 (PK11+PK12)/2 110111 (PK27+PK28)/2
011000 PK12 111000 PK28
011001 (PK12+PK13)/2 111001 (PK28+PK29)/2
011010 PK13 111010 PK29
011011 (PK13+PK14)/2 111011 (PK29+PK30)/2
011100 PK14 111100 PK30
011101 (PK14+PK15)/2 111101 (PK30+PK31)/2
011110 PK15 111110 PK31
011111 (PK15+PK16)/2 111111 PK31
HD66766R Rev. 1.0-1 / September 2002 Table 37 R, B pixel data and output level R, B pixel data Output level R, B pixel data Output level
00000 PK0 10000 PK16
00001 PK1 10001 PK17
00010 PK2 10010 PK18
00011 PK3 10011 PK19
00100 PK4 10100 PK20
00101 PK5 10101 PK21
00110 PK6 10110 PK22
00111 PK7 10111 PK23
01000 PK8 11000 PK24
01001 PK9 11001 PK25
01010 PK10 11010 PK26
01011 PK11 11011 PK27
01100 PK12 11100 PK28
01101 PK13 11101 PK29
01110 PK14 11110 PK30
01111 PK15 11111 PK31
HD66766R Rev. 1.0-1 / September 2002 Setting flow for low power consumption instruction Sleep Mode Setting the sleep mode bit (SLP) to “1” puts the HD66766R in the sleep mode, where the device stops all internal display operations, thus reducing current consumption. Specifically, LCD operation is completely halted. Here, all the SEG (SEG1 to SEG396) and COM (COM1 to COM176) pins output the “GND” level, resulting in no display. If the AP1-0 bits in the power control register are set to “00” in the sleep mode, the LCD drive power supply can be turned off, reducing the total current consumption of the LCD module. Table 38 Comparison of Sleep Mode and Standby Mode Function Sleep Mode (SLP = “1”) Standby Mode (STB = “1”) LCD control Turned off Turned off R-C oscillation circuit Operates normally Operation stopped Master/slave signal Operation stopped Operation stopped Standby Mode Setting the standby mode bit (STB) to “1” puts the HD66766R in the standby mode, where the device stops completely, halting all internal operations including the R-C oscillation circuit, thus further reducing current consumption compared to that in the sleep mode. Specifically, all the SEG (SEG1 to SEG396) and COM (COM1 to COM176) pins for the time-sharing drive output the GND level, resulting in no display. If the AP1-0 bits are set to “00” in the standby mode, the LCD drive power supply can bet turned off. During the standby mode, no instructions can be accepted other than the start-oscillation instruction. To cancel the standby mode, issue the start-oscillation instruction to stabilize R-C oscillation before setting the STB bit to “0”. When multi-chips are operated, be sure to be set to the standby mode from the slave level. Figure 45 Procedure for Setting and Canceling Standby Mode Set stand-by mode: STB = "1" Wait at least 10 ms Cancel stand-by mode: STB = "0" Turn on the LCD power supply: AP0-1 = 01/10/11 Turn off the display: D1-0 = "01" Turn on the display: D1-0 = "11" See the power supply circuit setting. Turn off the LCD power supply: AP1-0 = "00" Issue the start-oscillation instruction Wait at least 150 ms Procedure for Setting and Canceling Standby Mode Stand-by mode
HD66766R Rev. 1.0-1 / September 2002 Setting flow for power supply and display instruction Power-on / off Sequence To prevent pulse lighting of LCD screens at power-on/off, the power-on/off sequence is activated as shown below. However, since the sequence depends on LCD materials to be used, confirm the conditions by using your own system. Power supply circuit off control set by AP1-0 voltage polarity inverting circuit operation starting bit Set : BT3-1 = "1" Issue use-state instruction (1) 1ms more than 10ms (oscillation circuit stabilization time) more than 200ms (set-up circuit 2 / voltage inverting circuit stabilization time) Set BS3-0 bit Set VR2-0 bit Display on Issue other mode setting instruction (3) Power on Initialized bits D1-0="11" Bits for display on Note) Power on the Vcc Power on the Reset Set CT6-0 bit Set VC2-0 bit Set BT2-0 bit Set DC2-0 bit Set AP1-0 bit more than 50ms (set-up circuit 1, 2 stabilization time) Issue use-state instruction (2) Display on Sequence Display off sequence Normal display Power off setting bit Bits for display off Display off D1-0="00" use-state instruction Power off the Vcc Power On sequence Power Off sequence Figure 46 Power-on Sequence Figure 47 Power-off Sequence
HD66766R Rev. 1.0-1 / September 2002 Power-off sequence Normal case Issue LCD power instruction Turn off the display: D1-0 = 00 Turn off the power voltages : Vcc To the power on sequence Emergency case RESET = "L" To the power on sequence Driver SEG/COM output: GND level Turn off the power voltage: Vcc Power voltage : Vcc Vcc GND Vcc GND V1OUT GND Turn off the power voltage RESET is input as soon as possible. Driver SEG/COM output RESET Note: When hardware reset is input during the power-off period, the D1-0 bits are cleared to "00" and SEG/COM output is forcibly lowered to the GND levels. Figure 48 Power-off sequence
HD66766R Rev. 1.0-1 / September 2002 Partial Sequence Setting Flow BT2-0 bit setting (Note) BS3-0 bit setting DC2-0 bit setting VR2-0 bit setting CT6-0 bit setting Note: Change only BT2-0 with BT3-0 = “1” more than 200ms Step-up circuit output stabilizing time Power supply setting change BT2-0 bit setting (Note) BS3-0 bit setting DC2-0 bit setting VR2-0 bit setting CT6-0 bit setting Issue instruction for other mode setting Partial display Display OFF Display On D1-0="11" Display on Display OFF D1-0 =”00” Display Duty change Frame frequency adjustment Normal display NL-4-0 bit setting DIV, RTN bit setting Display OFF Display off D1-0 = “01” Power supply setting change more than 200ms Step-up circuit output stabilizing time Issue instruction for other mode setting Normal display Display OFF Display On D1-0="11" Display on Display OFF D1-0 =”00” Display Duty change Frame frequency adjustment Partial display NL-4-0 bit setting Display off D1-0 = “01”Display OFF DIV, RTN bit setting Figure 49 Normal to partial display Figure 50 Partial to normal display
HD66766R Rev. 1.0-1 / September 2002 Frame-Frequency Adjustment Function The HD6676 6R has an on-chip frame-frequency adjustment function. The frame frequency can be adjusted by the instruction setting (DIV, RTN) during the LCD drive as the oscillation frequency is always the same. When the display duty is changed, the frame frequency can be adjusted to be the same. If the oscillation frequency is set to high, an animation or a static image can be displayed in suitable ways by changing the frame frequency. When a static image is displayed, the frame frequency can be set low and the low-power consumption mode can be entered. When high-speed screen switching, for an animated display, etc. is required, the frame frequency can be set high. Relationship between LCD Drive Duty and Frame Frequency The relationship between the LCD drive duty and the frame frequency is calculated by the following expression. The frame frequency can be adjusted in the retrace-line period bit (RTN) and in the operation clock division bit (DIV) by the instruction. (Formula for the frame frequency) fosc Frame frequency = [Hz] Clock cycles per raster-row × division ratio × 1/duty cycle fosc: R-C oscillation frequency Duty: drive duty (NL bit) Clock cycles per raster-row: (RTN + 26) clock cycles Division ratio: DIV bit Example Calculation 1 Setting the maximum frame frequency to 60 Hz Display duty: 1/176 Retrace-line period: 0 clock (RTN3-0 = “0000”) Operation clock division ratio: 1 division fosc = 60 Hz × (0 + 26) clock × 1 division × 176 lines = 275 (kHz) In this case, the R-C oscillation frequency becomes 275 kHz. The external resistance value of the R-C oscillator must be adjusted to be 275 kHz. The display duty can be changed by the partial display, etc. and the frame frequency can be the same by setting the RNT bit and DIV bit to achieve the following. (Partial display): Display duty: 1/40 Retrace-line period: 1 clock (RTN3-0 = “0002”) Operation clock division ratio: 3 division Frame frequency = 275 kHz/ ((3 + 26) clock × 4 division × 40 lines) = 59.2 (Hz) Example Calculation 2 Switching the frame frequency to suit animation/static image display (Animation display): Frame frequency: 90 Hz Display duty: 1/176 Retrace-line period: 0 clock (RTN3-0 = “0000”) Operation clock division ratio: 1 division fosc = 90 Hz × (0 + 26) clock × 1 division × 176 lines = 412 (kHz) (Static image display): Frame frequency: 90 Hz Display duty: 1/176 Retrace-line period: 1 clock (RTN3-0 = “1101”) Operation clock division ratio: 1 division Frame frequency: 412 kHz/ ((13 + 26) clock × 1 division × 176 lines) = 60.0 (Hz)
HD66766R Rev. 1.0-1 / September 2002 n-raster-row Reversed AC Drive The HD66766R supports not only the LCD reversed AC drive in a one-frame unit (B-pattern waveform) but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 64 raster- rows (C-pattern waveform). When a problem affecting display quality occurs, such as cross-talk at high-duty driving of more than 1/64 duty, the n-raster-row reversed AC drive (C-pattern waveform) can improve the quality. Determine the number of raster-rows n (NW bit set value + 1) for alternating after confirmation of the display quality with the actual LCD panel. However, if the number of AC raster-rows is reduced, the LCD alternating frequency becomes high. Because of this, the charge or discharge current is increased in the LCD cells. Figure 53 Example of an AC Signal under n-raster-row Reversed AC Drive Notice : Specify the number of AC drive raster-rows and the necessity of EOR so that the DC bias is not generated to the LCD. 3 4 5 6 7 8 9 10 11 12 13 175 1 frame 176 1 2 3 4 5 6 7 8 9 10 11 12 13 175 1 2 3 1 frame 176 -wave form drive - 1/176 duty - 11 raster-row reversal - Without EORs B-pattern waveform drive C-pattern C-pattern waveform drive - 1/176 duty - 11 raster-row reversal - With EORs 1 2 -1/176 duty
HD66766R Rev. 1.0-1 / September 2002 Screen-division Driving Function The HD66766R can select and drive two screens at any position with the screen-driving position registers (R14h and R15h). Any two screens required for display are selectively driven and a duty ratio is lowered by LCD-driving duty setting (NL4-0), thus reducing LCD-driving voltage and power consumption. For the 1st division screen, start line (SS17-10) and end line (SE17-10) are specified by the 1st screen-driving position register (R14h). For the 2nd division screen, start line (SS27-20) and end line (SE27-20) are specified by the 2nd screen-driving position register (R15h). The 2nd screen control is effective when the SPT bit is “1”. The total count of selection-driving lines for the 1st and 2nd screens must correspond to the LCD-driving duty set value. Figure 54 Display example in 2-screen division driving COM26 COM42 1/24 duty driving on 2 screen 1st screen: 7 raster-row driving 2nd screen: 17 raster-row driving Always applying non-selection level COM1 COM7 Always applying non-selection level -Driving duty: NL4-0 = "00010" (1/24 duty) -1st screen setting: SS17-10 = "00"H, SE17-10 = "06" H -2nd screen setting: SS27-20 = "19"H, SE27-20 = "29" H, SPT = "1"
HD66766R Rev. 1.0-1 / September 2002 Restrictions on the 1st/2nd Screen Driving Position Register Settings The following restrictions must be satisfied when setting the start line (SS17-10) and end line (SE17-10) of the 1st screen driving position register (R14h) and the start line (SS27-20) and end line (SE27-20) of the 2nd screen driving position register (R15h) for the HD6676 6R. Note that incorrect display may occur if the restrictions are not satisfied. Table 39 Restrictions on the 1st/2nd Screen Driving Position Register Settings 1st Screen Driving (SPT = 0) 2nd Screen Driving (SPT = 1) Register setting SS17-10 ≤SE17-0 ≤ “AF”H SS17-10 ≤ SE17-10 < SS27-20 ≤SE27-20 ≤ “AF”H Display operation
- Time-sharing driving for COM pins (SS1+1) to (SE1+1)
- Non-selection level driving for others
- Time-sharing driving for COM pins (SS1+1) to (SE1+1) and (SS2+1) to (SE2+1)
- Non-selection level driving for others Notes: 1. When the total line count in screen division driving settings is less than the duty setting, non-selection level driving is performed without the screen division driving setting range. 2. When the total line count in screen division driving settings is larger than the duty setting, the start line, the duty-setting line and the lines between them are displayed and non-selection level driving is performed for other lines. 3. For the 1st screen driving, the SS27-20 and SE27-20 settings are ignored.
HD66766R Rev. 1.0-1 / September 2002 Notes: 1. Generate an output voltage (VOUT) from step-up circuit 1 within the range from 4.0 to 5.75V. 2. Do not allow the output voltage (VCH) from step-up circuit 2 to exceed 22 V. 3. Do not allow the output from Vci2 to exceed VOUT voltage . 4. When capacitor with polarity is used, be sure that an inverted voltage is not applied to it in any state of the system. 5. Vci1 is used as both the reference voltage input and power supply in the step-up circuit. Keep sufficient LCD drive current. 6. Rated voltage of capacitors possible to be used are as described below. Required voltage depends on used panels. When actual voltage is less than 16V, capacitors with 16V rated voltage can be used. 6.3V: VREFM, VciOUT, C11, C12, VOUT, BIASC, Vci2, C21, C22, C23, VSH, VM 25V(16V): VCH, CE, VCL LCD Drive Voltage The required voltage can be calculated by applying the following expressions. Drive voltages are standard; generate a voltage to suit the panel to be used. LCD Drive Bias An optimal bias can be calculated by applying the following expression. The value that has been calculated is theoretically optimal. If a lower bias value than the optimal value is used to drive the LCD, contrast may be reduced depending on lighting conditions. However, the power consumption can be reduced by lowering the drive voltage. Adjust the value according to the system to be used. How to determine the VCH voltage VCH = NB x ND2 x VSH NB : Bias ratio ND2 : Step-up factor of the step-up circuit 2 Contrast adjustment RB : Contrast resistance (0.000R to 1.016R) VSH = VREFM x 2R / (Rb + 2R) Table 40 Bias value = N VSH-VM, VM-VSL N - 1 N - 1 2N N N VCH-VM, VM-VCL Vth: Threshold voltage of the LCD panel to be used. N: Display duty cycle. x Vth x Vth 0.992R1100000 1.000R0100000 0.008R0111111 Rb resist value 0.984R 1.008R 0.000R 1.016R 1111111 0010000 1000000 0000000 CT setting value CT0CT1CT2CT3CT4CT5CT6 RbFResist for adjusting contrast (0.000R\`1.016R) VSH VM VSL VREFM R Rb R VCH=VM~ ~ VCH step-up circuit 2 VCI2 VCI2=VM~NB NB Nc2 Figrue 56
HD66766R Rev. 1.0-1 / September 2002 How to determine the power setting value 1. Determine LCD drive bias Determine LCD drive bias first. LCD drive bias is theoretically (1/SQRT (display duty)) optimal ; however, the total drive voltage can be reduced by lowering bias ratio. Consider the display quality, the drive voltage and the current consumption. 2. Determine VOUT voltage Determine factor of Vc1 regulator and step-up factor so as to set output voltage, VOUT of step-up circuit 1 4.0 to 5.75V, setting input voltage Vci2 of step-up circuit 2 more than +0.5V. Since the entire electric power for driving LCD is supplied from step-up circuit, subsequent voltage fall need to be considered. 3. Segment drive voltage calculation Segment output drive voltage is calculated by the following expression. B : LCD drive bias ratio Vth: LCD threshold voltage 4. Common drive voltage calculation Common output drive voltage is calculated by the following expression. B : LCD drive bias ratio 5. Determine input voltage of step-up circuit 2 Determine input voltage of step-up circuit 2. This voltage is determined by dividing Vcom voltage by step-up factor; lower factors are used for low current consumption. Vci2 voltage need to be less than VOUT voltage (4.0 to 5.75 V)- 0.5V. Example of register setting on power supply Examples of register setting values on power supply are described below. Example 1: 1/176 duty ratio, Vcc = VREFL = 3.0V, 1/13 bias BS3-0 = H’8 : bias adjustment 1.4 times BT2-0 = H’4 : step-up circuit 1 2 times step-up circuit 2 5 times BT3 = H ’1 : operate voltage inverting circuit DC2-0 = H’6 step-up circuit 1 frequency 32 clocks step-up circuit 2 frequency 128 clocks TBD AP1-0 = H’1 : low fixed current in the amplifier VC2-0 = H’0 : Vci1 = 0.92 x Vcc = 2.75V VR2-0 = H’0 : VREFM = 1.1 x VREFL CT6-0 : appropriate contrast setting values 2 x B Vseg = (B-1) x VTH Vcom = Vseg x (B+1)
HD66766R Rev. 1.0-1 / September 2002 Example 2: 1/176 duty ratio, Vcc = VREFL = 2.4V, Vci = 2.8V, 1/13 bias BS2-0 = H’8 : bias adjustment 1.4 times BT2-0 = H’4 : step-up circuit 1 2 times step-up circuit 2 5 times BT3 = H ’1 : operate voltage inverting circuit DC2-0 = H’6 : step-up circuit 1 frequency 32 clocks step-up circuit 2 frequency 128 clocks TBD AP1-0 = H’1 : low fixed current in the amplifier VC2-0 = H’4 : internal Vci1 regulator off 2.8V directly supplied to Vci1 VR3-0 = H’2 : VREFM = 1.4 x VREFL CT6-0 : appropriate contrast setting values Example 3: Partial display, 1/24 duty ratio, Vcc = 2.4V, Vci = 2.8V, 1/4 bias BS2-0 = H’0 : bias adjustment 1.25 times BT2-0 = H’0 : step-up circuit 1 2 times step-up circuit 2 2 times BT3 = H ’1 : operate voltage inverting circuit DC2-0 = H’6 : step-up circuit 1 frequency 64 clocks step-up circuit 2 frequency 128 clocks TBD AP1-0 = H’1 : low fixed current in the amplifier VC2-0 = H’4 : internal Vci1 regulator off VR3-0 = H’2 : VREG 1 = 1.4 x VREFL CT6-0 : appropriate contrast setting values
HD66766R Rev. 1.0-1 / September 2002 HD66766R power supply level correlation Figure 57 HD66766R Power supply level correlation VOUT (4.0 to 5.75 V) GND Vci1 VREFL ( VCC) VREFM ( VOUT) VSH VM VCL BT2-1 (2 to 5 times) BT0 (2 to 3 times) BS3-0 (0.5 to 2.165 times) CT6-0 (contrast adjustment) Vcc VC2-0 (0.92 to 0.68 times) GND VCH Vci2 VR2-0 (1.1 to 3.4 times) Voltage polarity inversion between VCH and VM
HD66766R Rev. 1.0-1 / September 2002 Absolute Maximum Ratings Table 41 Item Symbol Unit Value Notes* Power supply voltage (1) Vcc V -0.3 to + 4.6 1, 2 Power supply voltage (2) Vcil V -0.3 to + 4.6 1, 3 Power supply voltage (3) VCH –VCL V -0.3 to + 46 1, 4 Input voltage Vt V -0.3 to Vcc + 0.3 1 Operating temperature Topr °C -40 to + 85 1, 5 Storage temperature Tstg °C -55 to + 110 1 Notes: 1. If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limit is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. 2. Vcc ≥ GND must be maintained 3. Vcil ≥ GND must be maintained. 4. VCH ≥ GND must be maintained GND ≥ VCL must be maintained 5. For die and wafer products, specified up to 85 °C.
HD66766R Rev. 1.0-1 / September 2002 DC Characteristics (VCC = 2.2 to 3.6 V, VCH-VCL=8V to 44V, Ta = –40 to +85°C*1) Table 42 Item Symbol Unit Test Condition Min Typ Max Notes Input high voltage VIH V VCC = 2.2 to 3.6 V 0.7 VCC — VCC 2, 3 Input low voltage VIL V VCC = 2.2 to 3.6 V –0.3 — 0.15VCC 2, 3 Output high voltage (1) (DB0-15 pins) VOH1 V IOH = –0.1 mA 0.75VCC — — 2 Output low voltage (1) (DB0-15 pins) VOL1 V VCC = 2.2 to 2.4 V, I OL = 0.1 mA — — 0.2 VCC 2 VCC = 2.4 to 3.6 V, I OL = 0.1 mA — — 0.15VCC 2 Driver ON resistance (SEG pins) RSEG kΩ ±Id = 0.05 mA, VLCD = 3 V — 0.35 3 4 Driver ON resistance (COM pins) RCOM kΩ ±Id = 0.05 mA, VCH - V CL = 44 V — 0.90 3 4 I/O leakage current ILi µA Vin = 0 to VCC –1 — 1 5 Current consumption during normal operation (VCC – GND) IOP µA R-C oscillation VCC = 3.0 V, VCH = 20V, VM = 1.6V, VCL = -16.8V,Ta = 25°C fOSC = 276 Khz (1/176 duty), 1/12 Bias CT minimum AP minimum, display all 0 Step-up 1 = two times Step-up 2 = five times VCI1 = 0.92 x VCC — 480. 600 6 VCC = 3 V, Ta = 25°C — 0.1 5Current consumption during standby mode (VCC – GND) IST µA Vcc = 3V, Ta = 85°C — — 50 VREFL input voltage VREFL V Vcc = 2.2V ∼ 3.6V — — Vcc VREFM output voltage VREFM V VOUT = 4.0V∼ 5.75V — — VOUT -0.5 Step up circuit 1 output voltage VOUT V 4.0 — 5.75 Step up circuit 2 output voltage VCI2 V — — VOUT – 0.5
HD66766R Rev. 1.0-1 / September 2002 Step up circuit characteristics Table 43 Item Terminal Unit Test Condition Min Typ Max Notes Step up circuit 1 VOUT V VCC = 3.0 [V] Vci step up factor = 0.92 Step up factor : two times Step up cycle: 32 divided cycle Load voltage = 400 [µA] 5.25 5.48 — — Step up circuit 2 VCH V VCC = 3.0 [V] VOUT = 5.5 [V] VREFL = 3.0 [V] VREFM = 1.1 x VREFL Constant current of operation amplifier: small Contrast adjustment value = 0.000R 1/12 bias Step up cycle of step up circuit 2: 96 divided cycle Step up factor: Five times Load current = 20 [uA] 21.2 21.3 — (9) Step up circuit 3 VCL V VCC = 3.0 [V] VOUT = 5.5 [V] VREFL = 3.0 [V] VREFM = 1.1 x VREFL Constant current of operation amplifier: small Contrast adjustment value = 0.000R 1/12 bias Step up cycle of polarity inversion circuit: 96 divided cycle Step up factor: Five times Load current = 20 [uA] -21.0 -21.2 — (9)
HD66766R Rev. 1.0-1 / September 2002 AC Characteristics (VCC = 2.2 to 3.6 V, Ta = –40 to +85°C*1) Table 44 Clock Characteristics (VCC = 2.2 to 3.6 V) Item Symbol Unit Test Condition Min Typ Max Notes External clock frequency fcp kHz VCC = 2.2 to 3.6 V 151 275 640 7 External clock duty ratio Duty % VCC = 2.2 to 3.6 V 45 50 55 7 External clock rise time trcp µs VCC = 2.2 to 3.6 V — — 0.2 7 External clock fall time tfcp µs VCC = 2.2 to 3.6 V — — 0.2 7 R-C oscillation clock fOSC kHz Rf = 200k Ω , VCC = 3 V 220 275 330 8 68-system Bus Interface Timing Characteristics Table 45 Normal Write Mode (HWM=0) (Vcc = 2.2 to 2.4 V) Item Symbol Unit Test Condition Min Typ Max Write tCYCE ns Figure 1 600 — —Enable cycle time Read tCYCE ns Figure 1 800 — — Write PWEH ns Figure 1 90 — —Enable high-level pulse width Read PWEH ns Figure 1 350 — — Write PWEL ns Figure 1 300 — —Enable low-level pulse width Read PWEL ns Figure 1 400 — — Enable rise/fall time tEr, tEf ns Figure 1 — — 25 Set up time (RS, R/W to E, CS*) tASE ns Figure 1 10 — — Address hold time tAHE ns Figure 1 5 — — Write data set up time tDSWE ns Figure 1 60 — — Write data hold time tHE ns Figure 1 15 — — Read data delay time tDDRE ns Figure 1 — — 200 Read data hold time tDHRE ns Figure 1 5 — — Table 46 High-Speed Write Mode (HWM=1) (Vcc = 2.2 to 2.4 V) Item Symbol Unit Test Condition Min Typ Max Write tCYCE ns Figure 1 200 — —Enable cycle time Read tCYCE ns Figure 1 800 — — Write PWEH ns Figure 1 90 — —Enable high-level pulse width Read PWEH ns Figure 1 350 — — Write PWEL ns Figure 1 90 — —Enable low-level pulse width Read PWEL ns Figure 1 400 — — Enable rise/fall time tEr, tEf ns Figure 1 — — 25 Set up time (RS, R/W to E, CS*) tASE ns Figure 1 10 — — Address hold time tAHE ns Figure 1 5 — — Write data set up time tDSWE ns Figure 1 60 — — Write data hold time tHE ns Figure 1 15 — — Read data delay time tDDRE ns Figure 1 — — 200 Read data hold time tDHRE ns Figure 1 5 — —
HD66766R Rev. 1.0-1 / September 2002 Normal Write Mode (HWM=0) Table 47 (Vcc = 2.4 to 3.6 V) Item Symbol Unit Test Condition Min Typ Max Note Enable cycle time Write tCYCE ns Figure 1 200 — — — Read tCYCE ns Figure 1 300 — — — Enable high-level pulse width Write PWEH ns Figure 1 40 — — — Read PWEH ns Figure 1 150 — — — Enable low-level pulse width Write PWEL ns Figure 1 100 — — — Read PWEL ns Figure 1 100 — — — Enable rise/fall time tEr, tEf ns Figure 1 — — 25 — 10 — — Using status read Set up time (RS, R/W to E, CS*) tASE ns Figure 1 0 — — Not using status read Address hold time tAHE ns Figure 1 2 — — — Write data set up time tDSWE ns Figure 1 60 — — — Write data hold time tHE ns Figure 1 2 — — — Read data delay time tDDRE ns Figure 1 — — 100 — Read data hold time tDHRE ns Figure 1 5 — — — High-Speed Write Mode (HWM=1) Table 48 (Vcc = 2.4 V to 3.6 V) Item Symbol Unit Test Condition Min Typ Max Note Enable cycle time Write tCYCE ns Figure 1 100 — — — Read tCYCE ns Figure 1 300 — — — Enable high-level pulse width Write PWEH ns Figure 1 40 — — — Read PWEH ns Figure 1 150 — — — Enable low-level pulse width Write PWEL ns Figure 1 40 — — — Read PWEL ns Figure 1 100 — — — Enable rise/fall time tEr, tEf ns Figure 1 — — 25 — 10 — — Using status read Set up time (RS, R/W to E, CS*) tASE ns Figure 1 0 — — Not using status read Address hold time tAHE ns Figure 1 2 — — — Write data set up time tDSWE ns Figure 1 60 — — — Write data hold time tHE ns Figure 1 2 — — — Read data delay time tDDRE ns Figure 1 — — 100 —
HD66766R Rev. 1.0-1 / September 2002 80-system Bus Interface Timing Characteristics Normal Write Mode (HWM=0) Table 49 (Vcc = 2.2 to 2.4 V) Item Symbol Unit Test Condition Min Typ Max Bus cycle time Write tCYCW ns Figure 2 600 — — Read tCYCR ns Figure 2 800 — — Write low-level pulse width PWLW ns Figure 2 90 — — Read low-level pulse width PWLR ns Figure 2 350 — — Write high-level pulse width PWHW ns Figure 2 300 — — Read high-level pulse width PWHR ns Figure 2 400 — — Write/Read rise/fall time tWRr, WRf ns Figure 2 — — 25 Setup time (RS to CS*, WR*, RD*) tAS ns Figure 2 10 — — Address hold time tAH ns Figure 2 5 — — Write data set up time tDSW ns Figure 2 60 — — Write data hold time tH ns Figure 2 15 — — Read data delay time tDDR ns Figure 2 — — 200 Read data hold time tDHR ns Figure 2 5 — — High-Speed Write Mode (HWM=1) Table 50 (Vcc = 2.2 to 2.4 V) Item Symbol Unit Test Condition Min Typ Max Bus cycle time Write tCYCW ns Figure 2 200 — — Read tCYCR ns Figure 2 800 — — Write low-level pulse width PWLW ns Figure 2 90 — — Read low-level pulse width PWLR ns Figure 2 350 — — Write high-level pulse width PWHW ns Figure 2 90 — — Read high-level pulse width PWHR ns Figure 2 400 — — Write/Read rise/fall time tWRr, WRf ns Figure 2 — — 25 Set up time (RS to CS*, WR*, RD*) tAS ns Figure 2 10 — — Address hold time tAH ns Figure 2 5 — — Write data set up time tDSW ns Figure 2 60 — — Write data hold time tH ns Figure 2 15 — — Read data delay time tDDR ns Figure 2 — — 200 Read data hold time tDHR ns Figure 2 5 — —
HD66766R Rev. 1.0-1 / September 2002 Normal Write Mode (HWM = 0) Table 51 (Vcc = 2.4 to 3.6 V) Item Symbol Unit Test Condition Min Typ Max Note Bus cycle time Write tCYCW ns Figure 2 200 — — Read tCYCR ns Figure 2 300 — — Write low-level pulse width PWLW ns Figure 2 40 — — Read low-level pulse width PWLR ns Figure 2 150 — — Write high-level pulse width PWHW ns Figure 2 100 — — Read high-level pulse width PWHR ns Figure 2 100 — — Write/Read rise/fall time tWRr, WRf ns Figure 2 — — 25 10 — — Using status readSet up time (RS to CS*, WR*, RD*) tAS ns Figure 2 0 — — Not using status read Address hold time tAH ns Figure 2 2 — — Write data setup time tDSW ns Figure 2 60 — — Write data hold time tH ns Figure 2 2 — — Read data delay time tDDR ns Figure 2 — — 100 Read data hold time tDHR ns Figure 2 5 — — High-Speed Write Mode (HWM=1) Table 52 (Vcc = 2.4 to 3.6 V) Item Symbol Unit Test Condition Min Typ Max Note Bus cycle time Write tCYCW ns Figure 2 100 — — Read tCYCR ns Figure 2 300 — — Write low-level pulse width PWLw ns Figure 2 40 — — Read low-level pulse width PWLR ns Figure 2 150 — — Write high -level pulse width PWHW ns Figure 2 40 — — Read high -level pulse width PWHR ns Figure 2 100 — — Write/Read rise/fall time t WRr, WRf ns Figure 2 — — 25 10 — — Using status readSet up time (RS to CS*, WR*, RD*) tAS ns Figure 2 0 — — Not using status read Address hold time tAH ns Figure 2 2 — — Write data set up time tDSW ns Figure 2 60 — — Write data hold time tH ns Figure 2 2 — — Read data delay time tDDR ns Figure 2 — — 100 Read data hold time tDHR ns Figure 2 5 — —
HD66766R Rev. 1.0-1 / September 2002 Clock Synchronized Serial Interface Timing Characteristics Table 53 (Vcc = 2.2 to 2.4 V) Item Symbol Unit Test Condition Min Typ Max Write (received) tSCYC us Figure 3 0.1 — 20 Serial clock cycle time Read (transmitted) tSCYC us Figure 3 0.25 — 20 Write (received) tSCH ns Figure 3 40 — — Serial clock high-level pulse width Read (transmitted) tSCH ns Figure 3 120 — — Write (received) tSCL ns Figure 3 40 — — Serial clock low-level pulse width Read (transmitted) tSCL ns Figure 3 120 — — Serial clock rise/fall time tscr, scf ns Figure 3 — — 20 Chip select set up time tCSU ns Figure 3 20 — — Chip select hold time tCH ns Figure 3 60 — — Serial input data set up time tSISU ns Figure 3 30 — — Serial input data hold time tSIH ns Figure 3 30 — — Serial input data delay time tSOD ns Figure 3 — — 130 Serial input data hold time tSOH ns Figure 3 5 — — Table 54 (Vcc = 2.4 to 3.6 V) Item Symbol Unit Test Condition Min Typ Max Write (received) tSCYC us Figure 3 0.076 — 20 Serial clock cycle time Read (transmitted) tSCYC us Figure 3 0.15 — 20 Write (received) tSCH ns Figure 3 40 — — Serial clock high-level pulse width Read (transmitted) tSCH ns Figure 3 70 — — Write (received) tSCL ns Figure 3 35 — — Serial clock low-level pulse width Read (transmitted) tSCL ns Figure 3 70 — — Serial clock rise/fall time tscr, scf ns Figure 3 — — 20 Chip select set up time tCSU ns Figure 3 20 — — Chip select hold time tCH ns Figure 3 60 — — Serial input data set up time tSISU ns Figure 3 30 — — Serial input data hold time tSIH ns Figure 3 30 — — Serial output data delay time tSOD ns Figure 3 — — 130 Serial output data hold time tSOH ns Figure 3 5 — —
HD66766R Rev. 1.0-1 / September 2002 Load Circuits AC Characteristics Test Load Circuits Figure 78 Load Circuit Data bus: DB15 to DB0 Test point 50pF
HD66766R Rev. 1.0-1 / September 2002 Timing Characteristics 68-system Bus Operation Figure79 68-system Bus Timing Notes: 1) PWEH is specified in the overlapped period when CS* is low and E is high. 2) Parallel data transfer is enabled on the DB15-8 pins when the 8-bit bus interface is used. Fix the DB7-0 pins to Vcc or GND. RS R/W CS* E DB0 to DB15 DB0 to DB15 VIH VIL tASE tAHE PWEH tEftEr tDSWE tHE Wrire data tCYCE tDDRE tDHRE VOH1 VOL1 VOH1 VOL1Read data VIH VIL VIL VIL VIH VIH VIL VIH VIL VIH VIL PWEL VIL VIL Note 1) Note 2) Note2)
HD66766R Rev. 1.0-1 / September 2002 80-system Bus Operation Figure 80 80-system Bus Timing Note1) PWLW and PWLR are specified in the overlapped period when CS* is low and WR* or RD* is low. Note2) Parallel data transfer is enabled on the DB15-0 pins when the 8-bit bus interface is used. Fix the DB7-0 pins to Vcc or GND. CS* tWRftWRr tDSW tHWR tDHR VOH1 VIL VIH VIL RS WR * RD* VIH VIL VIH VIL tAS tAH VIL VIH Note 1) PWLW, PWLR PWHW, PWHR tCYCW, tCYCR VIH VIH VIL VIH VIL DB0 to DB15 DB0 to DB15 Wrire data Read dataVOH1 VOL1 VOL1 tDDR
HD66766R Rev. 1.0-1 / September 2002 Additional Issue HD66766R Contrast fluctuation on RAM access Hitachi one-chip driver; HD66766R has contrast fluctuation while accessing the internal RAM. This phenomenon occurs according to the structure of external circuit and the usage of HD66766R. Please have a clear understanding of the phenomenon and measures described below before using HD66766R. 1. Contrast fluctuation When HD66766R is mounted on glass, the grand terminal gets contact with resistance of ITO wiring. HD66766R has 8 GNDs, 4 AGNDs for power supply circuit, and another 4 GNDs for RAM and Logic. When all the GNDs are connected on glass with ITO, transferring display data to the internal RAM at high-speed causes high current consumption. And resistance of ITO wiring connected with GND terminal raises the voltage. The raised voltage is amplified with a step-up circuit, and it results in a decrease of VCH/VCL voltage causing contrast fluctuation on display. Figure 1 shows the mechanism of the phenomenon. Figure 2 shows decrease of VCH voltage according to RAM access frequency and resistance of ITO wiring. (The value shown in Figure 2 is the actual data of a typical sample of HD66766R measured by Hitachi’s jig.) 2. Measures ITO patterns on glass must be separated as shown in Figure 3. (Even if GND bumps are separated on LSI, if ITO patterns on glass are connected, GND level rises up in RAM circuit and Logic circuit.) Also, GND resistor should be designed to be less than 10 Ω , considering the decrease of VCH voltage caused by the raise of GND voltage. LCD RAM Voltage generating circuit Voltage decrease Voltage decrease VCH HD66766R RAM access current Resistance of ITO wiring GND Figure 1 Influence of ITO wiring resistance
HD66766R Rev. 1.0-1 / September 2002 Maintenance history report Rev. Date Contents
1.0 August 8, 2002 First release
P74 5.Determine input voltage of step-up circuit2 Line 3 From “4.5 to