Driver IC

HD66780

Hitachi Semiconductor

Dot Matrix Liquid Crystal Display Controller and Driver

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HD66780 HITACHI

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(Dot Matrix Liquid Crystal Display Controller and Driver) Description Features The LCD-IIA (HD66780) a dot matrix liquid © - 5 x 7 and 5 x 10 dot matrix liquid crystal crystal display controller and driver LSI dis- display controller driver plays alphanumerics, kana characters, and © -_-_ Can interface to 4-bit or 8-bit MPU symbols. It drives a dot matrix liquid crystal - Display data RAM: 80 x 8 bits (80 char- display under 4-bit or 8-bit microcontroller or acters, max) microprocessor control. All the functions | - Character generator ROM: 12000 bits; required for driving a dot matrix liquid crystal Character font 5 x10 dots: 240 characters display are internally provided on one chip. + Character generator RAM: 64 x 8 bits; Character font 5x8 dots: 8 characters or Designers can complete dot matrix liquid character font § x 11 dots: 4 characters crystal display systems with low chipcount - Both display data and character genera- by using the LCD-IIA (HD66780). If a driver tor RAMs can be read from the MPU LSI (H1D44100H or HD66100F) is connected to -_Internal liquid crystal display driver the HD66780, up to 80 characters can be —16 common signal drivers displayed. —40 segment signal drivers (Can be externally extended to 360 segments by The LCD-IIA is produced by the CMOS proc- liquid crystal display driver HD44100H or ess. Therefore, the combination of the LCD- HD66100F) IA with a CMOS microcontroller or micro- © - Duty factor selection (selectable by pro- Processor can complete a portable battery- gram) driven device with low power dissipation. =1/8 duty: 1 line of § x 7 dots + cursor ~1/11 duty: 1 line of § x 10 dots + cursor —1/16 duty: 2 lines of 5 x 7 dots + cursor + Maximum number of display characters as shown in table 1 + Wide range of instruction functions: Dis- 4 play clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift + Internal automatic reset circuit at power on (internal reset circuit) + Internal oscillation circuit —External resistor or ceramic filter ~External clock operation possible + CMOS process + Single +5 V logic power supply (exclud- ing power for liquid crystal display drive) + Operation temperature range: -20°C to +78°C (-40°C to +85°C device available ‘upon request) + 80-pin plastic flat package (FP-80B, FP- 80A) + Low power consumption

Ordering Information

Type No. Package HD66780FS_80-pin plastic QFP (FP-80B) HD66780FH_80-pin plastic OFP (FP-80A) HITACHI Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819» (415) 589-8300 167

HD66780 (LCD— II A) Pin Arrangement EP ESTES ESETER EE PEEEEEEEPEEEEL ET OENNAOOAAOAnOAOn scour RREEERRERS S3S2} cecengeseueass a atjsecn 5838858885 SeGu0 he G1 ICOM se DOO000OOOOOnOoo noon, sas wolcom.. PEDEPEPRTERESETE ITT SEG Ce sIcom,, ston Lcome seGuC) sco; sts) scons Seon Siem, = stout “Bicone St..Ce seE}com, = sean. SBcoms 86150 3sE)com, secu}: scons seer SH come stout “Deon: secu)i2 Sco. seo: “come SEG C13 se]com, see stcom see tt Som sesh “peu SEG, Chis socom, SGN “coms sec, C]ie Econ, seep} “icoms SG, C7 at com, sears “Bcom secs Clie ab com: set}. spcoms 5&6. Chie metry seca» “Deo, sec, C0 “soe, secs} “Deon: seG; E21 ‘auto, seceC}> “fjos; sec, O22 ‘Bos: sees} Stes. cx Ga aoe, sec; “toe. os, Ch, oneraannananango™ Sol" aR rReaeeaaeaanns ia DOOUOUOOOOUI SEE EE PRL Pur rity Seccsccttsae2. 88 Bags *** adh? °8e* aads Bsssssggfzo8d.88 (FP-80) (FP-208) (Top-View) Pin Description No. of Signal Lines vo Connected to Function RS 1 Input MPU Selects register RW 1 Input MPU Selects read or write E 1 Input MPU Starts data read or write DB7-DBo 8 v0 MPU Bidirectional data bus ch 7 Output Driver LSI Serial data latch clock ce 7 Output Driver LSI Serial data shift clock M 1 Output Driver LSI UCD waveform AC switch signal o 1 Output Driver LSI Character pattern data COM1-COMi6 16 Output cD ‘Common signals SEG)-SEGa0 40 Output ucD Segment signals Vivs 5 Power supply LCD drive voltages Vee, GND 2 Power supply +5 V and ground OSC1-OSC2 2 System clock HITACHI 168 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300

HD66780 (LCD—IIA) Pin Function | RS (Register Select) D (Serial Data) | RS selects the register that the MPU is acces- © The LCD-IIA outputs serial character pattern sing. RS = 0 selects the instruction register data corresponding to the common signals to for MPU writes, and the busy flagand address © the HD44100H or HD66100F driver LSIs on D. counter for reads. RS = 1 selects the data register for MPU reads and writes. COM;-COMis (Common) R/W (Read/Write) COM:-COMx. are the LCD common lines. Common signals that are not used are de- R/W selects whether the MPU will read from _—selected. At 1/8 duty factor COMs-COMye are (R/W = 1) or write to (R/W = 0) the LCD-IIA. not used, so they output non-selected waveforms. At 1/11 duty factor COMi2-COMis E (Enable) are not used, so they output non-selected waveforms. The MPU sets the E input high to signal the start of the read/write operation. SEG,-SEGw (Segment) | DBr-DB» (Data Bus) SEG1-SEGuao are the LCD segment lines. | The bidirectional, three-state data bus, DBo- Vi-Vs (LCD Voltages) : DB, transfers data between the MPU and the LCD-IIA. DB, can be used as the busy flag. | The LCD-IIA requires the V;-Vs voltages to ‘The lower-order four lines, DBo-DBy, are not + — output LCD-driving waveforms. used in four-bit interface operation. Vcc, GND (Power Supply, Ground) Cla, CLe (Clock 1, Clock 2) Voc is the LCD-ILA's logic power supply. GND The CL; output signals the HD44100H or _is the power supply ground. HD66100F driver LSI to latch the serial data sent on line D. The CLz output signals it to OSC;, OSC; (Oscillator 1, Oscillator 2) shift the data. OSC; and OSC; are the connections for the M (Master AC Signal) LCD-IIA system clock. The LCD-IIA can use its internal oscillator if OSC, and OSC: are The HD44100H or HD66100F driver LSIs use connected to a resistor or ceramic filter. An the M output to convert the LCD drive external clock can be input to OSC). waveform to AC. Table 1 Number of Display Characters No. of Display Duty No. of Display Lines factor Extension HD44100H HD66100F Characters Tine 1/8, Not ~ = 8 characters x 1 line display Y/11 provided "VY “Provided 9 pes. 6 pes. 80 cheractrs X 1 line —____ NB charactors pe.) (16 characters/ec) line 1/16 Not = = 8 charactors x 2 lines display duty —_provided Provided 4 pcs.(8 characters 2 pos.(16 charac- 40 characters * 2 lines x 2 lines/pc.) ters x 2 lines/pc.) HITACHI Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 169

a SSsSSSSSSSsSSSSSSSssSSSSSSSSSSS HD66780 (LCD— II A) Se HD66780 Block Diagram az 9 os o 3eEe 6 8 — pike € 8 29 §828¢ azoo [a] [-) we ooo > sssss Ey @ Busy Data Instruction Flag Register (DR) Register (IR) ql Instruction

3 Character ° Decoder

3 Generator

er ? (CG RAM) |. | 3 3 512 bits _ 3§3 3 Es § 2 aoe $3 Character ° Generator Display Data ROM one (CG ROM) Oe Mi) n 12000 bits 6 bite $ Cursor Blink —] i

5 Control Circuit oe

& 2s z 40-bit 16-bit Shift ES £ Latch Circuit Register 5 g 2 g ‘Segment Signal ‘Common Signal ° Driver Driver g 2 ° 6d sz dds 88 88 HITACHI 170 Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300

HD66780 (LCD— II A) Block Function to DD and CG RAM. When an instruction for address is written in IR, the address informa- Registers tion is sent from IR to AC. Selection of either DD or CG RAM is also determined concur- The HD66780 has two 8-bit registers, an _rently by the instruction. instruction register (IR) and a data register (DR). After writing into (or reading from) DD or CG RAM display data, AC is automatically in- The IR stores instruction codes such as dis- cremented by 1 (or decremented by 1). AC play clear and cursor shift, and address contents are output to DBo-DBs when RS = 0 information for display data RAM (DD RAM) _—and R/W = 1, as shown in table 2. and character generator RAM (CG RAM). The IR can be written from the MPU but not read Display Data RAM (DD RAM) by the MPU. The display data RAM (DD RAM) stores dis- The DR temporarily stores data to be written play data represented in 8-bit character into the DD RAM or the CG RAM and datato _—_codes. Its capacity is 80 x 8 bits, or 80 char- be read out from DD RAM or CG RAM. Data _acters. The display data RAM (DD RAM) that written into the DR from the MPU is auto- _is not used for display can be used as general matically written into the DD RAMortheCG data RAM. Relations between DD RAM ad- RAM internally. The MPU also uses the DRfor dresses and positions on the liquid crystal data storage when reading data from the DD _ display are shown in figure 1. RAM or the CG RAM. When the MPU writes address information into the IR, the LCD-IIA The DD RAM adress (App) is set in the address sends data to the DR fromthe DDRAMorthe counter (AC) and is represented in hex- CG RAM by internal operation. Data transfer adecimal. to the MPU is then completed by the MPU Teading DR. After the MPU reads the DR, the When there are fewer then 80 display cher- LCD-IIA sends data in the DD RAM or CG __acters, the display begins at the head positon. RAM at the next address to the DR for the —_ For example, 8 characters using an HD66780 next read from the MPU. Register selector _are displayed as shown in figure 2. (RS) signals select these two registers (table 2). When the display shift operation is perfor- 4 med, the DD RAM address moves as shown in Busy Flag (BF) figure 3. When the busy flag is 1, the HD66780isinthe A 16-character display using an HD66780 and internal operation mode, and instructions will an HD44100H is shown in figure 4. not be accepted. As table 2 shows, the busy flag is output to DB 7 when RS = 0 and R/W _—_The relation between display position and DD = 1, The next instruction must be written RAM address when the number of display after confirming that the busy flag is 0. digits is increased through the use of one HD66780 and two or more HD44100Hs can be Address Counter (AC) considered an extension of figure 4. The address counter (AC) assigns addresses Since the increase can be 8 digits for each Co eSSSSSSSSSSSSSSSSSSSSSSseesesFesSsSSSSSSSSSFFessFssee Table 2 Register Selection RS Rw Operation 0 ° IR write as internal operation (Display clear, etc) ° 1 Read busy flag (DB7) and address counter (DBo-DBe) 1 0 DR write as internal operation (DR to DD or CG RAM) 1 1 DR read as internal operation (DD or CG RAM to DR) SSS — a a OOO HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 + (415) 589-8300 171

HD 66780 (LCD — 1A) Table 3 (iene Stanners HOSSTOOR DG oie and Character Pattern Pl lc lO peewoltt] | EVAR T |e alee py povomle ||P LAiGY ays) ie [PF cl Sicy ne eatSes Gores pooven| | ASCE ics] | [a FE soo peewee) RAE Tiedt | Tb Palsy peeie JAE Weu) | say Ish pve) SIF Ma alpe) pele PEGS) | RR igir peel] EAR Ris) 4 RL pmo] SDV | aT ey penned PRE Feliz) | ine] peo] FRE CK 2 a foe F prom fe ILI) eee peel SMe) | alRN Del] peel TA ne aE SSONZEECCMRCM | HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 175

HD66780 (LCD ~ II A) a a et Table 4 shows the relation between CG RAM _As table 4 shows, an area that is not used for addresses and data and display patterns. display can be used as general data RAM. eS Table 4 Relation between CG RAM Address and Character Codes (DD RAM) and Character Patterns (CG RAM Data) For 5 x 7-dot character patterns Character Codes CG RAM Character Patterns {DD RAM Data) Address (CG RAM Data) 765 43 2 1 0 643210 76543210 Higher Lower | Higher Lower Higher Lower + Order Order +: t Order Order Order Order ~ Bits Bas | Bts Bits | | Bits Bits 0000+ 000 000000 rs 0 i | 001 000 | o10 000 Character | od O Pattern H 100 oO 00 Example 101 0 O[fjo | 110 0 0 OL] Cursor | | . rad _ * * * 07 Co) Oo 00 Position | 001 o}TLofi to H 010 T4109 4-4) Character | o11 00] 1[0 0 Pattern 100 71 141] Example 2 i 107 | 0 0]1f0 0 | 110; | 0 ol1jo o / | td [x ** 00000 ooo xe ® - oo: o000%11 1) 144 | | 320 | | 101 * No effect i110 (Don't care) rtd eae Notes: 1. Character code bits 0-2 correspond to CG RAM address bits 3-5 (3 bits: 8 characters) 2. CG RAM address bits 0-2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor Maintain the 8th line data, corresponding to the cursor display position, in the O state for cursor display. When the 8th line data is 1, bit 1 lights up regardless of cursor presence. 3. Character pattern row positions correspond to CG RAM data bits 0-4, as shown in the figure (bit 4 being at the left end) Since CG RAM data bits 5-7 are not used for display, they can be used for the general data RAM 4. As shown in table 3 and 4, CG RAM character patterns are selected when character code bits 4-7 are all 0. However, since character code bit 3 is ineffective, the R display in the character pattern example, is selected by character code 00 (hexadecimal) or OB (hex- adecimal) 5. 1 for CG RAM data corresponds to selection for display and 0 for non-selection HITACHI 176 — Hitachi America Ltd * Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane. CA 94005-1819 « (415) 589-8300

HD66780 (LCD ~— IT A) Table 4 Relation between CG RAM Address and Character Codes (DD RAM) and Character Patterns (CG RAM Data) (Cont) For 5 x 10 -dot character patterns Character Codes CG RAM Character Patterns (DD RAM Data) __ Address (CG RAM Data) 76643210 $4321 0 76543210 Higher Lower Higher Lower Higher Lower + Order Order Order Order + +-Order Order + Bis Bits Bits Bits (Bits Bits 0000+ 00 000000 *** 00000 i | 0001 00000 | ! oo10 Tlofi 10 | | 001} ! 1110 0/1] Character ! 0100 j |1fO 0 of 1; Pattern | | 0101 | 1[0 0 0[1) Example | i 0110 1171 1]0 | o1dt 1f0 000 | 1000 | 1/0000 | 1001 | 1}0 000 Cursor | | 1010 [+ * * 0 0 0 0.0 = Position i | ,oO17 i | 1100 41014 i t 1110 | { yaad [et ew eR Re 0000 eae | 0001 t a — 4 1010 see \\ ,oO.s a es | 1100 4 | ,107 ‘ raidiga No effect i : rrdt yok A eH oH Re Don't care) Notes. 1. Character code bits 1, 2 correspond to CG RAM address bits 4, 5 (2 bits. 4 characters) 2. CG RAM address bits 0-3 designate character pattern line position. The 11th line is the cursor position and display is performed by logical OR with cursor Maintain the 11th line data corresponding to the cursor display position in the O state for cursor display. When the 11th line data 1s 1, bit 1 lights up regardless of cursor presence Since the 12nd-16th lines are not used for display, they can be used for the general data RAM 3. Character pattern row positions are the same as 5 = 7 dot character Pattern positions. 4 CG RAM character patterns are selected when character code bits 4-7 are all 0. However, since character code bit 0 and 3 are ineffective, P display in the character pattern example is selected by character code 00. 01, 08 and 09 (hexadecimal) 5. 1 for CG RAM data corresponds to selection for display and O for non-selection HITACHI Hitachi America, Ltd « Mitac Plaza * 2000 Sierra Point Pkwy. ° Brisbane, CA 94005-1819 « (415) 589-8300 177

HD66780 (LCD — IIA) eee eee Timing generation Circuit latched when all needed data has arrived. The latched data controls the driver for The timing generation circuit generates tim- generating drive waveform outputs. ing signals to operate internal circuits such as DD RAM, CG ROM, and CG RAM. RAM read _—The serial data can be sent to HD44100H or timing needed for display and internal oper- _HD66100Fs, externally connected in cascade, ation timing by MPU access are separately _to display an extended number of characters. generated so that they may not interfere with each other. Therefore, when writing The LCD-IIA always starts sending serial data to the DD RAM for example, there will data at the display data character pattern be no undesirable influence, such as flicker- corresponding to the last address of the dis- ing, in areas other than the display area. This _ play data RAM (DD RAM). circuit also generates timing signals to oper- ate the externally connected drivers Since serial data is latched when the display (HD44100H or HD66100F). data character pattern, corresponding to the starting address, enters the internal shift Liquid Crystal Display Driver Circuit register, the HD66780 drives the head of the display. The rest of the display, corresponding The liquid crystal display driver circuit con- _to later addresses, are added with each addi- sists of 16 common signal drivers and 40 _ tional HD44100H or HD66100F. segment signal drivers. When the character font and number of lines are selected by a Cursor/Blink Control Circuit Program, the required common signal drivers automatically output drive waveforms. The —‘The cursor/blink control circuit generates the other common signal drivers continue to cursor or blinking. The cursor or blinking output non-selection waveforms. appear in the digit residing at the display data RAM (DD RAM) address set in the The segment signal driver has essentially the address counter (AC). same configuration as the driver LSI HD44100H. Character pattern data is sent When the address counter is (08), the cursor serially through a 40-bit shift register and _position is as shown in figure 10. HITACHI 178 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300

HD66780 (LCD— IIA) AC6 ACS AC4 ACZ3 AC2 ACI ACO e [ofofo]sfofelo} | Ina 1-line display (Digit) 1 2 3°94 6 6 7 8 9 10 11 Display Position [00% [02 [02] 0s [os foe ]or ge [os [oa] ) po nam Cursor Position (Hexadecimal) In a 2-line display (Digit) 1 2 3.4 6 6 7 8 9 10 11 __Display ws [cor [ea] oso [o[or[g] [en] | So anaine [4041 [a2] 49 [aa] 450] a7 [ao] ao) ea] | tein | Cursor Position | Note: The cursor or blink appears when the address. counter (AC) selects the character generator RAI | fe pitetiper tite ‘depleyed pike eomnnieas eeition when AC is the CG RAM address. | Figure 10 Cursor or Blink HITACHI Hitachi America, Ltd, «Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 179

HD66780 (LCD-— II A) MPU Interface The HD66780 can send data in either two 4- transferred first, then the lower order 4 bits bit operations or one 8-bit operation so itcan (contents of DBy~DB3 when interface data is interface to both 4-and 8-bit MPU's. 8 bits long) is transferred. When interface data is 4 bits long, data is Check the busy flag after 4-bit data has been transferred using only 4 bus lines: DBy—DBy. transferred twice (one instruction). Two 4-bit DBo—DB, are not used. Data transfer between operations will then transfer the busy flag the HD66780 and the MPU completes when and address counter data (figure 11). 4-bit data is transferred twice. When the interface is 8 bits long, data is Data of the higher order 4 bits (contents of _ transferred using the 8 data bus lines DBo— DB4— DB; when interface data is 8 bits long) is DB». SSS Reset Function Initializing by Internal Reset Circuit 3. Display on/off control a. D = 0: Display off The HD66780 automatically initializes (re- b, C = 0: Cursor off sets) when power is tumed on using the c. B = 0: Blink off internal reset circuit. The following instruc- 4. Entry mode set tions are executed at initialization. The busy a. 1/D = 1: + 1(increment) flag (BF) is kept in busy state until initializa- b.S = 0: No shift tion ends (BF = 1). The busy state lasts 10 ms after Vcc rises to 4.5 V. Note: When power supply conditions in the electrical characteristics are not met using 1. Display clear internal reset circuit, the internal reset circuit 2. Function set will not operate normally and initialization a. DL = 1: 8-bit long interface data will not be performed. In this case initialize b.N = 0: 1-line display by MPU according to initializing by instruc- c. F = 0; 5x7-dot character font tion. ——SSSSSSSSSSSSSSSSSSSSSSSSS ES VS VS VS LS NY VE 0B, Kn) Cz, Cac» CAPEDOD DBe| <> ae, So), KAC2) OR EDO DBs | Ks Xa <, <p, Kon KOR DB, > GOD, K Aco) KOREN” Instruction (IR) Busy Flag (BF) and Data Register (OR) Write Address Counter (AC) | Read Read Figure 11 4-Bits Data Transfer Example HITACHI 180 — Hitachi America, Ltd. + Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300

HD66780 (LCD— IIA) SOOO Er Instructions Only two HD66780 registers, the instruction used most frequently. However, automatic register (IR) and the data register(DR)canbe —_incrementing by 1 (or decrementing by 1) of directly controlled by the MPU. Prior to HD66780 internal RAM addresses after each internal operation start, control information is data write lessens the MPU program load. temporarily stored in these registers, to allow The display shift especially can be performed interface from HD66780 internal operation to concurrently with display data write, en- various types of MPU's which operate at bling the designer to develop systems in different speeds or to allow interface to | minimum time with maximum programing peripheral control IC's. HD66780 internal efficiency. For an explanation of the shift operation is determined by signals sent from —_ function in its relation to display, see table 7. the MPU. These signals include register selection signals (RS), read/write signals During internal operation, no instruction (R/W), and data bus signals (DBy—DBy), and other than the busy flag/address read are here called instructions. Table 5 shows _ instruction will be executed. Because the the instructions and their execution time. busy flag is set to 1 while an instruction is Details are explained in subsequent sections. being executed, check to make sure it is on 0 before sending an instruction from the MPU. Instructions are of 4 types, those that: Note: Make sure the HD66780 is not in the 1, Designate HD66780 functions such as busy state (BF = 0) before sending the display format, data length, etc instruction from the MPU to the HD66780. If 2. Give internal RAM addresses the instruction is sent without checking the 3. Perform data transfer with internal RAM _busy flag, the time between first and next 4. Others instructions is much longer than the instruc- tion execution time. See table 5 for a list of In normal use, category 3 instructions are _—_each instruction’s execution time. HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 181

HD66780 (LCD— II A) eee eee Table 5 Instructions Execution Time See (top oS 260 Instruction —RS_R/WDB7 DB¢ DBs DB, DBs DB2 DB; Bp Description kHz) Clear 0-0 0 0 0 0 0 0 O 1 Clearsentire display andsetsDD 1.64 ms Display RAM address O in address counter Return 0 0 0 0 0 0 0 0 1 * Sets DD RAM address 0 in 1.64 ms Home address counter. Also returns display being shifted to original Position. DD RAM contents remain unchanged Entry 0 0 0 0 0 0 0 1 WOS Sets cursor move direction and 40 us Mode Set specifies shift of display. ‘These operations are performed during data write and read Display 0 0 0 0 0 0 1 D C B Sets entire display on/off (D), 40 us On/oft cursor on/off (C), and blink of Control cursor position character (B) Cursor or 0 0 0 0 0 1 S/CR/L * * Moves cursor and shifts display 40 us Display without changing DD RAM Shift contents Function 0 0 0 O 1 DLN F © « Sets interface data length (OU, 40a8 Set number of display lines (N) and character font (F) SetCGRAMO 0 0 1 ACG Sets CG RAM address. CGRAM 40 us Address data is sent and received after this setting. SetDDRAMO O 1 ADD ‘Set DD RAM address. DD RAM 40 us Address, data is sent and received after this setting. Read Oo 1 BF AC Reads Busy flag (BF) indicating 0 us Busy Flag internal operation is being per- & Address formed and reads address counter contents Write Data 1°00 Write Data Writes data intoDD RAM orCG 46 us. to CG or RAM DD RAM Read Data 1 1 Read Data Reads data from DD RAM orCG 46 xs from CG or RAM DD RAM Notes: 1. VO = 1: Increment BF == 1: Internally operating /D = O: Decrement BF = 0: Can accept instruction S = 1: Accompanies display shift OD RAM: Display data RAM S/C = 1: Display shift CG RAM: Character generator RAM S/C = 0: Cursor move ‘Aco: CG RAM address R/L_ = 1: Shift to the right ‘Ago :DD RAM address R/L_ = O: Shift to the left Corresponds to cursor DL = 1: 8 bits, DL = O: 4 bits address N = 1: 2 lines, N = 0: 1 line AC : Address counter used F = 1: 8x10 dots, F = 0: 5x7 dots for both DD and CG RAM 2. * No effect (Don't care) 3. Execution time changes when frequency changes. Example: When fcp or fosc is 270 kHz: 250 40 us x 270 7 37 us HITACHI 182 Hitachi America, Ltd. «Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300

HD66780 (LCD— IIA) aaa ae for a 1-line display and 16 digits for a 2-line When the liquid crystal display panel has display. unused extra scanning lines, avoid undesir- able influences due to cross-talk in the float- In figure 31 examples (a) and (b), there are ing state by connecting the extra scanning unused common signal terminals, which lines to these common signal terminals (fig- always output non-selection waveforms. ‘ure 32). a COM; SSS=——a—S SS ESF com, FT SEG, E—I]] ----e eeeLLLL Uquid Crystal (8 characters SEG ao} * 1 line) (a) Example of a 5 x 7-dot, 8-character x 1-line Display (1/4 Bias, 1/8 Duty Factor) eo. ———— aS —_—— HD66780 SSF Liquid Crystal i Display Pane! (8 characters SEGi *1 tine) (b) Example of a 5 x 10-dot, 8-character x 1-line Display (1/4 Bias, 1/11 Duty Factor) OM, oo com | a com, -—— Me | comef ttt tite 068780 | oa SEG, ll] i Liquid Crystal i Display Pane (8 characters SEGso} *2 lines) (c) Example of a 5 x 7-dot, 8-character x 2-line Display (1/5 Bias, 1/16 Duty Factor) Figure 31 Liquid Crystal Display and Connections to HD66780 HITACHI 190 Hitachi America, Ltd, » Hitachi Plaza + 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300

HD66780 (LCD — ITA) SSS OO OEE NA) Connection for Changed Matrix Layout: In Relation between Oscillation Frequency the preceding examples, the number of ines and Liquid Crystal Display Frame Fre- ‘was matched to the number of scanning quency lines. The display types in figure 33 are pos- sible by changing the matrix layout in the Figure 35 shows examples of liquid crystal liquid crystal display panel. display frame frequency when the oscillation frequency is 250 kHz (1 clock = 4 ys). In either case, the only change is the layout. Display characteristics and the number of Connection with Driver LSI HD44100H or liquid crystal display characters depend on HD66100F the number of common signals (or duty fac- tor). Note that the display data RAM (DD You can increase the number of display RAM) address for 8 characters x 2 lines and characters by externally connecting liquid 16 characters x 1 line are the same as shown. crystal display driver LSI’s HD44100H or in figure 31. HD66100F to the HD66780. Power Supply for Liquid Crystal Display When connected to the HD66780, the Drive HD44100H or HD66100F is used as a segment signal driver. The HD44100H and the Various voltage levels must be applied to HD66100F can be connected to the HD66780 HD66780 terminals V; to Vs to obtain liquid directly since they supply CLi, CL2, M, and D crystal display drive waveforms. The voltages signals and power for liquid crystal display must be changed according to duty factors. drive. Figures 36 and 37 show connection Table 9 shows the relation. examples. Vico gives the peak values for liquid crystal Note: Connection of voltage supply terminals display drive waveforms. Resistance dividing Vi through V¢ for the liquid crystal display Provides each voltage as shown in figure 34. drive is complicated. yuu DuyFusw aapowusunyintmucyepmmew FeAl Table 9 Duty Factor and Power Supply for Liquid Crystal Display Drive 4 | Power Supply Paclor Blas Vi ve Va Ve ve WBA 1/4 Voc (1/4Mico Veo ~(1/21Mico Vee - (1/2)Vico Vee - (9/4)Vico Vee - View 1/16 1/5 Voc = (1/5)Vuco Vee - (2/8)Vuco Vee - (3/5)Vico Vee - (4/5)Vico Vee - Vico

106 VS Vee" (1/8Mico Ver - (2/8)Vico_Vec - (8/5)Vico Vee -(4/5)Vico__Vec- Vico

COM, | com, 2 HD66780 SEG. 5 x 7-dot, 8-character x 1-line Display (1/4 Bias, 1/8 Duty) Figure 32 Using COM to Avoid Cross-Talk on Unneeded Scanning Line HITACHI Hitachi America, Ltd. «Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 191

ee SSSSSSSSSSSSSSSSSSSOAae HD66780 (LCD— IIA) eI TON ATA) Up to 9 HD44100Hs can be connected fora 1- _of 80 character diaplay digits. The connection line display (duty factor 1/8 or 1/11) and upto -—s method in figures 36 and 37 remains un- 4 for @ 2-line display (duty factor 1/16). (For changed for both 1-line and 2-line display the HD66100F, 5 and 2 units respectively.) | and both § x 7-and § x 10-dot character RAM size limits the HD66780 to a maximum _fonts. SSMS (1) 1/8 Duty Factor 400 clocks Vee com oy, V2 (V3) Va Vs: 1 frame 1 frame 1 frame = 4 (us) x 400 x 8 = 12800 (us) = 12.8 (ms) Frame frequency = “F28 may ~ 78-1 (He) (2) 1/11 Duty Factor 400 clocks Vee CoM, oy, Va (V3) 4 Ve Ve . 1 frame 1 frame 1 frame = 4 (us) x 400 x 11 = 17600 (ws) = 17.6 (ms) Frome frequency = 77-7may = 56.8 (He) (3) 1/16 Duty Factor 200 clocks ce COM: Vy Va Vs Ve Vs: 1 frame 1 frame 1 frame = 4 (us) x 200 x 16 = 12800 us) = 12.8 (ms) Frame frequency = —5-gimay- = 78-1 (He) Figure 36 Liquid Crystal Display Waveforms (at fosc = 250kHz) HITACHI Hitachi America, Ltd. « Hitachi Ptaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819» (415) 589-8300 193

HD66780 (LCD—II A) LI § 28 Yj} ox Val 8 ve _ TY | = vi SS os SP . 3 a? | > M a $22 & a 255 mn UI

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= > i ; geet 4 iz g ° dg? $2555 3 ia t 5 a = oo Figure 36 Example of Connecting HD44100H to HD66780 HITACHI 194 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. + Brisbane, CA 94005-1819 » (415) 589-8300

HD66780 (LCD— ITA) a Ma a —," 8 ——ae | 3 a a ie M a Cll r=} FA Clr —T_| . t teteadde } 3 fox YW E=FFFE ; 8 YESEEEPAH ; _—---- Ve § e = ye TT Ss *E eee | 3 Ye ea TTT ry enoe——+- +++ 3 be ad we i A z chi mil By Fy a dazs oss = oO > 85 % ° g Lt - 5 +4 g 3 Figure 37 Example of Connecting HD66100F to HD66780 HITACHI Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 195

i SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSSse HD66780 (LCD-— II A) Instruction and Display Correspondence moves from the first to the second line after 8-bit Operation, 8-digit x 1-line Display the 40th digit of the first line has been writ- (Using Internal Reset): Table 10 shows an _ten. Thus, if there are only 8 characters in the example of an 8-bit x t-line display in 8-bit _first line, the DD RAM address must be set operation. The HD66780 functions must be _after the eighth character is completed (see set by the function set instruction prior to table 12). Note that the first and second lines display. Since the display data RAM can store _of the display are shifted. data for 80 characters, as explained before, the RAM can be used for advertising displays In the example, the display is shifted when when combined with display shift operation. _ the cursor is on the second line. However, if Since the display shift operation changes the shift operation is performed when the display position only and DD RAM contents _ cursor is on the first line, both the first and remain unchanged, display data entered first _ second lines move together. When you repeat can be output when the retum home opera- _the shift, the display of the second line will tion is performed. not move to the first line, the same display will only move within each line many times. 4-bit Operation, 8-digit x 1-line Display (Using Internal Reset): The program must set Note: When using the internal reset, the functions prior to 4-bit operation. Table 11 _conditions in “Power Supply Condition Using shows an example. When power is turnedon, —_ Internal Reset Circuit” must be satisfied. If 8-bit operation is automatically selected and not, the HD66780 must be initialized by the LCD-IIA attempts to perform the first _ instruction. (See “Initializing by Instruction”) write as an 8-bit operation. Since nothing is connected to DBo-DBs, a rewrite is then _ Initializing by Instruction required. However, since one operation is completed in two 4-bit accesses, a rewrite is If the power supply conditions for correctly needed to set the functions (see table 11 step operating the internal reset circuit are not 3). met, the LCD-IIA must be initialized by instruction. Thus, DB,-DB; of the function set is written When interface is 8 bits long, use the initial- twice. ization procedure in figure 38. 8-bit Operation, 8-digit x 2-line Display: When interface is 4 bits long, use the initial- For a 2-line display, the cursor automatically _ ization procedure in figure 39. HITACHI 196 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD66780 (LCD— II A) Table 10 8-Bit Operation, 8-Character x 1-Line Display Example (Using Internal Reset) Step No. _ Instruction Display Operation | 1 Power Supply On (HD68780 ie Initiaized. No display appears. initialized by the internal reset circuit) | 2 Function Set Sets to 8-bit operation and selects 1- RSRWWOB7- = + = By line display and one of the three char- 00001100 ([ ] acter fonts. (Number of display lines and character font cannot be changed after this.) 3 Display On/Off Controt Turns on display and cursor. Entire 00000011 1 0 [_______] display is on space mode because of initialization @__ Entry Mode Set Sets mode to increment the address by 00 0.000001 1 0 ;————) _oneand to sift the cursor tothe right at the time of write to the DD/CG RAM. Display is not shifted. 5 Write Data to CG RAM/DD RAM Writes “H”. The DD RAM hes already 1001001000 been selected by initialization when the [Ho] power is turned on. The cursor is incremented by one and shifted to the right. & Write Data to CG RAM/DD RAM SCs = 1001001001 7 i 8 Write Data to CG RAM/DD RAM Writes “I”. 1001001001

9 Entry Mode Set Sets mode for display shift at the time

ooo00000111 of write. 10 Write Data to CG RAM/DD RAM Writes space. 1000100000 11 Write Data to CG RAM/DD RAM Writes “M". 1001001 1-01 12 E 13 Write Data to CG RAM/DD RAM Writes “0”. too1rooiri1i4

14 Cursor or Display Shift Shifts only the cursor position to the

00000100 + + ([MICROKO left.

15 Cursor or Display Shift Shifts only the cursor position to the

00000100 » left. T6 Write Data to CG RAM/DD RAM TEROCO Writes “C* (correction). 1001000011 The display moves to the left.

17 Cursor or Display Shift Shifts the display and cursor position to

ooo0oo0T1T «* & 2 the right.

18 Cursor or Display Shift Shifts only the cursor position to the

00000101 « + (MICROCO right.

19 Write Data to CG RAM/DD RAM Writes “M™

20 z :

21 Return Home Returns both display and cursor to the

HD66780 (LCD— IIA) Table 11 4-Bit Operation, 8-Character x 1-Line Display Example (Using Internal Reset) : Step No. _ Instruction Display Operation 1 Power Supply On (HD66780 is Initialized. No display appears. initialized by the internal reset circuit) a

2 Function Set Sets to 4-bit operation

RS RW DB, - = DB, —-_]_ In this case, operation is handled as 8 ° ° 0 ° 1 oO J bits by initialization, and only this _ instruction completes with one write

3 Function Set Sets to 4-bit operation and selects 1-

0 0 0 0 1 0 line display and one of the three char- 0 0 0 0 «* «# (tte fonts. 4-bit operation stats from — this point on and resetting is needed. (Number of display lines and character font cannot be changed after this.) 4 Display On/Off Control Turns on display and cursor. Entire 0 0 0 0 0 0 {~~ ] display is in space mode because of oo 1 1 1 ~0 ~ 7 initialization.

5 Entry Mode Set ‘Sets mode to increment the address by

0 0 0 0 0 o ——— _ one and to shift the cursor to the right, 0 0 0 1 1 °0 [atthe time of write, to the DD/CG _ RAM. Display is not shifted 6 Write Data to CG RAM/DD RAM Writes “H”. The DD RAM has already 1 0 0 1 °0 0 been selected by initialization when the 1 0 1 0 0 0 [H______] __ power is turned on. The cursor is in- cremented by one and shifted to the right After this, control is the same as 8-bit operation. HITACHI 198 Hitachi America, Ltd. « Hitachi Plaza + 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 « (415) 589-8300

HD66780 (LCD— IIA) Table 12 8-Bit Operation, 8-Character x 2-Line Display Example (Using Internal Reset) ‘Step No. _ Instruction Display Operation : 1 Power Supply On (HD66780 is Initialized. No display appears. intialized by the internal reset circuit) ——|

2 Function Set Sets to 8-bit operation and selects 2-

RS RWOB 7+ . . Bo ee line display and one of the three char- 00001110 #* * acter fonts. 3” Display On/Off Control ‘Turns on display and cursor. All display 0000001110 — is in space mode because of initializa- tion.

4 Entry Mode Set ‘Sets mode to increment the address by

: 0000000110 ‘one and to shift the cursor to the right, at the time of write, to the DD/CG 5 Write Data to CG RAM/OD RAM Writes “H”. The DD RAM has already 1001001000 been selected by initialization when the : power is turned on. | ‘The cursor is incremented by one and | —_—_stifted to the right

6 E H

7 Write Data to CG RAM/DD RAM Writes “I”,

8 Set 0D RAM Address: Sets RAM address so that the cursor

0011000000 may be positioned at the head of the 2nd line. 9” Write Data to CG RAM/DD RAM [HITACHI] Writes “M™. 4 10 i i 11 Write Data to CG'RAM/DD RAM Writes “0°.

12 Entry Mode Set ‘Sets mode for display shift at the time

0000000111 tAES of write. 13 Write Data to CG RAM/DD RAM Writes “M”. Display is shifted to the 1001001101 left. TCROCOM The first and second lines’ shift is operated at the same time. 14 i E

18 Return Home Returns both display and cursor to the

0000000010 MICROCOM original position (address 0). HITACHI Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 199

HD66780 (LCD— II A) Frc tan, Wait more than 15 ms after Vcc rises to 4.5 V RSRMW DB; DBy DBs DB, DB, DB, 0B, 08y| [BF cannot be checked before this instruction © 0 0 O 1 4 + + * *)} Function set (interface is 8 bits long) Wait more than 4.1 ms BF cannot be checked before this instruction O_O 0 0 1 1 + + + *) Function set (Interface is 8 bits long) BF cannot be checked before this instruction © 0 0 O 1 1 _+ + * =] Function set (Interface is 8 bits long) BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instruction _ time (see table 5) RS RW DB, DB¢0850B, 08308708; 08>) — Function set (Interface is 8 bits long 0 0 0 0 1 1_N F_* | Specifiy the number of display lines and character font.) 0 0 0 0 0 0 1 6 0 0] The number of display lines and character font cannot O80 OOO OO] (Be Changed afterwards 0-0 0 0 0 0 0 1 WO S| display ott Display Clear Initialization ends Entry Mode Set Figure 38 Initialization by Instruction, Eight-Bit Interface HITACHI 200 Hitachi America, Ltd. + Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD66780 (LCD— IIA) Wait more than 15 ms after Vcc rises to 4.5 V oo o on} Function set (Interface is 8 bits long) [Wait more than 4.1ms oo Oo o rit Function sat (Interface is 8 bits long) BF cannot be checked before this instruction 4 oo oO oO 1 1 Function set (Interface is 8 bits length) RS R/W DB, DB. OB, DB, BF can be checked after the following instructions. 0 0 0 0 1 0 When BF is not checked, the waiting time between O70 OOOO instructions is longer than the execution instruction 0 0 000 0 0 0 1 000 Function set (Set interface to be 4 bits long.) o_o o o o 4 Function set (Interface is 4 bits long. Specify the num- ber of display lines and character font.) oo o 1 vO Ss The number of display lines and character font cannot be changed afterwards. Initialization ends Display off Display Clear Entry Mode Set Figure 39 Initialization by Instruction, Four-Bit Interface HITACHI Hitachi America, Ltd. » Hitachi Plaza » 2000 Sierra Point Pkwy. ° Brisbane, CA 94005-1819 « (415) 589-8300 201

HD66780 (LCD— II A) ee OES LCD-II and LCD-IIA Table 13 shows the differences between the _figure 40, is used for alternation in 1 frame, LCD-II and LCA-IIA. and B type, shown in figure 41, for alternation in 2 frames. B type has better display quality There are two types of multiplex waveforms _in highly multiplexed drive. for LCD driving: A and B. A type, shown in SSSSSSsSsssssseeeSeSSS Table 13 Functions Comparison between LCD-II and LCD-IIA Item LCD-II (HD44780) LCD-IIA (HD66780) _Note Display RAM ‘80 bytes (80 characters) Same as LCD-II {Maximum number of display characters) ; ; * Character generator ROM 7200 bits 12000 bits (Kinds of characters) 192 characters 240 characters 5%7:160 characters 510: 240 characters _ 5X10: 32 characters _ Character generator RAM 64 bytes ‘Same as LCD-II (Number of characters) (8 characters) LCD driving terminals 16 COMs ‘Same as LCD-I! (Maximum number of 40 SEGs display characters/ (16 characters) unit) Character font 5x8 dots Same as LCD-II (with a cursor) __ 5x11 dots 7 Multiplexing duty ratio 1/8, 1/11, 1/16 ¥LCD driving voltage 1/4 bias 3.0 to 11 (v) 3.0 to Vee (V) Vee to Vs (V) 1/5 bias 4.6 to 11 (v) 3.0 to Vee (v) LCD driving waveform “A waveform __B waveform See figures 40,41 * Bus timing 1, 1.5 MHz 2 MHz . Instruction codes 11 instructions Same as LCD-Ii Power-on reset circuit Yes Same as LCD-II Oscillator Ceramic filter, Rf, Same as LCD-II (Frequency) external clock (250 He) Interface HD44100H HD44100H or HD66100F Package FP-80, FP-80A Same as LCD-II Pin arrangement Refer to p.98 Same as LCD-II — a arengement _______Refertop.98 _Sameas LCD Note: * indicates the modified items on LCD-IIA. HITACHI 202 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300

HD66780 (LCD— IIA) Segment Common-segment m4, an ' 1 frame | 1 frame ! | Figure 40 A-Type Waveforms (1/3 Duty Factor, 1/3 Bias) | ; Common-segment + ‘1 frame + Figure 41 B-Type Waveforms (1/3 Duty Factor, 1/3 Bias) HITACHI Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 203

=—_—_ HD66780 (LCD-— II A) a Character Pattern Development Procedure The numbers in the above figure correspond = —_—§, Hitachi performs computer processing to the following operations: with the EPROM to create a character pattem listing and sends it to the user. 1. Determime the correspondence between _—6. If there is no problem in the character character codes and character patterns. pattern listing, Hitachi creates trial LSIs. 2. Create a listing indicating the correspon- and sends samples to the user. The user dence between EPROM addresses and evaluates the samples. When it is con- data. firmed that character patterns are cor- 3. Program character patterns in the rectly written, mass production of LSI is EPROM. started. 4. Send the EPROM to Hitachi. SSS trae ee Compuree [s=] |: pater kang cross data beg Evalue character a 2 ves L~ ] [~~] J \\==-/ © <x > we ves Figure 42 Character Pattern Development Procedure HITACHI 204 Hitachi America, Ltd. » Hitachi Plaza ¢ 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 * (415) 589-8300

—— sw HD66780 (LCD-— II A) Character Pattern Program Method In order to evaluate ROM patterns, we rec- ommend to use our LCD controller HD61830. The relationship between the EPROM We also supply LCD control board (CB1026R) address and character pattern is shown in table 14 SSS Table 14 Character Data in EPROM EPROM Address Data (right sile up) usa) Ary Ato As Ae Ar Ag As As’ Ay Ay Ar Ao) Oo O; O2 Os Og Os O6 O7 0 0 0 0:0 0 0 0 0 ie) ie) oO 1 i) ie) io) ce) io) , oo Oo 0 1 0 oO} 1 4) 0/1 oo 1 1) 4/0 of] 4}a 0 1 0 0} 1/0 0 oj} 14 Pororotr 0 0 0 1 0 1 GO T44} 0 0 Of 1 oO 1 1 OF} 0} 4 4 4°14 o 1 1 150 0 0 of 1 4 "10 0 0 0 0 0 0 | 1 ;1 0 0 1 0 0 0 o}1 1 ° 1 i) °O ce ° ie) io) 1 ° 1 1 1 10.0 1 1 fe) 1 er) 1 1 1 1 ee Character code Line code Notes: 1. EPROM Data Os-O; are invalid 2. Data "O” must be programed at 11th line (cursor position) 3. Data at 12-16th line are invalid 4. Data at Oo locate at the left side of screen. (The relation between the bit number and position 1s reversed, compared with HD44780.} HITACHI Hitachi America, Ltd * Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94095-1819 + (415) 589-8300 205

HD66780 (LCD—IIA) SSS Handling Unused Character Patterns a. When unused character patterns are not programed 1. EPROM data outside the character pat- tern area If an unused character code is written in the LCD-II DD RAM, all dots are lit. Ignored by the character generator ROM No programming for a character pat- for display operation so it can be 0 or 1. tern is equivalent to all bits lit. (This is because the EPROM is filled with 1 2. EPROM data in CG RAM area when the EPROM is erased.) Ignored by the character generator ROM b, Program 0 for unused character pat- for display operation so it can be 0 or 1. tems 3. EPROM data used when the user does not Nothing is displayed even if unused use any LCD-I character pattern character codes are written in LCD-II DD RAM. (It is equivalent to space.) Handled in one of the two ways explained below. Select one of two ways according to the user application. Absolute Maximum Ratings Item ‘Symbol! Rating Unit Power Supply Voltage Vee -0.3 to +7.0 v Input Voltage Vr -0.3 to Vec + 0.3 v Operating Temperature Topr -20 to +75 c Storage Temperature Tstg -B5 to +125 c Notes: 1.If LSIs are used above the absolute maximum ratings, they may be permanently destroyed. Using them within electrical characteristic limits is strongly recommended for normal opera- tion. Use beyond these conditions will cause maifunction and poor reliability. 2. All voltage values are referred to GND = 0 V. 3. Applies to V1 to VS. The relation: Vcc2V12V32V42V5=GND must be maintained. (high to low) HITACHI 206 Hitachi America, Ltd. » Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD66780 (LCD— IIA) EEE

Electrical Characteristics

item Symbol Min Typ Max Unit Test Condition Note : Input High Voltage (1) Vint 2.30 - Veo OV (2) Input Low Voltage (1) Var = - O68 V (2) Input High Voltage (2) Vin2___Vec- 1.0 — Vec V _ (12) Input Low Voltage (2) We - - 10 WV (12) Output High Voltage (1)(TTL) Vout 240 - - Vv clon = 0.205 mA (3) Output Low Voltage (TTL) Vor Vt = 1.6 mA 3) Output High Voltage (2)(CMOS) Von2 _0.9Vec ~ ~~ ~—SV_—-ton = 0.04 mA (4) Output Low Voltage (2)(CMOS) Vor — = O.1Vce Vt = 0.04 mA (ay Driver On Resistance (COM) Room ~ = 20 ka tid = 0.05 mA (10) to each COM Pin Driver On Resistance (SEG) Roc OSC tI = 0.05 mA (10) to cach SEG Pin Input Leakage Current he 1 - 1 uA Vin = 0 to Vec (5) Pull up MOS Current “lp 50. 125 250 “A Vec=5V Power Supply Current (1) ect = 0.65 0.8 mA Ceramic filter oscillation (6) Vec = 5V, fosc = 250 kHz Power Supply Current (2) Tee2 = 0.35 0.6 mA Rf oscillation, ) External clock operation (11) Vee = 5 V, fosc = fop = 270 kHz External Clock Operation nc cccsceeeeeeseecndentgnceasseeenesgeeneneneeeeeeeeeerewe™ coeeeeceecceceeee External Clock Frequency foo 126 260 360 kHz a External Clock Duty Duy 45 50 55 % m ) External Clock Rise Time ep = = 02 us a) ) External Clock Fall Time tree = - 0.2 us (7) | intemal Clock Operation (Rf Oscilation) on - ) Clock Oscillation Frequency fose. 190 270 350 kHz Af = 82 kN+2% (8) Internal Clock Operation (Ceramic Filter Oscillation) . cceeesnssnsessasee Clock Oscillation Frequency fosc 245 250 255 kHz Ceramic filter ) LCD Voltage Vicon 3.0 - Voc V Vec-Vs 1/5 bias (13) Vicon 3.0 - Vec_~ V 1/4 bias (13) Notes: 1. Figure 43 shows the I/O pin configurations except for liquid crystal display output. 2. Input pins and I/O pins. Excludes OSC: pin. 3.1/0 pins. 4. Output pins. 8. Current flowing through pull-up MOS’s and output drive MOS's is excluded. 6. Input/output current is excluded. When input is at an intermediate level with CMOS, excessive current flows through the input circuit to the power supply. To avoid this, input level must be fixed at high or low. 7. External clock operation as shown in figure 44. 8. Internal oscillator operation using oscillation resistor Rf (figure 45) 9. Internal oscillator operation using a ceramic filter (figure 46). 10. Rom applies to the resistance between power supply pin (Vcc, V1, Vs, Vs) and each common signal pin (COM; to COMie). Rsec applies to the resistance between power supply pin (Vcc, V2, V3, Vs) and each segment signal pin (SEG: to SEGao). HITACHI Hitachi America, Ltd. + Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 207

HD66780 (LCD— IIA) ——_—Seeee SSS 11, Relation between operation frequency and current consumption is shown in figure 47. (Vcc = 5 V) 12. Applied to OSC; pin. 13. When each COM and SEG output voltage is within +0.15 V of LCD voltage (Vcc, V1, V2, Va, Va, Ve) when there is no load. Sees ‘@ Input Pin Pins: RS, R/W (MOS with pull-up) Pins: E Vv. (MOS without Vee — Vee pull-up) Pmos 34 Pos PMOS Pull-up MOS NMOS NMOS @ Output Pin Pins: CLy, Cle, M, D Vee PMOS NMOS @1/0 Pin Pins: DBo to DB, (MOS with pull-up) Yee Vee P Pp N vi P| Enable Data (Output Circuit) (Three-state) Figure 43 Pin Configuration HITACHI 208 Hitachi America, Ltd. » Hitachi Plaza + 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD66780 (LCD— IIA) ose; Open OSC, Th T

0.7 Vee

0.8 Vee Duty Factor = 7 x 100%

0.3 Vee:

Osc, Rf Rf: 82kQ + 2% Osc, Since oscillation frequency varies depending on OSC; and OSCz2 terminal capacitance, wiring 4 length to these pin should be minimized. Figure 45 Internal Oscillator, Resistor Cc, osc, Ceramic fitter: CSB250A (Murata) RE 1MO +10% Cy : 680 pF 10% ose, Cz: 680 pF + 10% G fe 2 Rd: 3.3ko +5% Ceramic fitter Note: This circuit is a standard one and we do not insure the oscillation frequency character- istics. Study the actual circuit ratings in using this circuit. Figure 46 Internal Oscillator, Ceramic Filter HITACHI Hitachi America, Ltd. Hitachi Piaza » 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 * (415) 589-8300 209

HD66780 (LCD — IIA) Etch ca 1.8, . 7 ® = Vic - V: ra_t_[ T T ] vee ove = Vs 50.26 x 1.2 a are Operatior By oe a a toa not for the co output level 6 4 a ure 48). The LCD drive voltage oat__| 7 | condition for the LCD output level oe cpested in ".cb vonage Vice" oo I. | T | 700 200 300 400 500 Figure 48 Vi, Vs Voltages fose or fop (kHz) Figure 47 Frequency vs Current HITACHI 210 Hitachi America, Ltd.» Hitachi Plaza» 2000 Sierra Point Pkwy. « Brisbane, CA 94006-1819 « (415) 589-8900

HD66780 (LCD— ITA) Bus Timing Characteristics (Voc = 6.0 V+10%, GND = 0 V, Ta = —20 to +75 ‘C) Write Operation (Writing Data from MPU to HD66780) ttm Symbol Min Max__—Unit__—‘Test Condition Enable Cycle Time tevce 500 = ns Fig. 52 Enable Pulse Width (High level) PWen 220 = ns Fig. 52 Enable Rise/Fall Time ter, ter = 20 ns Fig. 52 Address Set-up Time (RS, RW-E) tas 40 = 18 Fig. 52 ‘Address Hold Time tan 10 = ns Fig. 52 Data Set-up Time tosw 60 = ne Fig. 52 Data Hold Time th 10 = ne Fig. 62 Read Operation (Reading Data from HD66780 to MPU) tem Symbol Min Max_—Unit__—_—‘Test Condition Enable Cycle Time tevee 500 = 8 Fig. 53 Enable Pulse Width (High vel PWen 250 = 8 Fig. 53 Enable Rise/Fall Time ter, ter = 20 ns Fig. 53 Address Set-up Time (RS, RW-E) tas 40 = ns Fig. 53 ‘Address Hold Time tan 10 = ns Fig. 53 Data Delay Time Toor = 250 ns Fig. 53 Data Hold Time tour 20 = ns Fig. 63 4 5.0V RL=2.4ko Test Point 10k@ Diode S00F 1S2074@ Figure 49 Load Circuit (DBo—DB7) HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 211

HD66780 (LCD— II A) Timing Characteristics Write Operation ca | RS Vas Vis nw Mus PWex Fatt - Views - Vet tevce | Figure 62 Bus Write Operation Sequence (Writing Data from MPU to HD66780) | Read Operation ~ E32 4 Vi Var, aw Ves Von tan ed ij Var ‘or Var . = Vou Von Figure 63 Bus Read Operation Sequence (Reading Data from HD66780 to MPU) HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 * (415) 589-8300 213

HD66780 (LCD— II A) Interface Signal with Driver LSI HD44100H or HD66100F ta 0.8 Vee \\0.9 Vee cu 0.1 Voc tom |, town cts 0.9 Vee | 0.9 Vee

0.1 Vee i

fosVer o.8vecy 0.1 Voc _0.1 Vee M

0.1 Vee

Figure 54 Sending Data to Driver LSI HD44100H or HD66100F HITACHI 214 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300

Selected Specification

Hitachi Semiconductor HD66780 overview.

Summary

Dot Matrix Liquid Crystal Display Controller and Driver

Description

Dot Matrix Liquid Crystal Display Controller and Driver

Source title HD66780 Datasheet(PDF) - Hitachi Semiconductor

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