HD66523 HITACHI

Document overview

  • Manufacturer or author: pROVIDED bY www.digicamel.com(free datasheet download site)
  • PDF pages: 19

Technical content

Features

  • LCD timing generator: 1/200, 1/240 duty cycle timing are generated internally.
  • Number of LCD drivers: 240
  • Power supply voltage: 2.4V to 3.6V
  • High voltage LCD drive circuit: ±20V
  • LCD driving technique: Multi-line addressing for low power consumption.
  • Programmable vertical retrace period: zero to 192 lines
  • Low power consumption
  • Internal display off function
  • On-chip oscillator combined with external resistor and capacitor.
  • Package: TCP

fication Symbol Pin Name I/O Number of pins Functions Power supply VCC VCC Power supply 2V CC –GND: logic power supply GND GND Power supply VLCD1, VLCD2 VLCD Power supply

2 Power supply for LCD driving circuit

VEE1 , VEE2 VEE Power supply VRH1, VRH2 VRH — 2 LCD drive level power supply VM1, VM2 VM — 2 VRL1, VRL2 VRL — 2 Control signals M//G36 Master/ Slave I 1 Select master or slave mode. DUTY Duty I 1 Selects the display duty cycle. Low level: 1/200 display duty ratio High level: 1/240 display duty ratio BP4 to BP0 Blanking period I 5 Set vertical retrace period /G27/G32/G26 Display off control I/O 1 Control the display-off function. /G27/G2C/G36/G33/G32/G29/G29 Display off I 1 Turn off the LCD. During display off, all LCD driver output VM level SHL Shift left I 1 Pin SHL switches the shift direction of the scanning direction. /G35/G28/G36/G28/G37 Reset I 1 Reset the LSI internally. CR, C, R Oscillator — 3 Oscillator with external resistor and capacitor TEST1, TEST0 Test I 2 Test pins, must be connected to GND. LCD timing CL1 Clock 1 I/O 1 The bidirectional shift register shifts data at the falling edge of CL1. During master mode, this pin outputs a data transfer clock with a two times larger cycle than the internal oscillator (or the cycle of the external clock) with a duty of 50%. During slave mode, this pin inputs the external data transfer clock. FLM First line marker I/O 1 During master mode, pin FLM outputs the first line marker signal. During slave mode, this pin inputs the external data first line marker signal. FX1, FX0 Scanning function I/O 2 Output scanning function signals during master mode. Input scanning function signals during slave mode. BLANK Blank O 1 This pin shows vertical retrace period. LCD drive output X1 to X240 X1 to X240 O 240 Select one from among three levels, VRH, VM and VRL.

Table 1 M/ /G36/G36 Signal Status M//G36/G36 Mode LCD Timing Generator Status of CL1, FLM and /G27/G32/G26/G27/G32/G26 H Master 1/200 or 1/240 duty cycle Output L Slave Stops Input Table 2 Retrace period BP4 BP3 BP2 BP1 BP0 Horizontal Retrace Period Number of lines 00000 0 00001 6 00010 1 2 00011 1 8 00100 2 4 00101 3 0 00110 3 6 00111 4 2 01000 4 8 01001 5 4 01010 6 0 01011 6 6 01100 7 2 01101 7 8 01110 8 4 01111 9 0 10000 9 6 10001 1 0 2 10010 1 0 8 10011 1 1 4 10100 1 2 0 10101 1 2 6 10110 1 3 2 10111 1 3 8 11000 1 4 5 11001 1 5 0 11010 1 5 6 11011 1 6 2 11100 1 6 8 11101 1 7 4 11110 1 8 0 11111 1 8 6

H H X240 → X1 L X200 → X1 L H X1 → X240 L X1 → X200

CL1 FLM DOCCRCR M/SDISPOFF BP4~0 DUTY X1 to X240 Level shifter VM2 VRL2 VRH1 VM1 VRL1 240 240 FX0 FX1 SHLRESET I/O control VRH2 LCD driver Decoder Level shifter 240 Selector VRH–VRL VCC –GND LCD timing generator Scanning function generator TEST1 TEST0BLANK 1. CR Oscillator: The CR oscillator generates the HD66523 operation clock. During master mode, since the operation clock is needed, connect oscillation resistor Rf with oscillation capacitor Cf. When the external clock is used. Input external clock to pin CR and open pins C and R (Figure 1). When using the HD66523 during slave mode, the operation clock will not be needed; therefore, connect pin CR to VCC and open pins C and R (Figure 2). 2. Liquid Crystal Timing Generator: The liquid crystal timing generator creates various signals for the LCD. During master mode (M//G36 = VCC ), the generator operates the HD66523’s internal circuitry as a common internal driver using the generated LCD signals. In addition, signals CL1, FLM and /G27/G32/G26 created by this generator can synchronously display data on a liquid crystal display by inputting them into the RAM-provided segment driver HD66522 used together with HD66523. During slave mode (M//G36 = GND), this generator stops; the slave HD66523 operates based on signals CL1, /G27/G32/G26 and FLM generated by the master HD66523.

Table 4 HD66523 Connection List Connection Example M/S DUTY BP4 to BP0 RESET DISPOFF R C CL1 FLM DOC FX1 and FX0 SHL X1 to X240 A H H H H H H HH Sets the number of lines for retrace period From MPU or external reset circuit From MPU or external reset circuit From MPU or external reset circuit From MPU or external reset circuit From MPU or external reset circuit From controller From controller From controller From controller B C D E H L H H Sets the number of lines for retrace period Sets the number of lines for retrace period Sets the number of lines for retrace period Sets the number of lines for retrace period R f R f R f R f H L COM1 to COM240 COM240 to COM1 H L COM1 to COM240 COM240 to COM1 H L COM241 to COM480 COM480 to COM241 H L COM1 to COM240 COM240 to COM1 H L COM1 to COM240 COM240 to COM1 C f C f C f C f To CL1 of HD66522 To FLM of HD66522 To CL1 of HD66522 To FLM of HD66522 From CL1 of HD66523 From FLM of HD66523 To CL1 of HD66522, HD66523 To FLM of HD66522, HD66523 To CL1 of HD66522, HD66523 To FLM of HD66522, HD66523 To DISPOFF of HD66522 To DOC of HD66523 To FX1 and FX0 of HD66522 To FX1 and FX0 of HD66522 To FX1 and FX0 of HD66523 To FX1 and FX0 of HD66522, HD66523 From DOC of HD66523 To DISPOFF of HD66522 To DISPOFF of HD66522 To DOC of HD66523 Notes: H = VCC (Fixed) L = GND (Fixed) R f: Oscillation resistor C f: Oscillarion capacitor To FX1 and FX0 of HD66522, HD66523 To DISPOFF of HD66522 ——External Clock ——External Clock CR

FX1,FX0 123456789 1 0 1 1 1 2 1 3 1 4 VRL VM X10 X11 X12 VRH Figure 12 LCD Drive Output Timing at 3n + 3’s frame (n = 1, 2, 3, )

The example of power circuit is shown in Figure 13. When you want to change contrast, both levels, VRH and VRL must be changed. VCC GND VLCD (variable) VEE (variable) VDD (fixed) VCC VCH (SEG) VCL (SEG) VEE VRL (COM) GND VM (COM, SEG) DC/DC Converter VLCD VRH (COM) Note: VM level must keep following equations; (VRH–VM) = (VM–VRL) (VCH–VM) = (VM–VCL) VCL > GND VCH < VDD Figure 13 Example of Power Supply Circuit

Item Symbol Rating Unit Note Power voltage Logic circuit V CC –0.3 to + 7.0 V 1 LCD drive circuit VRH –0.3 to +25.0 V VRL –20.0 to +0.3 V Input voltage (1) VT1 –0.3 to V CC +0.3 V 1, 2 Input voltage (2) VT2 V EE – 0.3 to VLCD + 0.3 V 1, 3 Operating temperature T opr –20 to + 75 °C Storage temperature T stg –40 to + 125 °C Notes: 1. The reference point is GND (0V) 2. Applies to pins M//G36 , DUTY, BP4 to BP0, /G27/G32/G26 , /G27/G2C/G36/G33/G32/G29/G29 , SHL, /G35/G28/G36/G28/G37 , CR, CL1, FLM, FX0 to FX1, and TEST1 to TEST0. 3. Applies to pins VM1 and VM2. Supply the same voltage to pairs VRH1 and VRH2, VM1 and VM2, VRL1 and VRL2. 4. If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It should always be used within the limits of its electrical characteristics in order to prevent malfunction or unreliability.

Electrical Characteristics

DC Characteristics (VCC = 2.4 to 3.6V, GND = 0V, VLCD = 18 to 23V, VEE = –12 to –17V, Ta = –20 to +75°C) Item Symbol Applicable Pins min. typ. max. Unit Measurement Condition Note s Input high level voltage VIH1 0.8 × VCC —V CC V1 Input low level voltage VIL1 0 — 0.2 × VCC V1 Output high level voltage VOH 0.9 × VCC —— V I OH = –50 µA 2 Output low level voltage VOL — — 0.1 × VCC VI OL = 50 µA 2 Input leakage current (1) IIL1 –2.5 — 2.5 µA VIN = V CC to GND 1 Input leakage current (2) IIL2 VRH1, VRH2, VM1, VM2 VRL1, VRL2 –25 — 25 µA VIN = VLCD to V EE 1 Vi-Vj ON resistance R ON X1 to X240 — 1.0 2.0 k Ω ION = 100µA 3 Current consumption (1) IMS — — T.B.D. µA Master mode 1/240 duty cycle, C f = 100pF R f = 180kΩ VCC = 3.0V Current consumption (2) ISL — — T.B.D. µA Slave mode 1/240 duty cycle, f CL = 16.8 kHz, VCC = 3.0V Current consumption (3) ILCD — — T.B.D. µA Master mode 1/240 duty cycle, C f = 100pF R f = 180kΩ VCC = 3.0V VLCD = 23V V EE = –17V Notes: 1. Applied to input pins M//G36 , DUTY, BP4 to BP0, /G27/G2C/G36/G33/G32/G29/G29 , SHL, /G35/G28/G36/G28/G37 , TEST1, TEST0 and CR, and I/O pins, /G27/G32/G26 , CL1 and FLM during input state. 2. Applied to output pins, FX1 and FX0, and I/O pins, /G27/G32/G26 , CL1 and FLM, during output stagte.

3 Indicates the resistance between on pin from X1 to X240 and another pin from the V pins,

VRH1/VRH2, VM1/VM2 and VRL1/VRL2, when load current is applied to the X pin; defined under the following conditions: VRH = +23V, VRL = –17V VM = 1/2 * (VRH–VRL) 4. Input and Output currents are excluded. When a CMOS input is floating, excess current flows from the power supply to the input circuit. To avoid this, ViH and ViL must be held to V CC and GND levels, respectively.

Item Symbol min. typ. max. Unit. Measurement Condition Notes Operating frequency (1) fopr1 10 — 200 kHz Master mode (External clock operation) Operating frequency (2) fopr2 5 — 100 kHz Slave mode frequency of CL1 Oscillation frequency fOSC 30 36 42 kHz C f = 100pF R f = 180kΩ External clock duty Duty 45 50 55 % Master mode 3 External clock rising time tr — — 100 ns Master mode 3 External clock falling time tf — — 100 ns Master mode 3 Notes: 1. External clock is supplied to CR pin during master mode, and C and R pins must be left open. 2. Applies to the clock which is supplied to CL1 during slave mode. CR must be connected to GND, and C and R pins must be left open. 3. Applies to the external clock which is supplied to CR during a master mode. 0.8*VCC 0.5*VCC 0.2*VCC tr tH tL tH + tL tH tf Duty = × 100% Figure 14 External Clock