HD66205F

HD66205 HITACHI

Document overview

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• PDF pages: 16

Technical content

. ss . . | (Dot Matrix Liquid Crystal Graphic Display | Common Driver with 80-Channel! Outputs) ,

Description

‘The HD6620SF/HD6620SFL/HD6620STF/HD HD6620ST, tape carrier package (TCP) devices 66205TFL/HD6620ST/HD6620STL, the row LCD powered by 2.7-5.5 V, respectively. driver, features low output impedance and as many as 80 LCD outputs powered by 80 intemal LCD Features drive circuits, and can drive a large liquid crystal graphic display. Because this device is fabricated * Duty cycle: 1/64 to 1/240 by the CMOS process, it is suitable for battery- * High voltage driven portable equipment, which fully utilizes the — LCD drive: 10-28 V low power dissipation of liquid crystal elements. + Display off function | The HD66205 has a complete line-up: the » Internal 80-bit shift register | HD66205F, a standard device powered by 5Vt + Various LCD controller interfaces 10%; the HD66205FL, a 2.7-5.5 V, low power — LCTC series: HD63645, HD64645, |! dissipation device; the HD6620STF and HD64646 ' HD66205TFL, thin film package devices each — LVIC series: HD66840, HD66841 powered by 5 V + 10% and 2.7-5.5 V; and the — CLINE: HD66850

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—_"JMo> SD 66205 Ordering Information 1 (Flat package and die shipment) Type No. Voltage Range Package HD66205F SV + 10% 100-pin plastic QFP (FP-100) HD66205FL 27-55V 100-pin plastic QFP (FP-100) HD66205TF SV+10% 100-pin thin plastic QFP (TFP-100) HD66205TFL 27-55V 100-pin thin plastic QFP (TFP-100) HoD66205 SV + 10% Chip HCD66205L 2.7-5.5V Chi OE Chip Ordering Information 2 (tape carrier package) Type No. Voltage Range Outer Lead Pitch 1 Outer Lead Pitch2 Davice Length HD66205TA1 2.7-5.5V 0.15mm 0.80mm 4 sprocket holes HD66205TA2___2.7-5.5V 018mm 0.80mm 4 sprocket holes HD6620STA3___2.7-5.5V 0.20mm 080mm 4 sprocket holes HD66205TA6 2.7-5.5V 0.22mm 0.70mm 4 sprocket holes HD6620STA7 _2.7-5.5V 0.25mm 0.70mm 4 sprocket holes HD66205TAQL —_2.7-5.5V 0.22mm 0.70mm 3 sprocket holes Notes: 1. Outer lead pitch 1 is for LCD drive output pins, and outer lead pitch 2 for the other pins, 2. Device length includes test pad areas 3. Spacing between two sprocket holes is 4.75mm. 4. Tape film is Upirex (a trademark of Ube industries, Ltd. ). a 5. 35-mm-wide tape is used. 6. Leads are plated with Sn, 7. The details of TCP pattern are shown in * The Information of TCP. * HITACHI 707 M™@ 4496204 0045503 835 mm

a | HD66205 ee Pin Arrangement 2e2e2ne s22en as BELISSELLELSSSSLSAVs onoonON nnn Ono NOT SSSFSSSISSESSSSRLSITS xsi] 1 80[—) x30 xs2C] 2 79{- x29 xs3(] 3 78\\-) X28 x54] 4 77 x27 x65] 5 76[-) x26 xs6 (| 6 75 (J x25 xs7]7 74{J x24 x58] 8 73[2) X23 xs9] 9 72{J x22 x60 (| 10 71 [2 xt xe) 11 70{-] x20 | xe2 J 12 of) x19 x63] 13 68 x18 | xe4] 14 HD66205F 679 x17 xe5 2] 15 HD66205FL 66[- x16 | x66 J 16 (FP-100) 65[2) x15 | x67] 17 64 (I) X14 x69] 19 62,2) x12 | x70 CJ 20 61f) x11 | x7i C21 60{_] x10 | x72] 22 59[7 xo ' x73] 23 58{_] x8 ; x74] 24 87{_] x7 | x75 C25 56 |] x6 | x76 CJ 26 55{7] x5 | x77 27 54{7) x4 x78] 28 53(-] x3 x79] 29 s2{_] x2 | x80 [7] 30 si x1 BASSHSSSSSTIFT SSS SSS DUUDUUUDUUOUUOOUOUo } owees a So 205

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(Top View)

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YESQOE OLS OUT eneronsouco QRSIIS LES SVeLssosesssasas SBBSS8S8S5SSSESBSLISSLLRO x54 (2 740) X26 x56 C_]4 72[_] X24 x57 C5 710) X23 x58 C_J6 70[ 7] x22 x59 (17 69 {— 7] x21 x60 (_]8 681) X20 x61 C_j9 67([7] x19 x62 [_]10 66") x18 X63 (411 65[—) x17 x64 (12 HD66205TF 64[° 7) x16 x65 (_]13 63 (7) x15 x66 C114 HD66205TFL 62F-] x14 X67 15 FP-106 61 [7] X13 x68 (416 (TFP-100) 60[—] x12 x69 (417 5977) X11 X70 (_j18 5877 X10 x71 (19 57[-) x9 X72 (20 56] x8 x73 (j21 55[ 1X7 X74 (_j22 547) x6 X76 (24 52[7] x4 X77 (25 1) X3. 2 = Roos di cad (Top View) HITACHI 709 MB 4496204 OO4LSOS £01 mm LL

; | a HD66205 Pin Description Symbol Pin No. Pin Name Input/Output Classification | Symbol FPN00/TEP-t0) Veo 40/38 Veo = Power supply | GND 42/40 GND — Power supply } Vee 34732 Vee — Power supply | “I 37/35 vi Input Power supply | vs 35733 vs Input Power supply V6 36734 V6 Input Power supply cL 46/44 Clock Input Control signal M 44/42 M Input Control signal DI 48/46 Data in Input Control signal po 32/31 Data out Output Control signal SHL 41739 Shift left Input Control signal DISPOFF 39/37 Display off Input Control signal ! X—Xeo 51-100, 1-30/ X1-X80 Output LCD drive output 1-28, 49-100 NC 31, 33, 38, 43, No connection = = 45, 47, 49, 50/ 29, 30, 36, 41, 48, 45,4748 no HITACHI MB 4496204 004bSOb S45 ee

—_—— HD66205 —WSSS—S 205 Pin Functions DO: Outputs display data. DO of the last HD66205 must be open, and those of the other Power Supply HD66205s must be connected to DI of the next ; HD66205. Vocy Veg» GND: Vec-GND supplies power to the internal logic circuits. Voc—Veg supplies Powerto — SHL: Selects the data shiftt direction for the shift the LCD drive circuits, register. See figure 2. V1, V5, V6: Supply different levels of power to DISPOFF: A low DISP sets LCD drive outputs drive the LCD, V1 and Vyp are selected levels, X,-Xgo to V1 level. and V5 and V6 are non-selected levels. See figure 1. LCD Drive Output Control Signal X,~Xo: Each X outputs one of the four voltage levels V1, V5, V6, or Veg, depending on a CL: Inputs data shift clock pulses for the shift combination of the M signal and display data register. At the falling edge of each CL pulse, the levels, See figure 3. shift register shifts display data input via the DI pin. Other M: Changes LCD drive outputs to AC. NC: Must be open. DI: Inputs display data. DI of the first HD66205 must be connected to an LCD controller, and those of the other HD66205s must be connected to DI of the previous HD66205. a poate nen eeeeeeeee VI nreeeece= VEE Figure 1 Different Power Supply Voltage Levels for LCD Drive Circuits HITACHI m Mm 449b2e04 OO4bSO? 4é4 me Cenc nn

Figure 3. Selection of LCD Drive Output Level |

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= ___-- SSS 06205 Block Functions Shift Register LCD Drive Circuit ‘The 80-bit shift register shifts data input via the DI pin by one bit, and the one bit of shifted-out data is The 80-bit LCD drive circuit generates four output from the DO pin. Both actions occur vollage levels V1, V5, V6, and Veg, for driving an simultaneously at the falling edge of each shift LCD panel. One of the four levels is output to the clock (CL) pulse corresponding Y pin, depending on a combination of the M signal and the data in the shift register Level Shifter The level shifter changes 5-V signals into high- voltage signals for the LCD drive circuit, ————- Ss Block Diagram X1-X80 viv V6, VEE L LCD drive circuit DISPOFF a Logic Bb Shift register SHL DO HITACHI 713 MB 4496204 0046509 257 mm Ee

a | HD66205 | Comparison of the HD66205 with the HD61105 item HD66205 HD61105 Display off function Provided Not provided ) LCD drive voltage range 10-28 V 10-26 V Shitt clock phase selection function Not provided Provided (FCS pin) Relation between SHL and See figure 4 See figure 4 LCD output destinations Relation between LCD output See figure 5 See figure 5 levels, M, and data LCD drive V pins V1, V5, V6 V1, V2, V5, V6 (V2 level is the same as Vee level) ! Common signal SHL level Data shitt direction scan direction | | on | Di & SR80> SR79 > SRI X80 > x1 HD66205 Common signal | SHL level Data shift direction scan direction HD61105 Note the exact reverse relation for the two devices. Figure 4 Relation between SHL and LCD Output Destinations for the HD66205 and HD61105 M712 MtI—7 Lo a Lo - oF T ot7G 7 Xoutput level bY LoS VEEL VE Xoutput level YZ 4/Eape tp .¥Ea) HD66205 HD61105 Figure 5 Relation between LCD Output Levels, M, and Data for the HD6620S and HD61105

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a HD66205 , Application Example | Ee] <4 mm e pe 8 8E aa sain oH sed oe 589 ||| | hee a | 3 mm ve | itt fi sea | nea ll | ‘e Eul - ry | ee itd eetes | a | [ (eS | Hp | Ht === So AAA | Eee eT LA , if | LF Notes: 1. The resistances of Rt and R2 depend on the type of the LCD panel used. For example, | for an LCD panel with a 1/15 bias, Ai and R2 must be 3 kQ and 33 kQ, respectively. That is, R1(4*R1+ R2) should be 1/15. 2. To stabilize the power supply, place two 0.1-F capacitors near each LCD driver: one between the Voc and GND pins, and the other between the Voc and Vee pins.

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—_,_ He CU“SeSsWaM 062055, Absolute Maximum Ratings ttem Symbol ___ Rating Unit Notes Power supply voltage for logic circuits Veo 0.3 to +7.0 Vv 1 Power supply voltage for LCD drive circuits Veg Voc - 30.0 to Veg + 0.3 V Input voltage 1 Vr 0.3 to Voc + 0.3 v 1,2 Input voltage 2 Vio Vee - 0.310 Voge +0.3 V 1,3 Operating temperatura Tope ~20 to +75 °c Storage temperature Tog 55 to +125 °C 4 Notes: 1. The reference point is GND (0 V). 2. Applies to pins CL, M, SHL, DI, DISPOFF. 3. Applies to pins V1, V5, and V6. 4, -40 to +125°C for TCP devices. 5. It the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It should always be used within its electrical characteristics in order to prevent matfunctioning or degradation of reliability,

Electrical Characteristics

DC Characteristics for the HD6620SF/HD6620STF (Vcc = 5 V + 10%, GND = 0 V, Voc - Veg = 10 to 28 V, and Ta = -20 to +75°C, unless otherwise noted.) a fem Symbol Pins Min. Typ. Max. Unit Condition Notes Input high voltage Vi 1 O7xVeg — Veo v Input low voltage Va 10 — _03xVee V Output high voltage Vou 2 Vgc-04 — — V_ lon =-0.4 mA Output low voltage Vor 20 - —__ 04 Vb = 0.4mA Vi-Yj on resistance Ron 3 — — 20 kQ__ lon = 100 pA 1 Input leakage current 1 ti 1-10 — 10 HA Vin = Voc to GND. Input leakage current 2 Ina 4-3 — 2 WA__Viv = Voc to Vee Current consumption! Igyp = — — 100 BA fo, = 20 kHz 2 Voc - Vee = 28 V Current consumption2 _ lee - - 150 500 HA__Sameasabove 2 Pins and notes on next page. HITACHI 717 mM 445bec4 46513 768

DC Characteristics for the HD66204FL/HD66204TFL/HD66204T (Vcc = 2.7 to 5.5 V, GND =0 V, ' Voc - Vee = 10 to 28 V, and Ta = -20 to +75°C, unless otherwise noted.) Item Symbol Pins Min. Max. Unit__Condition Notes Input high voltage Vin 1 0.7xVoc Voc v Input low voltage Vin 1 ° 0.3 x Voc _V Output high voltage Vou 2 Vec-0.4 — Vo loy=-0.4 mA Output low voltage Vou 2 = 04 Vy =0.4mA Vi-Yj on resistance Ron 3 - 2.0 kQ lon = 100 mA 1 Input leakage current 1 Ins 1 1.0 1.0 vA __Vin= Voc to GND ' Input leakage current 2 Ina 4 -25 25 BA Vin= Voco to Vee Current consumption 1 —Igno - - 100 vA foy = 16.8 kHz 2 | f= 35 Hz Veo = 3.0V | Voc - Veg = 28 V | ‘Current consumption 2 lee _- - 250 pA Same as above 2 | Pins: 1. CL, M, SHL, Dl, DISPOFF 2. DO 3. X1-Xgo, V1, V5, VE | 4. V1, V5, V6 Notes: 1. Indicates the resistance between one pin from X,-Xag and another pin from V1, V5, V6, and | Vee. when load current is applied to the X pin; defined under the following conditions. Voc ~ Vee= 28 V | V1, V6 # Veg - (1/10(Veo— Vee)} V5 = Vee +{1/10(Voc - Vee)} , V1 and V6 should be near Voc level, and V5 should be near Vec level (figure 7). All votage | must be within AV. AV is the range within which Roy, the LCD drive circuits’ output impedance, is stable. Note that AV depends on power supply voltage Voc—Vee (figure 8). 2. Input and output current is excluded. When a CMOS input is floating, excess current flows from the power supply through the input circuit. To avoid this, Vy and Vj, must be held to Voc and GND levels, respectively. | 3. Applies to standby mode. ,

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a HD66205 AC Characteristics for the HD6620SF/HD6620STF (Voc = 5 V + 10%, GND =0 V, and Ta = -20 to +75°C, unless otherwise noted.) tem Symbol Pins Min. Max. Unit Note Clock cycle time tove cL 10 = BS ‘Clock high-level width 1 town cL 50 = ns Clock low-level width tow. cL 1.0 — ys Clock rise time t cL = 30 ns Clock fall time tt cL = 30 ns Data setup time tos 01, CL 100 — ns ' Data hold time tou 01, CL 100 = ns Dataholdtime 0 Ro Data cutputholdtime tow DOLCE 100 AC Characteristics for the HD6620SFL/HD6620STFL/HD6620ST (Vcc = 2.7 to 5.5 V, GND =0 V, | and Ta = -20 to +75°C, unless otherwise noted.) tem ‘Symbol Pins Min. Max. Unit Note . Clock cycle time tere cL 10 = us Clock high-level width 1 town cL 80 = ns ' Clock low-level width tow. cL 1.0 = us | Clock rise time cL = 30 ns | Clock fall time tt cL — 30 ns | Data setup time tos DIcL 100 = ns | Data hold time tou DI, CL 100 - ns | Data output delay time top DO, CL - 7.0 us 1 Data output hold time touw DO, CL 100 - ns Data output hold time Row Notes: 1. The load circuit shown in figure 9 is connected. | test point — 1 zt 30 pF Figure 9 Load Circuit

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