HD66100D

HD66100F HITACHI

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 17

Technical content

Features

• LCD driver with serial/parallel converting function
• Interface compatible with the HD44100H; connectable with HD43160AH, HD61830, HD61830B, LCD-II (HD44780), LCD-III (HD44790)
• Internal output circuits for LCD drive: 80
• Internal serial/parallel converting circuits  80-bit bidirectional shift register  80-bit latch circuit
• Power supply  Internal logic circuit: +5V ±10%  LCD drive circuit: 3.0V to 6.0V
• CMOS process

Table 1 shows the main differences between HD66100F and HD44100H. Table 1 Difference between Products HD66100F and HD44100H HD66100F HD44100H LCD drive outputs 80 × 1 channel 20 × 2 channels Supply voltage for LCD drive circuits 3 to 6V 4.5 to 11V Multiplexing duty ratio Static to 1/16 duty Static to 1/32 duty Package 100-pin plastic QFP 60-pin plastic QFP

Ordering Information

Type No. Package HD66100F 100-pin plastic QFP (FP-100) HD66100FH 100-pin plastic QFP (FP-100B) HD66100D Chip

Chip size (X × Y) Coordinate Origin Pad size (X × Y) 4.50mm × 4.50mm Pad Center Chip Center 100µm × 100µm TYPE CODE Y 1 100 30 51 46444237 39 Unit : µ m Pad Coordinate Pad Coordinate Pad Coordinate No. Function X Y No. Function X Y No. Function X Y

1 Y30 –1725 2100 35 V4 –880 –2100 69 Y62 2100 560

2 Y29 –1925 2100 36 GND –720 –2100 70 Y61 2100 720

3 Y28 –2100 2060 37 CL1 –470 –2100 71 Y60 2100 880

4 Y27 –2100 1865 38 72 Y59 2100 1040

5 Y26 –2100 1690 39 SHL –270 –2100 73 Y58 2100 1200

6 Y25 –2100 1520 40 CL2 –70 –2100 74 Y57 2100 1360

7 Y24 –2100 1360 41 DI 130 –2100 75 Y56 2100 1520

8 Y23 –2100 1200 42 DO 350 –2100 76 Y55 2100 1690

9 Y22 –2100 1040 43 77 Y54 2100 1865

10 Y21 –2100 880 44 M 620 –2100 78 Y53 2100 2060

11 Y20 –2100 720 45 79 Y52 1925 2100

12 Y19 –2100 560 46 V CC 980 –2100 80 Y51 1725 2100

13 Y18 –2100 400 47 81 Y50 1520 2100

14 Y17 –2100 240 48 82 Y49 1360 2100

15 Y16 –2100 80 49 83 Y48 1200 2100

16 Y15 –2100 –80 50 84 Y47 1040 2100

17 Y14 –2100 –240 51 Y80 1725 –2100 85 Y46 880 2100

18 Y13 –2100 –400 52 Y79 1925 –2100 86 Y45 720 2100

19 Y12 –2100 –560 53 Y78 2100 –2060 87 Y44 560 2100

20 Y11 –2100 –720 54 Y77 2100 –1865 88 Y43 400 2100

21 Y10 –2100 –880 55 Y76 2100 –1690 89 Y42 240 2100

22 Y9 –2100 –1040 56 Y75 2100 –1520 90 Y41 80 2100

23 Y8 –2100 –1200 57 Y74 2100 –1360 91 Y40 –80 2100

24 Y7 –2100 –1360 58 Y73 2100 –1200 92 Y39 –240 2100

25 Y6 –2100 –1520 59 Y72 2100 –1040 93 Y38 –400 2100

26 Y5 –2100 –1690 60 Y71 2100 –880 94 Y37 –560 2100

27 Y4 –2100 –1865 61 Y70 2100 –720 95 Y36 –720 2100

28 Y3 –2100 –2060 62 Y69 2100 –560 96 Y35 –880 2100

29 Y2 –1925 –2100 63 Y68 2100 –400 97 Y34 –1040 2100

30 Y1 –1725 –2100 64 Y67 2100 –240 98 Y33 –1200 2100

31 V EE –1520 –2100 65 Y66 2100 –80 99 Y32 –1360 2100

32 V1 –1360 –2100 66 Y65 2100 80 100 Y31 –1520 2100

33 V2 –1200 –2100 67 Y64 2100 240

34 V3 –1040 –2100 68 Y63 2100 400

M NC V CC NC NC NC NC (Top view) 100 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V EE GND CL1 NC SHL CL2 DI DO NC M NC V CC NC NC NC NC Y80 Y79 (Top view) HD66100FH (FP-100B) HD66100F (FP-100)

V CC , GND, VEE : VCC supplies power to the internal logic circuit. GND is the logic and drive ground. VEE supplies power to the LCD drive circuit. V1, V2, V3, and V4: V1 to V4 supply power for driving an LCD (Figure 2). CL1: HD66100F latches data at the negative edge of CL1. CL2: HD66100F receives shift data at the negative edge of CL2. M: Changes LCD drive outputs to AC. DI: Inputs data to the shift register. DO: Output data from the shift register. SHL: Selects a shift direction of serial data. When the serial data is input in order of D1, D2, ..., D79, D80, the relation between the data and the output Y is shown in Table 3. Y1–Y80: Each Y outputs one of the four voltage levels—V1, V2, V3, or V4—according to the combination of M and display data (Figure 2). NC: Do not connect any wire to these terminals. Table 2 Pin Function Symbol Pin No. Pin Name I/O VCC 46 V CC — GND 36 Ground — VEE 31 V EE — V1 32 V1 — V2 33 V2 — V3 34 V3 — V4 35 V4 — CL1 37 Clock 1 I CL2 40 Clock 2 I M4 4 M I DI 41 Data in I DO 42 Data out O SHL 39 Shift left I Y1–Y80 1–30, 51–100 Y1–Y80 O NC 38, 43, 45, 47–50 No connection —

Select one of four levels of voltage V1, V2, V3, and V4 for driving a LCD and transfer it to the output terminals according to the combination of M and the data in the latch circuit. Latch Circuit Latches the data input from the bidirectional shift register at the fall of CL1 and transfer its outputs to the LCD drive circuits. Bidirectional Shift Register Shifts the serial data at the fall of CL2 and transfers the output of each bit of the register to the latch circuit. When SHL = GND, the data input from DI shifts from bit 1 to bit 80 in order of entry. On the other hand, when SHL = VCC , the data shifts from bit 80 to bit-1. In both cases, the data of the last bit of the register is latched to be output from DO at the rise of CL2. LCD drive outputs Latch circuit Shift register 12 79 80 12 79 80 CL1 CL2 DI DO SHL = GND Y1 Y2 Y79 Y80 LCD drive outputs Latch circuit Shift register 12 79 80 12 79 80 CL1 CL2 DO DI SHL = VCC Y1 Y2 Y79 Y80 Figure 3 Relation between SHL and the Shift Direction

M (alternating signal) Y1 Y2 Y79 Y80 Latch circuit Bidirectional shift register 12 79 80 12 79 80 CL1 (latch clock) DI (input data) V1, V2, V3, V4 (power supply for LCD drive circuit) V CC GND V EE DO (output data) SHL (selects a shift direction) CL2 (shift clock) Logic circuit Logic circuit Figure 4 Block Diagram

SHL = GND Shift clock Input data Latch clock Outputs CL2 DI CL1 to Y80 SHL = VCC to Y80 Outputs D1 D2 D79 D80 D80 D80 Figure 7 SHL and Waveforms of Data Shift

Item Symbol Ratings Unit Note Supply voltage Logic circuits V CC –0.3 to +7.0 V 1 LCD drive circuits VCC –VEE –0.3 to +7.0 V Input voltage (1) VT1 –0.3 to V CC + 0.3 V 1 Input voltage (2) VT2 V CC + 0.3 to VEE – 0.3 V 2 Operation temperature T opr –20 to +75 °C Storage temperature T stg –55 to +125 °C Notes: 1. A reference point is GND (= 0V) 2. Applies to V1–V4. Note: If used beyond the absolute maximum ratings, LSIs may be permanently destroyed. It is best to use them at the electrical characteristics for normal operations. If they are not used at these conditions, it may affect the reliability of the device.

Electrical Characteristics

DC Characteristics (VCC = 5V ± 10%, VCC – VEE = 3.0 to 6.0V, GND = 0V, Ta = –20 to +75°C) Item Symbol Terminals Min Typ Max Unit Test Condition Note Input high voltage VIH CL1, CL2, 0.8 × VCC —V CC V Input low voltage VIL M, DI, SHL 0 — 0.2 × VCC V Output high voltage VOH DO V CC – 0.4 — — V I OH = –0.4 mA Output low voltage VOL — — 0.4 V I OL = +0.4 mA On resistance Vi–Vj RON1 Y1–Y80 V1–V4 —— 1 1k Ω ION = 0.1 mA to one Y terminal R ON2 —— 3 0k Ω ION = 0.05 mA to each Y terminal Input leakage current I IL CL1, CL2, M, DI, SHL –5.0 — 5.0 µA Vin = 0V to V CC Vi leakage current IVL V1–V4 –5.0 — 5.0 µA Output Y1–Y80 open Vin = VCC to VEE Current dissipation IGND — — 2.0 mA f CL2 = 1.0 MHz 1 IEE — — 0.1 mA fCL1 = 2.5 kHz Note: 1. Input/output currents are excluded; when an input is at the intermediate level in CMOS, excessive current flows from the power supply through the input circuit. To avoid this, VIH and VIL must be fixed at VCC and GND level respectively.

AC Characteristics (VCC = 5V ± 10%, VCC – VEE = 3.0 to 6.0V, GND = 0V, Ta = –20 to +75°C) Item Symbol Terminals Min Typ Max Unit Note Data shift frequency fCL CL2 — — 1 MHz Clock high level width tCWH CL1, CL2 450 — — ns Clock low level width tCWL CL2 450 — — ns Data set–up time f SU DI 100 — — ns Clock set–up time (1) tSL CL2 200 — — ns 1 Clock set–up time (2) tLS CL1 200 — — ns 2 Output delay time t pd DO — — 250 ns 3 Data hold time t DH DI 100 — — ns Clock rise/fall time fCT CL1, CL2 — — 50 ns Notes: 1. Set-up time from the fall of CL2 to that of CL1. 2. Set-up time from the fall CL1 to that of CL2. 3. Test terminal C L (Load capacitance on outputs) = 30 pF (Including jig capacitance) CL2 DI DO CL1 tCWL VIH tct tDH VIH VIL tct VIH VIL tSU tpd tSL VOH VOL VIH VIL tLS tcttct tCWH tCWH Figure 8 Timing Chart of HD66100F

to Y2–Y80 Data 0 corresponding to Y1 (COM signal) CL1 Figure 15 Timing Chart (when Y1 is Used as a COM Signal)