HD637B01Y0

Hitachi Semiconductor

CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER UNIT

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HD63701Y0 HITACHI

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HD63701Y0, HD637A01Y0, HD637B01Y0 {intng up. For Depa Ot Description Abeszaot voc . Pa so HO637B01¥0C cS The HD63701Y0 is a CMOS 8-bit single-chip micro- G3 computer unit with 16k-byte EPROM, programmed af iy by the same method as the standard 27256 EPROM. r @ J i It is available in a ceramic package. The user- KG programmable on-chip EPROM reduces lead time 6 ii between software development and production. The Sail 1 ceramic package with window is used in the debug- F ay y ging development stage and small volume produc- (0c-64s) tion. The ceramic package is a hermetically sealed 64-pin shrink DIP with quartz window that allows for EPROM erasure in the same way as a 27256 '@ PIN ARRANGEMENT EPROM. HD63701Y0C @ FEATURES vss 1 O “A Ey ‘le wi xray? © Instruction set compatible with the HD6301Y0 eaale> abl wan @ 16k bytes EPROM MPoC]+ sT) RAW/P72 @ 256 bytes RAM mPiC]s sol] OR/P73 © 53 parallel V/O lines ‘Res/ver C]* sof] BA/P74 @ Parallel handshake interface (port 6) __STevC]7 $817] Do/P30/EOo © Darlington transistor direct drive lines (port 2) and port 6) NMI/EAs TJ ¢ 577} Di/P31/EOs © 16-bit programmable timer P20/Tin(]* seL} 02/P32/EO: i P2s/Toutt C10 +5) D3/P3x/EOs © Bit reloadable timer p2x/ScikC]" 34] D4/P3«/E0e © Serial communications intertace (SC!) P2s/Re 2 #7] Du/P3s/EOs © Three kinds of memory-ready function for low-speed mem- P2a/Te C3 82] Da/P36/EOs ory access P2s/Tour2]4 81) »/P37/E07 © Halt function P2e/Tout3 L's sof] Aa/P 10/EAo © Error detection function (address error, opcode error) P2o/tcux C's aaf] AV/PLVEAL © Interrupts P5o/iROr CL}? aol) A2/P 12/EAz —3 external Ps,/ina2 C]'* 07 As/P1s/EAs —7 internal PS/MRC]'? 466) Aa/P1a/EAa © NCU operation modes malig = cB ae ea —Mode 1: expanded mode (internal ROM inhibited) p5e/08 L422 0B Ay/P 11/8, —Mode 2: expanded mode (internal ROM valid) PSL]? ab vec —Mode 3: single-chip mode P57 Cf <1) Aa/P40/EAs © EPROM programming mode P6o]s 40] Ae/P41/OE © Address space up to 65k bytes P6sC]e 396 Ato/P42/EAt0 © Low power modes P6227 20] Ans/P43/EAy —Sleep mode P63 C28 3] Ana/P4e/EAr2 —Standby mode P6. C]2* 30 Ans/P4e/EAr3 ' 4 jon ti P6s C)>° 25) Aia/P4e/EAs © Minimum instruction time 0.5 ys (f= 2 MHz) pees" 1B Aw/Pay/cE Pe, C22 2 Vee lf PROGRAM DEVELOPMENT SUPPORT TOOLS © Cross assembler and C compiler software for IBM PC and compatibles © In circuit emulator for use with IBM PCs and compatibles © Programming socket adapter for programming the EPROM-on-chip device. HD63701Y0C [0.11010 - | 64-pin ceramic HD637ANIYOC | _0.1to15 _| shrink DIP Hoes7Botvoc | 0.11020 | (0C-648) @ HITACHI 718 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

HD63701Y0, HD637A01Y0, HD637B01Y0 Block Diagram CeIn Po y= — £ GEE. = 5 vee gi8 Vss — Oo $248 P2o(Tin) | z = | { \\ j P2\\(Toutt) ee x i cpu cont RD /P7o P2a(SCLK) ie eae 3 3\\asek > on WR /P7: P23(Rx) mic} = 1a = 5 ii awe Fetowa =| ® 8 | EAE TT ttt pee P2s(Tout2) iis ‘ P26(Tout3) Wine P2x(TCLK) ; TT] D0/P30/EOo aq Ds/P3:/EO. ly HME z Dw Pau 1 « D2/P33/EO3 TIMER 1 2 Da/P34/EO« Ds/P3s/EOs De/P3e/EOe | so k= Dy/P37/EOr scl IL se a0 AW/P1s/EA - Aa/P12/EA2 ia As/P13/EA3 g As/P15/EAs PS5o(iRO) — ° 3) Ae/P16/EAs P5,(iROz) — 3 8 Ay/P17/EAy P53(HALT) | 8 val Aa/P4o/EAs Ps«(8) 2he 1 As/P41/OE P5s(08) «|. A1o/P42/EAt0 PB [m T 7 gle An/P4s/EAn Ps HAND z|9 Au2/P4a/EAt2 e)® Ais/P4s/EAi3 P60 Au/P4s/EAr P6: [| Ais/P47/CE P62 © « PGs 2/8 fS) Pe Slo P6s |e RAM EPROM me, P6> @HITACHI . Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 719

HD63701Y0, HD637A01Y0, HD637B01Y0 Pin Description Pin No. Mode 1, Mode 2 Mode 3 EPROM Mode Pin Pin Pin Oc-64s Name Function =————sName Function _Name Function

1 Vss Ground Vss Ground Vss Ground

2 XTAL Crystal connection XTAL__Crystal connection oe

3 EXTAL Crystal or external EXTAL Crystal or external

______Slock connection __ clock connection

4 MPo Mode select inputs MPo Mode select inputs

5 MPL MP;

6 RES” Reset input RES” Reset input Vep EPROM Programming

7 STBY Standby mode input STBY Standby mode input _

8 NMI Nonmaskable NMI Nonmaskable EAg Address bus, bit 9

9 P2o/Tin Port 2, bit O/ P2o/Tin Port 2, bit 0/

Timer 1 input Timer 1 input

10 P21/Tou 1 Port 2, bit 1/ P2:/Tou 1 Port 2, bit 1/

Timer 1 output 1 Timer 1 output 1

11 P22/SCLK Port 2, bit 2/ P22/SCLK Port 2, bit 2/

12 P23/Rx Port 2, bit 3/ P23/Rx Port 2, bit 3/

7: SCI receive input SCI receive input

13 P24/Tx Port 2, bit 4/ P24/Tx Port 2, bit 4/

SCI transmit output SCI transmit output 14 P2s/Tout 2. Port 2, bit 5/ P25/Tout 2 Port 2, bit 5/ _ Timer 1 output 2 ___ Timer 1 output 2 15 P26/Tour 3 Port 2, bit 6/ P26/Tour 3. Port 2, bit 6/ Timer 2 output 3 Timer 2 output 3 ee

16 P27/TCLK Port 2, bit 7/ P27/TCLK Port 2, bit 7/

Timer 2 clock Timer 2 clock _ 7

17 P5o/IRQi Port 5, bit 0/ P5o/IRQi_ Port 5, bit O/

_ Interrupt input 1 interrupt input 1

18 P5,/IRQ2 Port 5, bit 1/ P5i/IRQ2 Port 5, bit 1/

Interrupt input 2 Interrupt input 2 7

19 P52/MR Port 5, bit 2/ P52 Port 5, bit 2

_ Memory ready input

20 P53/HALT Port, bit 3/ P53 Port 5, bit3

_ Halt input __ au P54/IS Port 5, bit 4/ P5a/IS Port 5, bit 4/ _ Input strobe Input strobe

22 P5s/OS Port 5, bit 5/ P5s/0S Port 5, bit 5/

Output strobe Output strobe

23 P56 Port 5, P56 Port 5,

24 P57 bits 6 and 7 P5) bits 6 and 7

HD63701Y0, HD637A01Y0, HD637B01Y0 Pin Description (Cont) Pin No. Mode 1, Mode 2 Mode 3 EPROM Mode Pin Pin Pin pc-64s Name Function Name Function Name _ Function

25 P6o __ Porté, bits 0-7 PG Port6, bits 0-7

26 Pé P6:

7 P62 Pé2

28 P6s Pos

29 P6a PG.

30 P65 P65

31 P66 Pb. 32 Pe? P67 33 Voc. +5V power supply Voc +5V power supply Vcc_——-+5V power supply 34 ‘Ais Address bus, Pa, Port, bits 7-0 CE Chip enable

35 Ais __ bits 15-8 Pde Faia _ Address bus,

36 A Pas EAi3 _ bits 14-10

37 Are Pay Cra

38 An Pay cr

Pa EAio 40. OAs PA OE Output enable

4 Ae Pao FA Address bus, bit 8

43 Ar Address bus, Pla Port 1, bits 7-0 EA? Address bus, “4 As bits 7-0 Ple EAs _ bits 7-0

6 As Pls EAs

46 Ae Pla EAs

48 Ae Pla EAz

49 AL Ph EAL

«Ao Plo EAo

51 Dy Data bus, P3)___ Port3, bits 7-0 EQ, Data bus,

52 De bits 7-0 P36 £0, _ bits 7-0

53 Ds P35 £05

54 Da P34 E04

55s P33 £0; 56 De P32 f.

57 D P3 £0; _

58 Do P30 EQ

59 BA Bus available output _P7« _Port 7, bits 4-0 a

60 OR Load instruction P73,

6 R/W Read/Write output P72

62 WR Write output P71

~-RD Read output P70

64 E "External E External ~

clock output clock output ee @HITACHI Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 721

HD63701Y0, HD637A01Y0, HD637B01Y0 Mode Program (MPo, MP1) Timer 2 Clock Input (TCLK) These pins determine the MCU operation mode TCLK is timer 2’s external clock input. (expanded modes 1 or 2, or single-chip mode 3). — SCI Clock (SCLK) Standby (STBY) SCLK is the serial communication interface (SCI) The STBY pin puts the MCU in standby mode. 1/0 pin. Halt (HALT) Receive, Transmit (Rx, Tx) The halt contro! input stops instruction execution Rx and Tx are the SCI receive input and transmit and release the buses. When HALT switches low, output. the CPU finishes the current instruction, then stops and enters the halt state. Port 1 (Plo-P1z) Memory Ready (MR) In mode 3 (single-chip mode), these pins are an 8-bit I/O port. The memory ready control input lengthens the system clock’s high period to allow access to low- Port 2 (P29-P27) speed memory. oe Port 2 is an 8-bit I/O port. Read and Write (RD, WR) Port 3 (P3o- P37) The read and write outputs show active low outputs to peripherals or memories when the CPU is In mode 3 (single-chip mode), these pins are an 8-bit reading or writing. 1/O port. Read/Write (R/W) Port 4 (P49-P47) The read/write signal is high when the CPU is In mode 3 (single-chip mode), these pins are an 8-bit reading, and low when it is writing to peripherals or 1/0 port. memory. _ Port 5 (P50- P57) Load Instruction Register (LIR) Port 5 is an 8-bit I/O port. The LIR output is low when the CPU executes an opcode fetch cycle. Port 6 (P60- P67) Bus Available (BA) Port 6 is an 8-bit I/O port. The bus available output control signal goes high Port 7 (P70-P74) when the CPU accepts HALT and releases the buses. It is normally low. In mode 3 (single-chip mode), port 7 is a 5-bit __ output port. Input Handshake, Output Handshake (IS, 0S) Address Bus (Ao-A15) TS and OS are the handshake interface input and output. In modes 1 and 2 (expanded modes), these pins are the 16-bit address bus. Timer 1 Input (Tin) Data Bus (Do-D7) Tin is the external input-capture pin for timer 1. In modes | and 2 (expanded modes), these pins are Timer 1 Outputs 1 and 2 (Tout1, Tout2) the 8-bit data bus. Tout1 and Tout2 are the outputs of timer 1’s output Chip Enable (CE) compare registers. The chip enable input enables EPROM program- Timer 2 Output (Tout3) ming and verifying. When this signal is low, the EPROM is enabled. Tout3 is the output for timer 2. @ HITACHI : Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 723

HD63701Y0, HD637A01Y0, HD637B01Y0 Program Voltage (Vpp) EPROM Address Bus (EAo-EAu) Ve is the input for the program voltage (12.5V + In the PROM programming mode, EA,-EA,, are 0.3V) for programming the EPROM. the PROM address bus. Output Enable (OE) EPROM Data Bus (EAo-EA7 OE is the control for data verification output. In the PROM programming mode, EO)-EO, are the PROM data bus. @ HITACHI 724 Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300

executes it. This sequence starts when reset is ating states and port states. Table 1. CPU Operation and Port States

RD, WR, R/W=High Z UR, BA=High
HALT is unacceptable in mode 3.

4, E pin goes to high impedance state. 6 Keep: The output port is retained, and the input port goes to the high impedance state.

7 A oO} 7 B OF 8-Bit Accumulators A and B

Figure 2. CPU Registers Figure 3. CPU Operation Mode Transitions

a HD63701Y0, HD637A01Y0, HD637B01Y0 gs 288 5 a OE at oO Tih e222. Bs ese 5 i >——f] i me Pe ® PH |: O{OOO+0G of Re @HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 727

HD63701Y0, HD637A01Y0, HD637B01Y0 Reset Mode : To reset the MCU, hold RES low for least 20 ms during power-up. When RES is brought at least 3 clock cycles during operation, or for at high, the MCU begins the reset procedure Table 2, Registers at Reset Address Register Abbreviation R/W2 Value at Reset? 00 ~ Port 1 ODR (Data Direction Register) P1DDR w $FE

01 Port 2 DDR P2DDR w $00 a

02 Port 1 a PORTI R/W__ Indefinite

03 Port 2 ~ PORT2 R/W__ Indefinite

04 ~ Port 3 ODR P3DDR Ww SFE 05 Port 4 DDR P4DDR w $00.

06 Port 3 PORTS R/W_ Indefinite

07 Port 4 ~__PORT4 R/W Indefinite

08 Timer Control/Status Register 1 TCSR1 R/W $00

09 Free Running Counter (MSB) FRCH RW $00. OA Free Running Counter (LSB) FRCL —_R/W___$00 0B Output Compare Register 1 (MSB) ~~ OCRIH R/W $FF oc Output Compare Register 1 (LSB) OCRIL RW $F 0D Input Capture Register (MSB) ICRH R $00 _ OE Input Capture Register (LSB) 1CRL R $00 OF Timer Controi/Status Register 2 TCSR2 R/W $10 10 ___Rate/Mode Control Register. —~—==s«RMCR R/W $C

11 Tx/Rx Control Status Register 1 TRCSR1 R/W $20

12 Receive Data Register RDR R $00

13____ Transmit Data Register TOR W Indefinite

14 RAM/Port 5 Control Register RPSCR RW $FBor$78

15 Pot 5 PORTS R/W__ Indefinite

16 Port 6DDR P6DDR W $00

18 Port 7 PORT7 R/W___ Indefinite _

19 ‘Output Compare Register 2 (MSB) OCR2H R/W FO 1A ‘Output Compare Register 2 (LSB) OCR2L.t~*~<“‘«i‘éR $FF ~18 Timer Controi/Status Register 3 TCSR3 RW $20 1C Time Constand Register TCONR WwW SF 1D Timer 2 Up Counter T2CNT ___RwW $00, 1E Tx/Rx Control Status Register 2 TRCSR2”*s=«R/W $28 1F Reserved (Note 1) TSTREG = - a Port 6 Control/Status Register P6CSR RW $07 22 “Reserved = = =

23 Reserved Se

24 Reserved — = = =

| 25 Reserved = = = 26 __ Reserved = = =

27 Reserved = = =

Notes 1. Test register. Don't access this register. — es 2. R: Read-only register, W: Write-only register, R/W: Read/write register. 3. Unused bits set to 1 @ HITACHI | 728 Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD63701Y0, HD637A01Y0, HD637B01Y0 1. Latch the value of the port mode program pins Sleep Mode : The SLP instruction causes the CPU (MP, MP,) to stop operation and go into sleep mode. In sleep 2, Initialize the internal registers (table 2) mode, power dissipation is one-fifth of that in the 3. Set the interrupt mask bit active mode. 4, Put the contents of the last two addresses ($FFFE, FFFF) into the program counter @ Internal clocks stop (start address) and start the program from this @ Register contents are retained address. @ Peripherals function @ Interrupts are accepted Halt Mode : When the HALT signal is low, the CPU will be in halt mode. In halt mode, the CPU Table 1 shows the state of each port. Sleep mode is does not execute instructions, and address and data released by a RES, STBY, or interrupt. After being buses are released. released, the CPU goes to reset. standby, or interrupt, respectively @ = Internal clocks do not stop @ Peripherals (timer, SCI, etc) function Standby Mode : The MCU goes to standby mode @ Interrupts are accepted when the STBY signal goes low. or when the STBY flag in the RAM/port 5 control register (RPSCR : Table 1 shows the state of each port. Halt mode is $0014) is cleared by software ‘figure 5). In standby released when HALT goes high. A RES or STBY mode, power dissipation is reduced to several #A. signal also releases the halt mode and put the CPU into reset or standby modes, respectively. @ All clocks stop @ MCU goes to reset state @ RAM contents are retained Table 1 shows the state of each port. Reset releases standby mode. @HITACHI Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 729

Figure 5. Standby Mode Timing

instruction before beginning the interrupt sequence. begins at the vector address. Figure 6. Interrupt Block Diagram

Table 3. Interrupt Sources External Nonmaskable interrupt NM Generated by falling edge of NMI signal. Accepted regardless of interrupt mask bit. Interrupt request 1, 2 TRQi, Generated by low level at IRQi, IRQz pins. Table 4. Interrupt Vectors

to 9 ws. The one of three memory ready functions and restarts from $FFEE, $FFEF. During internal address or invalid memory access. memories. MR is also used as P5;. Table 5. Undefined Address Space Figure 7. Memory Ready Timing

The mode program pins, MP, and MP,, determine bytes. the operation mode of the MCU as shown in table 6. address bus or an input port. with the HMCS6800 buses. Port 7 is used for control accessed. Table 6. Mode Selection Note : “External RAM can be addressed by clearing the RAME bit in RPSCR ($0014). Table 7. Ports in Each Mode

3 Data Bus (Do—D7) Data Bus (Do—D7) 1/0 Port

4 Address Bus (As—Ais) 1/0 Port or Address Bus (Ag—Ais) 1/0 Port

7 RD, WR, R/W, LIR, BA RD, WR, R/W, LIR, BA Output Port

256 Bytes 256 Bytes 256 Bytes

can be used externally. used externally. Figure 8. Operation Mode Pin Function and Memory Map

direction of the port (0=input, 1=output). The capacitance. Figure 9. Port 1 Block Diagram

Port 2: Port 2is an 8-bit I/O port (figure 11). to directly drive the base of a Darlington transistor. direction of the corresponding bit of port 2 (figure Port 2 pins are also used as I/O pins by timers 1, 2. capacitance. It can produce 1 mA when Vou.=1.5 V controlled by registers in timers 1, 2, and the SCI.

1 Output Enable Signal

Figure 11. Port 2 Block Diagram (continued)

HD63701Y0, HD637A01Y0, HD637B01Y0 RES Fr ™ a D P22 DDR c Fs Fy a D ° £ sci '@) Cc £ | L\\ \\ ! Clock Input Enable t Signal | ee Clock Output Enable

1 Signal

+ Input Clock | we2p: DDR Write Signal {| WP2: Port Write Signal

1 RP2: Port Read Signal

Ry H | a ° ° H P2n DDR a c 5 é i < ° ° 7 SCI, Timer 2 P2, Data eatin £ \\

1 Input Enable signal

| SCI Receive Data, H Timer 2 External Clock i

1 WP2D: DDR Write Signal

! WP2: Port Write Signal | RP2: Port Read Signal j P23/Rx, P27/TCLK | @ HITACHI | 738 Hitachi America, Ltd. » Hitachi Plaza » 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300

DDR | DDR | DOR | DDR | DDR | DDR | DDR | DDR ony. Figure 12. Port 2 Register and Data Direction Register Table 8. Port 2 Pin Functions

HD63701Y0, HD637A01Y0, HD637B01Y0 Port 5: Port 5 is an 8-bit I/O port (figure 17) P5,-P5, are also used as control pins (table 9). The Each bit of the DDR {$0020) befines the data function of these pins is determined by the RAM/_ direction of the corresponding bit of port 5 (figure port 5 control register (RP5CR), except for P5,/IS 18). Port 5 can drive one TTL load and 30 pF and P5,/OS, which are controlled by the port 6 capacitance. control/status register (P6CSR) RES " mH | a D P5, DDR c é g WPS5D: DDR Write Signal a WP5: Port Write Signal P5._ Data 5 z c RAM/Port

5 Control

Register TRO: MR HALT * Value after reset; IRQ1E=0, IROZE=0, MRE=0"*, HLTE=1°° 1% #P52 and P53 can be used as I/O ports in spite of the value of this register in Mode 3 P50/IAGh, P5:/TAOz, P52/MR, P53/HALT RES R Q [> PSs DDR g 3 o | Ps | <q ° ° z WPSD: DDR Write Signal I: te Si PS. Data § WPS: Port Write Signal . c = RPS: Port Read Signal RPS wes Port 6 Control Status Register P56/5 (continued) | Figure 17. Port 5 Block Diagram i | @HITACHI | 742 Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

3 RPS: Port Read Signal

Figure 17. Port 5 Block Diagram (Cont)

DDR | DDR | DDR | DDR | DDR | DDR | DDR | DOR ony. Figure 18. Port 5 Register and Data Direction Register Table 9. Port 5 Pin Functions

i _ 63701 ¥0, HD637A01Y0, HDES7BO1YO RAM/Port 5 Control Register : The RAM/ @STBY FLAG: Clearing STBY FLAG by soft- port 5 control register (RPSCR: $0014) controls ware puts the MCU into standby mode. This flag onchip RAM and port 5 (figure 19). is set to 1 at reset, so reset cancels the standby mobe. If the STBY pin is low, this flag cannot be @IRQE. IRQ:E: Setting IRQE and IRQE to 1 cleared. selects P5, and P5, as the IRQ, and IRQ, interrupt inputs. These bits are cleared at reset. @RAME: When RAME is set to 1, on-chip RAM is enabled. When 0, it is disabled. RAME is set to 1 @MRE, AMRE: When MRE or AMRE is set to 1. at reset. This bit should be set to 0 before going P5, becomes the MR input. When both are 0. into standby state to protect on-chip RAM data. memory ready is inhibited (table 10). In mode 3. memory ready is always inhibited, regardless of @STBY PWR: When Vcc is not provided in these bits. MRE is cleared at reset, AMRE is set standby mode, STBY PWR is cleared. If STBY to Ll. PWR is set before the MCU goes to standby, and remains set after standby, Vcc was continuously @HLTE: When HLTE is set to 1, P5; becomes the supplied, and the contents of on-chip RAM are HALT input. When 0, HALT is inhibited. In valid. mode 3, HALT is always inhibited, regardless of HLTE. This bit is set to 1 at reset. @ HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 745

Figure 19. RAM/Port 5 Control Register Table 10. Memory Ready Function 0 _ 0 Memory ready inhibited. _ E clock automatically stays high one-cycle longer. This state is retained during reset. and slow memory outside. Input CS signal of slow memory to MR pin.

HD63701Y0, HD637A01Y0, HD637B01Y0 Port 6 Control/Status Register : The port 6 @OSS : When OSS is set, writing to port 6 initiates control/status register (P6CSR: $0021) controls an output strobe signal (OS/P5s). When OSS is and holds the status of the port 6 handshake cleared, reading port 6 initiates an OS. OSS is interface (figure 22). The handshake interface cleared at reset. functions as follows. @OSE: When OSE is set, P5s is the output strobe. 1, Latches the data input at port 6 on the falling OS. When cleared, it is a normal I/O port. edge of IS (P5,). 2. Outputs OS 'P5,) when reading or writing to @IS IRQ, ENABLE: When IS IRQ, ENABLE is port 6. set, IS FLAG set causes an IRQ, interrupt. When 3. When IS FLAG is set by the falling edge of IS, cleared, IS FLAG does not cause an interrupt. an interrupt occurs (figure 23). This bit is cleared at reset. @LATCH ENABLE: The LATCH ENABLE bit @IS FLAG: The IS FLAG is set by the falling edge controls the port 6 input latch (IS LATCH}. of IS. It is a read-only flag. It is cleared by When it is set, the input data at port 6 will be reading or writing to port 6 after reading the latched in at the falling edge of IS (P5,). Reading P6CSR. IS FLAG is cleared during reset. port 6 clears the latch. If LATCH ENABLE is 0. the input latch is disabled, and P5, acts as an Table 11 shows the conditions that set and reset the ordinary I/O port. LATCH ENABLE is cleared port 6 control /status register flags. at reset. | @ HITACHI | 748 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300

Figure 22. Port 6 Control/Status Register

6 ISiRQ1

Table 11. Port 6 Control Status Register Status Flags Set and Reset Conditions

outputs can vary from microseconds to seconds. Figure 26. Timer 1 Block Diagram

input capture. ICR is cleared at reset. matches, an output compare flag (OCF) is set in the read-only status bits. TCSR1 is cleared at reset. Figure 27. Timer Control/Status Register 1

HD63701Y0, HD637A01Y0, HD637B01Y0 @OLVLI: If OEl of TCSR2 is set, the value of cleared when the CPU reads the FRC's upper byte OLVLI will appear at Tout] (P2,) when a match ($0009) after it reads the TCSR1 with TOF=1. occurs between the FRC and OCR1 @OCF1: The read-only flag OCF1 is set to 1 when @IEDG: IEDG determines which edge of Tin/P2. a match occurs between OCR1 and the FRC. It is will trigger data transfer from the counter to the cleared when the CPU writes to the OCR1 ($000B ICR. IEDG=0 selects the falling edge (high to or $000C) after it reads the TCSR1 or TCSR2 low transition}, IEDG=1 selects the rising edge with OCF1 or OCF2=1. OCF1 is also available at (low to high transition). TCSR2, bit 6. @ETOI: When ETOI is set to 1, timer overflow @ICF: The read-only flag ICF1 is set to 1 when will cause internal interrupt IRQs. When it is Tin/P2, makes the transition defined by IEDG cleared, the interrupt is inhibited. and the FRC is transferred to the ICR. It is cleared when the CPU reads the upper byte or the @EOCI1: When EOCI! is set to 1, a counter match ICR after it reads the TCSR1 or TCSR2 with ICF with OCI! will cause an IRQ, interrupt. When it is =1.ICF is also available at TCSR2, bit 7. cleared, the interrupt is inhibited. Timer Control/Status Register 2: The timer @EICI: When EICI is set to 1, an input capture control/status register 2 (TCSR2: $000F ; figure signal (Tin) will cause an interrupt IRQ. When 28) is a seven bit register. All bits can be read and it is cleared, the interrupt is inhibited. the lower four can be written. The upper three are read-only status bits. All bits are cleared at reset, @ TOF: The read-only flag TOF is set to 1 when except bit 4, which isn’t used. the counter increments from $FFFF to $0000. It is nn nr Timer Control/Status Register 2 7 6 5 4 3 2 1 i) Output Enable 1 0-P2; is 1/0 port 1-P2; is Tout] Qutput Enable 2 0-P2s is 1/0 port 1-P2s5 is Tout2 Output Level 2 0-Tout2 outputs 0 1-Tout2 outputs 1 Enable Output Compare Interrupt 2 0-Interrupt on OCI2 inhibited 1-IRQ3 interrupt on OCI2 enabled Qutput Compare Flag 2 0-OCR2 and FRC don't match 1-OCR2 and FRC match Output Compare Flag 1 0-OCR1 and FRC don't match 1-OCR1 and FRC match Input Capture Flag O-No input capture trigger i 1-Tin triggered input capture 7 Figure 28. Timer Control/Status Register 2 | @ HITACHI i Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300 753

Toutl/P2, when there is a match between the either register. reloadable timer, which can count external events. occurs between the FRC and OCR2. waveforms. Table 12. Timer 1 Status Flags Set and Reset Conditions

Figure 29. Timer 2 Block Diagram

read the value of the T2CNT at any time without status register 3 (TCSR3). It is set to $FF at reset. T2CNT and the TCONR, or at reset. bits except for bit 7, CMF, can be written to. CMF. Time Constant Register : The 8-bit, write-only at reset. “Note : These clocks come from timer 1. Figure 30. Timer Control /Status Register 3

direction set in port 2’s DDR. To transmit data, set

the desired format in the RMCR and the TRCSR2. the SCI sends one or two stop bits of 1. ates in two modes: asynchronous with NRZ en- the CPU puts data in the TDR. (TRCSR1, TRCSR2) following bit will be strobed in the middle. + R,(P2;), input When PEN is set to 1, the SCI checks the parity bit. by EOP, the SCI set PER to indicate a parity error. Table 13. Timer 2 Status Flag Set and Reset Conditions

the received data by reading the RDR after reading SCI outputs transmit data and clock pulses. P2,, regardless of TE or RE. If they are 11, an reception, making P2, the serial input Rx. to P2, at 16 times (16x) the desired bit rate, but not and the RMCR. impossible. TE and RE should therefore never be SCLK is high. Setting TE in TRCSR1 enables transmission, transmitter should synchronize to these clocks. making P2, the serial output Tx regardless of the Reception of the first byte of data sets RDRF. the desired format in RMCR and TRCSR2. When transmitting eight more clocks. Transmit data is produced from a falling edge of a synchronous clock to the next falling edge. Receive data is latched at the rising edge. Figure 33. Synchronous Format

1: Transmit/receive control/status register 1 initialized to $20 at reset. Figure 34. Transmit/Receive Control/Status Register 1

HD63701Y0, HD637A01Y0, HD637B01Y0 @WU: WU is the asynchronous mode wake-up @RIE: When RIE is set, RDRF or ORFE set will function. When WU is set, the SCI stops receiving cause an IRQ, interrupt. When it is cleared, the data until the next message. The reception of a interrupt is inhibited. RIE is cleared at reset. frame of consecutive 1s wakes the SCI up, clears 5 . @TDRE: The SCI sets TDRE when the TDR is WU and starts reception. The RE flag should be transferred to the transmit shift register in the set before setting WU. The wake-up function is asynchronous mode, leaving the TDR empty. It is not available in synchronous mode. set in the synchronous mode when the transmit shift register is empty. TDRE is cleared by @TE: When TE is set, transmit data will appear readin the TRCSRI o the TRO? and. wae’ ‘ 7 . new data to tl while =1. is at Tx/Poe It is preceded by @ one frame re, _set to] at reset. The TDRE should be cleared in amble in asynchronous mode, | the transmit state after TE is set. mode it appears immediately. @ORFE: The SCI sets ORFE when an overrun or @ TIE: When TIE is set, TDRE set will cause an framing error occurs during data receive. ORFE IRQ, interrupt. When it is cleared, the interrupt is is cleared by reading the TRCSR1 or the TR- inhibited. TIE is cleared at reset. CSR2 and the RDR when ORFE=1. ORFE is cleared at reset. @RE: When RE is set, a signal is input at Rx/P23. @RDRF: The SCI sets RDRF when data is When RE is cleared, P2, can be used as an 1/0 received normally and transferred from the port. receive shift register to the RDR. It is cleared by reading the TRCSR1 or the TRCSR2 and the RDR when RDRF=1. RDRF is cleared at reset. @HITACHI Hitachi America, Ltd. » Hitachi Plaza ¢ 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 761

HD63701Y0, HD637A01Y0, HD637B01Y0 Transmit/Receive Control/Status Register parity bits in the asynchronous mode. If it is 0, it 2: Transmit/receive control/status register 2 uses no parity. (TRCSR2: $001E; figure 35) has seven readable bits, the lower three of which can also be written to. The above 3 bits (SBL, EOP, PEN) do not affect the SCI operation in the clocked synchronous @SBL: When SBL is 0, 1 stop bit is selected for mode. asynchronous mode. When SBL is 1, 2 stop bits are used. SBL is cleared at reset. @PER: PER is set when a parity error occurs. It is cleared by reading the RDR after reading the @EOP: EOP selects even or odd parity in asyn- TRCSR2 with PER = 1. chronous mode if PEN =1. If EOP is 1, the SCI uses odd parity. If it is 0, the SCI uses even parity. @ TDRE. ORFE, RDRF: TDRE, ORFE, RDRF are the same as in the TRCSRI. These bits can be PEN: If PEN is 1, the SCI generates and checks accessed at either address. Transmit/Receive Control/Status Register 2 7 6 5 4 3 2 1 0 (wom [one [ron [oon [7] om [cor [| on Stop Bit Length 0-1 stop bit 1-2 stop bits Even/Odd Parity 0-Even parity 1-Odd parity Parity Enable O-No parity 1-Parity Parity Error 0-No parity error 1-Parity error detected Transmit Data Register Empty 0-Data in TOR 1-TOR empty Overrun Framing Error 0-No overrun or framing error 1-Overrun or framing error detected Receive Data Register Full 0-No valid data in RDR 1-Valid data received in RDR | Figure 35. Transmit/Receive Control/Status Register 2 | @HITACHI | 762 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. ° Brisbane, CA 94005-1819 « (415) 589-8300

All bits are read/write. Bits 0-6 are cleared at reset. {0 the SCI. shown in tables 14 and 15. ags. Figure 36. Transfer Rate/Mode Control Register

Table 14. SCI Bit Times and Transfer Rates *When SS2 is 1, timer 2 provides SCI clocks. The baud rate is shown as follows with the TCONR as N. **The bit rate is shown as follows with the TCONR as N. Table 15. Baud Rate and TCONR Example *E/8 clock is input to the timer 2 up counter. E clock for all others.

Table 16. SCI Format and Clock Source Table 17. SCI Status Flags Set and Reset Conditions

PROM mode, the MCU doesn’t operate. It can be grammers and socket adapters. Table 18. EPROM Programmers and Socket Adapters Table 19. EPROM Mode Selection

Figure 38. EPROM Mode Pin Arrangement reliability. Table 19 shows how programming and type cannot. The EPROM on HD63701Y0s in ceramic “window” — grammer. packages can be erased by ultraviolet light. All . Erasing conditions are: ultraviolet (UV) light with HD63701Y0, the LSI may be permanently damaged. wavelength 2537 A with a minimum irradiation of 12.5 V is Intel’s 27256 Vee specification.

Figure 39. High-Speed Programming Flowchart with the HD6801 to use the entire instruction set of instructions. Accumulator (ACCX) Addressing: Only one OIM, EIM, or TIM. the second byte of the instruction, except for LDS instructions. directly. Storing data in this area reduces execution accessed. These are two-byte instructions. shows the detailed operation of the instructions.

Table 20. Instruction Set Summary

HD63701Y0, HD637A01Y0, HD637B01Y0 Accumulator, Memory Manipulation Instructions (Cont) cmtrs manele | oneer | woex [reno [wre | OM” STaT a [sa] lrl=[ + for[=[+ for] fon] ~[ + for[~[e] “Lielz| fe] puroae True TTT TT ffs po fie Te [ele Tele [ ey vue [TTT TT TTT [etsy [ieee Tele [e lolol] rower [wo | TTT TT feolefelste/ay TT | SEE pow TT TE [eof |iisgegpcc) [= so] roo TT Ty TP TT | fey leleyet [ole wonemen foo [TL TP wlelepelstay |p ele feta] fora TTT TE fes[e [eee] fe [tf fo] | pore TT TT TT Issa OOBBOE soaeuan fast TTT TTT felefefelsf ay TT [eet foli| Ce eG... ooneon ase TT TTT ETT TT TT it DOBBOR Gatatne [oso | TTL TY | [fs erate] [| Je] | anne [se 1) | delete [| poggon fms ose OL ee eatin fof Tor] eee poegon aaae [se TP mle epee ls] [doef efor] Cseseeeneee 00 OOonOn Coeeseeeeeeeeeoon poggo0 imams me TT TTT YT oe ss eet] |] | fe] | sma] TT ferfefela/s[efer[atat | [ [aw Tefe[i [i [fel isms [|] fovisfalers[efe[alaj | [ few Tefe[i[eyale] ema fo LL elt etel le [i fees ele f tele] Accumulator B-M+1 ew alee pola faf [| [armen fefet fs] [a [suse [eof 2] 2 po] a[2 jeol«{2|roja[a] | | [ewe [elefi[i[i[s| [ons savas suso_ [sof [a]oo]/2 el s[afesis|s/ | [ iewemen]efef Tet [s| wee [9m | || TTT TT felts farwn foetal fe | Accumulators saws (seen [wale [sez fale fe|mles| [| [wom lefef trel| (seca feel? | 2 oo}3[21ee[+[2|r2fe[a[ || Jewee [oe ls [fife] fem fe pat ece fede tat : CSSSSSS 0088880 00CeeCOOELO or (a IC I) | ree alco oo ef fea oe polar Yo fo eee] fesrmeane [am [| | fale afafe[ sp [| Lf wewmacw Yolo ls reo] | formas fom ||| ele [aeef7[3[ | | [| | [wenn [ole] ela e| | [eorimmacnte [em T [| tests tales [st TT TTT [maw Tefe [a [af a[e [Fest immediate [rm | | Pele tafests {oT TTT TT pwc reTeT eT TR [ | | @HITACHI | 770 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300

a HD63701Y0, HD637A01Y0, HD637B01Y0 Index Register, Stack Manipulation Instructions hakressna Modes Conan Case a eel EXTEND | PLIED | en re]*[2l2[ [| [+ for|~[ + Tor]~|+ Deco [ec[s {sleet «ja tacls[elec|s[s] [ [ [x-mmer Te alee an PT Joop pce ie] Deena Sk Pt weit io le se=1-sP releleie| [omonecvencine fx TT | TT | | TT [ef pore Telefe fole] [ison svcrrrfns | |] | |. [1.1 | [uals fsreise [elelo[ele le] [imesinsenee [vox joe, af aoe] [eels 2] re] s|3| Tartin [elelaiilele| Load Stack Pntr | LDS ae] 3] 3 |9e| 4 | [2 | ial | Host se, jele[afi[Rie| stow indexes [etx | || for] «2 [a ecten [ele tol ete] stow swex Por [sts | | | [ar/ 4/2) Sra eh VE AE Index Reg ~ Stack -1-SP ests atten bel Re _ ee Hatt few jelelelelele| ruonate frome | | TT TT [20|5 [1 [Ree lelelelelele| ul Ota Pou Eee veo (a Se euese | * [e[e| [ectanee | POET Tse [i Taccone fe] @ HITACHI Hitachi America, Ltd. © Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 771

HD63701Y0, HD637A01Y0, HD637B01Y0 Jump, Branch Instructions cmetore —hrmone aca omecr [ waor [oreo [wu] smaren [s[s]3{2[s [a] orl [* for] =[ for =[ + for[=[ [or [+] [el [af2| +e] Joann aware [oma [aol sie] TT TTT TT TT TT [me Tolefefeloye] event — Joma fe Lee eee eon | we feet es esfefet TTT TT TT TT TT fer Tefefofolefol Jeane itezero foea feisie{ | TT iT TT TT ty fe Telefefofofe] [annirezro [ect feo aie] | | TT | TT TT | [neveo [elelelolee Jerr tae fect feelaf2] [ | TTT TT TT TT femen-o [olefelele[o Jeans tier fom feel ste] { | TT TT TTT TT fereo [ofelefelolo| fecvenivazwe me forlsfet TTT TTT TTT TT fevmener fefefelolols| [gine “Corer Ofms leafs fet | TTT TT TT TT | [oven [ete fefofolel [earn tczwo [or fofatat TT TT TT TTT TT [wees [ole lofofole| C00 Se Cee OOOO [imo NtEwwtTone [esate | | TT TT TT TT | leo [ololofetele| [ean orm lovo Tasfs tat TT TT TT TTT TT fo [elefofofole| ni Oe Oooooo Joon tems [orc fenistal T | TT TT TT TTT [xo [elofofef oye] [eave rosutrovine|ese [aol sf2{ | | TTT iT Tt tt [efelefofele| Jaro fw TT TT sels fe vrefa fst TT | elofolelele| [re rosutouine [as | | | [sols] [aol s [2 feofe]a] | | | [+lelelofele| [reorwaion [wom TTT TTT TTT TT forts [s [eerearoe Telefe >Te Le] [aeerronreoret [em | TT TTT TTT TT fepol | | —-o— | [scours ST TT TT TT TTT feist pogooo [sstwarsintwrot [swe | TT TT TT TET TE Tafel lels[ofefele| [wet torttoromes war TT TT TE TT fe] [sole ete le| [swe de PPT TT TT pape] [ofo[e[efele| Note: “WAI puts R/W high; Address Bus goes to FFF; Data Bus goes to the three state, | @HITACHI 772 Hitachi America, Ltd. » Hitachi Plaza 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300

HD63701Y0, HD637A01Y0, HD637B01Y0 OV IEE EEEEEEEEOoeeeeeeee Condition Code Register Manipulation Instructions 7 ‘Addressing Modes Condition Code Register Operations sooiean Operation [34] 312 [110 [op] ~T# | [Hii [N[z[vic| Gearary | SCs Pa oc fof elelofoir| Clear Interrupt Mask | cul | oe | | fo[Riolefele| Clear Overtiow ata ja | [elelelelRie| Sat Cory | se feet le[elelole[s| [Set interrupt Mask [sel OF i an Set Overton sev fost it iv leleelels{e| tap foot a [a [Ancor | wa Lor}a[i1] cera __[elelelelele| —— Description of symbols —— Legend: Condition Code Symbols : OP — Operation Code (Hexadecimal) H_ Half-carry from bit 3 to bit 4 ~ Number of MCU Cycles 1 Interrupt mask Msp Contents of memory location pointed by Stack Pointer N Negative (sign bit)

4 Number of Program Bytes Z Zero (byte)

+ — Arithmetic plus V_ Overflow, 2's complement - Arithmetic Minus C Carry/Borrow from/to bit 7 @ Boolean AND R_ Reset Always = ~— Boolean Inclusive OR S Set Always @® Boolean Exclusive OR 1 Set if true after test or clear M Complement of M © Not Affected > Transfer into 0 ‘Bit=Zero

00 Byte=Zero

Note: Condition Code Register Notes : (Bit set if test is true and cleared otherwise) @ (BitV) Test : Result=100000007 @ (Bit C) Test : Result#00000000? @® (BitC) Test : BCD Character of high-order byte greater than 10? (Not cleared if previously set.) ® (Bit V) Test : Operand=10000000 prior to execution? ® (Bit V) Test : Operand=01111111 prior to execution? © (BitV) Test : Set equal to N@C=1 after the execution of instructions @ (Bit N) Test : Result less than zero? (Bit 15=1) ® (ANBit) Load Condition Code Register from Stack. ® (Bit) Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait state. @ (ANBit) Set according to the contents of Accumulator A. @ (BitC) Result of Multiplication Bit 7=1? (ACCB) @HITACHI Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 773

Table 21. Opcode Map

*Only each instructions of AIM, OIM, EIM, TIM

Table 22. Cycle-by-Cyele Operation

Table 22. Cycle-by-Cycle Operation (Cont)

| FFFF 1] Restart Address (LSB)

3 Jump Address 1 bY) 1 0 Next Op Code

3 Destination Address i) 1 | 0 1 Accumulator Data

4 Op Code Address +3 1 0 1 0 Next Op Code

5 Op Code Addresst+3 | 1 i} 1 i) _ Next Op Code

2 Op Code Address +2 1 i) 1 1 Jump Address (LSB)

6 Op Code Address+3 1 i) 1 O | Next Op Code

4 Address of Operand ie) 1 oo; 1 00

4 FFFF 1 Restart Address (LSB)

| Stack Pointer+1 C) Return Address (MSB)
(| FFFF 1 | Restart Address (LSB)

| Stack Pointer o | 1 | 0 { 1 | Return Address (LSB)
| Stack Pointer+1 1} 0] 1 1 | Conditional Code Register
‘| FFFF 1 1 1 | 1 | Restart Address (LSB)
| Vector Address FFFB r}ojfi fa ‘co of SWI Routine
(| FFFF 1 1 1 1 | Restart Address (LSB)

HD63701Y0, HD637A01Y0, HD637B01Y0 Absolute Maximum Ratings Item Symbol Value Unit Supply voltage Vee 0.3 to +7.0 Vv Vpp voltage Vep —0.3 to +13.0 v ih input voltage Vin —0.3 to Vec+ 0.3 v Operating temperature Tope 0 to +70 c Storage temperature Tstg —55 to +125 ct Note: This product has protection circuits in input ‘terminal from high static electricity voltage and high electric field. But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits To assure the normal operation, we recommend Vig, Vou: Vssi (Vor OF Vous) Vcc

Electrical Characteristics

(Vcc=5.0 V + 10%, f=0.1 to 2.0 MHz, Vss=OV, Ta=0 to +70°C, unless otherwise noted.) Item Symbol Min Typ Max Unit Test Condition Input high voltage RES, STBY, MPo, MP: Vin Vec—0.5 Vect+0.3 V EXTAL Vecx0.7 Voc+0.3 V ‘Other inputs 20 Vect03 V Input low voltage RES, MPo, MP}, SCLK(P22)3 Vit -0.3 06 v __All other inputs =03 08 Vv Input leakage current RES link 10.0 #A — Vin=0.5 to Vec—0.5V NMI, STBY, MPo, MP1 _ 1.0 vA Three state Ports 1, 2, 3, 4, Iitsil 1.0 UK Vin=0.5 to Voc—0.5V leakage current 567 . Output high voltage Vou 24 Vi ton =—200 uA __Weo=0.7 V ton=—10 yA . Output low voltage Vou 04 Vt =1.6mA Darlington drive Ports 2, 6 =lon 1.0 10.0 mA Vout=1.5V seurrent Input capacitance RES Bn, P= MH, All other inputs 125 pF Ta=25°C Standby current Not operating iste 30 15.0 uA Current dissipation? Isip 15 30 mA Sleeping (f=1 MHz?) 23° 45 mA Sleeping _(1=1.5 MHz?) 30° ©6.0 mA Sleeping (f=2 MHz?) toc ___7.0 10.0 mA Operating (f=1 MHz?) 105 15.0 mA Operating (f=1.5 MHz2) 14.0 200 mA Operating (f=2 MHz2) RAM standby voltage Vram 2.0 Vv Notes : 2 Current dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typ. or max. values about current dissipations at x MHz operation are decided according to the following formula: typ value (f=x MHz) =typ value (f=1 MHz) Xx max value (f=xMHz) =mex. value (1=1 MHz) Xx (both the sleeping and operating) 2. Only serial clock use. @ HITACHI Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, GA 94005-1819 (415) 589-8300 781

HD63701Y0, HD637A01Y0, HD637B01YO AC Characteristics (Vec=5.0 V +10 %, f=0.1 to 2.0 MHz, Vss=0 V, Ta=0 to +70 °C, unless otherwise noted.) Bus Timing HD63701Y0 6370010 11063780170 Item Symbol Min Typ Max Min Typ Max Min’ Typ Max unit Test x" Condition Cycle time teye 1 10 0.666 10 O05 10 us Fig. 40 Enabie rise time ter 2 25 25 ons Enabie fall time ter 25 25 250 ons Enable pulse width high level! PWen 450 300 220 ns Enable pulse width low level? PWeL 450 300 220 oO ns Address, 8/W delay time? tad 250 190 _ “160 ns Data delay time (Write) toow ~ 200 160 120s Data setup time (Read) —tpsr_-— 80 a 60 ms Address, R/W hold time! taH 80 - 50 40 ns Data hold time (Write)? ty 80 50 40 ns (Read) ur ° ° ° ns RD, WR pulse width? PWrw 450 300 220 i os RD, WR delay time trwo 40 40 40m RD, WR hold time tHrw 20 _ “20 20 “ons TR delay time tour 200 - “160 120° ons TR hold time a wR 10 10 i 10 ns MR setup time! ‘su 400 280 230 ns Fig. 41 MR hold time? tHMR 100 70 50 ns E clock pulse width at MR Pema 9 9 9 us - Processor control set-up time tecs 200 200 200 ns Fas 2 Processor control rise time tee 100 _ 100 100 ons Figs. 41, 42 Processor control fall time tect 100 100 100 ns BA delay time tea 250 190 160 ns Fig. 42 Oscillator stabilization time tre 20 20 2 ms Fig. 53 Reset pulse width PWest 3 3 3 - teye | Note: 1. These timings change in approximate proportion to teyo The figures in this characteristics represent those when teye iS minimum (=in the highest speed operation) @HITACHI 782 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 © (415) 589-8300 | .

HD63701Y0, HD637A01Y0, HD637B01Y0 Peripheral Port Timing

06370170 H0637A01Y0 063780170

tem Symbol Min Typ Max Min’ «Typ Max) Min. «Typ Max Unit Test Condition Peripheral data (Ports 1, 2, 3 wei time ass) (osu 200 200 200 ns. Fig. 44 Peripheral data (Ports 1, 2, 3 201 hold time 45,6) POH 200 ° 200 _™ Delay time (From enable fall edge to ee 3 tewo 300 300 300 ns Fig. 45 peripheral output) — Input strobe pulse woth tems 200 200 200 ns Fig. 49 Input data hold time (Port 6) tie 150 150 150 ns Input data set-up time (Port 6) us 100 100 100 ns Output strobe delay toso1 200 200 200 ns ‘Fig. 50 time __ tosp2 Timer, SCI Timing H063701Y0 HD637A01Y0 H0637B01Y0 hem symbol Min Typ. Max) Min’ Typ Max Min Typ Max Unit [OM em et Timer 1 input pulse width tewr 2.0 20 20 teye Fig. 48 Delay time (enable positive ~ ~ transition to timer output) trop 400 400 400 ons Figs. 46, 47 SCI input ‘Asyne mode) tggye. «1. 1.0 1.0 ~ tye Fie 48 clock cycle (Clock syne.) 20 2.0 20 teye Fig. 43 ‘SCI transmit data delay 0 a time (Clock syne, mode) trxo 220 220 22 ns Fig. 43 SCI receive data setup time (Clock sync. mode) _ ‘sex 260 760 260 s ‘SCI receive data hold time (Clock syne. mode) tuex 100 100 100 "s ‘SCI input clock pulse width tewscx 0.4 06 8604 06 04 06 — tScyc Fig. 48 Timer 2 input clack cycle teye 20 20 20 teye Timer 2 input clock pulse width tpwrcx 200 200 200 ns Timer 1 + 2, SCI input clock ~ ~ Hiapat texr 100 100 100 ns fisetime Timer 1+ 2, 7 imer 1 + 2, SCI input clock ext 100 100 100. ns @HITACHI Hitachi America, Ltd. » Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 (415) 589-8300 783

Figure 40. Mode 1, Mode 2 Bus Timing

Figure 44. Port Data Set-up and Hold Times Figure 45. Port Data Delay Times (MCU Write) Figure 46. Timer 1 Output Timing Figure 47. Timer 2 Output Timing

2.04 P54 (18) v

Figure 48. Timer 1 - 2, SCI Input Clock Timing Figure 49. Port 6 Input Latch Timing Figure 50. Output Strobe Timing Figure 51. Bus Timing Test Loads (TTL Load)

Data output delay time toe 0 - 500 ns. Figure 54. EPROM Programming/ Verify timing,

HD63701Y0, HD637A01Y0, HD637B01Y0 Warning Concerning the Board of Oscillation Circuit de that di tome no Avoid signal lines When designing a board, note crosstalk may dis- - Paap mal turb the normal oscillation if signal lines are placed Ymft-r-e-yauyR}X@é= — " ° near the oscillation circuit as shown in Figure 55. Ze Zz ag Place the crystal and C, as close to the HD63701Y0as Z ey possible. Ze HHS EZ : ao 2d oes tot HD63701Y0 i Hoea701Y0 (0C-64s) Do not use this kind of print board design. (Top view) Figure 55 Warning conceming board design Figure 56 Example of Oscillation Circuits in Board Design cof oscillation circuit Receive Margin of the SCI Table 23 Bit distortion tolerance ‘Character distortion tolerance Receive margin of the SCI contained in the (t-to) Ao (1-10) [To HD63701Y0 is shown in Table 22. £43.7% £4.37% Note: SCI = Serial Communication Interface. START 1 2 3 4 5 6 7 8 STOP Ideal Waveform Bit tenatn|+-to—a| Character length To, QHITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 « (415) 589-8300 789

Selected Specification

Hitachi Semiconductor HD637B01Y0 overview.

Summary

CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER UNIT

Description

CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER UNIT

Source title HD637B01Y0 Datasheet(PDF) - Hitachi Semiconductor

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