HD63484CP6

HD63484 HITACHI

Document overview

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Technical content

Advanced CRT Controller (ACRTC) The advanced CRT controller (ACRTC) CMOS —Colors: 16 bits/word VLSI microcomputer peripheral device can 1, 2, 4, 8, 16 bits/pixel (5 types) display both graphics and characters on ras- Monochrome to 64k colors max ter-scan displays. It is a new generation CRT —Pattern RAM: 32 bytes controller based on bitmapped technology. It —Converts logical X-Y coordinates to phys- executes high-level commands, like Line, El- ical address lipse, Paint, Patten, and Copy, issued by the —Color operation and conditional drawing MPU in screen X-Y coordinates, and performs —Drawing area control for hardware clip- the address translation necessary to draw ping and hitting into frame memory. It can draw in up to 64k @ Large frame-memory space colors, on three split screens and an inde- —Maximum 2 Mbytes graphic memory 2 pendent window, and perform area clipping and 128 kbytes character memory se- and hitting. parate from the MPU memory —Maximum resolution: 4096x4096 pix- The ACRTC controls a CRT in one of three els (1 bit/pixel mode) modes: character only, graphics only, and © CRT display control multiplexed character/graphics modes. —Split screens: three displays and one Therefore, the ACRTC has many applic- window ations, from character-only displays to large —Zoom: 1 to 16 times full-graphics systems. —Scroll: vertical and horizontal @ Interleaved access mode for flashless The ACRTC reduces CPU software overhead display and superimposition and enhances system throughput. @ External synchronization between ACRTCs or between ACRTC and external device (TV system or other controller) @ Two programmable cursors Features © Three scan modes —Non-interlaced ®@ High-speed graphics —Interlace sync —Drawing rate: 408 ns/pixel max (color —Interlace sync and video drawing) © Interrupt request to MPU —Commands: 38 commands including 23 @ 256 characters/line 32 raster/line, 4096 graphic drawing commands rasters/screen Dot, Line, Rectangle, Poly-line, Polygon, @ Maximum clock frequency: 9.8 MHz Circle, Ellipse, Paint, Copy, etc © CMOS, single +5 V power supply

Ordering Information

Part No. Clock Frequency (2CLK) Package HDese-4 “a Maz ar) HD 63404-6 6 Miz {G4-pin coramic DIP) H063484-8 BMH: fae pes4eara “4 Mae ope H63484P6 6 MHz (64-pin plastic DP) Hoes4a4Pe 8 Mir ‘HD63484P98 9.8 Miz HOeSéeacPa A MHz — ~ CP-68 - Hosaaeacrs* = 6 MHz (68-pin plastic PLCC) HO63484CP8_ 8 MHz HD63484CP38 9.8 MHz Hoesasave a MHE PC-68 HD62484¥8 6 MH {68:pin PGA) Hossdeave BMH HD63484YS8 9.8 MHz a Hoemass¢ 4M SSCS HOB3484PS6 6 MHz {64-pin plastic shrink DIP) HD63484PS8 BMH: ‘HOesap4psee 9.8 MH Note: Wide temperature range (—40C* to +80C) version is available. @HITACHI Hitachi America, Ltd. * Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 * (415) 589-8300 213

TT SSSSSsSSessssssssSSSSSsSSSsSSSSSSSSsSSSSSSSSS HDESB4Y Pot (-) e1svaraiarsistotar9) GETSOOO QGO Gao COTO) Oro) 610) OIOn Qo, GO, QO olay O19) Goer. . . Goo Siaretoietaie oIeto) GQOOGOQOOOOO® (Top View) (Bottom View) Pin Mo. PinName PinNo. Pin Name Pino. Pin Name _ Pin No. Pin Name ’ ‘MAD, (T) 18 RS B MA, /RA,, 82 ‘REG 2 man, (7) 3 TACK (rT) * MAg/RAy J HEYNE 3 ‘MAD, (T) 2 iRO (0,0) ” MAD, (1) oo EXSYNC 4 ‘MAD, (1) ra ‘VSYNe zB ‘MAD, (1) 5 om

5 MAD,(T) 22 Vee Ey MAD, (T) 56 Dm

6 Vee 23 Ves “0 ‘MAD, (T) 7 Bm

7 Ves 2 Ves a 2CLK 8 om

a y, cid om a2 McYC CJ m ° as 2% Om 43 (DRAW & Ohm 10 ‘MRO aT am “ MAD, (1) a o.m " ‘MAD, {T) cd on 45 ‘MAD, (T) 62 PA, 2 ‘MAD, {T) 2 27) 6 MAD, (1) a MA, JRA,

3 OiSP, 0 b,m a ISP, 64 MAD,, (7)

“4 LPSTB co Dy iT) 48 cud, 6 MAD, (1)

15 Vee 32 Dy) 43 cs 6 CHR

16 cub, cy Ves 50 ‘RES a BACK

47 Rw Ed MA,,/RA, st DONE (0,0) 68 2,

HD63484, HD63484P, HD63484PS HD63484CP wa ho =D usre A 2 SEE EE wor G2 Ce as BBS bbeSss Ts eof) oes Bie onthe sSRB299 21 e Cj. orf) wana WOO IOAIDREGAn.” ns qs: sfJmrom pace eee 8 E888 Le cid Cs se) maou BYACRII tndex sofJmAo oreo. f> Ej sion navo.0164 ss por oes sxPJuaoun — ASYWCE) B ae HB om — YeneE SB BratKiTy Cho ss] a0 EXBYNE Ee “Eas Wvo.07 Cr i) Baw ves? »Bzcin rome Ghz ops omen "Eos wre Oo sal weve ym Goo of MAD, vee cj cy a ee one pe Shorea whe “pve ounce “Baan ow Go sua Behe eEaman.in om Che oO = re <P a“ a" Seo ROCuoE ER LOGC UW wm Cho aD) micas EERE EEEEF EEE Ea om = Gla 2} mao. ida ait Ca all) mao. 332372 ow Efe ao mao. ow Es of a0, ow Efe 296) wav. ow Cher ef) ao ts ©.D: Open drain own = Cee a] ma rernae T: Three state out Che ef] mesma oun ho 246 snsaraas out Eh af] armas on »Eh~ @ HITACHI 214 —— Hitachi America, Ltd, « Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300

Group Mnenonic _DIP PLCC PGA _ 1/0 Function MPU. RES 6 7 50 ! ACRTC reset interface DD s* 17-32 19-34 25-32 «(1/0 Data bus (three state) 55-61 RW 3 4 V7 _|__Read/write strobe cs 4 5 49 1 Chip select RS 6 G 18 I Register select DTACK 10 " 19 © _ Data transfer acknowledge (three state) p, iRO nu 12 20 fe) Interrupt request (open drain) DMAC OREO 8 9 520 DMA request interface = BACK 9 10 67 1 DMA acknowledge _____ BONE 7 8 51 VO DMA done (open drain) : CRT 2CLK 50 53 a | ACRTC clock interface == MADy-MAD,,* 61-57, 65-61, ‘1-5, 11,12 VO Multiplexed frame buffer 48-38 51-41 37-40,44- address/data bus a 46, 64, 65 _ _ AS 5387 9 O _Adress strobe MA,,/RA-* 37-34 «40-37. 34-36. =O ~—_——sdHHigher-order address bits/ MA,,/RA3 _ character screen raster address RA, 33 36 62 © — High-order character screen : ee __ raster address bit CHR ____ 6 __© Graphic or character screen access: mcyc 52 Es 42 O Frame buffer memory access timing _ a a signal - MRD 55 59 10 O __Frame buffer memory read DRAW 54 58 43 O __Draw/refresh signal DISP1, DISP2 63,62 «67,66 + 47,13 +O _ Display enable Cubi,cuD2 1,2 23 48,16 Cursor display VSYNC 13 4 2 fe) CRT vertical sync pulse HSYNC 12 13 53 . CRT horizontal sync pulse - EXSYNC 1 16S 1/0 External sync LPSTB 64 ea 4 I Lightpen strobe Power Voe 14,49 1, 15,52 6, 15, 22 +5V Supply OC Ves 16,51 17,18, 7, 8,23 Ground 35,54, 24, 33 *: PGA pin numbers don’t correspond to Dy-D,5, MADg-MADy5, MAye/RAg-MA\\o/RAg. Please refer to the pin arrangement. @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 215

MPU Interface of the character screen raster address (up to __ 32 rasters). RES (Reset): RES is the MPU hardware reset. CHR (Character): CHR output indicates whether a graphic or character screen is be- Do-D,, (Data Bus): D,-D,, are the bidirec- ing accessed. tional data bus to/from the host MPU or DMAC. D,-D, are used in 8-bit data bus MCYC (Memory Cycle): MCYC is the mode. frame buffer memory access timing output, _ _ one-half the frequency of 2CLK. R/W (Read/Write): R/W input controls the direction of host/ACRTC transfers. MRD (Memory Read): MRD output con- __ trols the frame buffer data bus direction. CS (Chip Select): CS input enables trans- fers between the host and the ACRTC. DRAW (Draw): DRAW output differen- lates between drawing and CRT display re- RS(Register Select): RS input selects the fresh cycles. ACRTC register to be accessed. It is usually connected to the least significant bit of the DISPi, DISP2 (Display 1, 2): The DISP1 host address bus. and DISP2 programmable display enable outputs can enable, disable, and blank logi- DTACK (Data Transfer Acknowledge): cal screens DTACK output provides asynchronous bus cycle timing. It is compatible with the CUD1, CUD2 (Cursor Display 1, 2): HD68000 MPU DTACK output. CUD1 and CUD2 outputs provides cursor timing programmed by ACRTC parameters IRQ (Interrupt Request): IRQ output gen- such as cursor definition, cursor mode, cur- erates interrupt service requests to the host sor address, etc. MPU. VSYNC (Vertical Sync): VSYNC outputs DMAC Interface the CRT vertical synchronization pulse. DREQ (DMA Acknowledge): DACK tre- HSYNC (Horizontal Sync): HSYNC out- ceives DMA acknowledge timing from the puts the CRT horizontal synchronization host DMAC. pulse. DONE (DMA Done): DONE terminates EXSYNC (External Sync): EXSYNC al- DMA transfer. It is compatible with the lows synchronization between multiple HD68450 DMAC DONE signal. ACRTCs and other video signal generators. CRT Interface LPSTB (Lightpen Strobe): LPSTB is the lightpen input. 2CLK (Dot Clock): 2CLK is the basic ACRTC operating clock, twice the frequency 4, of the dot clock. Block Diagrams ACRTC Functions MAD,-MAD,, (Frame Memory Address/ Data Bus): MAD,-MAD,;, are the multi' © The ACRTC consists of 5 major functional plexed frame buffer address/data bus. blocks (figure 1). They operate in parallel to __ __ achieve maximum performance. AS (Address Strobe): The AS output de- multiplexes the address/data bus (MAD, MPU Interface: The MPU interface inter- MAD,,). faces asynchronously with the host MPU. Its functions include programmable interrupts MA,,/RA,-MA,,/RA, (Memory Address/ handling, and DMA handshaking control. Raster Address): MA,,/RA,-MA,./RA; are the upper bits of the graphics screen ad- CRT Interface: The CRT interface manages dress multiplexed with the lower bits of the the frame buffer bus and the CRT timing in- character screen raster address put and output control signals. It also se- lects display refresh or drawing address out- RA, (Raster Address): RA, is the high bit puts. @ HITACHI 216 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300

———S— HD63484 Drawing Processor: The drawing proces- CAT Resatuton sor interprets commands and command par- f@0t clock} ‘ ameters issued by the host bus (MPU and/or 1280. 1024 Pphgs eee DMAC) and performs drawing operations on nouns) fl Rp | | the frame buffer memory. It executes yor H QP ACRTC drawing algorithms and converts [| QT 2rrrmr | logical X-Y addresses to physical frame buf- eae | Uf, fer addresses. 00x «80 | GH} ay g ZY It communicates with the host bus via se- 640» 400 L “ parate 16-byte read and write FIFOs aera | } 10 «400 u Display Processor: The display processor “888 etry 400 manages frame buffer refresh addressing Sparton mode based on the user-specified display screen see ese Pkaerese ncrement mode organization. It combines and displays as {BA Semana many as 4 independent screen segments (3 horizontal split screens and 1 window) us- Figure A. ACRTC Operation Frequency ing an internal high-speed address calcula- and Supportable CRT Display Range tion unit. It controls display refresh outputs in graphic (physical frame buffer address) or High-Speed Drawing Support character (physical refresh memory address The ACRTC drawing speed depends on its + row address) modes. operation frequency, Consequently it takes less time to draw with a 9.8-MHz clock than with an Timing Processor: The timing processor 8-MHz clock. Figure B compares drawing capa- Generates the CRT synchronization signals bilities of the 9.8-MHz ACRTC and the 8-MHz and signals used internally by the ACRTC. CRTC Registers: The ACRTC registers that are visible to software are partitioned in the {a) Short vector drawing (50 dots/vector) same way. They reside in the internal pro- k vectors/sec.) cessor appropriate to their function. The re- 50) = | gisters in the display and timing processors 40 are loaded with the basic display parame- “ ters during system initialization. During op- i so eration, the host communicates primarily with the ACRTC's drawing processor via the f 20 | on-chip FIFOs. i | High-Speed (= 9.8 MHz) Version of ACRTC dl | To keep up with the demand for improve- oMHz Set | ments in the quality and resolution of CRT mon- Operation frequency itors, Hitachi has introduced a 9.8 MHz version (b) Block transfer of 1k x 1k dots of the HD63484 (ACRTC). (M dots/sec.) It can be used for 2 1. High-resolution displays such as in office 20 2 workstations, business personal computers, 17 and CADICAM displays L. i 2. Applications requiring faster drawing than o | the current ACRTC with an 8-MHz 2CLK op- 5 1 eration frequency. 5 ost High-Resolution Display As shown in figure A, the 9.8-MHz allows the bed] fee, | following configurations for a 4-bit/pixel system Operation frequency 1. CRT monitor with 1024 x 808 dots, + 8 DA or | Note: Figure B shows the ideal drawing speed where the +4SA ACRTC is assumed to pertorm only drawing. 2. cat moni from 800 x 480 to 960 = 720 Figure B. ing Ca ity Compart- . son between 9.8-MHz and 8-MHz ACRTCs. @HITACHI Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 217

a RES _ Ma Drawing ORE otel|eagin | Address cack —f4 egiser —Adses Be yn] wee, Foxe | Jeter: |) Data | Processor Ft we Ee) le Controif || [wats] ama Unit | Ls, MAD: —MAD Is | Display [Ie Mans RA— { Aderess [fo Mai /R Ay |_Ae RAY a) t Raster | orm port al Omviey featasene | CAT | | Processor [s Inte : i= cnr = ; cHR Dre | ] cud, | | Wilton mine j SYNC. ~VSYNE - _ H ° _— s LT ex Pips Vee Vs Figure 1 ACRTC Block Diagram System Configuration The ACRTC can use an external DMA con- troller. A DMA controller increases system Current CRT controllers provide a single bus throughput when many commands, parame- interface to the frame buffer that must be ters, and data must be transferred to the shared with the host MPU, However, re- ACRTC. Advanced DMAC features, such as freshing large frame buffers, and accessing the HD68450 “chaining” modes can be used the frame buffer for drawing operations can to develop powerful graphics system archi- quickly saturate the shared bus. tectures, As shown in figure 2, the ACRTC uses se- However, more cost-sensitive or less per- parate host MPU and frame buffer inter- formance-sensitive applications do not re- faces. This allows the ACRTC full access to quire a DMAC. The interface to the ACRTC the frame buffer for display refresh and can be handled under MPU software con- drawing operations and minimizes the trol. ACRTC's use of the MPU system bus. A re- lated benefit is that a large frame buffer (2 While both ACRTC bus interfaces (host Mbyte for each ACRTC) can be used, even if MPU and frame buffer) are 16 bits wide, the the host MPU has a smaller address space ACRTC also offers an 8-bit MPU mode for or segment size restriction. easy connection to popular 8-bit busses, @ HITACHI 218 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

———— HD63484 (] f) RES MAte—MAi9 meu Ft] y] | iaa (8/16b) [41 Frame Ky [Lees re putter [_ STACK’ | | Max, 2MB Kt HE |_| Mab sysem (4 EET as] : Memory =i [pvw } ACRTC DISPT,2 L a [g | [Come aoe | | ~ LPSTB

3 FY none | zernt || a y)

DMAC =I | 2CLK SYNC Video a leven RSYNC z2| Sanat Figure 2 System Configuration Programming Model Address Space The ACRTC allows the host to issue com- operations (for example, 4 bits), to 16-bit mands in logical X-Y coordinates. The word frame buffer addresses. ACRTC converts these physical linear word addresses with bit field offsets in the frame Registers buffer. Figure 3 shows the relationship be- tween the logical X-Y screen address and The ACRTC has over 200 bytes of accessible the frame buffer memory, which is organ- registers (figures 4, 5 and table 1). They are ized as sequential 16-bit words. The host organized as hardware access, direct access, may specify logical pixels of 1, 2, 4, 8, or 16 and FIFO access. physical bits in the frame buffer. The sys- tem in figure 3 uses 4-bit logical pixels, al- Hardware Access: The ACRTC is con- lowing 16 colors or tones to be selected. nected to the host MPU as a standard mem- ory-mapped peripheral that occupies two Up to four logical screens (upper, base, word locations of the host's address space. lower, and window) are mapped onto the The RS (register select) pin selects one of ACRTC physical address space. The host these two locations. When RS = 0 (low), specifies a logical screen physical start ad- read operations access the status register, dress, logical screen physical memory width and write operations access the address re- (memory words per raster), logical pixel gister. physical memory width (bit per pixel), and the logical origin physical address. Then the The status register summarizes the ACRTC ACRTC converts logical pixel X-Y addresses state. It monitors the overall state of the issued by the host MPU or the ACRTC ACRTC for the host MPU. drawing processor to physical frame buffer addresses. The ACRTC also performs bit ex- When the MPU wants to access a direct ac- traction and masking to map logical pixel cess register, it puts the register’s address @HITACHI Hitachi America, Ltd, * Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 219

Figure 3. Logical/Physical Addressing into the ACRTC address register. display period, and blink period. pausing commands, defining DMA proto- via the write FIFO to the command register. The operation mode register defines basic register. VSYNC, etc), logical display screen size and commands.

Figure 4. Programming Model

Figure 5. Hardware Access and Direct Access Registers

Horizontal Window Display (HWR) Register No.~r92 CS=0, RS—1, R/W=0/1 p. Figure 5. Hardware Access and Direct Access Registers (cont)

Table 1. Drawing Parameter Registers **: Set two’s complements for negative values of X and Y axis.

The ACRTC allows the frame buffer to be menus”. blanked under software control. ground screen, the window is displayed. grammable. A typical application might use screens are “superimposed” on the display. Table 2. Logical Screen

0 Upper screen Background screens

1 Base screen _

2 Low screen _ _ ee a

3 Window screen

Figure 6. Screen Combination Examples

frame memories, a 2-Mbyte frame buffer by the horizontal display register (HDR). output controls which memory is accessed. bigger than the display area (figure 7). Figure 7. Frame Memory and Display Screen Area

Figure 9. Display Screen Specification

1. First the MPU must specify drawing

Ten data transfer commands move data be- itilizing the area definition registers. frame buffer, or within the frame buffer. lor, edge definition, etc. All commands, parameters, and data are ter. initialized, the MPU must perform two buffer.

Table 3. ACRTC Command Table Command ALINE Absolute Line 3 PL+18 . RLINE Relative Line 3 PrL+18.

1. Applies to rectangular figures. Time varies for other shapes.

Table 4. Command Operation Codes and Parameters

1. Graphic drawing commands abbreviations

E: Edge color definition—E = 0, edge color is data in edge color register; E = 1, edge color is any color except data in color register ‘SL: Slant (figure 33) SD: Scan direction (igure 33) S: Source scan direction (figure 30) DSD: Destination scan direction (figure 31) 4. Parameter abbreviations X, Xt... Xm: Absolute X address trom origin point Y. Y1, ..., Yn: Absolute Y address from origin point dX: Reeiative X address from current pointer 4Y: Relative Y address from current pointer 1: Number of nodes X11, ..., dXn: Relative X address from each node Yt.) d¥n: Relative ¥ address from each node 1: Number of dots on radius a, b: ratio of dX squared to dY squared in ellipse—a'b = dX2:dY2 DX: X-direction dot number DY: Y-direction dot number Xc: Absolute X address of canter point of arc/oliipse Ye: Absolute Y address of center point of arc/ellipse ) dXc: Relative X address from current point to center point of arc/ellipse 2 dc: Relative Y address from current point to center point of arc/ellipse Xe: Absolute X address of end point of arciellipse Ye: Absolute Y address of end point of arc/ellipse Xe: Relative X address from current point to end point of arcfelipse dYe: Relative Y address trom current point to end point of arc/ellipse Xs: Absolute X address of start point of arc/ellipse Ys: Absolute Y address of start point of arc/ellipse dXs: Relative X address from current point to start point of arc/ellipse dYs: Relative Y address from current point to start point of arc/ellipse Program Transfer itially empty write FIFO, the MPU does not have to synchronize to write FIFO status. For program transfer, the MPU specifies The ACRTC can fetch and execute these the FIFO entry address and then writes commands faster than the MPU can issue commands/parameters to the write FIFO them. under program control (RS = high, R/W, CS = low). The MPU writes are normally syn- Command DMA Transfer chronized with FIFO status by software polling or interrupt. Commands and parameters can be trans- . . ferred from the MPU system memory by an Software Polling: WFR, WFE interrupts external DMAC. The MPU initiates and are disabled. terminates command DMA transfer under software control (CDM bit of CCR). Com- 1, MPU program checks the SR (status re- mand DMA transfer can also be terminated gister) for write FIFO ready flag (WFR) by asserting the ACRTC DONE signal. = 1, then writes 1 command/parameter DONE is an input in command DMA trans- word. fer mode. 2. MPU program checks the SR (status re- In command DMA transfer mode, the gister) for write FIFO empty flag (WFE) ACRTC issues cycle stealing DMA requests = 1, then writes 1 to 8 command/par- to the DMAC when the write FIFO is ameter words. ready. The DMA data is automatically sent . from system memory to the ACRTC write Interrupt Driven: WFR, WFE interrupts FIFO regardless of the contents of the ad- are enabled. dress register. 1. MPU WFR interrupt service routine Make sure that the write FIFO is empty writes 1 command/parameter word. and all previous commands are terminated . . . before starting the command DMA trans- 2. MPU WFE interrupt service routine fer. writes 1 to 8 command/parameter words. Data DMA transfer cannot be executed in Register Access Commands: When writ- command DMA transfer mode. ing register access commands to an in- @HITACHI Hitachi America, Ltd. * Hitachi Plaza « 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300 233

—<—— HD63484 Table 7, Graphic Drawing Commands Command Function AMOVE Move the current pointer (CP) to an absolute logical pixel X-Y address RMOVE Move the current pointer (CP) to a relative logical pixel X-Y address ALINE Draw a straight line from the current pointer (CP) to a command-specified end point in ab- solute coordinates RLINE Draw a straight line from the current pointer (CP) to a command-specified end point in relative corrdinates ARCT Draw a rectangle defined by the current pointer (CP) and a command-specified diagonal point in absolute coordinates ) RRCT Draw a rectangle defined by the current pointer (CP) and a command-specified diagonal point in relative coordinates APLL Draw a polyline (multiple contiguous segments) from the current pointer (CP) through command-specified points in absolute coordinates RPLL Draw a polyline (multiple contiguous segments) from the current pointer (CP) through command-specified points in relative coordinates APLG Draw a polygon which connects the current pointer (CP) and command-specified points in absolute coordinates RPLG Draw a polygon which connects the current pointer (CP) and command-specified points in relative coordinates RCL Draw a circle of radius R placing the current pointer (CP) at the center ELPS Draw a ellipse whose shape is specifed by command parameters, placing the current pointer (CP) at the center AARC Draw an arc by using the current pointer (CP) as a start point with an end point and a cen- ter point in absolute coordinates RARC Draw an arc by using the current pointer (CP} as a start point with an end point and a cen- ter point in relative coordinates AEARC Draw an ellipse arc by using the current pointer (CP) as a start point with an end point and a center point in absoiute coordinates REARC Draw an ellipse arc by using the current pointer (CP) as a start point with an end point and a center point in relative coordinates AFRCT Paint a rectangular area specifed by the current pointer (CP) and command parameters (absolute coordinates) according to a figure pattern stored in the pattern RAM (tiling) RFRCT Paint a rectangular area specifed by the current point (CP) and command parameters (rel- ative coordinates) according to a figure pattern stored in the pattern RAM (tiling) PAINT Paint a closed area surrounded by edge color using a figure pattern stored in the pattern RAM (tiling) DOT Mark a dot on the coordinates indicated by the current pointer (CP) PTN Draw a graphic pattern defined in the pattern RAM onto a rectangular area specifed by the current point (CP) and by the pattern size (rotation angle: 45°) AGCPY Copy a rectangular area specifed by the absolute coordinates to the address specifed by the current pointer (CP) (rotation angle: 90°/mirror reflection} RGCPY Copy a rectangular area specified by the relative coordinates to the address specified by the current pointer (CP) (rotation angie: 90°/mirror reflection} @HITACHI Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy, # Brisbane. CA 94005-1819 « (415) 589-8300 235

a SSeSSSSSSSSSSSSSSSSSSSsSSsSSSSSSSSSSSSSSSSSSSSSSSSSSS Absolute Maximum Ratings item Symbol Rating Unit —$ OE Supply Voltage Vee (Note 1) —0.3 to +7.0 Vv Input Voltage V,, (Note 1) 0.3 to Veg +03 V Allowable Output Current Ilgl (Note 2) 5 mA Total Allowable Output Current Ql (Note 3) 120 mA Operating Temperature Toor Oto +70 *c Storage Temperature Tato —55 to +150 Cc OO Notes: 1. Referenced to Vs — 0 V. 2. The maximum current that may be drawn from, or flow out of, one output, or one common in- put/output terminal. 3. The total sum of currents that may be drawn from, or flow out of, all output or common input/ output terminals. 4. Using an LSI beyond its maximum rating may result in its permanent destruction LSls should usually be used under recommended operating conditions. Exceeding any of these conditions may adversely affect reliability SSS Recommended Operating Conditions item Symbol Min Typ Max Unit =| — OOOO Supply Voltage Vee (Note) 4.75 5.0 5.25 Vv Input Low Voltage Vj, (Note) 0) 07 Vv me ON Input High Voltage (4, 6, 8 MHz versions) Vix (Note) 22 Vee v (9.8 MHz version) Viw (Note) 24 Vee v Operating Temperature Toor 0 2 75 °c Note: Referenced to Vs, = OV @HITACHI 238 Hitachi America. Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy ¢ Rrishane (A Q4NNK.1810 « (415) 520.2200

Electrical Characteristics

(Voc=5.0V + 5%, Vss=0V, Ta=0°C to +70°C unless otherwise noted) Test Item Symbol Min Max Unit Condition sem ee OO Input High Level All inputs Vow 22° Vee OV 4, 6, 8 MHz Voltage versions 24° Vee OV 9.8MHz * version Input Low Level All inputs Vi -03 07 V ? Voltage Input Leak Current RW, CS, RS, RES, DACK, |, -25 25 pA V,=0.4 to Veg 2CLK, LPSTB Hi-Z Input Current Dy-D,g, MAD,-MAD,., hsi -10 10 pA V0.4 to Vee EXSYNC Output High Level Dy-D,s, MAD,-MAD,., Vow Vee BA Igy 400A Voltage CUD1, CUD2, DREQ, -1.0 DTACK, HSYNC, VSYNC, EXSYNC, MRD, DRAW, AS, DISP1, DISP2, CHR, MCYC, RA, MA,./RA,- MA, 9/RA, Output Low Level Dy-Dys, MAD,-MAD,«, Vou 05 Vv lop=2.2mA Voltage CUD1, CUD2, DREQ, _ DTACK, HSYNC, VSYNC, EXSYNC, MRD, DRAW, AS, DISP1, DISP2, CHR, MCYC, RA,, MAy/RAg MA,,/RA, iRO, DONE vo, 05 Vv lo t2.5 mA Output Leak IRO, DONE hop 10 pA Vouw™Vec Current (Hi-Z) Input Capacitance Dy-Djs, MADg-MAD,., EX- C,, 17° pF Vm OV, SYNC, R/W, CS, RS, RES, Ta=25°C, DACK, 2CLK, LPSTB f=1.0 MHz Output Capacitance TRO, DONE Cou 15 pF OV, = OV, Ta-25°C, f=1.0 MHz Current Consumption lee 60 mA 4MHzversion 80 mA 6MHz version 100 mA 8MHz version 120. mA 9.8 MHz version Ee @HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 239

AC Characteristics (V.~=5.0V + 5%, Vss=0V, Ta=0 to +70°C unless otherwise noted) Clock Timing 4 MHz 6 MHz 8 MHz 9.8 MHz Reference Symbol} Version Version Version Version Unit | Figure [Min [Max [Min [Mex [Win [Max [Min [ Max_| Nomber | [eoeatenFoweor oraax | + [1 «| +] 6] +] e] 1] 88 [me] [7 [evck Cie Taw | tye | 280 | 1000_| 167 ['660_| 35 |i60 1 vex [7006 | vw] |? | Clock High Level Pulse tPWCH 500 | 75 ry el] | 500 i" | ” Width _ . Clock Low Level Pulse {PWCL [5 | 500 | 75 [so | [8 | 500 | Width SA [Ls [cock renting et [=e = oT oe Te MPU Read/Write Cycle Timing symbol |__ Version Version Version Version | Unit | Figue | Min [mex] Min [Max [Min [Mex | Min] Mex | Number [s [RWmp tie ws | re = | eof - [sol - | *|-[m] [2 [RAW Hots Tine | aw [Co [=o Tot = Poly | [8 [Rs seup time | wes [70 [= Jeo [Tso = [T= | 18-20 A [io [eS Seutm tess | oo | = [ao - | ol) ot | | La GN [13 [Reowor time [wai | oT To [oT eT -T | [14 [Reosntsacons Tene [wane | — [go | — (ioe [= feo | wp] | 15 [Reed Date Hold Time ee [16 [Reed Dete Tum off time T ewoz | — [60 | [eo [= [60 ) [a0 ve | [37 [OTEK ones Tine Bio [ona] =| go — eof = [ao | ee | [18 [OTAEK Dey Tine Drow [wrx | o [=o [To [= [oe = fe [820 fe iorsmmemene ome Tee = [wl | ls Pole [20 STACK Tun GH Teme roa; wre | | 100 | - | yoo) - 1 100] 100] me | i al a Time 4 [22 [wie wertine wwwai[ 0 [oe Te =e = Ta] [23 [Wete Dow Sup Tine [wos [a0 [= [60 | oT Tl - [a | [24 [wie Osteo Tere [won [to Pe ee = Te @HITACHI 240 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 © (415) 589-8300

DMA Read/Write Cycle Timing 7. JSS See ‘Symbol Version Version Version Version Unit Win [Max | Min [ Wo | Min | Max | win [Max | [28 | BREG Delay Time + «ROD [150 [= [so | [to [=f to Ts 26 | ORE Dewy Tre | oraoa | — | 90 | — | eo | = [7% | - | 90 | ms | OMA RAW Soup Tne [roms | 7o | — | eo | - Tso [= | so] = | | 26 [DWARWHod Tine own) of = | of | of = | o] = [rs] 28 [BACK Soup Tne | was | 50) = [ao [| ap = | [fs | 32 [OMAReadWatTime | Rw | o | - [oo] = | of = 7 of] - [me | 33_| DMA Read Data Access Time [= [100 [= [eo | = | 80 | ns | | [ 34 | DMA Read Data Hold Time reerp= fey pet ep eye 22 Time | Pico fet et ee ee Zou | Btol) it 38 | OMA DTACK Release Time | 1D0TLH - | 90 - | 8 epee yet ete [etn montne [one |S [ees Dey Pets ey ae H to Z) \\ [ 20 | BONE Output Dey Tne | wono_| - | 90 | - | so | - | 70) - [ 70] oe | 41 | DONE Output Turn Off Time tONLZ - 90 - | 80 isi ld | Time 2 48 [Cont iw Pike wea onpw [ee [4 [OA Wee Wor teme [www [oT Fo | = | oo = To = Tm | ng [45 [DA WeteDstaSeup Tne [owns | 80 | — | eo) — | a] — [ap [mw | [46 [OMA Wee Ouinvo tine Twwow | vo [ =) wo] = | wo, | ol [| feTo @ HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300. 241

Frame Memory Read/Write Cycle Timing 4.MHz 6 MHz 8 MHz 9.8 MHz Reference tem ‘Symbol Version Version | Version Version Figure | 48 [AS “Low” Level Pulse With | PWASL | 80 = = [= [ns | [#2 | enon Aas tu Tre | wav | = [es T= Te] EE [$2 [Menon Asa Oy te [wma [16 es | ie | wo | ie | vo] 0] wp ww | [#8 [Meron Assess Ho Tne 1 want [as [= [ae ast fe P| } Time (A to Z) Time | [35 [Monon Red Daa Tne [wR |W) — P= et = t= | MAVRA Delay Time tmarad | - | 100 | = | 90 | | = [ | ns | 25-28 [58 | MATRA Hold Time wana | 10 | — | 10) = |] - [| 8 [=] ms | 28-27 [se [weve demytiw weve [seo] s tet sf sos | we fm | ane] [<0 [WRD Dy Tine wo |= [80 |= eo P= ot = | | | [si [novos Te eam oT ef ee 64 | Memory Write Data Delay | 1MWDD so} - | eo) — 7o | — Pate] Time ‘ | 85 | Memory Wite Oata How Tme | WWDH) 10| - | 10] - | 0) - | s|- tm] ” | Memory Address Setup wast | 10 | — wo] = wo | — 7] 40 [-["] Time 4 | | | Pere TPE Time 2 | 2. New characteristics No.50 and No.62 shown above are applicable only to lot numbers 5M", 6*, 7°*, and greater (* means don't care) For the other lot numbers, applicable characteristics are as follows: |e | sim Pewme veer [ene en [en U ee | so | sor | - [ao f - [| - fos [es | Lez | wao [ — Tos |= [eo | = fo Ts | @ HITACHI 242 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

Display Control Signal Output Timing 4 MHz 6 MHz 8 MHz 9.8 MHz Reference ‘Symbol Version Version Version Version Figure [Mn [Mex | Min [Mex [Min [Mex | win | Max | Number ME Geey Time | ws | — [a0 [ - | eo | - | 70 | - | | ns | 26-20 | [68 |VEVNC Dewy time ‘(| _wso | — [ 90 | - [eo | — | 70 7 - | 6 | re | [68 [OSPY, OFZ Dey Tme | wsro [= [90 | - {eo [| 70 [- | s | ne | [70 [CUDT. CUBZ Dewy Tme | cud | - | 90 [| — [eo = | vo = | so [ne | [7 [ERSTE OvostOewy Tree [xo | 20 | oo] a] a) | | | #[m| [72 [CHA Delay Te | ecw | = | 90 | = Teo [= | 70 | = [8 | ns | fof 2, Pep EXSYNC Input Timing — SS Sel Version Version Version Version Figure [Max | Min [Max | win [Max | “Min [Max | Number SYNC pet Puise waatn | exsw | a | — | [= [3 | | s - T eve | [re [emCron seu tee [wes | 6 [- ef - sl- | »[- |] [ii fexswne neato tw [ewe eT se P= eT Te | LPSTB Input Timing 4 MHz 6 MHz 8 MHz 9.8 MHz Reference ‘Symbol Version Version Version Version| Unit | Figure | [Min] Mox |Win [Mex | Min | Mex | Min [ Max | Number [78 |tPste Unceran tomer | wror | 70 | - | 70 | = [vo | - | a | - | [72_[tPste new Te? wro2 | w=) | - | wt - | | | [eo [irsTainput Hod time | wen | 0 | — | yo | = | to | ~ | io [= [ns | [er [wsternmmnine [an Te) = |e] - |) «[- 1] +[— [or] RES and DACK Input Timing 4 MHz 6 MHz 8 MHz 9.8 MHz Reference hem Symeo! Version Version Version Version Unit] Figure BACK Setup Tine tor FES | waxsR | 100 | pet = fot | 83 [DACK Hold Tne for RES | wDakHR | 0 | jo | | = |i | 33 | [ee [resi rave wan [wes [ol wo) - [wf - |) - [wey @HITACHI Hitachi America, Ltd, « Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 243

Figure 17. 2CLK Waveform

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Note that in 9.8 MHz version, Vy is 2.4 V. Figure 25. Display Cycle Timing

Note that in 9.8 MHz version, Vin is 2.4V. Figure 26. Frame Memory Read Cycle Timing (ACRTC ~ Frame Memory)

—_—SSY— HD63484 eee 2cLK 0.7V ® 0.7V 0.7V. wB \\ Vec-2.0V “s bw | oay cz) ns MAD,—MAD,, ofvee 2 OV. Bhp vee2.0V, Vce-2.0V opy Address Ctoay ata | Day @ cal MA,,/RA, : MA,5/RA) RA, @ 2 H mcyc oev 60) 6) @ ® Note: Vi (input high voltage minimum value) is 2.2 V in 4-, 6-, 8-MHz version Note that in 9.8 MHz version, Vix is 2.4 Figure 27, Frame Memory Write Cycle Timing (ACRTC ~ Frame Memory) © HITACHI 254 Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300

Figure 28. Frame Memory Refresh/Video Attributes Output Cycle Timing

Figure 29. Display Control Signal Output Timing