HD6321

HD6321 HITACHI

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Technical content

PIA (Peripheral Interface Adapter) The HD6321/HD6821 Peripheral Interface Adapter provides the universal means of interfacing peripheral equipment to the HD6321P, HD6821P HD6800 Microprocessing Unit (MPU). This device is capable of interfacing the MPU to peripherals through two 8-bit bi- directional peripheral data buses and four control lines. No external logic is required for interfacing to most peripheral devices. The functional configuration of the PIA is programmed by the MPU during system initialization, Each of the peripheral data lines can be programmed to act as an input or output, and each of the four control/interrupt lines may be programmed for one of several control modes. This allows a high degree of flexibility in the over-all operation of the interface (OP-40)

FEATURES

© Two Bi-directional 8-bit Peripheral Data Bus for interface to HD6321FP Peripheral devices © Two programmable control, Data Direction Registers © Four Individually Controlled Interrupt Input Lines: Two Usable as Peripheral Contro! Outputs © Handshake Control Logic for Input and Output Peripheral Operation al CA,, CA; . Port A(PAy ~ PAy) p © High-Impedance 3-State and Direct Transistor Drive Periphe- ral Lines ‘© Two TTL Drive Capability on All A and B Side Buffers —H06321- © Low-Power, High-Speed, High-Density CMOS (FP-54) © Wide Range Operating Voltage (Vcc = 5V + 10%) © Compatible with NMOS PIA (HD6821) (Refer to Electrical The specifications of the HD6321 are for preliminary and may Specification as to Minor difference) change hereafter. Please make an inquire at sales office upon adoption of the HD6321. —HD6821— © Compatible with MC6821, MC68A21 and MC68B21 @ TYPE OF PRODUCTS Type No Padkage HD6321P 1.0 MHz HD63A21P 1.5 MHz DP-40 HD63821P_| Cugg 2.0MHz HD6321FP 4.0 MHz HO63A21FP 1.5 MHz FP.54 HD63821FP 2.0 MHz HD6821P 1.0MHz | HD68A21P 1.5 MHz DP-40 HD68B21P_| og 2.0 MHz HD6821 1.0 MHz HD68A21 1.5 MHz DC-40 HD68B21 2.0 MHz @HITACHI 660 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

i EEE = ABSOLUTE MAXIMUM RATINGS Supply Voltage 0.3 ~ 47.0 0.3~ 47.0 v Input Voltage -0.3~+7.0 -0.3~ +7.0 Vv Maximum Output Current [To ftom Maximum Total Output Current | IEloit** [too | Tm Operating Temperature °c * With respect to Vgs (SYSTEM GND) Maximum output current is the maximum current which can flow in or flow out from one output terminal and 1/0 common terminal, (PAg~PA>, CA;, PBg ~PB7, CBz, D9~D4) ‘¢ Maximum total output current is the tote! sum of output current which can flow in or flow out simultaneously from output ‘tarmingis and 1/0 common terminals, {PAg~PA7, CA2, PBg~PB7, CBz, Op~ D>) (NOTE) Permanent LS! damage may occur if maximum ratings are exceeded. Normal operstion should be under recommended: operating conditions. If these conditions are exceeded, it could affect reliability of Lusi. = RECOMMENDED OPERATING CONDITIONS ven [sma [og HERE [a om [-min. [typ | max. [min] typ Tmax. | Supply Voltage [vee* | 45 [50 | 55 | 475 [ 50 | 525 | v Input “Low” Voltage [vir | o [= Tos [-o3 [ = Tos [ov D~Dz, PAg~ PA,, CA;, CA; Input “High” | pp” pp, 2 | Vee voltage ce, ce. | AME ViH* - + Vee v TS; , CS, ,RSo, | Vee RS, , RES ‘+ With respect to Vs (SYSTEM GND) ** Characteristics will be improved. @ HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 661 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

= PIN ARRANGEMENT © HD6321P, HDG821P © HD6321FP sccea 788 vaio aca, iiie gaeee PAo{2] fag} CAz REIS pata] fis}iRGA f-FF1, EISELE] pa[4] (37) ROB <Ne> (af ba <ne> Pas(5] [36] RSo <NC> (FJ fea <Nc> PAL | [35] RS: <NC> [8] Ie) <NC> PAs(Z) (34) RES PA. [3] ae PA, (To) : PALE] [33] Do pal Ee res Pata] [32}D: ra he PBo[10] [31)Dz Pe, ( kao, PB [30] Ds Pe, fia] fey 2 PBs (73) (28] Ds PB, [16] 39D. pa.{i4] [27) De re ba a o Pes (78) [26] D> <nc> fia] [30 0; PBs (16) {25} <Nc> fal 35] <NC> PB/(17) 24}Css <Nc> fi] (34 <nc> cB2{19] Pea\\cso Vee (20) [21)R/w EERE EEE er ae 0 eur sidd$ Edbdu (Top View) (Top View) (OP-40, DC-40) (FP-54) @ HITACHI 662 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

™@ BLOCK DIAGRAM Tontrol Control A CA2 ter A o PL =the oO. Date Direction ° Toei

03 Oate Bus md {DORA}

Oo (088) ee Re Os PAo o, at ptt PA, PA? {| PA; PAs PAs PAs PA, Vee PBo Ves Output 8 CSo ( ) Peripheral 8; cS: Interface Pe CS] soe ° re RSo and id) RS, aw °e, aw € Control 2 wes Data Direction Ce od ener 8 ORS) “tee [|] _(00ne . Interrupt Stetus ce. ne Control 8 CB, @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 663 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

= ELECTRICAL CHARACTERISTICS : © DC CHARACTERISTICS (HD6321; Vec = 5V +10%, HD6821; Vec = BV #5%, Vas = OV, Ta = -20 ~+78°C, unless otherwise noted.) tem Symbot HD6321 Unit [econ | wn [oa [max [Tow conaton| mn [oot [a] Dp~D>, PAg~PAy, i CA CA, PBo~PBy, | Input “High” Vor Sus v | v inpur “High” Volioge Te IW, Co, CS m4 CS1, RS, RSy, RES. Inout "vow" votwge | ailinpus | vu | fos |= fos} |-o3 | - [oalv RW, RES, RSo, RSs, Input Leakage Current | C89. C54, 05>, CA, Vin “0 ~Vee Vin=0~Vee | 25 aA CBy,& Input Currant Do~O7,PBe~PB, cay] ITS! | Vin"O47Vec| “20 | = || Voroe2a\\SeT70| “* DD; CE ee [ton <~1A [Vee-ox] = [=] igh’ Ve PAg~PAs, CA, ton =—4oowa | ar | - [= | ea Ourpur “Hien” Votage | pp, ~PB>, CBr VoH [ign <-t04a |Vvec-o1] - | — | v : PAg~PAr, CA: i Lion = 200.0 [2arr* [=| | lon =~ 104A [Vee “0.1 — J} P89 ~ PBs, CBr lon = 200.8 | 2.4] T=) iRGA, TRO ton=6ma [ - [- [ osfion= tema | — [Toa] Cutout “Low Value | Pao PAs, Cay vou fioceaama iou=t6ma | - | - 0a] v Do ~ [vou=24v | -208 [— 7 - [na Output “High” Current | PAQ~PAr, CAz Vou =24v""[ -200 |} — [ua PBo~PBr, CB [vou=1sv | -1.0 | = [-0/ ma Output Leakage Current vem Lee faahecey [pte Input Capacitance at acd = = Cin | Tas 25°C Te = 25°C pF RAV RES Boo BS (tombe 1 homme “Ty BLE ' Vin = OV Vin = ov Output Capacitance iROA, ROB Cour | Ta= 26°C Te 25°C - 10) pF _. f= 1,0MHz f= 1.0MHz #PiAp ~PAz, CAr, PBo~ PB, CB; are specified E = 1,0MHz as input, ‘elnput level rt eee VIM min * Vee ~ 0.8V | &- 20MHe Supply Current Vit max = 0.8V an wee an PBo~PB7,CB2 are £ = 1.0MH2 tec put = LEMie [=e] ma Under Date Bus RW oownion ae . Ta = 25°C, Veg = 5.0V * HD68B21; Voy =2.2V min [PAg~PAr, CA; ** Supply current is defined on the condition that there is no current flow from output terminals. Supply current will be increased when the ‘current from output termine! exists. Also the current will be increased for charging and discharging the capacitive load, Please take this cate into consideration in estimating system power. @ HITACHI 664 Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

© AC CHARACTERISTICS (HD6321; Vec = SV + 10%, HD6821; Ve = SV + 5%, V5g = OV, Ta = ~20 ~ +75°C unless otherwise noted) 1, PERIPHERAL TIMING [rin _]max [min Tmax [min [max [ein [max [rnin [mex [min [max | Perohara Dee Setup Tine fwosu| Fin [100 | - [roo] - [roo] = [ao [— [rae | - [roo | - [rw Peripheral ta Hold Time leon | ews | of- [of - | of- J] of- 7 of- | of- [nm SERFS forme [te [ares |- [me] [ae] [ae] ~ foe] - [| |e Transition to CA; negative | Eneble-+CA; Negative | toar nm comin SESE [omen rn [oem | ree [fm] = fae] = fee feel - [oe |= fo Cantante Ear ponte” | Enable, Poste . Heated sosetacunit[emwen |ow | ree | [om] - [ow - [ro] - fe] - fo - on» ‘active transition to CA2 CA, + CA, trsz Fig. 3 i penis wanton Delay Time, Enable negative a oe oe Se See Delay Time, Enable negative | Enable -+ Peripheral Vee~30% ¥, ll eo eee ol EERE Jomencs [ose [mere - [mm] - [me] [l= feel - [ml [a ‘transition to CB, negative | Enable + CB, o position BESET |wmeomon foe | ree [=| -[ | -[={ |=] |=) fel Valid to CB, negative: Peripheral Data + CB; " tons Bee omnes | | vee |= [ef fom] = [feel le lo transition to CB, positive a iotee pave” ou cox [mer | renewe |e] - [a - [| = [no | = [oo | - [a - | Pulse Width, CA,/CB, Ly sracesrmr = fowom fen] ey [= fond [om [ml ~~ fol - fm gemstone [oe ee | fl fel fel el feel ‘transition t0 CB, positive | CB; -» CB, Ld tanaon ingrupt Reis Tine, | coe ecmaimae = [momo | om | rme | - [om] - [| ~ [oe] - [re] ~ fv] - [vo] = ImarvetRewonse Tine [ROR IROH | tngy | fia. | - [oo] — [oo] ~ [col — [reco] — [rooo] — [reno] re imerapt our Putm win [Ar Ch-601.60 | rw | Fe8 eeu] — leven] — [eran] — [sor] - ford - fore] — fw eowt “Low Tine [res Te [reo [200] = J 200 [= J 200 | Prove] = [ooo | = [soo] = | w ‘* The Reset line must be “High” # minimum of 1 Os before addressing the PIA. '** Atleast one Enable “High” pulse should be included in this period. @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300 665 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

a HD6321/HD6821 2. BUS TIMING 1) READ trae oven Tre ipet_]Fa[row | 866 | — Yoon] foo] — foes | — [emt Po Enable Pulse Width, “High” [Pwenn | Fin 11 | 480] - [reo] - [220 | - [aso | - [200 [- [xo] — | rm Enable Puls Width, “Low” [ewer | tess | 490| - [200] - [210 | - [aso] - [200 | - [20] - | insti im Rin Fates Jantge | Pan | -[ @- 1] - [| -] =) -[ =] - pe sarup time [aceron,rimicnaoe [tas | fis? | 90! - | eo - [40 | = [rao] - [v4 | - | 70[ - | paren oT Ian | re | vo] -[w]-)]-] wo] -]@]-] wf - 1 ODay Tre Moon [ret | tot two - [reo] — [om [- [ao] — frm be bet Hod Te foun | ta12 | [roo] zo [roo m9 [reo] | - | w[-] | - [mw 2) * WRITE -_- SSS SS coon fect [re [oom | — [owe] — [en | = = Emi Pa otha [mie [re | oo] - [amo] - [no [oo] - [om] [ao - [x Setup Time fins | Fiera | 90) -| 60] - | 40 | -[ sao] - [a0] - | 0] - | m necro Hone [Aion AEnligs [ew ot Po | wo} el] of pol Data Setup Time lrosw | Fata | wes! - | oo) - | oof -| ves] - | oo | - [oo | - [om Data Hold Time fronw | fiers] ro) -[ vo] - | 0] -{ wf -[ of - [of - | @ HITACHI 666 Hitachi America, Ltd. ¢ Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

@ PIA INTERFACE SIGNALS FOR MPU Input Pin No. 22, 24, 23 (DP-40) The PIA interfaces to the HD6800 MPU with an eight-bit Pin No, 29, 31, 30 (FP.54) bi-directional data bus, three chip select lines, two register select lines, two interrupt request lines, read/write line, enable line and reset line. These signals, in conjunction with the HD6800 These three input signals are used to select the PIA, CSo and MA output, permit the MPU to have complete control over CS, must be “High” and CS, must be “Low” for selection of the PIA. VMA should be utilized in conjunction with an MPU the device. Data transfers are then performed under the control address line into a chip select of the PIA. of the E and R/W signals. The chip select lines must be stable © Bi-Directional Data (Dp ~D7) for the duration of the E pulse. The device is deselected when any of the chip selects are in the inactive state. Input Pin No. 33 ~ 26 (DP-40) © Register Select (RSo snd RS,) Pin No. 43 ~ 36 (FP-54) Input Pin No. 36, 35 (DP-40) The bi-directional data lines (Dp ~ D;) allow the transfer of Pin No. 50, 45 (FP-54) data between the MPU and the PIA. The data bus output drivers are three-state devices that remain in the high-impedance (off) The two register select lines are used to select the various state except when the MPU performs a PIA read operation. The registers inside the PIA. These two lines are used in conjunction R/W line is in the Read (“High”) state when the PIA is selected with internal Control Registers to select a particular register that for a Read operation. is to be written or read. © Enable (E) The register and chip select lines should be stable for the duration of the E pulse while in the read or write cycle. Input/Output Pin No. 25 (DP-40) + Interrupt Request (TRA and TRGB) Pin No, 32 (FP-54) Input Pin No. 38, 37 (DP-40) The enable pulse, E, is the only timing signal that is supplied to the PIA. Timing of all other signals is referenced to the leading and trailing edges of the E pulse. This signal will The active “Low” Interrupt Request lines (IRQA and IRQB) normally be a derivative of the HMCS6800 System ¢, Clock. act to interrupt the MPU either directly or through interrupt This signal must be continuous clock pulse. priority circuitry. These lines are “open drain” (no load device © Read/Write (R/W) on the chip). This permits all interrupt request lines to be tied together in a wire-OR configuration. Each IRQ line has two internal interrupt flag bits that can Input Pin No. 21 (DP-40) cause the IRQ line to go “Low ”. Each flag bit is associated with Pin No. 28 (FP-54) a particular peripheral interrupt line. Also four interrupt enable bits are provided in the PIA which may be used to inhibit This signal is generated by the MPU to control the direction _ particular interrupt from a peripheral device. of data transfers on the Data Bus. A “Low” state on the PIA Servicing an interrupt by the MPU may be accomplished by a line enables the input buffers and data is transferred from the software routine that, on a prioritized basis, sequentially reads MPU to the PIA on the E signal if the device has been selected. and tests the two control registers in each PIA for interrupt flag A “High” on the R/W line sets up the PIA for a transfer of data bits that are set. , to the bus. The PIA output buffers are enabled when the proper The interrupt flags are cleared (zeroed) as a result of an MPU address and the enable pulse E are present. Read Peripheral Data Operation of the corresponding data © Reset (RES) register. After being cleared, the interrupt flag bit cannot be enabled to be set until the PIA is deselected during an E pulse. The E pulse is used to condition the interrupt control lines Input FN eee, (CAx, CA, CB,, CB). When these lines are used as interrupt Pin No. 44 (FP.54) inputs at least one E pulse must occur from the inactive edge to _ the active edge of the interrupt input signal to condition the The active “Low” RES line is used to reset all register bits in edge sense network. If the interrupt flag has been enabled and the PIA to a logical zero “Low”. This line can be used as a the edge sense circuit has been properly conditioned, the power-on reset and as a master reset during system operation. interrupt flag will be set on the next actjve transition of the © Chip Select (CS, CS, and TS;) interrupt input pin. @ HITACHI Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 669 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

i =a 632 17IDCB2A © Port A Peripheral Data (PAy~PA7) © Peripheral Control (CA3) Input/Output Pin No. 2~ 9 (DP-40) Input/Output Pin No. 39 (DP-40) Pp Pl Pin No. 2~ 5,9~ 12 (FP-54) Pin No. 53 (FP-54) Each of the peripheral data lines can be programmed to act The peripheral control line CA can be programmed to act as an input or output. This is accomplished by setting a “1” in as an interrupt input or as a peripheral control output. the corresponding Data Direction Register bit for those lines The function of this signal is programmed by the Control which are to be outputs. A “0” in a bit of the Data Direction Register A. When used as an input, this signal is in High-im- Register causes the corresponding peripheral data line to act as pedance state. an input. During an MPU Read Peripheral Data Operation, the data on peripheral lines programmed to act as inputs appears @ ‘Peripheral Control (CB, ) directly on the corresponding MPU Data Bus lines. The data in Output Register A will appear on the peripheral data lines that are programmed to be outputs. A logical “1” Input/Output Be No. % Gras written into the register will cause a “High” on the correspond- in No. : ing peripheral data line while a “0” results in a “Low”. Data in Output Register A may be read by an MPU “Read Peripheral The peripheral Control line CB; may also be programmed to Data A” operation when the corresponding lines are programm- act as an interrupt input or peripheral control output. ed as outputs. This line is programmed by Control Register B. But conceming HD6821, this data will be read properly if When used as an input, this signal is in High-impedance. the voltage on the peripheral data lines is greater than 2.0 volts for a logic “1” output and less than 0.8 volt for a logic “O” output. Loading the output lines such that the voltage on these lines does not reach full voltage causes the data transferred into the MPU on a Read operation to differ from that contained NOTE? !. r ow Ml be greater tan ey spirit eed ad in the respective bit of Output Register A. that “High” time of E signal is not contained in © Port B Peripheral Data (PBy~ PB) Interrupt pulse, an interrupt flag may not be set. a seen Cs cen ee ce Coe Input/Output Pin No. 10 ~ 17 (DP-40) : Pin No. 13 ~ 18, 23 ~ 24 (FP-54) trigraet ou t+— va ten a Gye Time Each of the Port B peripheral data bus can be programmed to act as an input or output like PA) ~ PA;. PBy ~ PB, are in High-impedance condition because they . are three-state outputs just like PA) ~ PBy when the peripheral ‘Electrical Characteristics buses are used as inputs, when programmed as outputs, MPU _—(1) DC Characteristics read of Port B make it possible to read the output register tem Sym- | old mask | Rmask | yg regardless of PBy ~ PB, loads and concerning HD6821, these ol [imin. [ max. | min. [max | line may be used as a source of up to 2.5 milliampare (typ.) DoD7, PApPAy at 1.5 volt to directly drive the base of transistor switch. Input PBoPBy, Ay, CAa, Vee ’ “High” | CBs, CB; Vin, Ve v © Interrupt input (CA; and CB,) volege LEO. e508), ' j30 | “ {TS2, RSo, Sy, RES| had Input Has ie % 8 pss, (2) AC Characteristics (Only for HD63B21: in No. 54, - | oid mask | Amesk | ‘The peripheral Input lines CA, , and CB, are input only lines 7 that set the interrupt flags of the control registers. The active ae ming meno) ns transition for these signals is also programmed by the two con- pew canto) ress, trol registers. ~ rouge Bus Timing (WRITE) Setup time (Address, ns RW-Enable) @HITACH! Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300 671 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

—eeeeeSSSSSSSSSSSSSSSsFSsSSmh HD6321/HD6821 SSS “Old” maskversion _Lotthumner corresponding peripheral data line as an input; a “1” results in an output. © Control Registers (CRA and CRB) eoo0 eanD The two Control Registers (CRA and CRB) allow the MPU to control the operation of the four peripheral control lines CA;, HO6321FP CA,, CB, and CB,. In addition they allow the MPU to enable JAPAN JAPAN the interrupt lines and monitor the status of the interrupt flags. pa ro Bits 0 through 5 of the two registers may be written or read by the MPU when the proper chip select and register select signals RY mask version — «pe are applied. Bits 6 and 7 of the two registers are read only and W* 10 added are modified by external interrupts occurring on control lines CA,, CAz, CB, or CB;, The format of the control words is sonar saan shown in Table 2. H06321P Hogs21FP Table 2 Control Word Format =APAN JAPAN [>| ¢ [Ts [«]s [2 [To] ® INTERNAL CONTROLS There are six locations within the PLA accessible to the MPU p> fis fs fe Ts 72 Ti To) data bus: two Peripheral Registers, two Data Direction Re- CRE ['noe [tRaez] cbs convot] Rone | EBs convo | gisters, and two Control Registers. Selection of these locations is controlled by the RSo and RS, inputs together with bit 2 in the Control Register, as shown in Table 1. Date Direction Access Control Bit (CRAZ and CRB2) Bit 2 in each Control register (CRA and CRB) allows Table 1 Intemal Addressing selection of either a Peripheral Interface Register or the Data Direction Register when the proper register select signals are | applied to RSp and RS,. rs, | as, Gra? Tone? Location Selected {Interrupt Flags (CRAG, CRA7, CRBS, end CRB7) 1 = The four interrupt fag bits are set by active transitions of oO o | a x Peripheral Regeuter A Of ets | Peripher Register AY signals on the four Interrupt and Peripheral Control lines when —2 2 | 0 | = __|__ Onis Dection Rept A those lines are programmed to be inpuls, These bits cannot be 0 1 x _| x | Controt Register A set directly from the MPU Data Bus and are reset indirectly by a 1 0 x 7 | Peripherel Register 8° Read Peripheral Data Operation on the appropriate section. 1 o x i 90 Oata Direction Register B Control of CA, and CB, Interrupt Lines (CRAO, CRBO, CRA1, tid x x Control Register B and CRB1) The two lowest order bits of the control registers are used to UDeepreatartece apne agtoectwm consinng avon! Sonltl the Inerapt input ines CA, and CBs. Bis CRAD and Gate busand outoutregater. iad CRBO are used to enable the MPU interrupt signals 1RQA and TROB, respectively. Bits CRA1 and CRBI determine the active © Initialization transitivn of the interrupt input signals CA, and CB, (Table 3) A “Low” reset line has the effect of zeroing all PIA registers, Control of CA, and CB, Peripheral Control Lines (CRA3, This will set PAg~PA;, PBy~PB;,CA, and CB, as inputs, and © CRA4, CRAS, CRB3, CRB4, and CRBS) all interrupts disabled. The PIA must be configured during the Bits 3, 4 and 5 of the two control registers are used to restart program which follows the reset. control the CA; and CB, Peripheral Control lines. These bits Details of possible configurations of the Data Direction and determine if the control lines will be an interrupt inout or an Control Register are as follows. output control signal. If bit CRAS (CRBS) is “0” CA; (CB;) is an interrupt input line similar to CAL (CB1} (Table 4). When © Data Direction Registers (DDRA and DORB) CRAS (CRBS) is “I", CA; (CB,) becomes an output signal The two Data Direction Registers allow the MPU to control that may be used to control peripheral data transfers. When in the direction of data through each corresponding peripheral the output mode, CA, and CB, have slightly different data line. A Data Direction Register bit set at “0” configures the characteristics (Table 5 and 6). @ HITACHI 672 Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Control Register A (CRA) [7s [s[4[3} 21] | [IROAt | IROA2 | Control CAz [DORA | Control CAs a CRAO CAi, interrupt output mask bit | CA1 interrupt output mask bit (CAt Peripheral | CRA7 (IRG A1) is set according | CRA7 (IRQA1) is set according Controt Lines) | to the Interrupt signal CA1, but | to the interrupt signal CA1, and IROA is masked and not output | ROA changes ‘low’. {in short, IRQA = ‘high’). CRA CRAT (IRQA1) is set when CA1 | CRA7 (IRQA1) is set when CAt (CA\\ active is fallen. is risen. edge bit) CRA2 Data direction register A Peripheral interface register A (DDRA) CRAS CA2| CAg interrupt output mask bit | CAg interrupt output mask bit CA2 CARG (IRQAg) is set according | CBR6 (IRQAg) is set according (Peripheral to the interrupt signal CAg, but | to the interrupt signal CA2. I Control TROA is masked and not output | And IRQA changes ‘low’ ' Line) (in short, IROA = ‘high’). 1 CRA4 CRAG is set when CAz is fallen | CRAG is set when CA is risen. | CAz (active edge bit) CRAS CRA4=0 CRA4 =0 Handshake mode bit Handshake mode bit The output CAg is ‘low’ when | After reading, CA2 is ‘high’ ‘E’ pulse is fallen on MPU is when next ‘E” pulse is fallen on read the data from Peripheral | MPU is read the data from lA Interface Register A and CAz is | Interface Register A and, after q ‘high’ when CBy is active reading, CAg is ‘high’ when (edge). next ‘E’ pulse is fallen. CRA4 CRAG is the handshake mode _| The content of CRAG is out to bit. CA2. , CRAS CA2 is input mode CA2 is output mode CAg input output select bit CRAG (IRQA2) No interrupt request from CAz_ | interrupt request from CA2 is or CAz is output (Reset Mode) | occurred. CRA7 (IRQA1) | No interrupt request from CAy. | Interrupt request from CA} is occurred. @ HITACHI Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 673 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Control Register B (CRB) Control CBz | DDRB | Control CB; CRBO CBy, interrupt output mask bit | CB1 interrupt output mask bit (CBy Peripheral | CRB7 (IRG B1) is set according | CRB7 (IROB}) is set according Control Lines) | to the Interrupt signal CBy, but | to the interrupt signal CBy, and TROB is masked and not output | ROB changes ‘low’. (in short, IRQB = ‘high’). CRB1 CRB7 (IRQB1) is set when CAy_ | CRB7 (IROB1) is set when CAy (CBy active is fallen. is risen. edge bit) CRB2 Data direction register B Peripheral interface register B {DDRB) CRB3 CB2| CB2 interrupt output mask bit | CBg interrupt output mask bit CB2 CBRE (IRQBg) is set according | CBR6 (IRQBz) is set according (Peripheral to the interrupt signal CB, but ; to the interrupt signal CB2. And Control TROB is masked and not output | TROB changes ‘low’ Line} (in short, IRQB = ‘high’). CRB4 CRBE is set when CB2 is fallen | CRB6 is set when CB2 is risen CBe (active I edge bit) tol CRB3 CRB4=0 CRB4=0 , ! Handshake mode bit Handshake mode bit ' The output CB2 is ‘low’ when | After reading, CB2 is ‘high’

1 Tead the data from Peripheral | MPU is read the data from

Interface Register B and CBg is | Interface Register B and, after ! ‘high’ when CB1 is active reading, CBz is ‘high’ when ' (edge). next ‘E’ pulse is fallen L CRB3 is the handshake mode _| The content of CRBS is out to Tee sees bit. CB2. CRBS CB2 is input mode CB2 is output mode CBa input/ output select bit CRBG (IROB2) | No interrupt request from CB2_ | Interrupt request from CBo is or CB2 is output (Reset Mode) | occurred. CRB7 (IRQB;) —_| No interrupt request from CBy. | Interrupt request from CBy is occurred. @ HITACHI 674 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Table 3 Control of Interrupt Inputs CA, and CB, CRAI CRAO Interrupt Input Interrupt Flag | rear (CRB1) (CRBO) CA, (CB;) CRA? (CRB7) | TROA (TROB) 0 + Active Ser“ on} of CA, | Disabled — TRO remains (CBy) “High” [) + Active Set “1” on + of CA, Goes “Low” when the inter- (cB,) tupt flag bit CRA? (CRB7) goes "1"

1 T Active Set “1” on t of CA; Disabled — TRO remains

_ 2 1 t Active Seti” ontotCA, | Goes “Low” when the inter- (cB) | tupt flag bit CRA? (CRB7) goes 1" (Notes) 1. ¢ indicates positive transition ("Low” to “High"’) 2. 4 indicates negative transition {“High™ to Low") 3, The Interrupt flag bit CRA7 is cleared by an MPU Read of the A Peripheral Register we CRB7 is a ot ie Read of the @ Peripheral Register 4y A }0) is “0” when an intern urs (Inteer disabled) and is later brought “1”, TREA WHEE) occurs attr CRADICRBO Nwritentont Table 4 Control of CA; and CB; as Interrupt Inputs — CRAS (CRBS) is “0” CRAs | CRAs | cRas Interrupt Input Interrupt Flag wren {CRB5) | (CRB4) | (CRB3) CAz {CB2) CRAG (CRB6) TRA UIROB) 0 + Active Set “1 on} of CA Disabled — TRO remains _ ee _ ACB.) “High” f) + Active Set “1 on } of CAy Goes “Low” when the inter- (CB) rupt flag bit CRAG (CRB6) wey 0 T Active Set “1” on t of CA? Disabled — TRG remains 0 t Active Set ‘1 on t of CAz Goes “Low” when the inter- (CB:) rupt flag bit CRAG (CRB6) (Notes) 1. t indicates positive transition (""Low’’ to High") 2. 4 indicates negative transition ("High to “Low™) 3. The interrupt flag bit CRAG is cleared by an MPU Reed of the A Peripheral Register and CRBE + cleared by an MPU Read of the 8 Peripheral Register. ait Cras ieagsls “O" when an interrupt occurs (Interrupt disabled) and is later brought “1'" TROA (1ROB) occurs after CRA3 (CRB3) is written to 8 "1" Table 5 Control of CBz as an Output — CRBS is “1” CB: CRBS crea crea [Cleared Set 1 “Low” on the positive transition of “High” when the interrupt flag bit ‘the first E pulse after MPU CRB7 is set by an active transition Write “8” Data Register operation. of the CB, signal. (See Figure 16) 1 1 “Low” on the positive transition of “High” on the positive edge of the the first E pulse after an MPU Write first "E”’ pulse following an “E” "B" Data Register operation. pulse which occurred while the part was deselected. (See Figure 16) 1 “Low” (Tha content of CRB3 is output on CB,) 1 “High” (The content of CRB3 is output on CB,) @HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 675 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Table 6 Convol of CA; as an Output — CRAS is “1” CA; CRAS [Cleared Set 1 “Low” on negative transition of E “High” when the interrupt flag bit after an MPU Read “A” Data Opera- CRA7 is set by an active transition tion. of the CA, signal. (See Figure 16) 1 “Low” on negative transition of E “High” on the negative edge of the after an MPU Read “A” Data opera- first “E” pulse which occurs during tion. a deselect. (See Figure 16) 1 “Low” (The content of CRA3 is output on CA;)

1 High”

(The content of CRA3 is output on CA2) | PIA OPERATION © Initislizetion __ When the extemal reset input RES goes “Low”, all internal registers are cleared to “0”. Periperal data port (PAy~PA7, PBo~PB,) is defined to be input and control lines (CA; ,CA,. CB, and CB,) are defined to be the interrupt input lines. PIA is also initialized by software sequence as follows. © Program the data direction register access bit of the control reoieter tegister to “0” to allow to access the dada direction register. Store the contents of ACC into the deta direction register © The data of the control line function is set into the accurnu- lator, of which Data Direction Register Access Bit shall be programmed to “1”, Store the contents of ACC into the control register Transfer the control data from the accumulator into the control register. Imput/output processing © Read/Write Operation Not Using Control Lines <Resd Operation> CLR = CRA_—'« Clear the DDRA access bit of the control register to “O”. cLR DORA ¢ Clear all bits of the dada direction register. LDAA #804 © Set DDRA access bit of the control register to “1” to allow STAR , cRA to access the peripheral interface register. interface register into the accumulator LOAA' PIRA @HITACHI 676 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

ES ea ===—-—- a GBA GEB21 <Write Operation> CLR CRA «Set DDRB access bit of the control register to “0”. ogee Set the date diction register ‘0 LOAM #8raa) & Set all bits of the data direction register to “FF”. LOAA #804.) , Ser DDRB access bit of the control register to "I" to allow to sTaa , CAB access the peripheral interface register. ‘Store the data in the accumulator into ‘ Qu cree pint } « Write the data into the peripheral interface register. © Read/Write Operating Using Control Lines Read/write request from peripherals shall be put into the control lines as an interrupt signal, and then MPU reads or writes after detecting interrupt request. <Read > The following case is that Port A is used and that the rising edge of CA, indicates the request for read from peripherals. CLR CRA 6 Set the DDRA access bit to “0”. Sat the date direction register to "00" CLR DRA « Set all bits of the data direction register to “0”. LOAA #806 © Program the rising edge of CA, to be active, TROA is masked stan cra 8d DDRA access bit is set to 1. LOOP LDAA CRA Load the contents of tre conan register eet Loor | * Cnc whether the read request comes from peripherals Loed the contents of the peripheral LDAA PIRA —e_ Load the data from the peripheral interface register into the interface register into the accumulator accumulator. CRA flag is reset after this read operation. To read the peripheral data, the data is directly transfered to the data buses Do~D+ through PAp~PA, or PBy~PB, and they are not latched in the PIA. If necessary, the data should be held in the external latch until MPU completes reading it. When initializing the control register, interrupt flag bit (CRA7, CRA6, CRB7, CRB6) cannot be written from MPU. If necessary the interrupt flag must be reset by dummy read of Peripheral Register A and B. <Write> Write operation using the interrupt signal is as follows. In this case, B port is used and interrupt request is input to CB,. And the IRQ flag is set at the rising edge of CB,. @HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 677 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

CLR = CRB) Set DDRB access bit to “0” ‘Set the dete. i “RRO LOAA #806) © Program the rising edge of CB, to be active. IRQB is masked Svan cre | caaiam the rising edge of CBy to LOOP LDAA CRB 4 a Loe the ofthe conte! or too } © Check whether the write request comes from peripherals ragister into the accumulator oF not. Yes Load the cpoments of the output LDAA PIRB se _Reset the CRB7 flag by the dummy read of the peripheral interface register. Store the f the eccunu soe Minto the ouput renee STAB PIRB Store the data of the accumulator B to the peripheral interface register. Interrupt request flag bits (CRA7, CRA6, CRB7 andCRB6) @) CRAT flag is set and CA; becomes “High” (CA, auto- cannot be written and they cannot be also reset by write matically becomes “High” by the interrupt CA,). This operation to the peripheral interface register. So dummy read of indicates the peripheral to maintain the current data and peripheral interface register is needed to reset the flags. not to transfer the next data. To accept the next interrupt, it is essential to reset indirectly @ MPU accepts the read request by IRQA hardware interrupt the interrupt flag by dummy read of peripheral interface or CRA read. Then MPU reads the peripheral register A. register. © CA, goes “Low” on the following edge of read Enable Software poling method mentioned above requires MPU to pulse. This informs that the peripheral can set the next data continuously monitor the control register to detect the read/ to port A. write request from peripherals. So other programs cannot run at the same time. To avoid this problem, hardware interrupt may “Write Hand-sheke> crBa <0" be used. The MPU is interrupted by IRQA or IRQB when the CRBS = “1”, CRB4 = “0” and Tat to write the date b read/write request is occurred from peripherals and then MPU © eine Be sun nemainn igh” uti’ MPU seit analyzes cause of the interrupt request during interrupt pro- data tothe heral interface ‘ . Henahake Mode (0) CRB? flag is set and MPU accepts the write request. The functions of CRA and CRB are similar but not identical ©) MPU reads the peripheral interface reiter to reset CRE7 in the hand-shake modes. Port A is used for read hand-shake umm} - - operation and Port B is used for write handshake mode. @ Then MPU write data to the peripheral interface register. i i The data is output to port B through the output register. CAt and CB, are used for interrupt input requests and CAz © CB, automatically becomes “Low” to tell the peripheral and CB, are control outputs (answer) in hand-thake mode. that new data is on port B ie 17 Fig. 18 and Fig, 19 show the timing of hand-shake — @ ‘The peripheral read the data on Port B peripheral data Lines mode. and set CB, to “Low” to tell MPU that the data on the < Reed Hand-shake Mode> peripheral data lines has been taken and that next data can CRAS="1", CRA4="0” and CRA3="0" be written to the peripheral interface register. © A peripheral device puts the 8-bit data on the peripheral =< putse mode> data lines after the control output CA, goes “Low”. CRAS = “1”, CRA4 = “0” and CRA3 = “1” @® The peripheral requests MPU to read the data by using CA, CRBS = “1”, CRB4 = “0” and CRB3 = “1” input. This mode is shown in Figure 17, Figure 20 and Figure 21 gu @ HITACHI 678 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

MPU Read [} s-A6, “75, rd | PA,~PA, @ | Co ] @ ] CA, ae aa PgAEAD Reauen 7 1 KZ READ Request a WO» | \\ CRA? J ! cA, | over change of PA, ~PA,| is not allowed. | sHlowed to be wep OY next PA,~PA, are allowed to set, om Redev ®) |__ Reedy | Busy [emes[omforms] . gZ Rw MPU Write pu | I i a \\o | CSRS, “RS, q | TT 4 0,~0, (>t PB,~PB, Ci | 1 cB, paral ee —— PoWRITE Request 1 ty WRITE Request Df dummy Read { cRB7 @ I \\ = ce, J ia) ® PB, ~PB, date is old. - ce, 7 PO, PB, cae ianew. cor Figure 17 Timing of Hand-shake Mode and Pulse Mode @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 679 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Goes “High” on ml a talon Ch, Sa ide hs bond oy (IRQA1 Flag bit set) MPU after falling edge — . of enable signal {LOA A PIRa) CA, Enable signal (E) Handshaking with peripheral on ‘A’ side PIRA cA, a m | | cRA * 2 ° poguGoon an Seve: Data taken \\ Perioheca Says (LOA A PIRA) ‘Seu CRA?) Figure 18 Bits 5, 4, 3 of CRA = 100 (Hand-shake Mode) Gore Low on fay Goes “High” or transition Posit enable i af Of CB, (IRQB! flag bit set) tional ee. tide. (STA A PIRB) ce, i # LOLS LIL signal (e) Handshaking with peripheral on ‘8’ side -_ = ce, PIA cre ny

2 Ri °

3: Here's new date aR in Requet tor ave Figure 19 Bits 5, 4, 3 of CRB = 100 (Hand-shake Mode} @ HITACHI 680 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

CA, Normally Goes “Low” after » “Read 8 side tive seats . data’ instruction (LDA) edge of the (Negetive transition of E) next E pulse ya otter “Reade side data” Instruction LDA) Enable signal (E) Pulse mode Pulse output on ‘A’ side PIRA PIA CA,

2 CRA °

CELELEET) A Pulse initiated I ” “ my ae se _/” Dre “Rass” by MPU (LDA A PIRA) Figure 20 Bits 5, 4, 3 of CRA = 101 (Pulse Mode) CB, Nocratty mectpoune et . “High” Goes Low’ on the positi ules after A Geraifon of the fist rite B E pulse after a “write B ae a tide dee” iatruction gmat Enable ir Puise mode Pulse output on ‘BY side PIRB PIA cB, 2 cre ° fsoogoood) Pr, er sets (STA‘A FIRB) for peripheral! Figure 21 Bits 5, 4, 3 of CRB = 101 (Pulse Mode) @ HITACHI Hitachi America, Ltd. » Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 681 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

= SUMMARY OF CONTROL REGISTERS CRA AND CRB © Active Low Outputs Control registers CRA and CRB have total control of CAy, CAq,CB,, and CB, lines. The status of eight bits of the control When all the outputs of given PIA port are to be active “Low” registers may be read into the MPU. However, the MPU can only (True $ 0.4 volts), the following procedure should be used. write into Bit 0 through Bit 5 (6 bits), since Bit 6 and Bit 7 are set only by CA,, CAz, CB, , or CB,. a) Set Bit 2 in the control register. b) Store all 1s ($FF) in the peripheral interface register. © Addressing PIAs ©} Clear Bit 2 in the control register. Before addressing PIAs, the data direction (DDR) must first d) Store all Is ($FF) in the data direction register. be loaded with the bit pattern that defines how each line is to €) Store control word (Bit 2 = 1) in control register function, ie., as an input or an output. A logic 1” in the data direction register defines the corresponding line as an output while a logic “0” defines the corresponding line as an input, © <Example> Since the DDR and the peripheral interface resister have the same The B side of PIA] is set up to have all active low outputs address, the control register bit 2 determines which register is CB, and CB; are set up to allow interrupts in the HAND- being addressed. If Bit 2 in the control register is a logic “O", SHAKE MODE and CB, will respond to positive edges then the DDR is addressed. If Bit 2 in the control register is a (‘“Low"’to-""High” transitions), Assume reset conditions. Ad. lopic “1”, the peripheral interface register is addressed. There- dresses are set up and equated to the same labels as previous fore, it is essential that the DDR be loaded first before setting example Bit 2 of the contro} register. 1 LDA A#S <Example> 2. STA APIAIBC Set Bit 2 in PIAIBC (control register) Given a PIA with an address of 4004, 4005, 4006, and 4007, 3_~=« LDA B #$FF 4004 is the address of the A side peripheral interface register, 4 | STA BPIAIBD All 1s in peripheral interface cegister 4005 is the address of the A side control register. 4006 is the 5: CLR PIAIBC Clear Bit 2 address of the B side peripheral interface register. 4007 is the 6 STA BPIAIBD All Isin data direction register address of the B side control register. On the A side, Bits, 1,2, 7» | LDA A #827 and 3 will be defined as inputs, while Bits 4,5, 6, and 7 willbe 8 © STA APIAIBC 00100111 control register used as outputs, On the B side, all lines will be used as outputs. The above procedure is required in order to avoid outputs going “Low”, to the active “Low” TRUE STATE, when all Is are stored to the data direction register as would be the case if PIAIAD = 4004 (DDRA, PIRA) the normal configuration procedure were followed PIAIAC = 4005 (CRA) , PIAIBD = 4006 (DDRB, PIRB) © interchanging RSo And RS, PIAIBC = 4007 (CRB) Some system applications may require movement of 16 bits of data to or from the “outside world” via two PIA ports (A 1. LDA A #%11110000 (4 outputs, 4 inputs) side + B side). When this is the case it is an advantage to 2. STAA PIAIAD (Loads A DDR) interconnect RS, and RSo as follows. 3. LDAA#EEIIINI1 (All outputs) . 4. STAA — PIAIBD (Loads B DDR) RSo to Al (Address Line A1) 5. LDA A #%00000100 (Sets Bit 2) RS1 to AQ (Address Line AQ)

6 STAA PIAIAC (Bit 2 set in A control register a es

1. STAA — PIAIBC (Bit 2 set in B contra reba This will place the peripheral interface registers and control registers side by side in the memory map as follows. Statement 2 addresses the DDR, since the control register Bit 2) has not been loaded. Statements 6 and 7 load the control Table Example Address registers with Bit 2 set, so addressing PIAIAD or PIAIBD Pi f TALAD $4004 (DDRA, PIRA) accesses the peripheral interface register. PIAIBD $4008 (DDRB PIR, : PIAIAC $4006 (CRA) if © PIA Programming Via The Index Register Plalee $4007 (CRD The program shown in the previous section can be accom- The index register or stackpointer may be used to move the plished using the Index Register. 16-bit data in two 8-bit bytes with one instruction. As an 1. LDX — #$F004 example: 2 STK PIAIAD. —_SFO-PIAIAD SO4PIAIAC EDX PIAIAD ——PIALAD > IX: PIAIBD +» IX; 3. LDX — 4$FFO4 4. STX PIAIBD —_SFF-»PIAIBD$04+PIA1BC © PIA— After Reset When the RES (Reset Line) has been held “Low” for a Using the index register in this example has saved six bytes of |_ minimum of one microsecond, all registers in the PIA will be Program memory as compared to the program shown in the cleared, previous section. Because of the reset conditions, the PIA has beer defined us @HITACHI 682 Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

follows. = SUMMARY OF CA,-CB, PROGRAMMING 1. All I/O lines to the “outside world” have been defined as Bits 5, 4, and 3 of the control registers are used to program inputs. the operation of CA; -CB, 2. CA,,CA,,CBi, and CB, have been defined as interrupt input lines that are negative edge sensitive. 3. All the interrupts on the control lines are masked. Setting of b5 b4 bo interrupt flag bits will TROA or IROB to go “Low”. So interrupt flag bits will not cause * to-go “Low ca;—ce, [2] 01-) 0 (Mask) CA,—CB; Input Mode Taput + | 0 | Ol-) 2 (Allow) ba = Edge (0 -, 1 = +) Mode 0. | 1+) (Mask) b3 = Mask (0 = Mask, © SUMMARY OF CA,-CB, PROGRAMMING OJ M+) 1 (Allow) 1= Allow! Bits 1 and 0 of the respective control registers are used to program the interrupt input control lines CA, and CBy. ca,-ce, |! | 0 0— Handshake Mode Output, |1 | 0 1 Pulse Mode Mode |} | | 9} b3 Following Mode bt bo 1jrot 0 1 DO = Mask (0 = Mask, ¥ = Allow) 1 ° 1 1 Note that this is the same logic as Bits 4 and 3 for CA,-CB, when CA;-CB, are programmed as inputs. CA, CA, YO As Follow: ra Control Lines: PA, CA, — Positive Edge, Allow Interrupt PA, CA, — Pulse Mode Pa. CB, — Negative Edge, Mask Interrupt PA. CB, — Hand Shake Mode ‘As PA, sun py Sit 4 PIAIAD PIAIAC PAs PIAIBD PIA1BC PIA Configuration Solution ce, LDA A #$BC 90111100 cB, STA A PIAIAD 1/0 to DORA Pa, LOA A #SFF watt . , STA A PIAIBD 1/0 to DDRB . LDA A #$2F 0010 1111 STA A PIAIAC To “A” Control . LDA A #$24 0010 0100 . STA A PIAIBC Te “B™ Control . PB, Figure 22 PIA Configuration Problem @ HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300 683 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

a oSSSSSSSSSSSSSSSSSSSesSSSSeeeeeeeeSSSSS = NOTE FOR USE Compatibility with NMOS PIA (HD6821) Table 7 Comparison CMOS PIA (HD6321) with NMOS PIA (HD6821) [tem | CMOS PIA (HD6321) NMOS PIA (HD6821) Three-state output Pull-up output +5V +5 Port A a PMos PAe~PA, CMOS pA.~PA, oRA NMOS CA, OORA cA, ORA i 1 Date Bus Date Bur f Fe signet Measure for Input floating Three-state output Three-state output +ov +5V ___ Mos Done: Done. Pe. ~PB, NMOS PB, ~PB, Port B cB, ce. Output / ORB NMOS ors NMOS ia Buffer if 1 Measure for Input floating There is no difference between CMOS PIA and NMOS PIA in pin arrangement. @HITACHI 684 Hitachi America, Ltd. » Hitachi Plaza « 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.