HD63140

Hitachi Semiconductor

UNIVERSAL PULSE PROCESSOR

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HD63140A00 HITACHI

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Universal Pulse Processor (UPP) Description + 24 16-bit universal registers (UDR) «16 I/O terminals (8 internal registers for The Hitachi HD63140 Universal Pulse Proces- pulse I/O control are also provided) sor is a CMOS peripheral LSI consisting of - Interrupts can occur at the falling or ris- four independent modules: The universal ing edge of all pulse signals pulse processor core (UPC), 10-bit A/D con- + Pulse width resolution is 5 ys when verter, 1024-byte RAM, and watchdog timer. executing 16 commands at 4 MHz operat- ing frequency The UPC functions as a programmable pulse 1/O module with a 16-bit ALU. It can realize © @ A/D Converter an effective pulse I/O system suitable for versatile applications owing to 16 bit pulse I, + 10-bit x 10 channels successive approx- O terminals and 24 16-bit universal registers imation A/D converter programmable as counter, shifter, compare or - Scanning operation for up to 4-channels capture register. The UPC automatically per- of analog input forms complicated pulse control through the + Interrupts can occur upon completion of use of 15 commands, which sharply reduces conversion the burden on the MPU. The HD63140 sup- ports an asynchronous bus interface and is e RAM easily to connect to the HD6301X, HD6301Y, and HD68HC000 MPUs. + 1024-byte static RAM @ Watchdog Timer (WDT) + Overflow time is selected from 0.128 msec Features to 131 msec under 4 MHz operation fre- quency @ Universal Pulse Processor Core (UPC) @ Low Power Dissipation + 15 commands for executing pulse 1/O operation + Low Power dissipation due to CMOS + Up to 16 functions are programmble from process the MPU into the function table (RAM) + Standby mode is available

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Operating Clock Clock Clock Type No. Frequency Circuit Oscillator Operation Package HD63140 AOO PS 4,0MHz* Divide-by-4 Yes Available 64-pin plastic shrink - Circuit DIP (DP-64S) HD63140 BOO PS 4.0MHz** Divide-by-2 No Available 64-pin plastic shrink Circuit _ DIP (DP-64S) HD63140 AOO CP 4.0MHz* Divide-by-4 Yes Available 68 pin PLCC (CP-68) Circuit HD63140 B00 CP «4.0MHz** —_—Divide-by-2. No Available 68 pin PLCC (CP-68) Circuit rot * — 16MHz crystal or 16MHz external clock * # 8MHz external clock @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 705

Pin Description Pin Function Power Supply Pin No. Symbol DP-64S CP-68 PinName 1/0 Vee: Power supply pin (+5 V). Vec 12 13 Vee ! Ves: Ground pin: Connect all Vss to ground. Ves «1, 21,1, 2, 23, Vas ~ OT 49 35. 53 AVcc: Analog power supply pin for A/D converter (+5 V). Avec 61 65 AVee 1 —— —_— AVss: Ground pin for A-D converter; connect AVss 50 54 AVss ' to ground together with Vss (AVss = Vss = — GND) XTAL 3 4 XTAL 1 =. c Clock EXTAL 4 5 EXTAL f FT F —_ XTAL, EXTAL: A00: Connect to a crystal cLK 2 3 Clock ° whose frequency is four times the operation frequency (16 MHz crystal for 4 MHz opera- RES 6 7 Reset 1 tion). sTBy 7 8 Standby ' When using an extemal clock, its frequency oO _ should be four times the operation frequency Do-Dy 13-20 15-22 Databus 1/0 (16 MHz clock for 4 MHz operation), and the — — _XTAL pin must be disconnected. Ao-Aio 22-32 24-34 Address bus | Rw 8 9 Read/Write | should be two times that of the internal clock RT (8 MHz clock for 4 MHz operation), and the os 9 10 Data strobe | XTAL pin must be disconnected. OE 5 6 Output enable | CLK: CLK outputs a clock signal whose fre- > ———-_ quency is twice the operation frequency (8 cs 10 i Chip select | MHz clock for 4 MHz operation). READY 11 12 Ready ° Reset Wo 6468 rte Oyen RES: Low level input at RES initializes the __ _ _ drain) = BSE INT; 63 67 Interrupt 1 O Standby (open mere BN) STBY: Low level input at STBY stops the WOTO 62 66 Watchdog 0 internal clocks and puts the LSI into standby Timer Out (opens mode; RAM's data is preserved and other drain) circuits are reset. Uo/Pro- 48-33 51-36 Uo/Pio~ «VO Uss/P27 Us/P27 MPU Interface ANo-ANg 60-51 64-55 Analog input 1 Do-Dy: 8-bit bidirectional data bus. AcAwi Address input pins for specifying memory or registers. R/W: Controls data transfer direction between UPP and MPU. in general, R/W sig- nal output from the MPU is connected to RW. DS: Read. write operation is performed dur- ing low level of DS. @HITACHI 706 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 # (415) 589-8300

64-pin Plastic Shrink DIP 2. 68-pin PLCC ves 1D NTS z ae cee cukE) ° ef INT SEeciizssbeGi2e22 xrar Cs ef WoTo noAnAnnAnAnAnoonn extac C+ #1 AVce Sereer ON B5SEEERS oEds eo) ANo D8 eof an RES Cs SEAN: oon ° 206] AN sravc> so JANy neaoy E12 sf] Ane Rw Ce 57] ANa ve Cs vow ose ef] ANa we Che sek ave two s5{_] ANs ae b= “ reaoy C]": EI ANs Efe SB Veo G1? 53) AN? ote sa oy Do s2[7) ANs a tt 51D Use od. st ANs os C20 sof) unk DCs sof] AVss oe hat asf] uses Dats 4955] Vss > Gee ao vrs Ds)? 4817) Uo/Pio Vs Ces 47 bere OsCs a7 Uy/Pi AoC ast) Us Pos. DeC19 46[) U2/P 12 a C25 45) lorie D7 Ez «3 Us/P 13 oC. oe ocaasaenaegssep™ VssC]2" 440) Us/Pia qaooo Sn Ach a2 us/Pr6 «Fee fc Eee AoC} 4115) Uy/P ar $3555535 AsCles 40) Us/P20. Acre 395) Us/Pas (Top View) Aste? 39D Uio/P22 Ac Les 2 Us1/P23 AQ 36F) U12/P24 eC 43° 3822 Us2/Pas Ast: 4 Usa/Pae Aros 239 Uis/P27 Note) NC: Non-connected pins; Nothing can be Top View) connected to NC pins GE: Controls Do-D7 outputs. Do-D; are inhigh- _— request registers IRR16-IRR23 and interrupt impedance state during high level of OEeven —_—_ request at the completion of A/D conversion. in the read cycle. _ WDT Output GS: Read/write operations to/from memory or registers are performed during low levelof WDTO: Overflow output of watchdog timer. CS. In general, decoded signals for MPU up- per addresses are input to CS. UPP Input/Output READY: Inserts a wait cycle for MPU. This is Uo/Pio-Uis/P27: UPP pulse I/O pins. They can a three-state output. When accessing regis- _also be used as an MPU port according to the ters other than RAM, it enters the output _ set data of the UPP contact enable register. state during low level of CS. Except for this _ Input level of Uo/P1o-Uz/Pi7 is TTL, and Us/P20- case, it is in high-impedance state. Uss/P27 are Schmitt-trigger inputs. INTo: Logical sum (OR) output of interrupt | Analog Input request registers IRRO-IRR15. ANo-ANo: Analog input pins for 10-channel INT: Logical sum (OR) output of interrupt A/D converter. @HITACHI Hitachi America, Ltd, « Hitachi Plaza » 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 707

Counter/Timer, Pulse FRS Free-Running Counter/Timer with Sampling Input Functions Performs free-running counts and captures the counter at the rising or falling edge of the specified signal INS Interval Counter/Timer with Sampling Counter is captured and reset at the rising or falling edge of the specified signal ___(Measures pulse cycle.) _ es _ UDS ~“Up-Down Counter/Timer with Sampling Counter counts upward or downward according to the count direction specifi- cation signal, and is captured at the rising or falling edge of the specified signal GTS Gated Counter/Timer with Sampling Clock signal of counter is gated by the specified signal. and the counter is _ _. captured and reset at the rising or falling edge of the gate signa. Counter/Timer, Pulse FRC — Free-Running Counter/Timer witn Compare Output Functions Performs free-running counts, and outputs the result of comparison between compare register data and counter INC Interval Counter/Timer with Compare If counter is the same as the compare register data, pulse is output and counter _ is reset. (Outputs synchronous pulse.) __ “PWC Pulse Width Counter/Timer with Compare _ Result of comparison between compare register data and counter is output while counter is counting. Counter is reset at the rising or falling edge of the specified signal OSC One Shot Counter/Timer with Compare eT Counter continuously outputs one-shot pulses from the specified edge of the specified signal until the counter becomes equal to the compare register data Special Counter/ FFC Fifty-Fifty Duty Cycle Counter/Timer with Compare Timer Functions Outputs 50% duty cycle pulse TPC Two Phase Up-Down Counter ~ Increments or decrements counter according to the relation between two-phase pulse signals. GTC Gated Counter/Timer with Compare _ a The counter clock signal is gated by the specified signal, and the result of the comparison between compare register data and counter is output, Counter is _reset at the specified edge of the gate signal. (Compares pulse width.) “CTO Combination Trigger One Shot Counter/Timer | Counter continuously outputs one-shot pulses, ANDing trigger signal and enable signal until the counter becomes equal to the compare register data. Shifter and Pulse sit Shift Input \\/O Functions Input signal is shifted and latched at the specified edge of the specified signal. SOT Shift Output Outputs reloaded data, shifting or rotating it (Outputs scan signal.) SPO Shift Paraliel Output Outputs reloaded data in parallel, shifting or rotating it @ HITACHI 708 Hitachi America, Ltd. Hitachi Plaza » 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300

ein! Register Name Symbol- Rw as a > vote me (000 | Data Ovecton Rept 2 oor” w : 00 01 et Ovecton Regie} ORI WO — a) 002 ‘Pon Ost Repster “port? “AiW ee : - {003 Por 1 OataRageter “poati “aw” : . 008. Watchdog Timer Regier “WOTR “nwiove “wor ~ =~ “WOd ove2 “over “ovéo ~ 08 {006 TA/D Contol and Status Register” "ADCSA"A/W'ADEND “ADIE “ADST “SCAN "CH CH? “cH! “CHO. 00 (007. “A Data Reputer 0 "ADORO “A/W' (SB) : : ~ 008 |4/0 aw Reps © “apono “ww! use) = - ele “008 1/0 Dat Reputer | ADORT “A/W (SB) : - : . (008 A/0 Owe Peper 1 “apo "Aw us) | ~c08 [4/0 oa Roo 2 “ADOR2 “R/W MSE)” : a) 00€ A/D Date Regier 2) [AODR2 /R/W wy 0 De 000 {4/0 Ont Reger 3) ‘ADORI “RW” (MSE) : : O0€ [4/0 Oat Regste 31 japon Taw! sey Loe 00F | RAM ono! Repster ‘amen RwiRaMe O10‘ UPP Conact Enable Royster 2.‘ UCERZ _ W “UCEIS | UCEV4 “UCEI3 "UCEI2 ‘UcEI! “UCEIO “UcEs “UCEB ” 00 (O11 TURP Comuct Enable Repster i “cent | w "uce? ‘ucks "ces —Uces UcE? “ucer “uce! “uct ” "00 (012 UPP Output Regater 2 “lone Ww juis “use iar ust uous “us “013 | UPP Ops Repster | fuori ‘wu? us ‘us ‘ue us uz, “ur uo F014 xt Ont Ebi Repster Pnoen * ww! a PF 99 016 |Next Date Regier Non | w : . : Df ‘020. ‘UPP Syatom Convoi Register USCR TRAW'TST “TS? “TST “TST_|«—“TST__"GFE_“UROME” 08

021 Manemum Functon Numb Regster” MENA TW’ — |=” MEN MENS “MFA MFR) “MPNO

“022 Funevon Nome Regeter = TFNR RW T=” TFa FN FR? “FN FINO | o2e | Hee eee eee lem emr_fene | | Regieer Assignment Regier A | [026 [Regier Assionmant Register 8 [RasRB [Rrw| — | — [| = [Gena [eens [ecnz |ccni [ccno | + | [026 [V0 Amsionmert Regine A [NOARA_[R/w| — | FEDGA | FeDGA [cewa [cena [cpna [cent _[crno |" | [027 [V0 Ausignmert Rega 8 [ioane _[a/w| —" [repae [reboe |spna [sewa [cena [sent [sao {+ | [028 [V0 Amonment Regiewr © [roan |mrw| =" [ — | = [tupwaa [upwas [tewaz |urwat [Upnao |e | 029 [V0 Amiormers Regwter—_[toan [nw] =| =|" — | urwea_[upwes [iene [unos [upneo | "+ ‘2A “| rtoruot Enable Rooster 3 TERS, —jA/W/ INEZ IREZ2"1RED1__IREZO "REY" IREVE RENT IRE 00 028 intrvot Enable Regator 2 tena “wow imei ]imey4 Tine13 “imeI2 RET REI IRE "IRED 00 02¢imwrst Enable Repste’ ERT AMW'WRE? URES TIRES IREA —IRED_—IRED._ IRE. _IREO__ 00 020. fimerupt Request Rogater 3 TIRORS "A 1RR23.[uRaz?_vRR1 TiRAZO "IAAT _IRRYG IRR?" IRRIG 00 ‘G2e inns Request Regster 2” GRR "| RAIS R14 TiRAIG [wmmIZ[iRRIY "IRRIO "RAB 1RRB_” 00 O2F [iwi enuet Rooster ROR" [ARR "RAG “nm | iRA—iRR "na" IRPY “IRR 030 [inert Status Rogster 3. 1SR3__R_(RSZ9_"VRS22__"IRS2_"1HS20_"IRSIB_"IRSIB_IRSI7_"IRSI OO 031 “Jinterupt Sure Repater 2 ISRZ_ | [IRSYS_[1AS14_[iRSID [WRS12 [IRSIY IAGO" IRS9_1RSB_| 00 (02 __interupt Sats Rept} ism), "IRS? _, NSB "VRSS IRSA IRS "TRS2_—_ IRS" IRSO™ "00 039" "Titorpt Sta Cine Repstr'3 [SCRE | w "IMSC2S | WSCH2 inscZi | sCZOinsCi9 “InsCte insC17 “inscY6 00 034 |nwrpt Sutue Coo Roost 2 [iSCR2_| W TIRSCIS "WSCI4 “IRSCS \\IRSCT2 "iRSCIY IRSCIO_\\RSCO “IRSCE___00 O35 _|mwrut Sun Cow Foster 1 [(SCRY | W "IASC? “CO “iRSCB |IRSCA Insc ‘imsc2 _INSCT “MSCO” 00 036." UPP V0 Regate von ‘awiues Tu uz) uo us fue “uN ule 040] UP Oats Roger 6 Uoro fn ee ont ‘eran tne 980 Teen Seed 042 | uPP ne eg +) SJuont rw : . (043 UPP Oat Regater (0 Tuan "naw" a oe 3 “Oat UPP Ont Regator 2) wore Aw ‘ (045 | UPP Det Regier 2 (1 “uor2 “Rw cot moe (046 UPP Data Repair 3H) Tura “aw! ee " (1 _: Function table *: Undetermined Note : Reset data of not-used bit is described 1” (which is equal to read data) in this table. Read data of write-only bits is different from reset data described in this table @HITACHI Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy, « Brisbane, CA 94006-1819 « (416) 589-8300 709

Register Name RW, ex Sebo RW ggg "047 _1UPP Ova Repaier 3 ors Aw’ . [088 | UPP oa Reps ¢ my UDR RW 049 | UPP Oa Reger 410 ona “m/w ee 04k | UPP Owe Regie SiH) oR aw) 048 | UPP Dew Repco 6 Wore WwW (4c UPP Dut Register 6 1 uone AW x [UEP Dee Regier 8) one 40 [VPP Dew Regi 6) woe RW. - Lt OE _[UPP Date Repster 7m) Tuam aw “oar uPP Ont Regecer 710 von? AW (050__|UPP One Revit 8 (H) UoRe AW - 5 051" UPP das Resists 81) woe Cr 082" UPP Dat Rayer 9 ons Taw Too ee 053 [PP Dee Regs 9 WOR TR ner) 084” UPP Dota Regster 10 DRI “w/w coop eo osres O55 _UPP Ow Regie 1010) Tuono Rw 086 | UPP Date Rapste 17) Uoait nw ~ 2 a 057. UPP Data Regste 17) ‘oat “Aw - WoL Le 058._| UPP Date Repese 12 0) uaa 2 [aw a O58. [UPF Dae Reaver 12 1 Toma aw s (5A | UPP Oat Register 13 1H) “UoRTs fa" oe ec! 058 | UPP Date Regeter 131) ‘Uoa'3 {aw Oo oo ees -O6E_| UPP Date Register 14 (HH MORIA AM - ee (050 UPP Data Register 14 (Ui “ura aw ns O5€ | UPP Data Rogstr 15 tH) UoRIs Aw ners 05 _|UPP Daw Regio 159 Tuomis aw ‘060 "| UPP ate Register 6 (6) TUR [RW ens Get |UPF Dew Resear 1610 ore {Rw ne (062 | UPP Data Regier 171 Wont nw? | (64 UPP On Regist 18 1H) juonie awh, . 005 [UPP Ov Regerw 1810 Tuba RW) 66 [ure be Rapa 19.00" Tupets w, (068 | UPP Date Register 20 (H) UDR20 | RAW. eee ee ° aS . ‘85_[UPr one rvewr 2010 | UoR0 rw a ene (6A “UPP Dat Regatw 211K) | UDR21 RW - ee 5 068” UPP Data Rogar 21 UpRa RW nn ns ene onc UFF ov Regowr a2 ———fuonzz [art ae * (6 UPR Date Regater 23 1H) won awh (06F "UPP Dau Regine 23) | UDRa3 RW! an nr) RAM maw : me i @HITACHI 710 Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

it] cx. [ae convener] i — ourtow tre eon 10-bit esauton KO gs Knaus (at 4 MHz frequency) 10 channels hy Lf tf om BI pe — all aay g Cs a a Ds. 3 ro: KT vurro-viseer oe = P| > mt] a KT) oie iy ‘UPC : Universal Pulse processor Core FT: Function Table UDR | UPP Osta Register WOT : Watchdog Timer CPG Clock Pulse Generator @ HITACHI Hitachi America, Ltd. « Hitachi Plaza # 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 © (415) 589-8300 711

UPP Control Circuit is incremented from 0 during UPC operation. Table 1. MFNR and Number of Functions to be Executed

Function Number Register (FNR) when a 1 is written into the GFE bit is egual to 1, UPC operation is started from FNR = 1. Bt7 6 5 4 3 2 1 0 UPP System Control Register (USCR) [= [= J = [rv [ree [ve J Ton Bt7 6 5 4 3 2 1 0 RAW RWW RWW RW RW + [errr] erro] — [soon Address: $ 022 ; : w w w w RW RW RW Bits 7-5: Not used Address: $ 020 FN4-FNO (Function number): Function num- ber register (FNR) selects functions from the TST (Test): Test bits (bit 7-bit 4) are for test- function table like a program counter. During _ing, and cannot be used for user applications; UPC operation, the FNR is automatically in- _ clear to 0s when setting USCR. cremented and functions stored in the func- tion table are read and executed sequential- _Bit 3: Not used ly. Note that FNR = 0, 5, 10, or 15 indicates cycles for the MPU to read or write the UPP_ _—TST (Test): Test bit (bit 2) is also for testing data register; no functions are executed dur- _ only; clear to 0 when setting USCR ing these cycles. FNR is reset if its value becomes equal to that specified by MFNR. GFE (General function enable): The UPC is in FNR cannot be accessed by the MPU during _ operation and executes functions when GFE UPC operation, but can be when the UPC _—= 1, and is stopped when GFE = 0. This bit is stops operation. Function numbers from 1to _cleared by reset. 4, 6 to 9, 11 to 14, or 16 to 19 are to be specified in this register when programming functions. | UROME (UPP ROM enable): RAM is selected “UPC operation” means the state in which the —_as the function table when UROME = 0, and GFE bit of the UPP system control register © mask ROM when UROME = 1. This bit is (USCR) is equal to 1. cleared by reset. UPC operation is started from the same FNR _Clear to 0 (select RAM) when setting USCR value as it has when a 1 is written into the because mask ROM isn't supported. GFE bit. For example, if the data of FNR @HITACHI 71g Hitachi Amorira | td e« iitechi Dieea « DFW Clerre Deint Dias, 2 Drichene 7A OANNE 1040 « (440) £00 292m

the horizontal column are selected by | Commands" for each command description. is enabied only when GFE is equal to 0; that — (1). 0, must be set in MFNR. to “UPP Commands” for details. Figure 5. Function Table Configuration

Register Assignment Register A 1/O Assignment Register A (IOARA): (RASRA) This register specifies the clock input pin number as well as the edge direction to Bit7 6 5 4 3 2 1 ie define the external clock for a shifter or counter specified by RASRA. This register . clock and timer mode. R/W R/W R/W RW RW Bit 7 6 5 4 3 2 1 ° Address: $024 [= reo enema Bits 7-5: Not used R/W RW RW R/W R/W RW RW CTN4-CTNO (Counter/timer/shifter no.) CTN4-CTNO bits specify the number of UPP Address: $026 data register (UDR) (0 to 23) to be used as a counter, timer, or shifter in each function. (A Bit 7: Not used counter counts clocks specified by the 1/O assignment register, and a timer counts FEDGA (Falling edge A): When FEDGA bit is internal clocks of periodic cycle.) The same 1, counting or shifting is performed on the register can be specified by other functions. falling edge of the signal specified by CPN4- CPNO. Register Assignment Register B (RASRB) REDGA (Rising edge A): When REDGA bit is 1, counting or shifting is performed on the Bit7 6 5 4 3 2 1 i) rising edge of the signal specified by CPN4- CPNO. Eee When FEDGA and REDGA are both 1, count- R/W R/W RW RW RW ing or shifting is performed at both edges. When FEDGA and REDGA are both 0, count- Address: $025 ing or shifting is not performed even if the function is executed. Bits 7-5: Not used CPN4-CPNO (Clock/Shift clock Pin No.): CCN4-CCNO (Capture/compare/reload reg- CPN4-CPNO bits specify the input pin num- ister no.): CCN4-CCNO bits specify the UDR ber (0 to 23) of the clock signal for counter or number to be used as a capture register, shifter. (No external input/output pins are compare register, or data register (shift provided on 16 to 23. The bits of the UPP 1/0 command) in each function. The register register, which is one of internal registers, numbers are 0 to 23; however, 24 to 31 are set correspond to 16 to 23.) if these registers are not used. The same register can be specified by other functions. (A register, for example, which is specified as a counter by one function, can be specified as a compare register by another function.) @ HITACHI 718 Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300

1/O Assignment Register B (IOARB): This 1/O Assignment Register C (IOARC) register specifies the pulse input pin number as well as the edge direction for defining Bit7 6 5 4 3 2 1 ° sampling pulse, trigger pulse, reset pulse, and Bit 7 6 5 4 3 2 1 Oo RW R/W R/W RW RAW [— Fosoafru[enalena[sw in] Atta 02 R/W R/W R/W RW R/W R/W R/S Bits 7-5: Not used Address: $027 LPNA4-LPNAO (Level pin no. A): LPNA4- LPNAO bits specify the pulse output pin Bit 7: Not used number (0 to 23).* When no pulses are output, 24 to 31 are specified. FEDGB (Falling edge B): When this bit is 1, For the TPC and SPO commands, refer to sampling, triggering, resetting, or setting is “UPP Commands” in this data sheet. performed on the falling edge of the signal specified by SPN4-SPNO. 1/O Assignment Register D (IOARD) REDGB (Rising edge B): When this bit is 1, Bit 7 6 5 4 3 2 1 oO sampling, triggering, resetting, or setting is T specified by SPN4-SPNO. RW R/W RW RW RAW When FEDGB and REDGB are both 1, the above operation is performed at both edges. Address: $029 When they are both 0, the operation is not performed. Bits 7-5: Not used SPN4-SPNO (Sampling/trigger/reset set pin LPNB4-LPNBO (Level pin no. B): LPNB4- no.): SPN4-SPNO bits specify the input pin LPNBO bits specify the pulse input pin num- number (0 to 23)* of the sampling pulse for a ber (0 to 23)* of direction setting signal for capture register, trigger pulse for one-shot the counter or shiter, the input pin number of pulse output, reset pulse for counter, set gate signal or tigger enable signal, and the pulse for shifter, one pulse signal for two- input pin number of one pulse signal for two - phase pulse counting, and gate signal. phase pulse counting. % No external input/output pins are provided on 16 to 23. The bits of the UPP I/O register, which is one of internal registers, corre- spond to 16 to 23. @HITACHI Hitachi America | td e Hitachi Plaza e 2000 Sierra Pnint Pkwy e Brishane. CA 94005-1819 e (415) 589-8300 719

oo eeheeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS UPP Data Registers 0-23 (UDRO-UDR23) In this way, UDR should be read or written in UDR, consisting of twenty-four 16-bit regis- the order of upper byte first and lower byte ters, can function as counter/timer, shifter, second. capture, or compare registers according to function settings. Address: $40 - $06F The same register can be specified as referred by several functions. 1/O Port UDR is accessible by the MPU while both executing functions and suspended via a 16- HD63140 has sixteen I/O pins (Uo/P10-U7/P37, Us bit buffer register. /P20-Uis/P27) and an 8-bit UPP I/O register When a MPU write a data to the address of (UIOR) for pulse input and output. As shown the UDR upper byte, the data is written into _in figure 6, these I/O pins are connected with the upper byte of the buffer register. When it UPP output registers (UOR1, UOR2), port data continuously write a data to the address of registers (Port1, Port2), UPP contact enable the UDR lower byte, the data is written into _registers (UCER1, UCER2), and data direction the lower byte of the buffer register and all registers (DDR1, DDR2). These pins can also the 16 bits data of the buffer register is trans- be used as an MPU I/O port. In addition, Us/ ferred to the UDR at the same time. P29 to Uis/P27 are connected with next data During a read cycle, the reverse operation is _ register (NDR) and next data enable register performed, When a MPU read the UDR upper (NDER), and data set in NDR can be output at byte, all the 16 bits data of the UDR is trans- a certain timing. UIOR can be used when ferred to the buffer register andthen the data _— external output is not necessary like when in the upper byte of the buffer register is using the output of one function as input for read. When it continuously read the UDR another function. lower byte, the data in the lower byte of the The block structure of the registers is shown buffer register is read. in figure 7 SSS @ HITACHI 720 __ Hitachi America It © Hitachi Plaza e OF Cierra Print Pay « Rrichane (A OANNE 1240 « (ATE) ERO aN

Figure 6. I/O Register Configuration

Figure 7. Block Configuration of I/O Resisters

a HD63140 Data Direction Register 1, 2 (DDR1, UPP Contact Enable Register 1, 2 DDR2): DDR1, DDR2 specify data direction of (UCER1, UCER2): UCER1, UCER2 determine the corresponding bits of a port. Data is out- whether I/O pins are used as pulse I/O pins of put when the bit is 1, and input when 0. DDR1 the UPC or as I/O ports of the MPU in bit and DDR2 are cleared by reset. units. UPP Output Register 1, 2 (UOR1, UOR2): (1) Setting a UCE bit to 1 specifies the corre- During UPC operation, these registers cannot sponding pin as a pulse 1/O pin of the be accessed by the MPU since data are being UPC. The corresponding contents of UOR stored here by the UPC. However, while the are output onto this pin when DDR =1. If UPC is stopped, they are write accessible by this pin is specified as an input pin of the the MPU. After reset, this register value is UPC, I/O value of the pin is input regard- indefinite and should be initialized before less of DDR. setting GFE as required. These registers cannot be read directly during both operation (2) When a UCE bit is 0, the corresponding and suspension of the UPC. pin is specified as 1/O pins of the MPU port. The corresponding contents of port UPP I/O Register (UIOR): As the UPP I/O data register are output onto this pin register has no external input/output pins, when DDR=1. UOR is now separated pulses cannot be input to or output from it. from the pin, but can be used as an 1/0 However it can be used for relay when the register of the UPC. If this pin is specified output of one function is used as the input of as an input pin of the UPC, the values of another function. This register is accessible UORI and UOR2 are input. by the MPU both while executing and suspending UPC operation, but when UPC is Next Data Register (NDR): The next data in operation, the bit specified as output of register is write-enabled from the MPU. It is UPC cannot be set by the MPU. used when data, which was set in advance, is After reset, this register value is indefinite output in a certain timing. NDR value is out- and should be initialized before setting GFE put to port 2 upon transition of bit 0 of UOR2 as required. from 1 to 0, when the next data enable regis- ter (NDER) is 1 Port Data Register 1, 2 (Portl, Port2): These are output data registers when 1/0 Next Data Enable Register (NDER): The pins are used as an MPU port. Reading the next data enble register determines bit by bit port data registers address returns the input whether or not data in NDR is output to port output value of the pins. 2. When a bit is 1, the corresponding data in NDR can be output to port 2, and the corre- sponding bit of port 2 cannot be set by the MPU. When 0, it functions as a standard port, and the NDR value is not output to port 2. @HITACHI Hitachi America, Ltd. * Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 723

Interrupt Request Interrupt Enable Register (IER1-IER3): TER1-IER3 enables or disables interrupt The UPC can post interrupt requests at the requests. An interrupt is generated if the edge of input/output pulse Uo-Uz3. As shown corresponding bit of the interrupt status in figure 8, interrupt processing is controlled ragister is set when this register bit is 1, and it by the following four sets of registers: inter- is masked when it is 0. This register is cleared Tupt status registers (ISR1-ISR3), interrupt by reset. enable registers (IER1-IER3), interrupt request registers (IRQR1-IRQR3), and inter- Interrupt Request Register (IRQR1- Tupt status clear register (ISCR1-ISCR3), TROR3): IROR1-IROR3 is set by a logical AND Interrupt requests from pins 0 to 15 are out- of the interrupt status register and the inter- put to INTo, and those from pins 16-23 to rupt enable register. Interrupt request is all- INT}. owed by logical OR between each bit of this register as shown in figure 9. Interruput Status Register (ISR1-ISR3): The corresponding bits of this register are set Interrupt Status Clear Register (ISCR1- on detecting the edges of pulse signals from ISCR3): ISCR1-ISCR3 clears the interrupt Uo to Uzs. ISR3 is set at the falling edge of the status registers. The corresponding bits of the pulse signal. The upper 4 bits of ISR1 and ISR2 interrupt status register are cleared by writ- are set at the rising edge of the pulse signal, ing a 0 into this register. When a 1 is written and lower 4 bits are set at its falling edge. into this register, the data of the correspond- This register is cleared by reset, as well as by _ing bits of the interrupt status register are setting the interrupt status clear register. held. SSSSSSSSSSSSheeeeeee @HITACHI 724 Hitachi America, Ltd. © Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300

Figure 8. Interrupt Control Registers Configuration

A/D Converter Internal Registers ADST (A/D start): Writing a 1 into this bit starts A/D conversion. It remains 1 during A/D Control Status Register (ADCSR) conversion, and in single mode, it is cleared upon conversion completion. In scan mode, Bt7 6 5 4 3 2 1 0 conversion is started by setting this bit, and continues until this bit is cleared by the MPU. A/D conversion from the beginning. R/W R/W RWW RW RW RW BIW RW SCAN (Scan mode selection): Scan mode is Address: $ 006 selected when this bit is 1, and single mode when 0. In single mode, A/D conversion of ADEND (A/D end): The ADEND bit is set to1 _the selected channel is executed only once. In upon completion of A/D conversion. In scan scan mode, conversion of all the selected mode, it is set to 1 when the first A/Dconver- _ channels is sequentially continued until the sion of all the selected channels is completed. ADS bit is cleared. These bits are cleared by It is cleared by reading ADDR after reading _—reset. ADCSR, or by writing a 0 into this bit. This bit cannot be written with a 1. CH3-CHO (Channel selection): The CH3-CHO bits select an analog input channel. The rela- ADIE (A/D interrupt enable): The ADIE flag _ tionship between these bits and selected enables an interrupt request. Interrupt channels in single and scan mode is shown in request (INT:) is generated by setting table 2. These bits are cleared by reset ADEND if this bit is set to 1, and is masked if it is 0. This bit is cleared by reset. @ HITACHI Hitachi America, Ltd, © Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300 727

The result of A/D conversion is set in the A/D 5 of the ADDR's lower byte are output as 0. Table 2. Relation between Selected Channel and ADDR in Single and Scan Modes

0 O 1 oO > - AN2 _

1 O oO 1 - ANs = -

a HD63140 RAM Internal Resister RAM Control Register (RAMCR) Address: $00F Bt7 6 5 4 3 2 1 «0 RAME (RAM Enable): Writing 0 to this bit disables access to RAM (address $400-$7FF), pose’ T= [= [= [1-1] emg ah! Se tls entering the standby mode. This bit is set to 1 Rw by reset. Bit 6-0: Not used a Watchdog Timer Internal Register HD63140 is provided with a built-in pro- Bit §:_ Not used grammable 8-bit watchdog timer and can monitor the system. This watchdog timer MOD (Mode): The MOD bit specifies the out- consists of a prescaler, 8-bit counter, and _—_ put method of the overflow signal from the watchdog timer register (WDTR). WDTO pin. If the counter overflows when the When the timer overflows, low is output at MOD bit is 0, low is output for approximately WDTO pin. 8.5us (4 MHz operation). When it is 1, the The 8-bit counter and the watchdog timer _ inverse signal of the WDTR's OVF is directly register (WDTR) are mapped at the same _ output to the WDTO pin, and low output is address. With the first write to this address held until OVF is cleared by reading the after reset, data is set in the WDTR, andatthe © WDTR by MPU. same time, the 8 -bit counter starts counting up. However, with the second or subsequent —Bit 3: Not used accesses, data is set in the counter and no data can be written to the WDTR until the © OVC2-OVCO (Overflow cycle): OVC2-OVCO counter overflows. When this address is read, bits specify the dividing ratio of the 10-bit WDTR contents are read, and counter con- _prescaler, and defines the interval between tents cannot be read. When the timer over- | WDTR setting and counter overflow. The flows, 1 is set in WDTR's OVF bit, and the _ relation between the specified values of timer starts counting from 0. When OVF bit is OVC2 to OVCO and overflow time is shown in 1, the WDTR can be set again after reading _—table 3 the WDTR. When WDTR read is not perfor- med, not the WDTR but the counter is set. Bit7 6 5 4 3 2 1 ° Table 3. Overflow Time of Watchdog Timer (4 MHz operation) ove2 OVC1 OVCO Interval (ms) R RW RW RW RW RW oo 0 ° ° 131.072 Address: $ 005 0 0 1 32.768 OVF (Overflow flag): When the 8-bit counter ° 1 ° 8.192 reaches $FF, this bit is set to 1. It is cleared by ©—©—§ ——————— reset or reading WDTR. ° 1 1 2.048 WOE (WDT Output enable): When OVF is 1 1 ° ° 1.024 WDTO pin. When it is 0, no pulse is output 1 ° 1 0.512 This bit is cleared by reset. a 1 1 on 0.128 @HITACHI Hitachi America, Ltd. © Hitachi Plaza # 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 729

incremented, decremented, or shifted upon tion and decrementation. tions such as a gate signal are satisfied. Table 4. Register Data and Comparison

Table 5. UPP Function Format shifted at the specified direction edge of external clock signal Up. UR (LEFT/RIGHT) : When 0, register i is shifted to right. When 1, register i is shifted to left. i : Number of UDR functioning as a counter/timer or shifter. control signal input pin No. RA (REDGA) : Detects rising edge of signal Up when RA = 1. RB (REDGB) : Detects rising edge of signal Ug or Us when RB = 1.

a SSSSsSSSSSSSSSSSSSSSSSSSSSSS HD63140 SSeS commann| 1. Free-Running Counter/Timer with Sampling (FRS) 1. Value of register i (counter) is incremented or decremented on detecting the specified direction edge of clock signal Up. Incrementation or decrementation is determined by bit 2 of CMR. 2.Value of register { is set into register j (capture register) on detecting the specified direction edge of sampling signal Uq. 3.Overflow signal of register i is output to Ur. (Pulse signal counting) [EXAMPLE | Program in Function Table: C/T = 1, D/U = 0, FB = 1, RB = 0 Capture register (UDR i) Sm ns le Counter (UDR i a {Overiow) commano 2. Interval Counter /Timer with Sampling (INS) 1. Value of register i (counter) is incremented or decremented on detecting the specified direction edge of clock signal Up. Incrementation or decrementation is determined by bit 2 of CMR. 2. Value of register i is set into register j (capture register) and register i is reset on detecting the specified direction edge of sampling signal Uq. 3.Overflow signal of register i is output to Ur (Pulse signal interval measurement) | EXAMPLE | Program in Function Table: CT = 1, D/U = 0, FB = 1, RB = 0 Sampling signal Ua Copture register (UDR j) ‘Counter UDR 9 | Output signal Ur (Overtow! @HITACHI 732 Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300

COMMAND] 3. Up-Down Counter/Timer with Sampling (UDS) {Value of register i (counter) is incremented or decremented on detecting the specified direction edge of clock signal Up. Incrementation or decrementation is determined by count direction control signal Us and bit 2 (1/N) of CMR. _ Incrementation is performed if I/N © Us=1, and decrementation if I/N © Us=0. 2. Value of register i is set into register j (capture register) on detecting the specified direction edge of sampling signal Uq. 3. Overflow signal of register i is output to Ur. [Examete | Program in Function Table: C/T = 1, 1/N = 0, FB = 1, RB = 0 coo sore FMM ‘Sampling signal Uq ee convel sal Us Cape rept UDR 2 ouput sgral Ur fre U COMMAND] 4. Gated Counter/Timer with Sampling (GTS) 1. Value of register i (counter) is incremented or decremented on detecting the specified direction edge of clock signal Up, when gate signal Us is set as bit 0 (H/ L) of the CMR. Incrementation or decrementation is determined by bit 2 of CMR. 2. Value of register i is set into register j (capture register) and register i is reset on detecting at the specified direction edge of signal Uq. 3. Overflow signal of register i is output to Ur. (Gate width measurement) [EXAMPLE | Program in Function Table: C/T = 1, D/U = 0, H/L = 1, FB = 1, RB = 0 cece sora ve MUU ute sgt Us 1 TL Caprreepster(UOR ioreriad coe | cane non Output signal Ur | ‘owe! @ HITACHI Litarhi America | td « Hitachi Plaza e 2000 Sierra Point Pkwy. @ Brisbane. CA 94005-1819 © (415) 589-8300 733

cCommann| 5. Free-Running Counter/Timer with Compare (FRC)

1 Value of register i (counter) is incremented or decremented on detecting the specified

direction edge of clock signal Up. Incrementation or decrementation is determined by bit 2 of CMR. 2.Comparison result CR between register i and register j (compare register) is output to Ur. Output level is specified by bit 0 of CMR, and is equal toCR © HL [ EXAMPLE | Program in Function Table: C/T = 1, D/U = 0, H/L=0 cock sora MMT — =a Compare resister (UDR i eee ao | Count (UDR pect ouput signt tL COMMAND] 6. Interval Counter/Timer with Compare (INC) T. Value of register i (counter) is incremented or decremented on detecting the specified direction edge of clock signal Up. Incrementation or decrementation is determined by bit 2 of CMR. 2.When comparison result CR between register i and register j (compare register) is 1, the pulse signal specified by bit 0 of CMR is output to Ur and register i is reset. Range of register i is from 0 to (j) — 1 ((j) = the data of register j). Output pulse width is equal to pulse width resolution both in timer mode and counter mode. (Interval pulse output) EXAMPLE | Program in Function Table: C/T = 1, H/L = 0 cock sone FP LOO Compare register (UDR = man couram UDR _— - a | es |e @ HITACHI 734 Hitachi America. Ltd. ¢ Hitachi Plaza e 2000 Sierra Point Pkwy ¢ Brichane CA 94005-1819 e (415) 589-8300

a HD63140 EE ommano] 7. Pulse Width Counter/Timer with Compare (PWC) {The inverse of the signal level specified by bit 0 of CMR is output to Ur and register i (counter) is reset on detecting the specified direction edge of reset signal Uq. 2.Register i is incremented on detecting the specified direction edge of clock signal Up. 3.When comparison result CR between register i and register j (compare register) is 1, the output level of Ur is inverted and held until the next reset pulse is input. Register i keeps incrementing while CR=1. It is not reset while CR=0 even if a reset pulse is input. (When a reset pulse is input, the output level of Uris inverted regardless of the value of CR. ‘Accordingly if the value of compare register j is set to 0, the pulse width does not become 0, and a pulse having the same width as the pulse width resolution can be obtained.) | EXAMPLE | Program in Function Table: C/T = 1, H/L = 0, FB = 1, RB = 0 Reset signal Ua een | ee | ee | Counter UDR Compare register (UOR j} Output signal Ur COMMAND] 8. One Shot Counter Timer with Compare (OSC) 7. Counter (UDR i) starts and the inverse of the signal level specified by CMR’s bit 0 is output to Ur on detecting the specified edge of trigger signal Uq, and the value of register i (counter) is incremented on detecting the specified direction edge of clock signal Up. 2.When comparison result CR between register i and register j (compare register) is 1, the output level of Ur is inverted, register i is reset, and this level is held until the next trigger signal is input. Even if the next trigger signal is input while CR=0, it is ignored and no trigger takes place. (Similarly to the case of PWC, if the value of compare register j is set to 0, the pulse width does not become 0, and a pulse having the same width as the pulse width resolution can be obtained.) (One-shot pulse output) | Exampte | Program in Function Table: C/T = 1, H/L = 0, FB = 1, RB = 0 a r Compare register (UDR j) SS —_- en @ HITACHI Hitachi America. Ltd. Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 735

Value of register i (counter) is incremeted on detecting the specified direction edge of clock

10 FA =1

a HD63140 EE COMMAND] 11. Gated Counter/Timer with Compare (GTC) 7. Value of register i (counter) is incremented or decremented on detecting the specified direction edge of clock signal Up, when gate signal Us is set as specified by bit 0 of the CMR. Incrementation or decrementaion is determined by bit 2 of CMR 2.Comparison result CR between register i and register j (compare register) is output onto Ur. The output level is specified by bit 0 of CMR, and is equal to CR © H/T. Register i is reset at the specified direction edge of the gate signal. (Gate width definition) | EXAMPLE | Program in Function Table: C/T = 1, D/U = 0, H'L = 0, FB = 1,RB=0 coc som HMMM Gate signal Us Compare register (UDR j) on —<—F — ° i Counter (UOR 9 owns [C—O COMMAND] 12. Combination Trigger One Shot Counter, Timer (CTO) 7. When trigger enable signal Us is 1, the inverse of the signal level specified by CMR’s bit 0 is output to Ur on detecting the specified direction edge of trigger signal Uq, and then register i (counter) is incremented on detecting the specified direction edge of clock signal 4 Up. 2.When comparision result CR between register i and register j (compare register) is 1, the output level of Ur is inverted, register i is reset, and this level of Ur is held until the next trigger signal is input. Even if the next trigger signal is input while CR =0, it is ignored and no trigger takes place. (One-shot pulse output with trigger enable) [EXampte | Program in Function Table: C/T = 1, H/L = 0, FB = 1, RB = 0 cock et MAMAN waver enablesignatus ff Compare register (UDR j) J oO" J — Counter (VOR i ouput sone @HITACHI Hitachi America. Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 737

———— eee HD63140 “ee ee 1.Value of register i (shifter) is shifted and value of Ur is read to register | on detecting the specified direction edge of clock pulse Up. Shifting direction is determined by bit 2 (L/ R) of CMR. 2.Value of register i is set into register j on detecting the specified direction edge of sampling pulse Uq. (Serial input) | EXAMPLE | Program in Function Table: E/i = 1, L/R = 0, FA = 1, RA = 0, FB = 1, RB=0 corm IIT AINA Semen serst Ua Yr Ieout signal Ur SD) CED COP, CHD, Co), > CI, CID CI CID Ga yee a2 By sau (+4 \\ ws i Ey a in egate YOR Y i { ry hi commano] 14. Shift Output (SOT) 1. Value of register j is set into register i (shifter) on detecting the specified direction edge of set signal Uq. 2.Value of register i is shifted or rotated, and the shift output value is presented onto Ur on detecting the specified direction edge of clock signal Up. Mode for shift and rotation is determined by bits 2-0 of CMR as shown in table 7. The direction of rotation can be specified by shift direction control signal Us in certain modes as shown in table 7. 3.When S2(CMR's bit 2)=0, the LSB of register i is output to Ur, while $2=1, the MSB of register i is output to Ur. ; | EXAMPLE | Program in Function Table: E/l = 1, $0 = Si = $2 -0,FA=1,RA=0, FB=1,AB=0 cea wate TITITA AIRIAAr Set won Va Ya ii a Hi g 38575 \\ Cees ralgs } a H 8 aSyEVSVV\\e H g seveysyy ves H ae orell oil o fl ofl | (ler wll a ae Ott wan Ur IEOXDORE @HITACHI 738 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. ¢ Brisbane CA 94005-1819 » (416) &AG-Rann

a HD63140 ommano 15. Shift Parallel Output (SPO) 1. Value of register j is set into register i (shifter) on detecting the specified direction edge of set signal Uq. 2.value of register { is shifted or rotated and the lower 8 bits are output on detecting the specified direction edge of clock signal Up. Mode for shift and rotation is determind by bits 2-0 of CMR register as shown in table 7 The Girection of rotation can be specified by shift direction control signal Us in certain modes as shown in table 7 3.The lower 8 bits of the shifter are output according to the specification of IOARC. The specification method of the output is described in table 8. 04 determines the output SRetination, UORI or UIOR, and 03 to 00 are output-enable bits in 2-bit units. The SPO command cannot be output to UOR2 | EXAMPLE | Program in Function Table: E | = 1, SO - $1 = $2 = 0, FA = 1,RA~= 0, FB = 1,RB=0 Pee ee ee SetsignalUg | peor WOR ) as aE AA BH Be ‘ 82 ce Hi & a 60, WAT NAMM EG APPIN Re, S\\\\rlfs\\fs sls sysyy Vers OW \\Vers\\ere 8 oy o yoo V Vers nor vOR a “ PES SSMS ASRS SNA Neafectes off eflolef\\ h hes SAN NN SS /\\8s osf|o/ |e flof| | flee vse JL a j Bs 83} bod (od Lod Uf les ues FEV a 9) foo |} fo] OY NIL foe 4 oe OWT \\ Mer|fae|fee 0 fo \\folfol! Vi Ver Ce WS V WeoVer se 0 YoY olol ¥ Ves rues cupwion Uier¥ © Vofofas tse 27.0 YoY ofofofc| os oe |e {ee tsefes hoon oe fo fopot || ce SENS A A fesfecfles oho Noho f fles oe No Hf Heefaaf {e« sis}| o fo ffof| fl cz oe dLe TUL ffer leaf lee era lest Lo lol UU ler Note: 8’, C’ are respectively the lower 8 bits of data B and C @HITACHI titachi America, Ltd, « Hitachi Plaza * 2000 Sierra Point Pkwy.» Brisbane, CA 94006-1819 « (415) 589-6900 739

Table 7. The Relationship between SO to S2 and Shift or Rotation Mode in the SOT and

Table 8. Output Destination in the SPO Command an external clock to EXTAL pin. The fre- example of board design is shown in figure 11. twice the operation frequency. voltage must be more than Voc 0.7 V. Table 9. Typical Crystal Characteristics

8 PATCo crystal (CT A E

Figure 10. Crystal Connection Figure 11. Typical Board Design Applying a low level to the STBY pin places and the LSI is reset. level) are disconnected from internal circuits _tion. This relationship is shown in figure 12. Figure 12. Standby Mode Timing

a HD63140 Notes on using the watchdog timer. reset state after power-on if the system is constructed as shown in figure A. The watchdog timer is undefined at power- on and is not reset until the rising edge of the Please connect the output of the power-on- RES signal, Therefore the WDTO pin may reset circuit directly to the RES pin of the output a low level while alow level is inputto HD63140 in order to avoid this malfunction the RES pin after power-on. (see figure B). This may cause your system to stay in the a

063140 CPU v0

| RES RES AES | J >- Figure B @ HITACHI Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (415) 589-8300 743

according to the number of functions to be are read and executed. Figure 13. Filling Function Table with NOP edges can be detected. In addition, even in Tupt request routine. reset. Consequently, as indicated by B of fig- signal by the change of the sampled value. ruption. tion number as possible.

Recommended Operating Conditions item Symbol Min Typ Max Unit Supply Voltage Veo" 45 50 35 Vv Input Low Voltage Vin® 20 = Vee Vv Input High Voltage Vit o = 0.8 v ‘Schmitt-trigger Input Voltage Vr-* 10 0 2.0 v Schmitt-trigger Input Voltage Vrs 30 = 40 Vv Analog Supply Voltage AVco* = 5.0 = Vv Analog input Voltage Van 0 = AVoo Vv Operating Temperature Top =20 25 75 °6 “Note: *With respect to Ves = AVgg = OV.

Electrical Characteristics

(Vcc = 5 V 10%, Vss = 0 V, Ta = —20°C to+75°C, unless otherwise noted) Item Symbol __Min__Typ Max Unit Test Condition Schmitttrigger __—«Ua/Pao-UsiPyVr=~S*=<“CS*<‘SC‘ SCSC~CSSCSgure 2 Input Voltage Vec = 5.0V a 30 - 40 vi Vrt —Vy7 1.0 - _ Vv Input high Voltage RES, STBY Vie Vec-05 - Vec+0.3 V EXTAL VeexO7 — Vecr 0.3 V Other Inputs 20 - vers Vv Input low Voltage All Inputs Vie -03 - 08 v Input Leakage Current RES,STBY = lin - = 1.0 wA Vin = 0.6- Ao~A10,CS,R/W, Vee-0.5V DS,0E,ANo—ANg Three State Do-D7, READY | Irsii - — 10° uA Vin=0.5- Leakage Current Uo/Pi9~U7/P 17 Vec-0.5V (Off state) Us/P20-Uis/P27 Output high Voltage All Outputs Von 240° - 0 = Vi ton=—200 vA Ve-07 = = OV ston= 10 nA Output iow Voltage All Outputs Vou = = 04 Vlo=1,.6 mA Output Leakage Current INTo,INTr, how = = 1.0 uA Vin=Veo—0.5 (Off state) WDTO f=1.0 MHz . Ta=25°0 Current Dissipation* icc = = 30 mA __ fopr=4 MHz ** Standby Current Ista - = 15 uA (Except Alec) _ - a RAM Standby Voltage Vaan 20 - - Vv ‘Analog Supply Current Alec = = 1m ~~ Notes: + Current dissipation varies in proportion to operating frequency (fopr) * * fopr=fxrac/4 or fext/4: HD63140A00 =fex/2 : HD63140B00 @HITACHI 746 Hitachi America, Ltd, « Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

(Vcc = 5 V +10%, Vas = 0 V, Ta = —20°C to +75°C, unless otherwise noted) Item Symbol__Min Typ Max _Unit__ Test Condition Oscillation Stable Time tac = - 20. ms ‘Figure 17 Clock Frequency foor 7.0. — 4.0 MHz figure 25 Output Clock Frequency fur” oped SCM Output Clock High Pulse Width wei er Output Clock Low Pulse Width —twtC<“CS rs Output Clock Rise Time rr a a ( r,) Address SevupTime—=S~S~=~—CSs=‘“<s~Ss SSCs igure 18D until READY Low (Other than RAM) Delay Time from UDR(UPC) * twarr = = 3 “Ss DS Low until READY High Others* 750 ns Delay Time from DS High until READY Low _tcavz = = 80. ns DS High Pulse Width tows 80 - - ns Figure 18 RW Set-Up Time tas 10 - ns Figure 20 BAW Set-Up Time SN ______ Figure 21 R/W Hold Time _ taH 5 - - ns Figure 25 Read Data Delay Time (RAM) taoo = = 140 ns Read Data Delay Time from READY High taro = = 60. ns Read Data Delay Time from OE toro - - 80 ns Read Data Hold Time taDH 1 = ns Read Data Hold Time from OE High tonon 70 - - 78 Write Data Delay Time * twoo == «120s Figure 19 Write Data Set-Up Time twos 100 - - ns rove 3s Write Pulse Hold Time from READY High* twH 120 = - ns Write Pulse Low Width wwe 100. — - ns 4 Write Data Hold Time ‘twou 5 = = ns READY Turn Off Time from CS High ta1o = = 50. ns Figure 20-22 Figure 25 Notes: * At fopr = 4 MHz, these times vary in inverse ratio to operating frequency (fopr) Port I/O Characteristics (Vcc = 5 V +10%, Vss = 0 V, Ta = —20°C to +75°C, unless otherwise noted) Itom Symbol__Min _Typ Max Unit Test Condition Port input Data Set-up Time tpos 60 = ns Figure 23 Port Output Data Delay Time*_ te) Figure 2425 Notes: * At fopr = 4 MHz, these times vary in inverse ratio to operating frequency (fopr) @HITACHI Hitachi America, Ltd. « Hitachi Plaza # 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300 747

Figure 18. Read Cycle Bus Timing (RAM)

Figure 19. Write Cycle Bus Timing (RAM)

low transition point of CS and DS. high transition point of CS and DS. Figure 20. Read Cycle Bus Timing (Excluding RAM)

latest low transition point of CS, and DS. earliest high transition point of CS, and DS. Figure 21. Write Cycle Bus Timing (Excluding RAM)

RW | os toro: taro tcao2 READY } Figure 22, READY Timing for 1-Byte (Write) and 2-Byte (Read) Access @HITACHI Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 753

Output low voltage at measurement is 0.8 V. Figure 25. Test Load Cicurit

The definition of A/D conversion accuracy for value 1111...11. the HD63140 is described below. ideal A/D conversion characteristics of an digital output value and analog input value. analog input voltage value when digital All errors from (2) to (5) are included.

100 Tranter

Figure 26. The Definition of A/D Conversion 756 Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300.

Selected Specification

Hitachi Semiconductor HD63140 overview.

Summary

UNIVERSAL PULSE PROCESSOR

Description

UNIVERSAL PULSE PROCESSOR

Source title HD63140 Datasheet(PDF) - Hitachi Semiconductor

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