HD6305V0CP

HD6305V0 HITACHI

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HD6305V0,HD63A05VO, . . CMOS MCU (Microcomputer Unit) The HD630SVO is a CMOS 8-bit single-chip MCU which is similar to the HD6305X MCU family. This version is upward HD6305VOP,HD63A05VOP, compatible with the HD6805 family in respect to instructions. A HD63B05VOP CPU, a clock generator, a 4k-byte ROM, a 192-byte RAM, 31 I/ O terminals, two timers, and a serial communication interface (SCI) are incorporated in the HD6305V0. As a result of CMOS technology, the HD6305V0 consumes much less power than ‘1 NMOS counterparts. In addition, three low power dissipation 1 modes (stop, wait and standby) which further decreases power Y consumption, are included in the HD6305V0. Other notable features include enhanced instruction cycle of * the main instructions and the use of three additional instructions Y to improve system throughput. = HARDWARE FEATURES (DP-40) ® CMOS B-bit single-chip MCU © 4096 bytes of ROM HD6305VO0F,HD63A05VOF, © 192 bytes of RAM HD63B05VOF ® 31 bidirectional |/O terminals. © Two timers — 8-bit timer with a 7-bit prescaler (programmable pre- scaler; event counter} — 15-bit timer (commonly used with the SCI clock divider) ® On-chip serial interface circuit (synchronized with clock) © Six interrupts {two external, two timer, one serial and one software) © Low power dissipation modes — Wait. In this mode, the clock oscillator is on and the CPU halts but the timer/serial/interrupt function is operatable. Also, all registers are (FP-54) held, except the | bit in the condition code register is cleared HD6305VOCP, — Stop in this mode, the clock stops but the RAM HD63A05VOCP, data, /O status and registers are held Ex- cept the timer control register (bits 6 and 7) HD63B05VOCP and the | bit of the condition code register. — Standby. In this mode, the clock stops, the RAM data is held, and the other internal condition is re- set. ‘© Minimum instruction cycle time — HD6305VO. 1s (f = 1 MHz) — HD63A05VO 0.67 ws (f = 1.5 MHz) — HD63B05VO. 0.5 ws (f = 2 MHz) © Wide operating range Voc = 3 to 6V (f = 0.1 to 0.5 MHz) . — HD6305VO. f= 0.1 to 1 MHz (cP. 44) Wee = 5V + 10%) — HD63A05V0 f = 0.1 to 1.5 MHz Wee = 5V + 10%) — HD63B05V0 f = 0.1 to 2 MHz Wee = 5V + 10%) ® System development fully supported by an emulator = SOFTWARE FEATURES @ PROGRAM DEVELOPMENT SUPPORT TOOLS © Similar to HD6800 © Cross assembler software for use with IBM PCs and . Byte efficient instruction set compatibles © Powerful bit manipulation instructions (Bit Set, Bit Clear, and 7 Bit Test and Branch usable for ali RAM bits and all |'O termi- © In circuit emulator for use with IBM PCs and compatibles nals) © A variety of interrupt operations © Index addressing mode useful for table processing © A variety of conditional branch instructions © Ten powerful addressing modes ® All addressing modes adaptable to RAM, and I/O instructions © Three new instructions, Stop, Wait and DAA, added to the HO6805 family instruction set © Compatible instruction set with HD6305X @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 375

HD6305V0, HD63A05V0, HD63B05V0 = PIN ARRANGEMENT HD6305VOP,HD63A05VOP, HD6305VOF,HD63A05VOF, HD63BO5VOP HD63BO5VOF SscescttQ eae RES 138) vec Posse F Pag a mre FS) coca ARRAY num (3) [3g) xTAL neg} [ds Ar C4) [32] TIMER «| fag nc Ac CS] [26] STBY c: [a] faa, As [6] [38] 06/INT: of [ages Ae 134) os/EK co figl lige, As [33] De/Ax a: CQ] (32) 02/1 wey] fae A: (10) 133} Dz ne(2] fagnc Ao (it) (35) bs Po [ia] [zgnc Bo (12) [22) Oo o, (i [4T}Ac 8: G3] (28) Co 2 qa: 8» [is) (26) c. ; B. (g] (35) c, nofz] Ba)» 8s (2) (2a) Ca 0. Re Ol [S7)Nc Be (13) [23] Cs os tr {ig} Baa: Br (3) baa) Ce «INT; [20] [3g As Vss [2] 21) cy nef Banc (Top view) ‘Srey G2 [33] 4 HERB REESEHEaS (Top view) HD6305VOCP,HD63A05VOCP, HD63B05VOCP riley gid FE Fo} Foy) fo} fo} 1 £1 F535) 51 (3) Me Sg ouare fn | fag ote «] Bown ata [ago Hl go: nef [gnc | bao. ic [aoe ae fie. “a gc. Oi fae: SJEME SIEI SS ET ITS] eee sesssss {Top view) * NC pins are not for user application. Do not connect to any fine, @HITACHI 376 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300

HD6305V0, HD63A05V0, HD63B05V0 ® BLOCK DIAGRAM XTALEXTAL RES NUM INT STBY 7 8 Counter [4 > oe oe oS ; Is A AY ars cpu 5 Ds /INT: ro. AS 58/02 Ky | [a Tex Comer! BElosc-pioome fo? Terminels aS false ‘Condition Code — 63 53a B3/T* Terminals ae oe 5 _ Resistor g¢ (Se bttteo, Stack é De

6 Pointer «J

Be — il vO : celaskyy Program Flegister | Serial Terminals 28 et Counter oy | Se + Flogister & 33 io 08/28 4096 x 8 192 x8 toe g eal62K ROM RAM Terminals = 6! eel ee & a3 © HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 377

a HD6305V0, HD63A05V0, HD63B05V0 eres eee eee ee ee = ABSOLUTE MAXIMUM RATINGS Input voltage Vin -0.3~ Voc + 0.3 v Storage omperture 35— 180 *e [NOTE] These products have'a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding, ‘be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal ‘operation, we recommended Vin. Vout: Vgs S (Vin OF Vout) S Vcc: ® ELECTRICAL CHARACTERISTICS DC Characteristics (Vcc = 5.0V + 10%, Vgs = GND and T, = 0 ~ +70°C unless otherwise specified) Test - ee Input [ones | [20 [= vecvos fv Tnput volt- Vi, review" | Aliouts | Vou [sf - fT oe ee in an ee ee Input TIMER, leakage iNT, Mul uA current STBY Ao ~ A: Three- 0 ~ Ane 8) ~8 state 10 ~ Br, Itrsil Co ~Cr, current Do~by HA Input . f= MHz, capacity | ain | om | Vin = OV | - jf - |e | al * All output and RES terminal are open. (Vj, min = Vag - 1.0V, Vj, max = 0.BV), are penetrate current of input are not included, **The value at f = xMHz can be calculeted by the following equation: Icc (f = xMHz2) = Icc (f = 1MHz) multiplied by x x i @HITACHI | 378 Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

HD6305V0, HD63A05V0, HD63B05V0 EE eee © AC Characteristics (Voc = 5.0V + 10%, Veg = GND and Ta = 0 ~ +70°C unless otherwise specified) \\ Test HD6305v0 HD63A05V0 HD63B05V0 Unit It st _ condition [min [wp [max [min [tye [max [min [wp | mex | Clock MHz frequency crow [we |e f= | © fame) = ef ee [= [el INT pulse ty teye width tw || +360 "360 +200 ns INT? pulse teye teye RES pulse TIMER pulse teye teye teye Oscillation c= er * start time tosc | R= 602 20 | - ms (crystal) oe nax Reset delay External cap. _ 7 time tRHL 2.2uF 50 ms © Port Electrical Characteristics (Vcc = 5.0V + 10%, Vgg = GND and Ta= 0 ~ +70°C unless otherwise specified) Test B,C,D Output voit- ve if it volt: Input volt. Ports A, ; : —_ Input leak- Vin=05~ age current Mel Voc - 0.5V uA © SCI Timing (Voc = 5.0Vt10%, Vgs = GND and Ta = 0 ~ +70°C unless otherwise specified) Test HD6305VO HD63A05VO HD63B05V0 . item Symbol} congiti Unit ition |"mnin [tye [ max | min [ typ | max | min [ typ [ max | Glock Cyee <a [1 [ - |xreal oer] — [areas] 05 | — [16384] is Data Output Oey Tne ae ee ee Data Setup Tite <a cc ee Data Hold Time Leann | [ioe == P00 [== 00 | = = Ts @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 379

buts Oost +——_ TOR” for using these input terminals. Figure 1 SCI Timing (Internal Clock) Used to reset the MCU. Refer to “RESET™ for details. oe rout w —— grounded to Vgs. Figure 2. SCI Timing (External Clock port D, as an I/O port, the INT, interrupt mask bit in_the Used to input or output clocks for serial operation. [NOTES] 1. The load capacitance includes stray capacitance caused Used to receive serial data. Used to transmit serial data. Figure 3. Test Load The memory map of the HD630SVO MCU is shown in Fig.

8 DESCRIPTION OF TERMINAL FUNCTIONS During interrupt processing, the contents of the MCU registers

here. saving begins with the lower byte (PCL) of the program counter. © iNT INT, counter (PCH and PCL) are stacked.

a HD6305V0, HD63A05V0, HD63Bi ° 0000 O| PORT A_]s00 z 2 1-0 Ports 1" PORT B _|S01 (A ___] Accumulator Tuner 2{-PorTC |so2 7 0 64[ Ram 0040 © 4[_rorT A Don |$04 Register 192Bytes s[_rorr opa [S05 13 9 256 3400 B[ Timer Date Fes |SO8 13 65 5. k Not Used | \\ Slime crm Reo] s09 [o[ofofofofols Ts] sd ointer 4095 gorrr 10[ Misc Reg_|¢oa 4036] $1000 Condition [aL TwTze) é28e ROM Register (4,096Bytes) arr ves) | Sairbw 81801 interrupt 17[[sersts Rea $11 ~—Negative giai seer \\18f sci bam tes _1g12 1 a 819: $2000 me Half Not Used Carry Not Used Figure 6 Programming Model 63 $3F @ Program Counter (PC) The program counter is a 14-bit register that contains the ad- 16383] S3FFF dress of the next instruction to be executed. Figure 4 Memory Map of HD6305V0 MCU © Stack Pointer (SP) The stack pointer is a 14-bit register that indicates the address of the next stacking space. Just after reset, the stack pointer is set 76543210 at address SOOFF. It is decremented when data is pushed, and in- Condition Pull cremented when pulled. The upper 8 bits of the stack pointer are ode Register. stack pointer (RSP) insteuction, the pointer is set to address n-3 n+2 SOOFF. Since a subroutine or interrupt can use space up 10 ad- dress $00C1 for stacking, the subroutine can be used up to 31 n-2 Index Register n+3 levels and the interrupt up to 12 levels. . © Condition Code Register (CCR) nt Jo o| PH ova The condition code register is a S-bit register, each bit indicat- ing the result of the instruction just executed. The bits can be in- n [cus nts | dividually tested by conditional branch instructions. The CCR Push bits are as follows: Half Carry (H): Used to indicate that a carry occurred between + Ina subroutine call, only PCL and PCH are stacked bits 3 and 4 during an arithmetic operation (ADD, ADC). Figure § Sequence of Interrupt Stacking Interrupt (1): Setting this bit causes all interrupts, except a software interrupt, to be masked. If an interrupt occurs with the bit I set, it is latched. It will be w REGISTERS processed the instant the interrupt mask bit is There are five registers which the programmer can operate. reset. (More specifically, it will enter the inter- Tupt processing routine after the instruction fol- e Accumulator (a) . lowing the CLI has been executed.) This accumulator is a general purpose 8-bit register which Negative (N): Used to indicate that the result of the most re- holds operands of the result of arithmetic operation or data cent arithmetic operation, logical operation or processing. data processing is negative (bit 7 is logic ‘*1"). . Zero (Z) Used to indicate that the result of the most re- @ Index Register (x) . cent arithmetic operation, logical operation or The index register is an 8-bit register, and is used for index data processing is zero. addressing mode. Each of the addresses contained in the register Carry/ Represents a carry of borrow that occurred in consists of 8 bits which, combined with an offset value, provides: Borrow (C): the most recent arithmetic operation. This bit is an effective address also affected by the Bit Test and Branch instruc- In the case of a read/modify/write instruction, the index regis- tion, a shift instruction and a Rotate instruction. ii ter can be used like an accumulator to hold operation data or the : result of operation. ao INTERRUPT | If not used in the index addressing mode, the register can be There are six different types of interrupt: external interrupts | used {0 store data temporarily. (INT, INT,), internal timer interrupts (TIMER, TIMER,), serial \\ @HITACHI \\ Hitachi America, Ltd. « Hitachi Plaza # 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 381

HD6305V0, HD63A05V0, HD63B05V0 interrupt (SCI) and interrupt by an instruction (SWI). corresponding interrupt processing starts according to the priority. Of these six interrupts, the INT, and TIMER or the SCI and The INT, interrupt can be masked by setting bit 6 of the TIMER, generate the same vector address, respectively. Al- miscellaneous register; the TIMER interrupt by setting bit 6 of though, a different vector address is generated for a timer inter- _the timer control register; the SCI interrupt by setting bit 5 of the rupt during the wait mode, as shown in Table 1 setial status register, and the TIMER, interrupt by setting bit 4 of ‘When an interrupt occurs, the program in progress stops and _the serial status register_ then the CPU status is saved onto the stack. And then, the inter- The status of the INT terminal can be tested by a BIL or BIH rupt mask bit (I) of the condition code register is set and the instruction. The INT falling edge and falling edge/low level detec- start address of the interrupt processing routine is obtained from _tor circuit and its latching circuit are independent ot sestng_by a particular interrupt vector address. Then the interrupt routine _these instructions. This is also true with the status of the INT, starts from the start address. System can exit from the interrupt terminal. routine by a RTI instruction. When this instruction is executed, the CPU status before the interrupt (saved onto the stack) is @ Miscellaneous Register (MR; $000A) pulled and the CPU restarts the sequence with the instruction The external interrupt INT, and the TIMER interrupt have ext fo the one at which the interrupt occurred. Table I lists the identical interrupt vector addresses, as shown in Table I. For this priority of interrupts and their vector addresses. reason, bits 6 and 7 of a special register called the miscellaneous - register (MR: S000A) are available to contro! the INT, interrupt. Table 1_ Priority of Interrupts Moreover, bit 5 of the MR controls the sensing mode for the Priority | ___Irterrupt_| Vector Address INT interrupt detector (falling edge detector or falling edge/low level detector) 1 [RES—s|SIFFE, —SIFFF Bit 7 of the MR is the INT, interrupt request flag. When a falling edge is detected at the INT, terminal, bit 7 is set to “1” 2 [swiss StFFC, _S1FFD Then the interrupt routine software (vector addresses: $1FF8, 3 SIFFA, SIFFB $IFF9) checks bit 7 to see if an INT, interrupt occurred. Bit 7 — can be reset by software. 5 SIFF6, SIF? Miscellaneous Register (MR; $000) — 2 6 5 4 3 2 1 0

6 SCI/TIMER: | $1FF4, $1FF5 [ant [wre [ors LLL

A flowchart of the interrupt sequence is shown in Fig. 7. A INT, Interrupt Mask block diagram of the interrupt request source is shown in Fig. 8 TNT; tnterrupt Request Flag In the block diagram of Fig. 8, the external interrupt Nis a falling edge trigger input, whereas, the external interrupt IN can be configured as a falling edge trigger input or a combination of Bit 6 is the INT, interrupt mask bit. If this bit is set to “1”, falling edge and low level trigger input, depending on the status then the INT, interrupt is disabled. Both read and write are pos- of bit 5 in the miscellaneous register (MR). When an interrupt sible with bit 7, but ‘1 cannot be written in this bit by software. request is detected at the INT, or INT inputs, an interrupt re- In other words, an INT, interrupt request by software is not pos- quest is generated and latched. The INT interrupt request is au- sible. tomatically cleared if jumping is made to the INT processing Bit 5 is the control bit for INT interrupt detection. If this bit is routine. Meanwhile, the INT, request is cleared if “0” is written reset to “0”, the detection logic will detect a falling edge. When in bit 7 of the miscellaneous register. ___ this bit is set to ‘“1", the detection logic will detect a falling edge For the external interrupts (INT, INT,), internal timer inter- or a low level. rupts (TIMER, TIMER,) and serial interrupt (SCI), each inter- When reset, bit 7 is cleared to ‘‘0", bit 6 is set to “1” and bit Tupt request is held, but not processed, if the I bit of the condi- Sis cleared to “0”. tion code register is set. Immediately after the I bit is cleared, the | @ HITACHI | 382 Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300

a HD6305V0, HD63A05V0, HD63B05V0 <> Clear ee. yt MAIS | | as sate Fue vy men sero <> ) 0-+0DRs Sy Clear (NT Logic N $rorTDR S7F Teer Presale ‘$3F +SSR SSR7=1 $00 >5cR y ‘$5F > MR N anes RE= omer, Lond PC From PENX, a.cor <in> N : toed PC From Swi siFFC SIFFO INT: SIFFA, SIFFS TIMER: siFF8, SIFFS INT, : SIFFS, S1FFO TIMER (WAIT): STFF6, sir? SCI: $1FF4, S1F FS TIMER, : SIFF4, SIFFS Figure 7 Interrupt Flowchart i | @ HITACHI : Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300 383

a HD6305V0, HD63A05V0, HD63B05V0 Timer Control Register (TCR; $0009) A prescaler division ratio is selected by the combination of three bits (bits 0, 1 and 2) of the timer control register (see 76 6 4 3 2 1 0 Table 3). There are eight different division ratios: +1, +2, +4, T carlrcrelrcas|rcralrcrafrcna|rcrilrcrol +8, +16, +32, +64 and +128. After reset, the TCR is set to the +1 mode. a Preseeiencaler division ratio selection Table 3 Prescaler Division Ratio Selection Clock input source: Tier interrupt mask TCR Timer interrupt request . Prescaler division ratio After reset, the TCR is initialized to *E under timer terminal control” (bit $ = 0, bit 4 = 1). If the timer terminal is “1”, the 0 | of: | 22 counter starts counting down with “SFO” immediately after reset. When “1” is written in bit 3, the prescaler is initialized to ° [1 {| o | +4 “$7F"., This bit always shows ‘‘0” when read. Table 2 Clock Source Selection , Co fo | 18 TCR 2 oo | Teeral clock E tf —— 1 +128 0 | 3 | E under TIMER terminal control [| Ne cloning counting stoped 1 [31 | Event input from TIMER terminal Initialize b | Timer Control AN Register (internal (TCR;$0009) £ > [jp rcazfrenefrcasfrcna| rena rcmzfrcn}rcn0 D> D LT I TIMER 24 Input Timer Data Register _(TOR;$0008) Clock input Timer Interrupt Write Read Figure 9 Timer Block Diagram A timer interrupt is enabled when the timer interrupt mask rupt occurs, ‘*1"” is set in the timer interrupt request bit. This bit bit is “0”, and disabled when the bit is “1”. When a timer inter- can be cleared by writing ““O" in that bit. @HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 (415) 589-8300 385

HD6305V0, HD63A05V0, HD63B05V0 = SERIAL COMMUNICATION INTERFACE (SCI) ister and data transfer. This interface is used for serial transmission or reception of 8- bit data. Sixteen transfer rates are available in the range from 1 © SCI Control Register (SCR; $0010) 8 to approx. 32 ms (for oscillation at 4 MHz) The SCI consists of three registers, one octal counter and one prescaler. (See Fig. 10.) SCI communicates with the CPU 7 6 5 4 3 2 1 ~O via the data bus, and with the outside world through bits 3, 4 and 5 of port D. Described below are the operations of each reg- sca7jscrs SCRA }SCRS}SCR2 SCI Control Registers (SCR; 0010) sen7yscre Sens} Scr f ‘Transfer [WL Clock Generator DCR) Ft H , : I 7 H i a H ' (SOR:$0012) on ' ' 6 ha (nivale H ' Da(Rx) # me Ut EE ET TT] D3(Tx) + ' t----4 ‘SCI Status Register srg ee sods XD sa ae oe a y Not Used SCI TIMER2 Figure 10 SCI Block Diagram - Bit 7 (SCR7) SCR7 D3 terminal When this bit is set, the DDR corresponding to the D, be- comes ‘1"? and this terminal serves for output of SCI data. After ty) Used as 1/0 terminal (by DDR) reset, the bit is cleared to "0"

1 Serial data output (DDR output) Bit 6 (SCR6)

When this bit is set, the DDR corresponding to the D, be- comes “0” and this terminal serves for input of SCI data. After SCRE Dz terminal reset, the bit is cleared to “0”.

0 Used as 1/0 terminal (by DDR) Bits 5 and 4 (SCRS, SCR4)

EE These bits are used to select a clock source. After reset, the 1 Serial data input (DDR input) bits are cleared to “0”. - Bits 3 ~ 0 (SCR3 ~ SCRO) scrs|scra] Clock source | Ds terminal These bits are used to select a transfer clock rate, After reset, the bits are cleared to “0”. © fo |= use as 10 termina oy 1 | o | Internat Clock output (DDR output} 1 [1 | External | Clock input (DDR input) | @HITACHI 386 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300

a HD6305V0, HD63A05V0, HD63B05V0 oo OE eee ess ee Transfer clock rate Bit 4 (SSR4) Bit 4 is the TIMER, interrupt mask bit which can be set or SCR3 4.194 MHz cleared by software. When the bit is “1”, the TIMER, interrupt (SSR6) is masked. When reset, it is set to “1” 0 0 t) 0 tps 0.95 us Bit 3 (SSR3) ° 9 ° : 2us 1.91 Hs When “I” is written in this bit, the prescaler of the transfer oO 0 1 i) 4us 3.82 us clock generator is initialized. When read, the bit always is “or. 0 0 1 1 8 ys 7.64 us Bits 2 ~ 0 ‘ t a a i t Not used. 1 1 1 1 32768 us | 1/32s @ Data Transmission By writing the desired control bits into the SCI control regis- © SCI Data Register (SDR; $0012) ters, a transfer rate and a source of transfer clock are determined A serial-parallel conversion register that is used for transfer of and bits 3 and 5 of port D are set at the serial data output termi- data nal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the © SCI Status Register (SSR; $0011) SCI data register. The data written in the SCI data register is out- put from the D,/Tx terminal, starting with the LSB, syn- 2 6 5 4 3 2 1 2 chronously with the falling edge of the serial clock. (See Fig. 11.) wr K) WW When 8 bits of data have been transmitted, the interrupt request ssne] ss Ey <)> <<] bit is set in bit 7 of the SCI status register. This request can be ZNNYS masked by setting bit 5 of the SCI status register. Once the data has been sent, the 8th bit data (MSB) stays at the D,/Tx termi- Bit 7 (SSR7) nal. If an external clock source has been selected, the transfer Bit 7 is the SCI interrupt request bit which is set upon com- rate determined by bits 0 ~3 of the SCI control register Is iB. pletion of transmitting or receiving 8-bit data. It is cleared when nored, and the D,/CK terminal ig set as input. If the internal reset or data is written to or read from the SCI data register with clock has been selected, the D,/CK terminal is set as output and the SCR5S = “I”. The bit can also be cleared by writing “0” in clocks are output at the transfer rate selected by bits 0 ~ 3 of the it SCI conirot register. Bit 6 (SSR6) sev ce wid? Bit 6 is the TIMER, interrupt request bit. TIMER, is used TALL commonly with the serial clock generator, and SSR6 is set each yt 2 3. 4 5 6 2 time the internal transfer clock falls. When reset, the bit is onmnonniown BrmXuseX’ XX XX XX se cleared. It also be cleared by writing “0” in it. (For details, see san one vneh \\ TIMER,.) ‘mona Octo ‘ Bit 5 (SSR5) Figure 11. SCI Timing Chart Bit 5 is the SCI interrupt mask bit which can be set or cleared by software. When it is ‘*1", the SCI interrupt (SSR7) is masked. When reset, it is set to “1” © Date Reception By writing the desired contro! bits into the SCI control regis- ter, a transfer rate and a source of transfer clock are determined SSR7 SCI interrupt request and bits 4 and 5 of Port D are set at the serial data input termi- nal and the serial clock terminal, respectively. Then dummy-writ-

9 Absent ing or -reading the SCI data register, the system is ready for re-

1 Present ceiving data. (This procedure is not needed for the second and subsequent data receptions. It must be taken only after resetting.) The data from the D,/Rx terminal is input to the SCI data register synchronously with the leading edge of the serial clock SSRE TIMER, interrupt request (Gee Fig. 11). When 8 bits of data have been received, the inter- 0 Absent rupt request bit is set in bit 7 of the SCI status register. This re- 1 Present quest can be masked by setting bit 5 of the SCI status register. If an external clock source have been selected, the transfer rate de- termined by bits 0 ~ 3 of the SCI control register is ignored and the data is received synchronously with the clock from the D./ SSR5 SCI interrupt mask CK terminal. If the internal clock has been selected, the D./CK terminal is set as output and clocks are output at the transfer rate o Enabled selected by bits 0 ~ 3 of the SCI control register.

1 Disabled

@ TIMER. The SCI transfer clock generator can be used as a timer. The - clock selected by bits 3 ~ 0 of the SCI control register (4 us ~ SSR4 TIMER; interrupt mask approx. 32 ms (for oscillation at 4 MHz)) is input to bit 6 of the

0 Enabled SCI status register and the TIMER, interrupt request bit is set at

— =f seach falling edge of the clock. Since interrupt requests occur peri- i Disabled odically, TIMER, can be used as a reload counter or clock. @ HITACHI 1 Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 387

ay ‘compatible in respect of both input and output. [O} Transfer clock generator is reset and mask bit (bit 4 not used. ator. If wanting to use TIMER, independently of the SCI, specify connecting a capacitance to the RES input as shown in Fig. 14. “External” (SCRS = 1, SCR4 = 1) as the SCI clock source. If “Internal” is selected as the clock source, reading or writing 5v 45v. " oscillation frequency stability. Three different terminal connections are shown in Fig. 15. Figure 12. Input/Output Port (Ports A, B, C and D) Diagram ment of the crystal, respectively

HD6305V0, HD63A05V0, HD63B05V0 Oscillator Active Timer and Serial Clock Active All Other Clocks Stop Clear | bit Yes No to Standby Mode Yes No Edge/Low, Processor Clocks Nt apy initialize No CPU, TIMER, SCI, W/O and All No No Other Functions %, °S <Tcre>y

77 No No

“< "Se. | Yes Load PC from SIFFE, $1 FFF Restart Processor Clocks Load PC from Interrupt Vector Addresses Figure 18 Wait Mode Flowchart @ HITACHI 390 Hitachi America, Ltd. » Hitachi Plaza « 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 » (415) 589-8300

a Stop Oscillator and All Clocks Clear | bit TCR7 - 0 TCR6 1 SSR7 — 0 SSR6 — 0 SSR5—1 SSR4—1 Yes => No to Standby ~ Mode sdge of No. Turn on Oscillator BS Wait for Time Delay| YY No. to Stabilize | MR6= ha <> “es Load PC from Turn on Oscillator SIFFE, $1FFF fait for Time Delay| to Stabilize Load PC from Interrupt Vector Addresses Fetch Instruction Figure 19 Stop Mode Flowchart | @HITACHI | Hitachi America, Ltd, © Hitachi Plaza » 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 391 i I

Most of these instructions use two operands. One operand is for setting or clearing and the other for bit testing and branching. either an accumulator or index register. The other is derived See Table 8. tion ISR). See Table 5. which is executing a program. See Table 9. test its contents, and write the modified value into the memory MCU in the alphabetical order. Table 6. Table 11 shows the operation code map for the instructions

HD6305V0, HD63A05V0, HD63B05V0 Table 5 Register/Memory Instructions “Addrening Modes or tadered | Tadeed | raved | Soolen/ Canaion Operation Mneroni | rithmic tions | madato| Ovect_| Exendad No Ofaa|@-be aes |baronwol ‘Ahmet [or] « [— jor] a | — foe] s | ~ for! « | - lor} « [lor] « || li inizye Tod A trom Memory TOA |a8)2 | 2 [e6, 2[3 ce 3] 4 1F6| 13 [e612 [4 [08] 3/5 |M—A Tele] ; Loed X from Memory cox fae) 2[zlee[2]s [ce] sya rea] fee]2 | |oe|a|s tux ite : Store Aim Memory | —~STA iS au 213/67 ste Fri [a [7] 2 [4 ]o7] a [3 [aw . of Store Xin Memory Ba alee 2] ler[a felis lalla la foela[s [ew el elalale ‘had Memoryto + ADD PACES ENC ENEA ANE) JES EVEREST FICICSESES ‘Add Memary and Corry ] ' 1 1 : toa aoc 2 (99 2| 3 \\co) 3/4 /r9/1 ales 2 4 Jos) 3|5|Armec-a Alelayala Subwract Memory 3uB 212 [60 7p col 3[4{eo) 1] 3 te0,2/ sloola/s|a-m-a felelatata Subtract Memory from * + + ie wit row i ‘ale —<M=-C H ‘AND Memory to A AND AS 2/2 B4/2/3 C4 3) 4 F4 1/3/64) 2 4/04) 3)5)A- MHA ele naaie “OR Memory wth A ona laal2 2 [eal 2 [3 cal3 4 pal [9 [ealz sonia [5 [atmon Te einiate : wn & con__|aaj 212 [00] 2) 3 co] 3 ¢ r0) 1/9 e0|2, 4 [08] 3/5 arma jtlealale “Anahmetic Compare A rr 1 i 1 1 Pal ! \\ with Memory | cme jatf2]2|erj2/3 13] 4 iri} 3 fer 2/4 Jona 5 |A-M ee AAA with Memory cox |a3)2|2/B3| 2/3 |c3/3| 4 'F3|1| 3/3) 2/4 |03/ 3:5 |x-m elelniala Bit Test Memory with | | | { H t | ‘ | i A (Logeat Compare) er jas 2|2 05/2, 3 5/3 4 F5/1/3/e5/2/4|05;3/5 Am elelaale eee font 4+ ee sume urcondnons | amp j= |= | =\\a6) 2 [2 ec) 33 | 112 ec) 2] aoc] [4 sletetee “op te Sutrovire sR |= |=[ =a] 2 ‘cola [6 lro| 11s e0/2/s ool a6 eleeiee ‘Symbols: Op = Operation # = Number of bytes ~ = Number of eycles Table 6 Read/ModifyMWrite Instructions ‘crensing Modes operat un Tadered | Ttered | ese vavitnmete Oper Conation remonic ImptiediA) | Imphed(x) Oirect {No Offset) |(8-Bit Ottset)| ve ‘© Operatior or] [for] = [- for] s | for] «| for[s [-] x[[e[zfe Therement Tne yacht fa scl +2 facta ESC: AvisAarkyt Karri MTetelalale Decrement vec jaal fz foal a |e sala [soa] Ts feat? fo ]a-1-norxctxorm-i om 'efolatale Cea con jar) t/a [se] v2 [ar] a [8 [7] +s fer] 2 | 6 [00-8 or 00. -x or 00-m elefolrle Complement com 43, 1/2 |sal1[2)33/2 vfs ‘ea Kok or KX or MM fefefatart Negate if T (00-A-=A or OO-XX (2's Complement) Neg j40) 1 | 2/50: 112 [30) 2 1 {5/60 or 00-M--M elalala Rotate Lett Thru Carry ROL sal 1/2 1 CR Asse alala mormon | fol [ofeach [| >) — cy = be omen! Suet tat [se fff fel] ies + | Ot isseett} boo Wy" Loven! Sit ont “sr ' ia ori THI as ———— Sceetcioale ee JU 0 000 00000 Reee==-—esro DOOD ‘Arithmetic Shift taht asc__[asly | [50,1] 2 [se] 215 [76/1 Equal to 1S Tete[alala Test for Negative | ox Zao tst__|40 2) 4j7019 ‘A=00 oF X-00 or M—00 . Symbols: Op = Operation # = Number of bytes

7 Number of cycles

| @HITACHI | 398 Hitachi America, Ltd. © Hitachi Plaza 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 (415) 589-8300

HD6305V0, HD63A05V0, HD63B05V0 Table 7 Branch Instructions Addressing Modes . . Condition Code Operations Mnemonic | Relative Branch Test por] #]-| Hft[n[z[c Branch Always BRA 3 | None [ele Branch Never BRN 21 None _ ned ° Branch IF Higher ~ BHI 22 | C+zZ=0 elelelele “Branch IF Lower or Same BLS 23 C+Z=1 eelelieie Branch if Carry Clear | BCC 24 c=0 ~ ele + o[e (Branch IF Higher or Same) (BHS) c=0 ele ele BranchIF Carry Set. '|~~=#BCS | 28, 2 3 |c=1 Te fele| ac “(Branch IF Lower) (BLO) 2) 2/3 [c= elelelele “Branch IF Not Equal BNE 26 | 2 | 3 |Z=0 : elele ele Branch (F Equal Bea 27 | 2 | 3 |Z=1 elejeiele Branch IF Half Carry Clear | BHCC | 28 | 2 | 3 |H=0 eljeleiele Branch IF Half Carry Set | BHCS | 29 | 2 | 3 |H=1 7 ” elelelele Branch IF Plus Bp) | 2A) 2 | 3 |N=0 —I eielelele Branch IF Minus 2) 3 [N=1 elelelele Bit is Clear amc [2c | 2| 3 1-0 leleieieie Branch IF Interrupt Mask — 7 ~ . Bit is Set BMS | 2D| 2 | 3 |I=1 elejleiele Branch IF Interrupt Line | 7 TT mn is Low ) BIL 2—E, 2 | 3 jINT=0 ei eieieie Branch IF Interrupt Line ~ : 7 ( is High BIH | 2F 2 | 3 | INT=1 ie lelel ole Branch to Subroutine. | BSR | AD, 2.) 5 |—— releielee ‘Symbols: Op = Operation # = Number of bytes ~ = Number of cycles Table 8 Bit Manipulation Instructions t Addressing Modes Operations | Mnemonic ~ Bit Set Ciear_| Bit Test and Branch | Arthmete | Branch Condition Code oP [#[=| oP [= [= Operation | [HU iNizic Branch IF Bit nis clear [BACLAnin=0-7)| — | — | - [O1+2-n| 3| eo eie Set Bit n_ BSET nin=0--7) | 10+2-n| 2] 5 [elelele Clear Bit n TBCLAnin=0-7) 1142-1215] - |-]-[O-Mn_ | —— |[elelejele ‘Symbols: Op = Operation # == Number of bytes ~ = Number of cycles @ HITACHI Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 399

—_] 9h SSS HD6305V0, HD63A05V0, HD63B05V0 oes eee eee Table 9 Control Instructions [Addressing Modes T 7 Operations Mnemonic Implied Boolean Operation Condition Coda or [= | [aL Teyzye Transfer AtoX TAX 97 [11 2 [A=x [ejeleiele Transfer X to A TXA oF { 1 | 2 | xX+A — —_lelelelee Set Carry Bit SEC so] +] 1 [ic T Y s ee ee _ elelelert Clear Carry Bit cic 98 | 1 | 1 [onc le elelo _Set Interrupt Mask Bit | self 9a | i [ets ~ ” elifelele Clear Interrupt Mask Bit {CLI | 9A] 1 | 2 [Oi - _ Te[Olelele Software Interrupt _ Swi 83 | 1; 10 __jeltfelete Return from Subroutine RTS artis, — _ — lelelejere Return from Interrupt | RTI sof i[s| Patatria Reset Stack Pointer RSP gc] 1 | 2 | $FF~SP — “Telele ele No-Operation _ 1 NOP 90] 1 [1 [Advance Prog. Cntr. Only ssi lO loce “Decimal AdjustA~| SDAA ap Pt ta Saqyetis Binary ada or BCD chareters into “Tete Aba tte Stop | stop | ee[ 1/4 7 — felolelee Wait wait | ar | 1] 4 _ _ [oe Olelee Symbols: Op = eoereten bytes" At@ BCD characters of upper byte 10 or more? (They are not cleared if set in advance.) ~ = Number of cyctes Table 10 Instruction Set (in Alphabetical Order) ‘Addressing Modes __]_Sondition Code ee es es ee ee 7 TB Bit t q Mnemonic | | | | Indexed | Indexed | Indexed | Set/ | Test& | H Implied | Immediate | Direct Extended’ Relatwe [No Olfset)| (8-8it) | (16-810) | Clear | Branch |H| 1 | NI] ZC aD SS ASR x cane x | x | 1 fete Bcc [ Ts i elelelele ft — ~ BCLR if i x olelelele BCS” a _— elelejele 8EO a pet i [elelelee eacc ee ee fe ee es ee BHCS i i i i jejelelele BHI px | 4 Bane ° (HS) : T xy | eel ° = — ee — ain a x (eee eee COCCI BIL a [x re eleielele BIT _ ix x x x x "x ele ste (BLO) _ | x i if i ole elele BLS a -_ px _ i eles BMC | | x dt jejeleje ve BMi [_ ~ x {_ jel elelele Ms x i a CSC Be a x relelere art a ereefere BRA [elelele Condition Code Symbols: (to be continued) H Half Carry (From Bit 3) c Carry ‘Borrow ' Interrupt Mask a Test and Set if True, Cleared Otherwise N Negative (Sign Bit) e Not Affected z Zero 7 Load CC Register From Stack @HITACHI | 400 Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 # (415) 589-8300

HD6305V0, HD63A05V0, HD63B05V0 EB YOVY, BVO Table 10 Instruction Set (in Alphabetical Order) Addressing Modes Condition Code Mnemonic Indexed | Indexed | Indexed Set Test & Direct |Extended| Relative | (No Offset)} (8-Bit) | (16-Bit) Clear Branch N}ZI/C BRN a SO GS ECB CD DC) prewe efeTo fe dn a A SS CC CY SSET a DN NS OO OO GS OE SE) BSR a GN ES SS CD) cue a CR QO GO GOR SUD CD YK) cu [x opel ele CLA a ee GO OD CD) cMP [a ee fa tantn com ce Se Ge OS OO 9 9 cPx PO Tee fatata DAA CN 29 DEC a Ss SS) EOR po Te Peat ae iNC a a eS) JMP a ORS ee OS JSR a Oe OC) LDA a ce OS OO Cd SS Lox [a a Te Pe Ta aT ust [Pe EE ee fe Taq ayn USR Pox fe eet ta NEG a Be Se a NOP a CO CC) ORA a OO A ROL a Oe Ge SS ES ROR [x ee fata RSP a RS CS ial a A Ge QO RTS eG CS CC) sec a Oe Oc SAS SEC a NS ON OO CC Sei fox foe eee STA po ee re Pe a Tao stop fe efoto tele STX a Ee Oe ee A sus po eet afata Swi a CD TAX ES LR CO OO COC IC) TST a A Oc OO SO OO AW I TXA LE EC) war ee efoto lol eo Condition Code Symbols: H Half Carry (From Bit 3) c Carry Borrow ! Interrupt Mask ¢ Test and Set if True. Cleared Otherwise N Negative (Sign Bit) © — Not Affected Zz Zero ? Load CC Register From Stack @ HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300 401

HD6305V0, HD63A05V0, HD63B05V0 Table 11 Operation Code Map Bit Manipulation | Branch Read /Modify Write ~Controt Register/Memory Test & Set/ | | in Lae | Branch | Clear Rel [oiR| A | x |.x1|.xo | imp | imp [IMM| OI | ExT [0 i 2 y3f4ts{ej7ielstajete [F | + HIGH | Brseto | eSeTO | BRA | NEG Cu oe) easeri | aseti [ear | gc 2 [ 3} BRCLAT | BCLAT | BLS com sw’ cPx 3]u BASET? | sera | [cS a 419, BRCLR2 BCLR2 Bcs — - 4 BIT 5 BACLR2 uR2| Bcs | es oe ee arseTs | esets | ene | a a a rc. i arctAs [ ectr3 |" Bea | ASR Trax] STA 7 “RSET | asera | Brice | tstast” tere 0 BRCLAG BCLR4 | BHCS | ROL SEC; ADC EJ [A| ersers | esers [ppc [bec feuyona TT [ej ercurs | ectas | pM [OT [= [ser*) ADD 8 srsere | esers {amc [wc | fase] uri) g [| BACLRG | BCLRE | BMS [rsi-u[ TST [ TSt(-1) [DAA‘|NOP|BSR") JSAI+2) | JSR(+1) [ssme2] © [E| BRSeT7 | BSET7 | BIL = stop'| = tox [F{ @actA7 | BCLR7 BIH cua wai TxA STx [stati [38 [| 28 23 [es[iv2ia[zeli sili i[22]23j94[as[2aii 3] (NOTES) 1. “—" is an undefined operation code. 2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte countinumber of cycles). The number of cycles for the mnemonics asterisked (*) is a follows: RTI = 8 DAA = 2 TAX = 2 BSR = 5 RTS = 5 STOP = 4 RSP =2 Cll = 2 ‘SWI = 10 WAIT = 4 TXA =2 SEI = 2 3. The parenthesized numbers must be added to the cycle count of the particular instruction © Additional Instructions during sending/receiving of serial data may make sending/receiving The following new instructions are used on the HD6305V0: operation of SCI out of order. DAA Converts the contents of the accumulator into BCD code. Inthat case, the MCU executes the corresponding interrupt proc- walt Canees the MCU to enter the wait mode. For this mode, essing routine after the 4 dummy cycles. STOP Causes the MCU to enter the stop mode. For this mode, ‘When external interrupts (INT, INT) are held at the I bit mask, see the topic, Stop Mode. the MCU does not enter into the STOP mode by the STOP instruc- §@ PRECAUTION 1—BOARD DESIGN OF tionexecution. The MCU executes the corresponding interrupt proc- OSCILLATION CIRCUIT essing routine after the 4 dummy cycles, in this case, either. When connecting crystal and ceramic resonator with the XTAL and EXTAL pins to oscillate, observe the following in designing = Oy xTaL the board. , . rerat —4 (1) Locate crystal, ceramic resonator, and load capacity Cy and C) = ¢ as near the LSI as possible. (Induction of noise from outside to ‘ast 2 the XTAL and EXTAL pins may cause trouble in oscillation.) (2) Wire the signal lines to the neighbouring XTAL and EXTAL = pins as far apart as possible (3) Board design of situating signal lines or power supply lines near the oscillator circuit as shown in Fig. 35, should not be used because of trouble in oscillation by induction. The resistor Figure 34 Design of Oscillation Circuit Board between the XTAL and EXTAL, and pins close to them should <0 be 10M 2 or more. The circuit in Fig. 34 is an example of good FI FI board design. ? ig 3 id Il PRECAUTION 2—SENDING/RECEIVING a4 H G— Signal PROGRAM OF SERIAL DATA wa Fe Reading from or writing into the SCI data register (DSR: $0012) ite during sending/receiving of serial data may make sending/receiving extaL |} 4 operation of SCI out of order. _Hpesosvo nt 2 rt i PRECAUTION 3—WAIT/STOP INSTRUCTIONS PROGRAM _When I bit of condition code register is ‘1 and an interrupt (INT, TIMER/INT>) is held, the MCU does not enter into WAID mode by executing the WAIT instruction. Reading from or writing into the SCI data register (DSR: $0012) Figure 35 Example of Circuit Causing Trouble in Oscillation | @ HITACHI | 402 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300

HD6305V0, HD63A05V0, HD63B05V0 @ PRECAUTION TO USE BSR @ PRECAUTION WHEN USING BIL/BIH INSTRUCTION If there is 2nd BSR programmed on the address which is directed (1) Execute instruction after the INT voltage level has stabilized by first BSR, 2nd BSR may not be executed correctly. For this above Vyy or below Vi. reason, BSR should not be programmed on the address which is (2) INT voltage level needs to be stabilized while BIL/BIH instruc- directed by first BSR. tion execution. If necessary, please program as following ‘There may be a malfunction by glitch on control signal is BIL/ (1) On the address which first BSR directed, NOP instruction BIH instruction execution has exercised in unstabilized INT signal should be inserted before second BSR. level. (2) On the address which first BSR direct, JSR instruction should be programmed instead of 2nd BSR. wm fO BSR LBLI MiG rr \\ | O 0 LBLI BSR L8L2 =) ‘ } 1 i ' | Avoid BIL/BIH Instruction Execution vei2—--J. ~~ UBLs ---7- ----= example of maltunetion of 2nd BSA execution BSR LBL LBL Nor BSR LBL2 i LeL2--5- = j (NOP is inserted) esr LaLt LBLI JSR LBL2 LBL2 -— toc {JSR is used instead of BSR} @HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 » (415) 589-8300 403