HD6303YF

HD6303Y HITACHI

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HD6303Y,HDG6S3SAO03Y, HD63BO3Y,HD63CO3Y CMOS MPU (Micro Processing Unit) The HD6303Y is a CMOS 8-bit single-chip microprocessing unit which contains a CPU compatible with the CMOS 8-bit microcom- HD6303YP,HD63A03YP, puter HD6301V, 256 bytes of RAM, 24 parallel I/O pins, Serial HD63B03YP, HD63CO3YP Communication Interface (SCI) and two timers = FEATURES © Instruction Set Compatible with the HD6301V1 © 256 Bytes of RAM © 24 Parallel /O Pins © Parallel Handshake Interface (Port 6) © Darlington Transistor Drive (Port 2, 6) © 16-Bit Programmable Timer input Capture Register x 1 Free Running Counter 1 Output Compare Register x 2 {DP-64S) © 8-Bit Relosdable Timer External Event Counter HD6303YF,HD63A03YF, Square Wave Generation HD63BO03YF,HD63CO3YF © Serial Communication Interface (SCi) Asynchronous Mode (8 Transmit Formats, Hardware Parity) Clocked Synchronous Mode © Memory Ready

3 Kinds of Memory Ready

© Halt © Error Detection (Address Error, Op-code Error) © Interrupt — External 3, Internal 7 @ Maximum 65k Bytes Address Space © Low Power Dissipation Mode Steep Mode (FP-64) Standby Mode (Hardware Standby, Software Standby) © Minimum Instruction Execution Time — 0.548 {f = 2MHz) HD6303YH, HD63A03YH © Wide Range of Operation HD63BO3YH, HD63CO3YH Vec= 310 5.5V (f=0.1 to 0.5MHz) 40.1 to 1.0MHz : HD6303Y Vec= 5V+ 10% | #=0.1 to 1.5MHz - HO63A03Y f=0.1 to 2.0MHz : HD63B03Y #=0.1 to 3.0MHz ; HD63CO3Y @ PROGRAM DEVELOPMENT SUPPORT TOOLS © Cross assembler and C compiler software for IBM PCs and (EP-64A) compatibles © In circuit emulator for use with IBM PCs and compatibles HD6303YCP,HD63A03YCP HD63BO3YCP,HD63CO3YCP (CP-68) © HITACHI 126 Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 (415) 589-8300 , www.chipdocs.com Be sure to visit ChipDocs web site for more information.

a HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y tt i = PIN ARRANGEMENT @ HD6303YP. HD63A03YP, HD63B03YP, @ HD6303YF, HD63A03YF, HD63803YF, HD63C03YP HD63CO3YF eat Gf ka we EPERE RARER mr sg Rw CT [31] ov wp, G) aun Pao 3 ea o. Fas Pr & odn ro, wan o im Gy] Bo, Pa Col ons *eG) Bao, Px ea eat & Bet i: Bg, — ic ug Ao. nf fi 2. Poy 59°, Ps OY fe) as Px BAO, Po ea A to Fy Ao ss Da fi) as ay kaa. se [a] fa) © Poh BA: Pe Ga) vex & BoA: Poo Ca Be) as ro EBA. ro Fa] a Pld Bea, a Si as B- GEERT Pus Epa; fsdiiEsiicccd Pe Ea Vs ra Po Be ae (Top View) PoE = Per Ge io rofl Bya.. Peis Baa Po fil gas ra Baa. Pes By) pg Aw Po 9 Vee (Top View) @ HD6303YCP, HD63A03YCP, HD63B03YCP, @ HD6303YH, HD63A03YH, HD63B03YH, HD63C03YCP HD63C03YH Zz Z2 ce sEecwkia gegss5'se.eg2Esss PEGs shi gseg Sse. PRAPPPPAASEIS SES) BISIDIGIEISIOIGIEIBIEIGIBIBIEIE Pro {48} De P20 [10] [59 0» Pn 07) Fas Pn G] Fa] p, Paz (1) Ea) 0. Pa Gl [aa] Dy Pas [13 Ao, Pas Co] a5) Ds Paula 154) 0, Pu () [44] De Prs (15) [55] 0+ Pas Ce} [@} by P20 19) fS4) NC PZ coms Par 7} [53] Ac Py C2] [et] A: ne De] aA. Px Ce] [10] Ar Pso 29) [51} As Ps, OQ) [ap) As Ps: BO IS As Ps Oy [88] As Ps BI a9} A P,, Ga] [37] Ay Psa Bal [a8 As Ps [ia] om Po Bg HAs Py on Pos 2a] 4g) A, Poo Bal [a3] vss a a ES ver Ps, Bgl fad] Ay " . TS : EEEEEEEEEEEEEEaE REREESEEEEEEaSESE SedsdssFPPIFFste esses dds se Zicicice (Top View) (Top View) @ HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 127 ; ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y @ BLOCK DIAGRAM vi Pare oe cc Ves $SRbBW Vss —o 0 P2o( Tin) a Uy qf P2i(Tout)) « IE RD P2i(SCLK) rt 8) fFgs FY WR Pax(Rx ) tine w E RAW PralTx ) Tot 5 oR Pas( Toutz) S BA Pr«( Touts) . Patrets) PE oe cia aE é Da s Os bo 9 D, scl AL lA 2 Ar TIMER2 $a Ay Cee 3 3 As Poe ) — 3 Ay Psx(MR_ > wo |/8 3 Ps53(HALT) Ela < Ae PsllS Ole a . As Pss(OS ) 2 ge Aso pee ly | | | cal Ay Peo [| Ave Per « As Poa o/8 Pes gle e___ <9 Poo Slt Pes © RAM Pes 256Bytes Pe @HITACHI 128 Hitachi America, Ltd. * Hitachi Plaza « 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

a HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y @ ABSOLUTE MAXIMUM RATINGS i ee re Soom v put Vohage =03 Veet OS v Operating Terpartre “< Stonge Tenperture * (NOTE) This product has protection circuits in input terminsl from high atatic electricity voltage and high electric field. But be careful not to apply overvoltage more than maximum ratings to these high input impedance protection circuits. To assure the normal ‘operation, we recommend Vey, Vou: Ves X Ve, OF Vou) & Vee: @ ELECTRICAL CHARACTERISTICS @ DC CHARACTERISTICS (Voc = 5.0V + 10%, Vgg = OV, Ty = -20°C ~ +75°C, unless otherwise noted.) impo "Low Valage fantnputs wf YP = fort Input Leakage Current | Mp. agp, Vip = 0.5~Vec—0.5V pA Three State ~A15, Do~D>, RD, = Output “High” [iw=— 20004 | ee | = | utput “High” Voltage Vou [w= =t0.a | ve-o7 | - | - |v Darlington Drive _ seagre foewse [we [var || = [me ee Standby Covent [Ron Opwaion we || | 80 | 10 [Steering @=twaey [48 [30 | ma tue [CSmeping t= remem [=| 2a [48 [ma yrrent aoe aa Lise] mA Current Dissipation* Steeping (f=3 MHz) 45 | 90 | mA | opering w= 1mnen [= | 70 | 100 | ma tee [_ Operating t= remus) | — [108 | 15.0 | ma Operating teams) =| 2.0) 300 [ma FAN Senay Vue fmm pT ee T= * Vagmin = Voc — 1,0V, Vy max = 0.8V (All output terminals are at no load.) Current Dissipation of the operating or sleeping condition is proportional to the operating frequency. So the typ. or max. values about Current Dissipations at X MHz operation are decided according to the following formule: typ. value (f= X MHz) = typ. value (f= 1MHz) x X max. value {f = X Miz) = max. value (f = MHz) x X (both the sleeping and operating) * SCLK 0.6V (-20°C~0°C) @ HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 129 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO3Y lath tilt cartier lata @ AC CHARACTERISTICS (Vcc = 5.0V + 10%, Vgg = OV, T, = -20 ~ +75°C, unless otherwise noted.) BUS TIMING ° Test HDBOB01¥0 HDBICOLYO " mre | cevoton [ran [ve [as [mm [oe [oo [wn [ve [moe | win [oe [mm] Cyele Tine ye J [= [0 Toss |= To [os | 10 [0300 | “ Enable Rise Tine ‘e [- | = [-[-lef- oe Enable Fall Tine ‘es rT] —j[-{t*[-[-f# > T-]= |e Enable Pulse Widih “High” Lover” | PWey wo | — | [= fv [| — Tas Enable Pulse Width “Low” Level | PWex By | — | 300 | = = [140 — [= [os Faress, RAV Delay Tene wo [= [af - [-]wf—ft— |] -)— 7 Data Delay Time wrie | toow [-|-]| = wo | — | wl]— | ne Data Setup Time Read | tosn Lo {=| |= [ee [-}-{o|-] na Aaéress, RA Hold Time” Sas He ate tafe fC Data Had Timo [weer [tow | | [|= | [= [= [of [=] | = | m FI, WR Adcross Hold Time" [~ [|= | | | fo Te = a T= os FO, WR Data Hol Time* [we _| ef te et ns Data Hol Time [Read | tn _| fe [-]- [ee [-|- Te [y= fo [T= Tn FWA Putse wath | PW | [sso | = [= | 00 [| Peo [= [= [0 [=] me FD, WR Ooiay Tne [aw a ee ra RO. WA Hold Time | twnw_| ee ee ee eee TR Dotay Tine Kee | | ns TR Hola Time [so [= [=] [=] = To f= [|] | = | PorpheratReadaccess Time | eo | | | = PP J = P= fe [= oe MA Setup Tine" [20 [ = [= [eo [= | - = | m[- [= [ss MA Hold Tine" | aan _| [= | = fr [= T= | o[-[-[aln E Glock Pule wath at MA | Pena | [=[-]e{- |- fe |e | |e fos Procowsor ComolsetupTime | tees | fn.a.33. «| 200 | — | — | 200 | = | = | 0 [= [Ts ProceaserComoiniee Tine | tres 2, | | = | wo = | = | 00 [v0 | — [= [0 [ne Processor Gontol Fall Tine | = [= [1 [=] = Teo | 100 [= [= [os BA Delay Time | in [| fos | — [= [0 | = | = fio | = P| | 120 | ns Oscitaor Siabitaton time | ine | Pate | oof — | = [eo [= | — | 2 | | ~ | ms Reset Puse Wiatn [Pwr [Ts [~~ [= t-fs P= y= 7s [= [= fe “These timings change in approximate proportion 10 t-y.. The figures in this characteristics represent those when (is minimum (= in the highest speed operation) Peripheral Port Timing Test HD63803 7 “ Site [sendivon Trin Tove [rex [min [wp [wax ]min [ye [or] rin [we [mex] Peripheral Data Saisie” [roast [von | 2] - [- [ne [ = [- [oe] -[ [ae] - | - [= fogtine | Pass ve | | [ooo || [ome | [oe] -[- Sere [ower ome [mee = |= fow[ [Toe] -| oe] =] Enable Fall Edge to | Port 25,6 bed Peripheral Output) Inpur Strobe Pulee Wisth tows _| [200 [| — [200 | - [= [200 [= [= foo | [= [em time Tome fw | vio [io |= [ [ow [= [= [ow f= | = fone macemnense Jrove [es [poe [= T= [ow [Jom [= [Joe] [=| Time ns cormmwens fate [Eel Pe) be | @ HITACHI 130 Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO03Y CERO eee ee eee eee TIMER, SCI TIMING ‘tom [in [ve [rar [rin [om Trax [min [oe [mas [ rin [om [mon | Timer 1 input Pulse With [ver | ree [eof [— [eo [— T= [eof = f= Teo TH | Te severe [feel -[-[=]-[-fel--fl- [lel ‘Transition to Timer Output) [ree [oe |— {= foe [- |= Po [- ote TT to nese eree ‘we [ree [20 [— |= [20 [~ [= Peo T- [= feo fT [oe ‘SCI Transmit Data Delay Time tr 220 ns (Clock Sync. Mode) io ene f=[-[-T]-|-Jel-[-[=]-|-[ C1 Input Cock Pale Wath [es [= |os [oa [= [oe [oe] — [oe [on | — [00 [toe Tir 2 input Clack Oye [eo [=| = ee [-]- eof = [= [eo |} | Timer 2 input Cock Pulse Wah [ 200 [= [am [= | foo | [= [am [= [fo os BED RSOeeleene ‘Clock Rise Time Timer 1-2, SO input Clock Fal Time es ee ee ee ee ee a @HITACHI Hitachi America, Ltd. © Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 + (415) 589-8300 131 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y well as the IRQ mentioned below, the instruction being executed at the current instruction before the acceptance of the request. Unless ‘RMT signal detection will proceed to its compeletion. The interrupt the interrupt mask in the condition code register is set, the CPU mask bit of the condition code register doesn’t affect non-maskable Starts an interrupt sequence, if set, the interrupt request will be ig- interrupt at all nored. When the sequence starts, the contents of the program In response to an NMI interrupt, the contents of the program counter, index register, accumulators and condition code register counter, index register, accumulators and condition code register will be saved onto the stack, then the CPU sets the interrupt mask will be saved onto the stack. Upon completion of this sequence, a bit and will not acknowledge the maskable request. During the last vector is fetched from SFFFC and SFFFD to transfer their contents cycle, the CPU fetches vectors depicted in Table 1 and transfers into the program counter and branch to the non-maskable interrupt their contents to the program counter and branches to the service service routine. routine. (Note) At reset start, the stack pointer should be initialized on ‘The CPU uses the external interrupt pins (IRQ, and IRQ,) also an appropriate memory area and then the falling edge as port pins P,, and P,,, so it provides an enable bit to Bit 0 and | of be input to NMI pin. the RAM port 5 control register at $0014. Refer to “RAM/PORT 5 CONTROL REGISTER” for the details. ‘When one of the internal interrupts, ICI, OCI, TOI, CMI or SIO © Interrupt Request (AG), TRG) is generated, the CPU produces internal interrupt signal (IRQ,) ‘These are level-sensitive pins which request an internal interrupt IRQ, functions just the same as IRQ, or IRQ, except for its vector Sequence to the CPU. At interrupt request, the CPU will complete address. Fig. 16 shows the block diagram of the interrupt circuit. Each Status Register's Interrupt Enable Flag “1 Enable, "0" ; Disable * nahn ms toed] || Condition Cove (FOr oo Register oo 0”. Enable ‘cr per Oat oo interrupt RQ; =e Signal CMF oo an Lae z Sleep ge Cancel ™ LO Si ! ignal ircuit onwerw cecal swi Figure 16 Interrupt Circuit Block Diagram © HITACHI 136 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y ' , , Table 1 Interrupt Vector Memory Map. ries. Refer to “RAM/PORT 5 CONTROL REGISTER” for more details «ate ACT Po P +: Ppa) nenty Tse | (s8 | Interrupt This is an input control signal to stop instruction execution and terre | to release buses. When this signal switches to Low’, the CPU Highest [frre [frre | RES stops to enter into the halt state after having executed the present [Free [FEF | TRAP instruction. When entering into the halt state, it makes BA “High” (Frec [FFD | Mi and also an address bus, data bus, RD, WR, R/W high impedance. When an interrupt is generated in the halt state, the CPU uses the [rere |rrre_| sw interrupt handler after the halt is cancelled. When halted during the (Software Interrupt) sleep state, the CPU keeps the sleep state, while BA is “High” and [Free [FFFO | IHG, ISF (port 6 input Strobe) releases the buses. Then the CPU returns to the previous sleep ro state when the HALT signal becomes “High”. Jerre |ere7 | (Timer 1 Input Capture) (Note) Please don't switch the HALT signal to “Low” when the CPU executes the WAI instruction and is in the in- Frrg | OC terrupt wait state to avoid the trouble of the CPU's op- (Timer 1 Output Compare 1, 2) eration after the halt is cancelled. q FFF2 | FFF3 Tener 1 Overflow) . Bus Available (BA) . This is an output control signal which is normally ‘*Low’’ but FreD | CM! “High” when the CPU accepts HALT and releases the buses. The (Timer 2 Counter Match) HD6800 and HD6802 make BA “High” and release the buses at [Frea [Free | TRO, WAI execution, while the HD6303Y doesn’t make BA “High” j [ero [rr_| So under the same condition. owest (RORF + ORFE+ TORE+ PER) = PORT The HD6303Y provides three 8-bit 1/0 ports. Each port pro- vides Data Direction Register (DDR) which controls the I/O state ‘© Mode Program (MPo, MP;) by the bit. Set MP, “High” and MP, “Low”. © Read/Write (R/W) Table 2. Port and Data Direction Register Address This signal, usually be in read state (“High”), shows whether the CPU is in read (“High”) or write ("Low") state to the periph- [ Pon ascras | eral or memory devices. This can drive one TTL load and 30pF ca- Port | Port Address Data Direction Register pacitance. Pon2 | $0003 | $0001 © 0, WA Pons | soos | $0020 These signals show active low outputs when the CPU is reading/ Porté $0016 writing to the peripherals or memories. This enables the CPU easy to access the peripheral LSI with RD and WR input pins. These pins can drive one TTL toad and 30pF capacitance. ©@ Port 2 __ An 8-bit I/O port, Port 2 DDR (P2DDR) controls the 1/0 state. © Load instruction Register (LIR} This port provides DDR corresponding to each bit and can define ‘This signel shows the instruction opecode being on data bus input or output by the bit (“0" for input, “1” for output). {active low). This pin can drive one TTL load and 30pF capacitance. As Port 2 DDR is cleared during reset, it will be an input port Port 2is also used as an I/O pin for timer 1, Timer 2 and the SCI ‘© Memory Ready (MR; Pg2) Pins for Timers and the SCI set or reset each DDR depending on This is the input control signal which stretches the system their functions and become 1/O pins. When port 2 functions as an I/ clock's “High” period to access low-speed memories. HD6303Y port afler used as 1/0 pins of the timers or the SCI. the 1/0 direc- fan select three kinds of low-speed memory access method by tion of the pins remain as itis used as the 1/0 pin of timer and SCI RAM/Port $ Control Register's MRE bit and AMRE bit. In the Port 2 can drive one TTL load and 30pF capacitance. This port tase that CPU accesses low-speed memories by the external MR can produce IMA when Voy =1.SV to drive directly the base of signal (MRE="*1", AMRE="0"), the system clock operates in Darlington transistor. normal sequence when this signal is in “High” But this signal in ‘*Low", the “High” period of the system clock Pag (Tin) will be stretched depending on its “Low” level duration in integral P,, is also used as an external input pin for the input-capture. multiples of the cycle time. This allows the CPU to interface with This pin is an 1/0 port which is an input or output as defined by the low-speed memories (See Fig. 2). Up to 9us can be stretched. Data Direction Register (P,,DDR) (“0" for an input and “1” for ‘During internal address space access or nonvalid memory ac- an output). Then either a signal to or from Py, (“10" for an output cess, MR is prohibited internally to prevent decrease of operation _port, “from” for an input port) is always input to the Timer | input speed. Even in the halt state, MR can also stretch “High” period of | capture. system clock to allow peripheral devices to access low-speed memo- @ HITACHI Hitachi America, Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 137 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y a ee eee RES Rr 3 Q D 3 P20 ODR s c é p 3 Pao DATA ~ WP2D : DDR Write Signal WP2_ : Port Write Signal RP2 _: Port Read Signal Timer 1 Input Capture Input P2y (Tout 1), Pag (Tx), Pog (Tout 2), P2g (Tout 3) have a register which enables output. By setting these registers, ‘These four pins can be also used as output pins for Timer 1, they automatically will be output pins of timer or the SCL. Timer 2 and a transmit output of the SCI. Timer 1, and the SCI RES Q sf o Pan DDR 3 £ g D 3 PORT! 3 Pan DATA & Timer 1, Timer 2 and SCI ) c ~ ‘ f\\ ' EE eee + Output Enable Signal @ HITACHI 138 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y OE Ee _: NN ee os=<: P22 (SCLK} ble as an 1/0 port when the SCI has no clock input or output (as an a, is also used as a clock 1/0 pin for the SCI. It is selected as a output port if Pz, DDR= 1, as an input port if Px DDR=0) clock input or output pin by the operating mode of the SCI. It is usa- RES a P22 DDR £ 3 a) ba P22 DATA 3 a R c 5 : ‘\\ 2 ' + Clock Input Enable signal * Clock Output Enable signal n Input Clock Pg (Rx), Pay (TCLK) Since the SCI will be a clocked synchronous mode by an external ',, and Py, are also used as received data input pins for the SCI _clock-input during reset, the DDR of P,, is cleared automatically and external clock input pins for Timer 2. The SCI and Timer 2 and P,, is an input port. Set the SCI to a mode where P,, is not used have registers which enable input. Ifthe registers are set, the DDR = (CCO or CCI of the RMC Register is “0” or “*1" respectively) and (P,3DDR, P;,DDR) are cleared and P33 and Pyy will be input write “1"" to the Py, DDR to make P,, an output port pins for Rx and TCLK ‘RES WI ~ | EY la i+) o Pz» ODR 2 c 6 fs 0} £ 2n Pas DATA ~ SCI, Timer 2. c ' - Input Enable signal ! SCI Receive Data, mae 3 — MSB fe) Pay | Pas Pog Pop | Pay | P29} PORT2 DOR ($0001) pr | DOR oR opR| DA} DOA] (Write only. $00 during reset) PORT 2 ($0003) PEPE PTS tiahzed duning reset) @HITACHI Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 139 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

——s Xs HD6303Y, HD63A03Y, HD63B03Y, HD63CO03Y © Port S Pao (IRG,), Py, (TRA) An ®bit I/O port. The DDR of port 5 controls 1/0 state. Each bit P,, and P,, are also usable as interrupt pins. The RAM/port 5 of port S has a DDR which defines 1/0 state (*“0" for input and **1"" control registers of IRQ, and IRQ, have enable bits (IQIE, 1Q2E). for output), When these bits are set to ‘1, Py, and P,, will automatically be in- During reset, the DDR of port 5 is cleared and port 5 becomes terrupt input pins, an input port. Port $ is aiso usable as IRQ,, IRQ, RATT. MR and the strobed P52 (MAI. Pgs (HALT) signal of port 6 for handshake (IS, OS). It is set to input or output P,, and Py. are also usable as MR and HALT inputs. MR and automatically if it is used as these control signal pins (except P,., FATT have enable bits (MRE, HLTE) in the RAM/Port 5 Control TS). Since the DDR of port 5, as is port 2, is set or reset by the con- Register as IRQ, and IRQ,. Since MRE is cleared during reset, Py. is trol signal, I/O directions of the I/O ports are retained after the con- usable as an I/O port, and HLTE is set during reset, the DDR of Py trol signal is disabled. Port 5 can drive one TTL load and 90pF ca- will be automatically reset to be a HALT input pin. HLTE of the Pacitance. RAM/Port 5 Control Register has to be cleared to use P,, as an I/O port RES Rm 4 | la [ Pe DOR c¢ Pa s e & —_ WP5D: OOR Write signal PORT <] la od = WPS: Port Write signal 5n Pas DATA & RPS: Port Read signal c E RAM PORT|

16 Control

L) MR AACT * Initializing value during reset; IRQIE= "0", IRO2E = “0, MRE = “0”, HLTE = "1" Py, (iS) _ output port (set the DDR of P,, to “‘1""), an output signal from P,, P,, is also usable as the input strobe (IS) for port 6 handshake will be the input to IS. interface. This pin, as is P,,, is always an I/O port. If P,, is used as an RES R la D Ps DDR c EI} a s =H <t-—f.}-- Psa DATA € c & Port 6 Control Status Register S @ HITACHI 140 Hitachi America, Ltd. * Hitachi Plaza « 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300 , www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y Pup (08) by setting the OS enable register (OSE) of the port 6 Control Status P,, is also usable as the output strobe (@S) for port 6 handshake Register (P6CSR). interface. It will be an 1/0 port during reset, and an OS output pin Res a ‘o}—4a Pss DOR g c 8 P 2 [eH < Q i») = Pss DATA ~ 9 c Port 6 Contro!/Status Register ras poe ion ee “— OSE ( 1: OS output ! 0 OS output disable) > \\ Pag. P “4, and Py, are 1/0 ports. 9 RES R a oo Ps, DDR $ a g PORT fs < ° sect Te Pox DATA Fe c F MSB LSB Pal Pac] Pas] Par] Per] Peo | PORTS DDR ($0020) sin | |e] i] a] sin] oa] BS PORTS ($0015) CSS tialized dunng reset) @HITACHI Hitachi America, Ltd. « Hitachi Plaza ¢ 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300 141 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63BO03Y, HD63C03Y © Port 6 Port 6 controls parallel handshake interface besides functions as 8-bit I/O port. Port 6 DDR controls 1/0 state. Each bit of port 6 an I/O port. Therefore, it provides DDRs to control and IS LATCH has a DDR and designates input or output (“*0" for input, “1” for to latch the input data, output). During reset, Port 6 DDR is cleared and port 6 becomes an Port 6 can drive one TTL load and 30pF capacitance. it can drive input port. directly the base of Darlington transistor as port 2. RES R 3 la O 3 Pen DOR 8 c 4 Pee DATA c wee RES RPG + WP6D DDR Write signal lb q| WP6 Port Write signal IS LATCH RP6 Port Read signal c Port 6 se ise Control Status Register Per Pos Pe: PORTS DOR 80016) rite only, $00 PORTE ($0017) {R/W, not ini- re rm [re fru ]ro] re] ro] re] reset) a@ BUS P,, are cleared and become IRQ, input pin and IRQ, input pin. © Address Bus (Ay ~ Aig) When IRQ,E and IRQ,E are set, Py, and Py, cannot be used as an Address Bus (A, ~ A,,) is used for addressing the memory and ‘output ports. When *‘0", the CPU doesn’t accept an external inter- peripheral LSI. Tupt or a sleep cancelation by the external interrupt. These bits are This bus can interface with the bus of HMCS 6800 and drive one cleared during reset TTL load aid 90pF capacitance. Bit 2 Memory Ready Enable Bit (MRE) © Date Bus (Dy ~ D,) When using P,, as an input pin of the “memory ready” signal, 8-bit parallel data bus for data transmit between the memory or write “1” in this bit. When set, P,, DDR is automatically cleared peripheral LSI. This bus can drive one TTL load and 90pF capaci- and becomes the MR input pin. The bit is cleared during reset. tance. Bit 3 Halt Enable Bit (HLTE) @ RAM/PORT 6 CONTROL REGISTER When using P,3 as an input pin of the HALT signal, write 1" in The control register located at $0014 controls on-chip RAM and this bit. When this bit is set, P,, DDR is automatically cleared and port 5. becomes the Halt input pin. If the bit is “0”, the Halt function is inhibited and P,, is used as an I/O port. The bit is set to “*1"” during RAM/Port 5 Control Register (RPSCR) reset. 26 6 4 3 2 1 0 Bit 4 Auto Memory Ready Enable Bit (AMRE) STBY stev] When the bit is set and the CPU accesses the external address, PWR FLas| HATE sore “memory ready" operates automatically and stretches the E clock’s “High” duration for one system clock. When MRE bit of bit 2 is cleared and when the CPU accesses the external address space, the Bit 0, Bit 1 TAG, IR, Enable Bit (IRQ,E, IRQZE) function operates. When MRE bit is set and then the CPU accesses ‘When using P,, and P,, as interrupt pins, write “1"" in these bits the external address space with P,,(MR) pin in “low”, “memory When the bit is set to ‘*1", the DDRs corresponding to Py. and ready” operates automatically. This bit is set to “*1"" during reset. @HITACHI 142 Hitachi America, Ltd. ¢ Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO03Y CO OS Eee eee Table 3 “’Memory Ready” Function wre | amne_| Funetion © ‘When the CPU accesses the external address, “High” duration of E clock automatically becomes one-cycle longer. This state is retained during reset. 1 f° | “Memory ready” operates by Ps2 (MR) pin. The function is the same as that of the HD6301X0. When the CPU accesses the external address space with the Ps (MR) pin in “low”, the “auto memory 1 ready” operates. This function is effective if it has both “high-speed memory” and “slow memory” outside. Input CS signal of “slow memory” to MR pin. Bit 5 Standby Fiag (STBY FLAG) this bit is cleared (=logic 0") on-chip RAM is invalid and the By clearing this flag, HD6303Y gets into the standby mode by CPU can read data from external memory. This bit should be “*0"" software. This fg is set to “*1"" during reset, so the standby mode is before getting into the standby mode to protect on-chip RAM data. canceled with pin in ‘low’. The RES pin should be in ‘low’ until oscillation becomes stable (min. 20ms.). If the STBY pin in is Bit 7 Standby Power Bit (STBY PWR) in “low”, the standby mode can not be canceled with the RES pin When Vcc is not provided in standby mode, this bit is cleared. in “low™’. This is a flag for read/write and can be read by software. If this bit is set before standyby mode, and remains set even after returning Bit 6 RAM Enable (RAME) from standby mode, Vcc voltage is provided during standby mode On-chip RAM can be disabled by this control bit. By resetung and the on-chip RAM data is valid. the MPU, “'1” is set to this bit, and on-chip RAM is enabled. When (a) MRE=0, AMRE=1 Aaaress Wags Xena sas X_agsigs XX eneroat accross) {b) MRE=1, AMRE=1 E t Hi l H i Aodress “Yai Xone Xj _evernel scaieos General sasrens >) Bus E (Sides) FA (ES pin of “slow memory") (c) MRE=1.AMRE=0 (HD6301X0 Compatible Mode) é PoP Gd Aasress Taos X_ suse X | _ external sores | Boe wan X_| [X Sates XC sugiess smn MR Figure 17 Memory Ready Timing @ Port 6 Control/Status Register The following shows Port 6 Control/Status Register (P6CSR). Tris is the Control/Status Register for parallel handshake inter- face using Port 6. The functions are as follows, 7 6 5 4 3 2 1.0 1) Latches input data to Port 6 at the TS (P.,) falling edge. eT OS mo. TATON 2) Outputs a strobe signal O5 (P.,) outward by reading or wrt [Se] eee Jose [oss] a | - | - | - | soo21 ing to port 6. 3) When IS FLAG is set at the TS falling edge, an interrupt oc curs. “Bit 7 is Read-Only bit @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 + (415) 589-8300 143 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO3Y Bito strobe. When cleared, P,, functions as an I/O port. When set, P,, Bit 1 —_ Not used. functions as an OS output pin. (P,, DDR is set by OSE.) This bit is Bit 2 cleared during reset Bit 3: Latch Enable Bit 6:15 IRQ, Enable input Strobe interrupt Enable This register controls the input latch for Port 6 (ISLATCH). When set, an IRQ, interrupt to the CPU occurs by setting IS ‘When this bit is set to ‘‘1", the input data to port 6 will be latched FLAG of bit 7. When cleared, the interrupt does not occur. This bit inward at the TS (P,,) falling edge. An input latch will be canceled by is cleared during reset. reading Port 6, which enables to latch the next data. If cleared, the input latch remains canceled and this bit functions asa usual input —~Bit 7: IS Flag Input Strobe Flag port. This bit is cleared during reset This flag is set at the IS (P,,) falling edge. This flag is for read- only. When set, the flag is cleared by reading or writing to Port 6 Bit 4:088 Output Strobe Select after reading the Port 6 Control Status Register. This bit is cleared This register initiates an output strobe (OS) from P,, by reading during reset. or writing to port 6. When cleared, OS occurs by reading Port 6. When set, OS occurs by writing to Port 6. This bit is cleared during © MEMORY MAP reset _ The MPU can address up to 65k bytes. Memory map is shown in Fig. 20. 40 addresses ($0000 ~ $0027 except $00, $02, $04, $05, Bit 6: OSE Output Strobe Enable $06, $07, $18) are the internal registers as shown in Table 4, This register decides the enabling or disabling of the output HD6303Y = Port 6 Control/Status Register isFLaG| |S IRQ: ENABLE _—-p [>a be D Figure 18 input Strobe Interrupt block Diagram L, Po Voc IMP é xtat S| a Jexrar ES ay ‘TY oF

7 HD6303Y ea

a, [) ssaress as rorrs (_) [)aaavess us MY L Figure 19 HO6303Y Operating Function @ HITACHI 144 Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 , www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y Table 4 Internat Register a Initialized value 00° _| Port 1 DOR (Data Direction Register) P1DOR Ww SFE ot Port 2 DDR P2D0R w $00 02" = [Port PORT! RW indefinite

03 Port 2 PORT2 Rw indefinite

04° =| Port 3 DDR P300R w SFE os* Port 4DOR PADDR w $00 oe" Port 3 PORT3 RW indefinite o7 = | Pon PORTS RW indefinite

08 Timer Control/Status Register 1 TCSRI RW $00

og Free Running Counter (MSB) FRCH RW $00 OA _| Free Running Counter (LSB) FRCL RW $00 oB ‘Output Compare Register 1 (MSB) OCRIH RW SFF oc ‘Output Compare Register 1 (LSB) OCRIL RW SFF op Input Capture Register (MSB} ICRH R $00 OF Input Capture Register (LSB) ICRL R $00 OF Timer ControV/Status Register 2 TCSR2 RW $10

10 Rate/Mode Control Register RMCR | Rw $co

" Tx/Rx Control Status Register 1 TRCSA1 RW $20

12 Receive Data Register ROR , OR $00

13 Transmit Data Register TOR w indefinite

14 RAM/Port 5 Control Register APSCR RW SFB or $78

16 Port 5 PORTS RW indefinite

16 Port 6 DDR PEDOR w $00

W7 Port 6 PORT6 RW indefinite 18 Port7 PORT? RW indefinite 2

19 Output Compare Register 2 (MS8) OCR2H RW SFF

1A Output Compare Register 2 (LSB) Ocr2L RW SFF

18 Timer Control/Status Register 3 TCSR3 RW $20

1c Time Constant Register TCONR w SFF

10 Timer 2 Up Counter T2CNT RW $00

1E Tx/Rx Control Status Register 2 TRCSR2 RW $28 iF? | Test Register” TSTREG - -

20 PORT 5 DDR PSDOR w $00

21 | PORT 6 Control/Status Register P6CSR Rw | $07 22 =— - - ~ 23 _ - - - zs = Reserved = = = 26 =_ - - - 27 — - - - * External address Read-only register, W: Write-only register, RW Read/Write register * When empty bit is in the register. itis set to “1"" **** Register for test. Don’! access this register @HITACHI Hitachi America, Ltd. « Hitachi Plaza « 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 145 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63BO03Y, HD63CO3Y $0000 ‘© Output Compare Register (OCR) $0027 The output compare register is a 16-bit read/write register which = can control an output waveform. The data of OCR is always com- P| pared with the FRC. $0040 When the data matches, output compare flag (OCF) in the timer lnternal RAM control/status register (TCSR) is set. If an output enable bit (OE) in

256 Bytes the TCSR2 is ““1", an output level bit(OLVL) in the TCSR will be

$013F output to bit | (OCR 1) and bit 5 (OCR 2) of port 2. To control the output level again by the next compare, the value of OCR and OLVL should be changed. The OCR is set to SFFFF at reset. The ‘compare function is inhibited for a cycle just after a write to the up- per byte of the OCR or FRC. This is to set the 16-bit value valid in the counter register for compare. In addition, it is because counter ai is to set SFFF8 at the next cycle of the CPU's upper byte write to . the FRC Sees * For data write to the FRC of the OCR, 2-byte transfer in- struction (such as STX, etc.) should be used. © Input Capture Register (ICR) ($000D : 000E) The input capture register is 2 16-bit read-only register which stores the FRC’s value when external input signal transition gener- SFFFF ates an input capture pulse. Such transition is controled by input edge bit (IEDG) in the TCSR1. “This mode does not In order to input the external input signal to the edge detector, a include the addresses. bit of the DDR corresponding to bit 0 of port 2 should be cleared $00. 502. $04, $05, (“0”). When an input capture pulse occurs by external input signal Sone ase eee transition at the next cycle of CPU's high-byte read of the ICR, the input capture pulse will be delayed by one cycle. In order to ensure the input capture operation, a CPU read of the ICR needs 2-byte , transfer instruction. The input pulse width should be at least 2 sys- Figure 20 HD6303Y Memory Map tem cyctes. This register is cleared ($0000) during reset. m TIMER? © Timer Control/Status Register 1 (TCSR1) ($0008) The HD6303Y provides a 16-bit programmable timer which can The timer controi/status register 1 is an 8-bit register. All bits are simultaneously measure an input waveform and generate two inde- _readable and the lower 5 bits are also writable. The upper 3 bits are Pendent output waveforms. The pulse widths of both input/output read-only which indicate the following timer status. waveforms vary from microseconds to seconds. Bit S The counter value reached to $0000 as a result of coun- Timer 1 is configured as follows (refer to Fig. 22). ting-up (TOF). + ControW/Status Register 1 (8 bit) Bit 6 A match has occurred between the FRC and the OCR 1 + Control/Status Register 2 (7 bit) (OcFI) + Free Running Counter (16 bit) Bit 7 Defined transition of the timer input signal causes the + Output Compare Register 1 (16 bit) counter to transfer its data to the ICR (ICF). + Output Compare Register 2 (16 bit) The followings are the each bit descriptions. + Input Capture Register (16 bit) © Free-Running Counter {FRC)($0009:000A) Timer Controv/Status Register 1 The key timer element is a 16-bit free-running counter driven 2 68 5 4 3 21 9 and incremented by system clock. The counter value is readabie by Software without affecting the counter. The counter is cleared dur- [et [ocr] 7%] eer coer era nef oeves $0008 ing reset. ‘When writing to the upper byte ($09), the CPU writes the preset value (SFFF8) into the counter (address $09, $0A) regardless of Bit © OLVL1 Output Level 1 the write data value. But when writing to the lower byte (SOA) after OLVL) is transferred to port 2, bit 1 when a match occurs be- the upper byte writing, the CPU writes not only lower byte data into tween the counter and the OCRI. If bit 0 of the TCSR2 (El), lower 8 bit, but also upper byte data into higher 8 bit of the FRC is set to ‘1", OLVLI will appear at bit 1 of port 2. The counter will be as follows when the CPU writes to itbydou- Bit 1‘ IEDG Input Edge ble store instructions (STD, STX, etc.) This dit determines which edge, rising or falling, of input sig- nal of bit 0 of port 2 will trigger data transfer from the counter to the ICR. For this function, the DDR corresponding to por 2, bit should be cleared beforehand $08 Write $OA Write IEDG=0, triggered on a falling edge “High” to “Low") TEDG= 1, triggered on a rising edge E (“Low” to “High") Counter value : $FFFB : S5AF3 7 Bit 2 ETO! Enable Timer Overfiow Interrupt In the case of the CPU write ($ 5AF3) to the FRC ‘When this bit is set, an internal interrupt (IRQ,) by TOI inter- Tupt is enabled. When cleared, the interrupt is inhibited. Figure 21 Counter Write Timing Bits EOCI1 Enable Output Compare interrupt 1 @ HITACHI 146 Hitachi America, Ltd. Hitachi Plaza « 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y When this bit is set, an internal interrupt (IRQ,) by OCH in- Bit 7_—_ The same status flag as the ICF flag of the TCSR1, bit 7. terrupt is enabled. When cleared, the interrupt is inhibited. The foliowings ure the each bit descriptions. Bit 4 EICI Enable Input Capture interrupt When this bit is set, an internal interrupt (IRQ,) by ICI inter- Bit 0_OE¥ Output Enable 1 rupt is enabled. When cleared, the interrupt is inhibited This bit enables the OLVL! to appear at port 2, bit | when a Git 5 TOF Timer Overtlow Flag match has occurred between the counter and the output com. This read-only bit is set when the counter increments from pare register 1. When this bit is cleared, bit I of port 2 will be an SFFFF by 1. Cleared when the counter's MSB byte ($0009) is 1/0 port. When sei, it will be an output of OLVLI automatically. read by the CPU after the TCSRI read at TOF=1 Bit! OE2 Output Enable 2 Bit 6 OCF Output Compare Flag 1 This bit enables the OLVL2 to appear at port 2, bit 5 when a This read-only bit is set when a match occurs between the match has occurred between the counter and the output com- OCR1 and the FRC. Cleared when writing to the OCR! ($000B pare register 2. When this bit is cleared, port 2, bit $ will be an I/ ‘or $000C) after the TCSR1 or TCSR2 read at OCF=1. port. When set, it will be an output of OLVL?2 automatically Bit 7 IGF Input Capture Flag Bit 2 OLVL2 Output Levet 2 This read-only bit is set when an input signal of port 2, bit 0 OLVL? is transferred to port 2, bit 5 when a match has oocur- makes a transition as defined by IEDG and the FRC is transfer- red between the counter and the OCR2. ff bit 5 of the TCSR2 red to the ICR. Cleared when reading the upper byte ($000D) of (OE2), is set to “1”, OLVL2 will appear at port 2, bit 5. the ICR after the TCSR1 or TCSR2 read at ICF=1 Bit 3 EOCIZ Enable Output Compare Interrupt 2 When this bit is set, an internal interrupt (IRQ,) by OCI2 in- © Timer Control/Status Register 2 (TCSR2) ($000F) terrupt is enabled. When cleared, the interrupt is inhibited. The timer control/status register 2 is a 7-bit register. All bits are Bit 4 Not used readable and the lower 4 bits are also writable. But the upper 3 bits «Bit B__—_ OCF2 Output Compare Flag 2 are read-only which indicate the following timer status. ‘This read-only bit is set when a match has occurred between Bit $A match has occurred between the FRC and the OCR2 the counter and the OCR2. Cleared when writing to the OCR2 (OCF2). ($0019 or $001A) after the TCSR2 read at OCF2=1 Bit 6 Bit 6 —OCF1 Output Compare Flag 1 Bit 7 _ ICF Input Capture Flag Timer Control/Status Register 2 OCF and ICF are dual addressed. If which register, TCSR1 or TCSR2, CPU reads, it can read OCF! and ICF to bit 6 and bit 1 8 ss 3 21% Both the TCSRI 4 TCS! b 4 joth the TCSRI and TCSR2 will be cleared during reset. [1 Joer|ocr - [roospnafoez for] soon (Note) If OE1 of OE2 is set to “1” before the first output com- pare match occurs after reset restart, bit | or bit 5 of port 2 will produce ““0™ respectively _ ~HD6303. internet Dow Bus Output Compare ‘Output Compare Free Running Tapa Capture Regester 2 Register 1 16 Ba Counter Register TT Sa) Ga) —- a aes | Ho > al opted |e, | | oye TesA — Le | | jo on a ee ar) = fle food TCSR2 A ‘wo, | $0F -O a Figure 22 Timer 1 Block Diagram @ HITACHI Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 (415) 589-8300 147 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y Se nc tt @ TIMER 2 selected by TOSO and TOS} of the TCSR3 will appear at port 2, bit In addition to the timer 1, the HD6303Y provides an 8-bit re- 6. When CMF is set, the counter will be cleared simultaneously and loadable timer, which is capable of counting the external event. The then start counting from $00. This enables regular interrupts and timer 2 contains a timer output, so the MPU can generate three in- waveform outputs without any software support. The TCONR is set dependent waveforms. (Refer to Fig. 23.) to “SFF” during reset. The timer 2 is configured as follows: + Control/Status Register 3 (7 bits) © Timer Controi/Status Register 3 (TCSR3) ($001B) + 8-bit Up Counter The timer control/status register 3 is a 7-bit register. All bits are + Time Constant Register (8 bits) readable and 6 bits except for CMF can be written. The followings are each pin descriptions. © Timer 2 Up Counter (T2CNT) ($001D) This is an 8-bit up counter which operates with the clock decided Timer Control/Status Register 3 by CKSO and CKS1 of the TCSR3. The CPU can read the value of the counter without affecting the counter, In addition, any value ul 6 4 3 2 4 0 can be written to the counter by software even during counting cmrlecmi] — Tosi] roso soos The counter is cleared when a match occurs between the counter and the TCONR or during reset If the write operation is made by software to the counter at the cycle of counter clear, it does not reset the counter but put the write Bit CKSO Input Clock Select 0 data to the counter. Bit! CKS1 Input Clock Select 1 Input clock to the counter is selected as shown in Table 5 de- © Time Constant Register (TCONR) ($001C) Pending on these two bits. When an external clock is selected, The time constant register is an 8-bit write only register. The bit 7 of port 2 will be a clock input automatically. Timer 2 detects data of register is always compared with the counter. the rising edge of the external clock and increments the counter. When a match has occurred, the counter match flag (CMF) of The external clock is countable up to half the frequency of the the timer control status register 3 (TCSR3) is set and the value system clock ig! Tt Timert FRC Clock ' ime Input 1 Constant C] Clock Port 2 Register Select ' Bit 7 Output : Level ¢ Port 2 ike ne : “ [eee] - [om fonfendes fois IRQs ol | Figure 23 Timer 2 Block Diegram @ HITACHI 148 Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

a HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y Table § input Clock Select selected by CKS1 and CKSO (Table 5) is input to the up counter. (Note) Py, outputs “0” when T2E bit cleared and timer 2 set in output enable condition by TOS! or TOSO. It also outputs cKs1 | cxso_ | Input Clock to the Counter “0” when T2E bit set “1°” and timer 2 set in output ena- 00 | Eelock ble condition before the first counter match occurs.

3 E clock 8" Bit 8 Not Used

ck Bit 6 ECMI Enable Counter Match Interrupt 1 [0 | __ Eclock/128" ‘When this bit is set, an internal interrupt (IRQ,) by CMI is +t [External clock enabled. When cleared, the interrupt is inhibited. Bit 7 CMF Counter Match Flag * These clocks come from the FRC of the timer 1. If one of these clocks is This read-only bit is set when a match occurs between the up ‘selected as an input clock to the up counter, the CPU should not write to counter and the TCONR. Cleared by writing “*0" at CMF= 1 by the FRC of the timer 1 software (unable to write ‘*1" by software) Each bit of the TCSR3 is cleared during reset Bit 2 TOSO Timer Output Select 0 Bit 3 TOS1 Timer Output Select 1 = SERIAL COMMUNICATION INTERFACE (SC!) ‘When a match occurs between the counter and the TCONR The Serial Communication Interface (SCI) in the HD6303¥ timer 2 outputs shown in Table 6 will appear at port 2, bit 6 de- contains the following two operating modes: asynchronous mode by pending on these two bits. When both TOSO and TOSI are "0", the NRZ format, and clocked synchronous mode which transfers bit 6 of port 2 will be an 1/0 port. data synchronously with the clock. In the asynchronous mode, data length, parity bits and number of stop bits can be selected, and eight Table 6 Timer 2 Output Select transfer formats are provided. The SC! consists of the following registers as shown in Fig. 24 [_tos0_| Block Diagram. Tosi | Toso Timor Output ~ Transmit/Receive Control Status Register 1 (TRCSR1) © | © | Timer Output inhibited + Rate/Mode Control Register (RMCR) o| 1] Togle Output" + Transmit/Receive Control Status Register 2 (TRCSR2) = + Receive Data Register (RDR) T [9 | output “o' + Recevie Shift Register ae ee + Transmit Data Register (TDR) ~ Transmit Shift Register * When a match occurs between the counter and the TCONR, timer 2 To operate the SCI, initialize the RMCR and TRCSR2, after output level is reversed. This leads to production of # square wave with selecting the desirable operating mode and transfer format. Next, 50% duty to the external without any software support set the enable bit (TE or RE) of the TRCSR1. Operating mode and transfer format should be changed when the enable bit (TE, RE) is cleared. When setting the TE or RE again after changing the operat- Bit 4 —T2E Timer 2 Enable Bit ing mode of transfer format, interval of more than a 1-bit cycle of When this bit is cleared, a clock input to the up counter is the baud rate or bit rate is necessary. If a 1-bit cycle or more is not inhibited and the up counter stops. When set to “1"", a clock allowed, the SCI block may not be initialized Panty Check Generator TRCSR2 se rob to TAcsAt ol TTT LTT J] | bembrcbond mele [eel [oe] ef TILT TT) | Cadets [re] {| Transmit Shift Register Bit Rate Tamer 1 FRC ] Generator Timer 2 [re] Figure 24 SCI Block Diagram @HITACH! Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 149 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO3Y eee eee eee eC‘ © Asynchronous Mode the contents of the TRCSR2 and RMCR at first, and set RE bit of Asynchronous mode contains 8 transfer formats as shown in TRCSRI. The first “0” (space) synchronizes the receive bit flow. Fig. 25. Each bit of the following data will be strobed in the middle. If'a stop Data transmission is enabled by setting TE bit of the TRCSR1, bit is not “I”, a framing error assumed and ORFE is set then port 2, bit 4 will unconditionally become a serial output inde- When a framing error occurs, receive data is transferred to the pendently of the corresponding DDR Receive Data Register and the CPU can read the error-generating To transmit data, set the desirable transmit format with RMCR _ data. This makes it possible to detect a line break. and TRCSR2. When the TE bit is set, the data can be transmitted When PEN bit is set, the parity check is done. If the parity bit after transmitting the one frame of preamble (“1”). does not match the EOP bit, a parity error occurs and the PER bit is The conditions at this stage are as follows. set, nol the RDRF bit. Also, when the parity error occurs the re- 1) If the TDR is empty (TDRE=1), consecutive I's are pro- ceive data can be read just like in the case of the framing error. duced to indicate the idle state The RDRF flag is set when the data is received without a fram- 2) If the TDR contains data (TDRE=0), data is sent to the —_ing error and a parity error. Transmit Shift Register and data transmit starts IERDRF is still set when receiving the stop bit of the next data, During data transmit, a start bit of "0" is transmitted first. Then ORFE is set to indicate the overrun generation, CPU can get the re. 7-bit or 8-bit data (starts from bit 0) is transmitted. With PEN=1, _ceive data by reading RDR. When 7 bit data format is selected, the the parity bit, even or odd, selected by EOP bit is added, lastly the 8th bit of RDR is “0”. stop bit (1 bil or 2 bis) is sent When the CPU read the receive Data Register as a response to When the TDR is “empty”, hardware sets TDRE flag bit. Ifthe RDRF flag or ORFE flag afier having read TRCSR. RDRF o- CPU doesn’t respond to the flag in proper timing (the TDRE is in ORFE is cleared, set condition till the next normal data transfer starts from the trans- (Note) Clock Source in Asynchronous Mode mit data register to the transmit sift register), ““1"" is transferred in- If CC1:CCO= 10, the internal bit rate clock is provided at P,, stead of the start bit “0” and continues to be transferred till data is regardless of the values for TE or RE. Maximum clock rate is provided to the data register. While the TDRE is “1"", “0” is not E+16. transferred. If both CCI and CCO are set, an external TTL compatible clock Data receive is possible by setting RE bit. This makes port 2, Must be connected (0 P,, at sixteen times (16x ) the desired bit bit 3a serial input. The operation mode of data receive is decided by rate, but not greater than E. x) [stan] yet oats sto] ai CS (# [stay] yeroaa—sdpaniry] aston _] «7 [Bran] 8B Data Paring stor] 2s Ec 0 Ta Figure 25 Asynchronous Mode Transfer Format © Clocked Synchronous Mode When an external clock input is selected and the TDRE fag is In the clocked synchronous mode, data transmit is synchronized “0, data transmit is performed from port 2, bit 4, synchronizing with the clock pulse. The HD6303Y SCI provides functionally inde-_with’8 clock pulses input from external to port 2. bit 2. pendent transmitter and receiver which makes full duplex operation Data is transmitted from bit 0 and the TDRE is set when the Possible in the asynchronous mode. But in the clocked synchronous Transmit Shift Register (TSR) is “‘empty"". More than 9th clock mode an SCI clock 1/0 pin is only P,., $0 the simultaneous receive _pulse of external are ignored. and transmit operation is not available. In this mode, TE and RE When data transmit is selected to the clock output, the MPU should not be in set condition ("1") simultaneously. Fig. 26 gives a produces transmit data and synchronous clock at TDRE flag clear. synchronous clock and a data format in the clocked synchronous 2) Data receive mode. Data receive is enabled by setting RE bit. Port 2, bit 3 will be a 1) Data transmit serial input. The operating mode of data receive is decided by the Data transmit is realized by setting TE bit in the TRCSR1. Port TRCSRI and the RMCR. 2, bit 4 becomes an output unconditionally independent of the Ifthe external clock input is selected, 8 external clock pulses and Value of the corresponding DDR. the synchronized receive data are input to port 2, bit 2 and bit 3 re- Both the RMCR and TRCSR should be set in the desirable oper-_spectively. The MPU put receive data into the receive data shift reg. ating condition for data transmit. ister by this clock and set the RDRF flag at the termination of 8 bit @HITACHI 150 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO3Y I a data receive. More than 9th clock pulse of external input are ig- ceive data should be input from external synchronously with this nored, When RDRF is cleared, the MPU starts receiving the next clock. When the first byte data is received, the RDRF Nag is set. data instantly. So, RDRF should be cleared with P,, ‘“High” After the second byte, receive operation is performed by sending When data receive is selected with the clock output, 8 syn- the synchronous clock 10 the external after clearing the RDRF bit. chronous clocks are output to the external by setting RE bit. So re- $F Transmit Direction Synchronous clock Z » Bree fefetefeleleVZ YA ZZ Nor Vali = Transmit data is produced (rom a falling edge of @ synchronous clock to the next falling edge. + Receive data is latched at the rising edge. Figure 26 Clocked Synchronous Mode Format . i i R Bit 5 TORE Transmit Data Register Empty Tegnamit/Receive Control Stetus Reaister trresny) TRE is set by hardware when the TDR is transferred to the The TRCSR1 is composed of 8 bits which are all readable. Bits 0 Transmit Shift Register in the asynchronous mode, while in to 4 are also writable. This register is initialized to $20 during reset. clocked synchronous mode when the TDSR is “empty”. This Each bit functions are as follows. bit is cleared by reading the TRCSRA or TRCSR2 and writing new transmit data to the TDR when TDRE=1 TDRE is set to | , “1° during reset Transmit/Receive Control Status Register Bite Onte “Overrun Framing Error 26 43° 2 1 0 ORFE is set by hardware when an overrun or a framing error is generated (during data-receive only). An overrun error occurs [rom forefrone| me T me [ ve] re] we] soot when new receive data is ready to be transferred to the RDR during RDRF still being set. A framing error occurs when @ stop bit is “0”. But in clocked synchronous mode, this bit is not af- fected. This bit is cleared by reading the TRCSR1 or TRCSR2, Bit WU Wake-up and the RDR, when RDRF=1. ORFE is cleared during reset. In a typical multi-processor configuration, the software pro: Bit 7 RDRF Receive Data Register Full tocol provides the destination address at the first byte of the RDRF is set by hardware when data is received normally and message. In order to make uninterested MPU ignore the re- transferred from the Receive Shift Register (RSR) to the RDR. maining message, a wake-up function is available. By this, unin- This bit is cleared by reading TRCSRI or TRCSR2, and the terested MPU can inhibit all further receive processing till the RDR, when RDRF=1. This bit is cleared during reset next message starts. Then wake-up function is triggered by consecutive Is with | © Transmit Rate/Mode Control Register (RMCR) frame length. The software protocol should provide the idle time The RMCR controls the following serial 1/0: between messages. + Baud Rate + Data Format By setting this bit, the MPU stops data receive till the next + Clock source + Port 2, Bit 2 Function message. The receive of consecutive *“I"" with one frame length + Operation Mode wakes up and clears this bit by hardware and then the MPU re- Alt bits are readable/writable. Bit 0 10 5 of the RMCR are cleared starts receive operation. However, the RE flag should be already during reset. set before setting this bit, In the clocked synchronous mode WU is not available, so this bit should not be set. Transfer Rate/Mode Control Register Bit 1 TE Transmit Enable When this bit is set, transmit data will appear at port 2, bit 4 2? 6 5 4 3 2 1 0 after one frame preamble in asynchronous mode, while in ecuted regardless of the value of the corresponding DDR. When TE is cleared, the serial 1/0 doesn't affect port 2, bit 4 Bit 2 THE Transmit Interrupt Enable Bito sso When this bit is set, an internal interrupt (IRQ,) is enabled Bit 1. SS1_—_—_Speed Select when TDRE (bit 5) is set. When cleared, the interrupt is Bit $ —- SS2 inhibited Bit3 RE Receive Enable These bits control the baud rate used for the SCI. Table 7 lists When set. a signal is input to the receiver from port 2, bit 3 the available baud rates. The timer 1 FRC (SS2=0) and the timer 2 regardless of the value of the DDR. When RE is cleared, the up counter (SS2= 1) provide the internal clock to the SCI. When serial 1/0 doesn’t afffect port 2, bit 3 selecting the timer 2 as a baud rate clock source, it functions as a Bit 4 RIE Receive Interrupt Enable baud rate generator. The timer 2 generates the baud rate listed in When this bit is set, an internal interrupt (IRQ,) is enabled Table 8 depending on the value of the TCONR when RDRF (bit 7) of ORFE (bit 6) is set. When cleared, the (Note) When operating the SCI with internal clock, do not per- interrupt is inhibited. form write operation to the timer/counter which is the @HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 151 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO3Y ee eeeee— Table 7 SCIBit Times and Transfer Rates (1) Asynchronous Mode XTAL 4.9152Me $82_8s1_ss0 G | 6iaacne 1228aMH 000 m6 76 15/38400Ba0d | 165/62500Ba0d ~~ | 1313/7 6800Ba00 0 0 1) eFi28 208.8/480080ud | 1285/7812 SBeud | 104 2..5/9800Baud o + 0! — €-1024 1 671ms/6008aud | 1 024ms/976 6Baud | 633 3.5/1200B004 °o ’ it £+ 4096 6 6 7ms/150Baud 4096ms/244 1Baua | 3.333ms/300Baud 1 - - * . + * When SS? is “1”, Timer 2 provides SCI clocks. Fhe baud rate is shown as follows with the TCONR as N. _ it {input clock frequency to the Neo~ 355 (2) Clocked Synchronous Moge* oo Oo E-2 2 pit 133 psi 1 psbit 0.667 y/o 0 0 4 E-16 | 16 ys/bit 10.7 ,sibit Busi 5.33 s/o o 1 0 E - 128 128 ,sibit 85.3 sibit 64 stot 42.7 nsibit ’ ‘ ia f 7 in a “Bit rates in the case of internal clock operation In the case of external clock operation. the external clock is operatable up to DC ~ 1/2 system clock ‘** The bit rate is shown as fullows with the TCONR as N. it) = 40Ne1) f input clock frequency to the N=0~ 255 Table 8 Baud Rate and Time Constant Register Example 110 | 2 ry 35 aw 70" 150 | 127 19? | 207 295 st 300 | 63 ns) 127 207

600 Ey o | 51 63103

1200 Hl 1s 23 25 ca) st

4800 | 3 Ss | | 7 12 3600 1 2 - 3 - 19200 - | = 1 2 38400 - if - ia - ° - —— 2 * E/8 clock is input to the timer 2 up counter and E clock otherwise Table 9 SCI Format and Clock Source Control Gea C1 00 | Fox Mode | Gioa Souce [Pow 2.000] Pou? 803] _Pontane Oo oO O | Bbit data | Clocked Synchronous | External Input 1 tr As hronous Internat Not Uses” oe Borders | Arve ene a When the TRCSRI, RE bit 16 "1", © = 1G | Bbitdata_| Asynchronous H internat Output” 4) Sit 3 is used as a serial input ° 1 1 B-bit data | Asynchronous External Input | 1 oO oO B-bit data | Clocked Synchronous | Internal Output i 1 cy 1 Pit deta | Asynchronous Internat Not Used"* | . When the TACSR1, TE bit is "1", 1 10] 7bit data | Asynchronous | toternat Outport iit a i ube Sea riot Doon, 1 ttf rit data | Asynchronous External Input * Clock output regardless of the TROSR 1, bit RE and Th ** Not used for the SCL @ HITACHI 152 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

i HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y clock source of the SCI. If this bit is "0", the stop bit is 1-bit. If "1", the stop bit is 2-bit. This bit is cleared during reset Bik2 cco Bit 1 EOP Even/Odd Parity Bit 3 CC1 —_ Clock Control/Format Select® This bit selects the parity generated and checked when the Bit4 C2 PEN is ‘“1". If this bit is “0", the parity is even. If “1”, itis odd This bit is cleared during reset ‘These bits control the data format and the clock source (refer to Bit 2 PEN Parity Enable Table 9). This bit decides whether the parity bit should be generated * CCO, CCI and CC2 are cleared during reset and the MPU and checked in the asynchronous mode or not. If this bit is “0”, goes to the clocked synchronous mode of the external clock the parity bit is neither generated nor checked. If 1", itis gen- ‘operation. Then the MPU automatically set port 2, bit 2 into erated and checked. This bit is cleared during reset. the clock input state. When using port 2, bit 2 as an output ‘The 3 bits above do not affect the SC! opertion in the clocked port, the DDR of port 2 should be set to ‘*1"" and CCI and synchronous mode. CCO to 0" and **1"" respectively. Bit 3 Not Used Bit 4 PER Parity Error Bit 6 Not Used This bit is set when the PEN is ‘*1"" and a parity error occurs. Bit 7 Not Used It is cleared by reading the RDR after reading the TRCSR2, when PER=1 © Transmit/Receive Control Status Register 2 (TRCSR2) BitS TORE The TRCSR? is a 7-bit register which can select 2 data format in Transmit Data Register Empty the asynchronous mode. The upper 3 bits are the same address as Bit6 ORFE the TRCSRI. Therefore, the RDRF, ORFE and TDRE can be read ‘Overrun/Framing Error by either the TRCSR1 or TRCSR2. Bits 0 to 2 of the TRCSR2 are Bit 7 — RDRF used for read/write. Bits 4 to 7 are used only for read. Receive Data Register Futl + Each flag of the TDRE, ORFE, and RDRF can be read from Transmit/Receive Controt Status Register 2 either the TRCSRI or TRCSR2 7 6 5 4 3 2 1 9 Ga a a 2 Bit 0 SBL_ Stop Bit Length This bit selects the stop bit length in the asynchronous mode. {@ PRECAUTION 1 The clock-output of case | or case 2 is determined by “1” or “0” In the synchronous clocked receive operation with clock-output, of SCI internal operation clock of RDRF clearing cycle. In addition, there are three cases for clock pulse timing after RDRF clear as in the case of low voltage operation (Voc < 4.5V), the clock-output shown below. of case | may transfer to case 3 Please consider above in designing system, since transmitting receiving time is not uniform. ROR read cycle (RORF clear) PL FTLIFLEA LF LS Lt bitd clock-output —] | ott case 1 t bit case 2 t bit 0 case 3 J (note) Whenbitrateis €/2, t,=E, and t= 2E. £/16, t= BE. ty = 16E. Diagram for Precaution 1 @HITACHI Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 * (415) 589-8300 153 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y eee eemESEOEeeeee PRECAUTION 2 If transmit data is written to TDR, and then TE bit is cleared with When transmitting through clock-synchronous serial communi- - TDRE = 0 to stop transmitting, TDRE remains “0”. cation interface, TE bit should not be cleared with TDRE of TRCSR In this case, even if TE bit is set and transmit data is written again, (Sl) is “0” the TDR data is not transmitted. The TDRE set and clear conditions of SCI are shown as follows. Please note that TE bit must be cleared after the last data has been transmitted Clear condition (This caution is not applied to asynchronous serial communica- 1. TOR — transmit When writing to TOR tion interface.) shift register after TRSCR read, (asynchronous) with TORE = 1, TORE = TIMER, SCI STATUS FLAG TDRE | 2. Transmit shift is cleared. Table 10 shows the set and reset conditions of each status fag in register is empty. the timer 1, timer 2 and SCI (clock-synchronous) 3. RES =0 Table 10 Timer 1, Timer 2 and SCI Status Flag [| Set Condition Clear Condition P6CSR Falling edge input to Pg, (S) 1. Read the PECSR then read or write the PORTE, when IS FLAG = 1 2. RES=0 ICF FRC —= ICR by Rising or Falling edge input to 1. Read the TCSR1 or TCSR2 then ICRH, | P2o when ICF = 1 (Selecting with the IEOG bit) 2 RES=0 ocr OCRI = FRC 1. Read the TCSA1 or TCSR2 then write to the OCR1H or OCR1L, when OCF1 = 1 2. RES=0 Timer OcF2 ‘OCR2 = FRC 1. Read the TCSR2 then write to the OCR2H 1 or OCR2L. when OCF2 = 1 } 2. RES=0 TOF FRC = $FFFF+ 1 cycle 1, Read the TCSR1 then FRCH, when TOF=1 2. RES=0 Timer CMF T2CNT = TCONR 1. Write “0” to CMF, when CMF = 1 2 2. RES=0 RORF Receive Shift Register — ROR 1. Read the TRCSR1 or TRCSR2 then ROR, when RORF = + 2. RES=0 1. Framing Error (Asynchronous Mode) 1. Read the TRCSR1 or TRCSR2 then ROR, when Stop Bit = 0 ORFE = 1 2. Overrun Error (Asynchronous Mode} 2. .RES=0 Receive Shift Register — RDR when scl RORF = 1 TORE 1. Asynchronous Mode Read the TRCSR1 or TRCSR2 then write to the TOR — Transmit Shift Register TOR, when TORE = 1 2. Clocked Synchronous Mode Transmit Shift Register is “empty” 3. RES=0 Parity when PEN= 1 1. Read the TRCSR2 then ROR, when PER=1 2. RES=0 (Note) — ; Transfer = ; equal ICRH, Upper byte of ICR OCRIL; Lower byte of OCR1 OCR1H; Upper byte of OCR OCR2L; Lower byte of OCR2 OCR2H, Upper byte of OCRZ FRCH; Upper byte of FRC @ HITACHI 154 Hitachi America, Ltd. ¢ Hitachi Plaza » 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y ms LOW POWER DISSIPATION MODE This sleep mode is effective to reduce the power dissipation for a The HD6303Y provides two low power dissipation modes, sleep _system with no need of the HD6303Y's consecutive operation and standby. ©. Standby Mode © Sleep Mode The MPU goes to the standby mode with the STBY ‘‘Low” or The MPU goes to the sleep mode by SLP instruction execution. _by clearing the STBY flag. In this mode, the HD6303¥ stops all the In the sleep mode, the CPU stops its operation, while the registers’ clocks and goes to the reset state. In this mode, the power dissipa- contents are retained. in this mode, the peripherals except the CPU _tion is reduced to several »A. During standby, all pins, except the such as timers, SCI, etc. continue their functions. The power dis- power supply (Voc, Vsg), the STBY, RES and XTAL (which out- sipation of sleep-condition is one fourth that of operating condition puts ‘“0"), go to the high impedance state. In this mode, power The MPU returns from this mode by an interrupt, RES or (Vcc) is supplied to the HD6303Y, and the contents of RAM is re- STBY; it goes to the reset state by RES and the standby mode by tained. The MPU returns from this mode during reset. When the “STBY. When the CPU acknowledges an interrupt request, it cancels MPU goes to the standby mode with STBY “Low”, it will restart at the sleep mode, returns othe operation mode and branches to the _the timing shown in Fig. 27(a). When the MPU goes to the standby interrupt routine. When the CPU masks this interrupt, it cancels mode by clearing the STBY flag, it will restart only by keeping the the sleep mode and executes the next instruction. However, for ex- RES “Low” for longer than the oscillating stabilization time. (Fig. ample, if the timer 1 or 2 prohibits a timer interrupt, the CPU 27(b)) doesn’t cancel the sleep mode because of no interrupt request. vee

1 Re |

— 1 a H i HD6303Y s RES ' 2 : > io \\

2 Sey j | l '

toy : ' pal tot 1 ot v foe — oh — 2} Ves Ves Standby Mode © Oscitator, — © Save Registers Start ° pawiron 8 Control Register Set Tine Restart (a) Standby Mode by STBY Vee ss . “Ly HD6303Y je ‘a> H Standby Mode | t OSTBY FLAG © Oscitator, Clear sen Te Restart RES | I> Mp LJ (b) Standby Mode by the STBY Flag Figure 27 Standby Mode Timing @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 155 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y eS eee m= TRAP FUNCTION ts como and (TRAP) when fetching an undefined instruction of an instruction from non-memory space. The TRAP prevents the system-burst a a cee caused by noise or a program error © Op Code Error | a a et When fetching an undefined op code, the CPU saves registers as. well as a normal interrupt and branches to the TRAP (SFFEE, Preven Onetet SFFEF). This has the priority next to reset. A , CLT TED[(] coneree corte ccm © Address Error cor eren eno When an instruction fetch is made from the address of internal ore register, the MPU generaters an interrupt as well as an op code sere error. But on the system with no memory in its external memory ae areemen area, this function is not applicable if an instruction fetch is made from the external non-memory area. Addresses where an address Figure 28 CPU Programming Model error occurs are from $0000 to $0027 This function is available only for an instruction feich and is not _the address where a data is stored. 256 bytes (80 through $255) can applicable 10 the access of normal data read/write. be addressed directly. Execution times can be reduced by storing (Note) The TRAP interrupt provides @ retry function differently _ data in this area so it is recommended to make it RAM for users" from other interrupts. This is a program flow return to the data area in configurating a system. This is @ 2-byle instruction, address where the TRAP occurs when a sequence returns while 3 byte with regard to AIM, OIM, EIM and TIM. to a main routine from the TRAP interrupt routine by Extended Addressing RTI. The retry can prevent the system burst caused by In this mode, the second byte shows the upper 8 bit of the data noise, etc stored address and the third byte the lower 8 bit. This indicates the However, if another TRAP occurs, the program repeats absolute address of 3 byte instruction in the memory the TRAP interrupt forever, so the consideration is neces- Indexed Addressing sary in programming The second byte of an instruction and the lower 8 bit of the in- dex register are added in this mode. As for AIM, OIM, EIM and @ INSTRUCTION SET TIM, the third byte of an instruction and the lower 8 bits of the in- The HD6303Y provides object code upward compatible with the dex register are added HD6801 to utilize all instruction set of the HMCS6800. It also re- This carry is added to the upper 8 bit of the index register and duces the execution times of key instructions for throughput im- _the result is used for addressing the memory. The modified address provement. is retained in the temporary address register, so the contents of the Bit manipulation instruction, change instruction of the index _index register doesn’t change. This is a 2-byte instruction except register and accumulator and sleep instruction are also added AIM, OIM, EIM and TIM (3-byte insteuction) The fotlowings are explained here. Implied Addressing + CPU Programming Model (refer to Fig. 28) An instruction itself specifies the address. This is, the instruction + Addressing Mode addresses a stack pointer, index register, etc. This is a one-byte in- * Accumulator and Memory Manipulation Instruction (refer to struction. Table 11) Relative Addressing + New Instruction The second byte of an instruction and the lower 8 bits of the pro- * Index Register and Stack Manipulation Instruction (refer to gram counter are added. The carry or borrow is added to the upper Table 12) 8 bit. So addressing from — 126 to + 129 byte of the current instruc- + Jump and Branch Instruction (refer to Table 13) tion is enabled. This is a 2-byte instruction + Condition Code Register Manipulation (refer to Table 14) (Note) CLI, SEI Instructions and Interrupt Operation + Op Code Map (refer to Tabie 15) When accepting the IRQ at a preset timing with CLI and SEI instructions, more than 2 cycles are necessary be- © Programming Model tween the CLI and SEI instructions. For example, the fol- Fig. 28 depicts the HD6303Y programming model. The double lowing program (a)(b) don't accept the IRQ but (c) ac- accumulator D consists of accumulator A and B, so when using the cepts it accumulator D, the contents of A and B are destroyed © CPU Addressing Mode : : : The HD6303Y provides 7 addressing modes. The addressing : : : mode is determined by an instruction type and code. Tables 11 : : cL through 15 show addressing modes of each instruction with the ex- cL cu NOP ecution times counted by the machine cycle SEI NOP NOP When the clock frequency is 4MHz, the machine cycle time be- : SEI SEI comes microseconds directly : : : Accumulator (ACCX) Addressing : : : Only an accumulator is addressed and the accumulator A or Bis : : selected. This is a one-byte instruction. : . . Immediate Addressing (a) (b) (©) This addressing locates a data in the second byte of an instruc- tion. However, LDS and LDX locate a data in the second and third ‘The same thing can be said to the TAP instruction instead byte exceptionally. This addressing is a 2 or 3-byte instruction. of the CLI and SEI instructions Direct Addressing In this addressing mode, the second byte of an instruction shows @HITACHI 156 Hitachi America, Ltd. ¢ Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y Table 11 Accumulator, Memory Manipulation instructions pang Mode Conan Co Operavone | Moemon'c Tiaweb [DIRECT | INDEX [EXTEND [IMPLIED | Pereerrs.emreramm C8 CED ES EC [or [-[=for]- [lor] -[+lor[-[-[o»]-]-| w[ pele fe 7a eT ESRC MERCCIED EMCS CED [caooe feo te tz fouts [a teete[ayeefefa[ | [jeew=e de fefefifs) 1 eee Sa Op ae ee aad eso t add With Carry Fae _ffate pled pt ewes se Tee feos fowtoTefeniate bo fe 1 nono ror | anom faa [2 [2 [oa | [2 Tae] | Co [ete frf. pee eubebheth atari h eter Ba Te bie tabi fee testeo [I felefe fray Thetesteletetepep DT few dee fete fa Tow pee Ee obese tee peop ebles— epee Compare empa [ar [2]? [9x [3 | ralaferjept | [fa-m fe deft ite ree ferro ple fete peat hh : Conon en TT rates TY [=f [effets camaiement 6 Poe rae — ett pees tt th Hatt leltelets Complements | NEG | ae trpotets[ | [ foo-m=m fete ete tae UNegarel weca TT PT] eff ooze Pe Pe a 2 [rnece | ot oot] roose=e To te ef fea owematauns | DAA LETT ET [ef foomnrmient ate [= [|e] [2 Fa A OCS CD ECE ee a [oeca | Pty aa “att gogmoo a san EYE ON CE ee CHC CS CH Takane OF a PCH ECC ED XN CO [cone forte [aoe [a ea fee fe es ao = eeeeeemeee (CD (SCA ie ee CO CEI [ince TT im CPT ohey feet fecrse fe fe tet isye Lose T1oaa les 12 |2 196 [3 [2 jas] |? [es [a] LH MA — ee om Emu, FSA eT fatee [ala [rete] noe le fete fale Muttioly Urwoned | MUL | AxB-A 6 oc a OR, Inclusive [onan fea] 2 Roma’ fofeteye ial [amas forte rte afar vena maguuWe Posh Date \\ ns ee [efeyeleTele ese | [fo | HL ee aaseoe Pol Owe poe ET CI SP 1 = SPM A oogud [ous [PTT pty [seva=se.mo-e |e lefele|efe Rerae ie Pre ete ep * aaa Reh tron Pp pty yt Alt ceseeses SOIQGOIGU [ras teh . GuucK Rotate Right ee 4 Ty iy Tye, — ere itt Corer pt petitd *) Ser? eet tey [crore fT Die ttd poggon (Note) Condition Code Register will be expisined in Note of Table 14, (continued) © HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 157 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y ee eee Table 11 Accumulator. Memory Manipulation Instructions | Addressing Modes conn aoe Ovararons wwremors |'wuto. [OWECT | imoex Jexreno TwmPiico | pu QMO. Is aT the or |-|]on[~ [x lor] [oor |- [a or |- [a nfulwfeivte oat ro mEOORWGH — S000 Archaic “asta 7 TEL EE fae pits | OMCOETEE LE « ofurieye Paste | CELTr a) Ti ee fete Oo Eerie fee LLL | do care: jo Shit Roma id | leyslatn [eps] tt oe fete Teter Aanewie asa Tf | ahi.) Grotto ffehiyet: Tasers ry tr SECA oF Peeper: Lovieat vausna OP Sey Tt Tati f [eC Da lela Or Rom Lops seo | | L Joel ogee 8 elelal: Aecmemer sta wor} ple teeye let | [ye cw ete tele ye Reta | se || | fools fe feos 2 [rol | Lesa mooggGE a _ [suse foofat2foo{2fofeo fel rireets Ty Jere itt fe Oovete Subvect | sued 83 [3/3/99 |4 2 |a3!s|2 [ea sia] i A @-MMsr-A Bw leleitii itt rn | | ; Telit tases sleltitels Subsrect ‘soca [ez (32 [oa j3 [2 [aa] [2 fez !a la] [ | facmecoa efelefeliqi _WAN Carry seco }ez{2}2 Joo }s {2 ter} fea [a fa] eM -C=8 eerie Yantra ft tt ean welififace ofetifiteye _Aecumurarort rea | . FC 6 Cy eS COCCI Kemer oe TP feotele folate yy te oo A Minus asta] nen wo] i]t [a -00 efefite fale csre i - soli frjeroo fe tet tetefa Aedimmedaw fam ft datelstentotat TT tT [wm ae fefetetetate re 7 ry meCCCe elel:filale EOR immediate | EI [hs o MeN el:[: fale Test medate [refs [afoot OC OO EGE (Note) Condition Code Register will be explained in Note of Table 14 @HITACHI 158 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 » (415) 589-8300 . www.chipdocs.com _Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO3Y ®@ Additional instruction TIM .... (M)(IMM) In addition to the HD6801 instruction set, the HD6303Y pre- Executes “ AND" operation to immediate data and changes pares the following new instructions. the relative flag of the condition code register. Executes “AND” operation to immediate data and the second immediate data and the third address modifier. memory contents and stores its result in the memory XGDX . .. (ACCD)= (1X) OIM . .. (M)+ (IMM) — (M) Exchanges the contents of accumulator and the index regis- Executes “OR" operation to immediate data and the memo- ter. ry contents and stores its result in the memory. SLP Executes “EOR™ operation to immediate data and the TION MODE" for more details of the sleep mode. memory contents and stores its result in the memory. Table 12 Index Register, Stack Manipulation Instructions ‘adressing Modes Condition Code Porter Operations two] OIRECT | INDEX | EXTEND Aranmave Operation [5 ]4[3[2]1 lo [or [- [= lor |- [= lor [- [efor [-Te or] To | [a] iin lz vic Compare index Reg | CPx pepele pet els lafeche te pes ——Peehth [Decrement index Rey | OEX py ep ty oooeod [Decrement Stack Pore | DES TI . ae P| jofelefo]e}e Linerement tegen Rea | INK Oe CIO ce OOOO “irerament Stack Pour | INS aa ee en er OOOO ‘Lees Inoe Res cox epee Ree M= mew = [ele la ie iale Tena sweee pore [tos [3] [2 Jae[s |? foe |s| Cer aL Oe IG Store inden Reg | STX Cats Ga ffs} ) | pen x= een [ole la fe faye Store Suck Pos | STS oF a] [art fs[a{ | {jer =misr = meni eter [i [ale Tedex Reg Stack Pr] XS meemen [1 [x-1= 9° sogooo ~Bowck Powe inex Rew” TSK a [ao[v yr |srev=x eye te fete te a Ox pape |e yeex=x efoto fetes Puan Data PsHx S [i [x, -My Pot > ee Xj - May. SP = 1+ SP a SP 1 = SP Mg > Xe .

7 SP + 1 = SPM = Xe

“Exchange _ UI CET ela fxccox Te Tole fofel (Note) Condition Code Register wit! be explained in Note of Table 14. @ HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 159 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

= CO HD6303Y, HD63A03Y, HD63B03Y, HD63CO03Y ee i ttt ttt Table 13 Jump, Branch Instruction — ae =e Operations [pearive [ ovmect [| woex [extend [ruses _| geon ° — [or] Ts Torl=Te for[=T=[or]- [= [or] -Te | fa] itnfz [vic way | ena Profs fa hee Po fo foe Branch Never OD Beaneh If Carry Claw [3] if TPT 7 [3s pa j [evo epee ye fey Branch (1 Corry Set [3] ee eee grancnit= zero [eea far ae [peat ee fe fe fete ernent>2we [ace facta fot TT TT TT woven fee fe fo foto sanenit> zee [ocr faef ala TTT em ovire pole fe le fete Bene Hohe ee ep C22+0 gogcoo pene HS Zee ber tater ttt tt | [| [zewower Telefe te feye carrer [ee aah | Branch it < Zero Hepes Ee a Pen ie CD OG a ore Hee es seers [we fe 9) CO Free Branch It Overflow Sai] pee ee o Se es [ieee tt te fel 5 e Subroutine | OSA [001512 | TT] Boogoo wre power esp peppy | gagago women fo tt [armen TEE Rewarn From Inverrust] RT! | PES ——¢ —— Return From eer te TTT = 5 | [elle Te Sofrwere inverruot [ow Tet ots |e fe [ee wor tor inverroon’ [war TT TT TT TTT pele fr] Bogood Seep st ate Fr es foto le (Note) * WAL aw Hi "W' “Condition Code Regi wil be splanes mNower aoe eas ea @ HITACHI 160 Hitachi America, Ltd. Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y Table 14 Condition Code Register Manipulation Instructions Pascennanoded Tondion Code Regaver Operations Bootean Operation SERESESERC [or |~Te Pepi tw[z {vtec ‘Ger Carty ee onc fete [eye ts ta ‘Cer Interrupt Mek cu Tore fa [sf oss tH : ‘Cheer Overflow cov 1] =v Oo [eTe] ° ‘Set Corry SEC cn yee [ote yeyefeTs Set Interruot Maoh [ser or tat fe[s[etetete pees | ee ate ‘Accumulator A= CCR TAP A= cer : —— v —— Go keeae —erdett tons Lfete Plot LEGEND CONDITION CODE SYMBOLS OP Operation Code (Hexadecimal) H_ Half-carry from bit 310 bit 4 ~ Number of MCU Cycles 1 Interrupt mask Msp Contents of memory location pointed by Stack Pointer NN Negative (sign bit! # Number of Program Sytes Z Zero (byte) + Arithmetic Plus V Overflow, 2's complement = Arithmetic Minus © — Carry/Borrow from/to bit 7 © Boolean AND A Reset Always + Boolean Inclusive OR S Set Always @ Boolean Exciusive oR t Serif true after test or clear M_ Complement of M © = Not Affected + Transfer into QO Bit = Zero

00 Byte = Zero

(Note) Condition Code Register Notes: (Bit set if test is true and cleared otherwise) @ (Bit V) Test: Result = 100000007 2 @ (BirC) — Test: Result § 000000007 @ (orc) Test: BCD Character of high-order byte greater than 10? (Not cleared if previously set) @ (Bit V) Test: Operand = 10000000 prior to execution? @ (Bit V) Test: Operand = 01111111 prior to execution? 6) {Bit V) Test: Set equal to N@ C = 1 after the execution of instructions (Bit ND Test; Result less than zero? (Bit 15=1) @® {ANBit) Load Condition Code Register trom Stack @ (Bal) ‘Set when interrupt occurs. If previously set, a Non-Maskable Interrupt is required to exit the wait state. (@ {AW Bit) Set according to the contents of Accumulator A. a (Bit C) Result of Muitiplication Bit 7=1? (ACCB) Table 15 OP-Code Map oF ace ACCA or SP ACER or CODE 8 4 imm | Om | NO | ext | MM [ OW | IND | EXT | wt | ooo [coor [ oor0 Toots oom [roo [oor [rare {von | vie | vier [one fin | osfet i pztestetTs Tetra Te Te foje tr [aoe | free fou Tom es ee cme TI om rua | Eg ra] ca tn [nee | « [sno | —“Jece foes | (sh os AND [ey Tovar ['s [asco |) | ecs_[yxs_| em a 5 to] 6 [TAP | TAB | ONE | PSHA AOR tOA Te ra Tea [Tea [ota | P5H6 | ASR A STA z (iow [e wx [xeox] eve [rux| asf FOR te] [ioe [Ts [oex [oan favs [rts POL A row fa [cov eu aBx | DEC ~ ~___ORA [al coe sev er {aT i — x00 ie [nee Tee |} ect cen woo fe [ne fo | Ler | ssn] st a ‘2 [ine] [eer | =I - 10s at __tox UNpEFINED OF CODE C=] * Only each instructions of AIM, OIM, EIM, TIM @ HITACHI Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 161 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO03Y a a = CPU OPERATION and port states © CPU Instruction Flow When operating, the CPU fetches an instrution from a memory © ‘Operation at Each instruction Cycle and executes the required function. This sequence starts with RES. Table 17 shows the operation at each instruction cycle. By the cancel and repeats itself limitlessly if not affected by a special in- _pipeline control of the HD6303Y, MULT, PUL, DAA end XGDX struction of a control signal. SWI, RTI WAL and SLP instructions _instructions, etc. prefetch the next instruction. $o attention is ace ghange this operation, while NMI, IRQ,, IRQ,. IRQs, HALT and essary to the counting of the instruction cycles because wie different STBY control. Fig. 29 gives the CPU mode transition and Fig. 30 from the usual one—from op code fetch to the neat insttuction op the CPU system flow chart. Table 16 shows CPU operating states code ee >, AE Ae Saye eo gel \\3\\52 Ss) \\8\\° SS om Ves ace. 8; 2 \\3 ___RES=0 3 G v ; > 4 é ex ao Wy NGS Ne, “} 9 ON & ? Yo WG &y J s a zp Standby \\_STBY=0/ Steep Mode Mode Figure 29 CPU Operation Mode Trensition Table 16 CPU Operation State and Port, Bus, Control Signal State Poa? i ies Reon Bob) i T ControlSignt [OO fT | “ +1 FD, WR. AW, UF = 4, 8A = L *2 AD, WR. R/W = 1, UR BA =H "3 E pin goes to high impedance state. @ HITACHI 162 Hitachi America, Ltd. ¢ Hitachi Plaza ¢ 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO03Y eg2> ¢£ . aus B », ne © HIF 3eb of z ae &— Hf i, 23 H a 2 : z E> > ps > € liegt, &—FHIK |} "Lead & | | We aM | , g) OOO OO 0% “ee @HITACHI Hitachi America, Ltd. # Hitachi Plaza ¢ 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 ¢ (415) 589-8300 163 ‘www.chipdocs.com Be sure to visit ChipDocs web site for more information.

Table 17. Cycle-by-Cycle Operation 164 Hitachi America, Ltd. * Hitachi Plaza « 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO03Y ddress Mod Cycle ce loom | Mwon [em] re [om] tm | cue INDEXED "JMP 1 Op Code Address +1 1 0 OFF a 2 FFFF 1 | Restart Address (LSB) 3 | Jump Address 1 First Op Code of Jump Routine ADI ADD 1 Op Code Address +1 oF 0 1 1 Offset AND BIT 2 FFFF 1 1 1 1 Restart Address (LS8) CMP EOR 3 | x+Oftser 1 ° y 1 | Operand Data LDA ORA 4 | Op Code Address +2 1 ° 1 | 0 | Next op code sec SUB | 1st | st a Op Code Address +7 T 0 Offset FFFF 1 Restart Address (LSB) IX +Offset ° Accumulator Data Op Code Address +2 1 Next Op Code ‘DDD Op Code Address +1 T y Offset CPX Loo FRFF 1 Restart Address (LSB) Los LOX IX+ Offset 1 Operand Data (MSB) susD 1X+Offset+1 1 Operend Data (LSB) Op Code Address+2 1 Next Op Code STO STs 1 Op Code Address +1 1 0 Offset STX 2 (| FFFF 1 Restart Address (LSB) 5 3 | Ix+Oftse ° Register Oata (MSB) 4 | Ix+Offset+1 0 Register Data (LSB) 5 __| Op Code Address +2 1 Next Op Code JSR Op Code Address+1 v Offset FFFF 1 Restart Address (LSB) Stack Pointer 1 | Return Address (LSB) Stack Pointer—1 1 | Return Address (MSB) 1X+ Offset 0 _| First Subroutine Op Code ASL ASR Op Code Address +1 1 | Offset COM DEC FFFF 1, Restart Address (LS8) INC LSR 1X+ Offset 1 | Operand Data NEG ROL FFFF 1 | Restart Address (LSB) ROR 1X+ Offset 1 | New Operand Data OP Code Address + 2 i] Next Op Code . TIM Op Code Address +1 1 0 Immediate Date Op Code Address +2 1 ° Offset FFFF 1 1 Restart Address (LSB) 1X+ Offset 1 o Operand Data Op Code Address +3 1 ° Next Op Code CLR Op Code Address +1 1 0 1 Offset FFFF 1 1 1 | Restart Address (LSB) IX+ Offset 1 0 1 Operand Data IX+ Offset ° | 1 1 | 00 Op Code Address+2 1 ° o Next Op Code AIM EIM 1 Op Code Address+1 1 () T Immediate Data om 2 | Op Code Address +2 1 ° 1 1 | Offset 3 | FRFE 1 1 1 1 | Restart Address (LSB) 7 4 | 1X+Oftset 1 oj} 1 1 | Operand Data

5 FFFE 1 ‘ 1 1 | Restart Address (LSB)

| 6 | IX+Offset oj 1 ° 1 | New Operand Data 7_| Op Code Address +3 1 jo 1 0 _| Next Op Code (Continued) @ HITACHI Hitachi America, Ltd. © Hitachi Plaza ¢ 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300 165 www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y eee EXTEND IMP T_ | Op Code Address +1 7 0 7 T_] Jump Address (MSBy 2 | Op Code Address +2 1 ° 1 1 | Jump Address (LSB) 3__| Jump Address 1 0 1 © | Next Op Code ADC ADD TST 1 Op Code Address +1 1 0 T 1 Address of Operand (MSB) AND 8IT 2 | Op Code Address +2 1 0 1 1 | Address of Operand (LSB) CMP €OR 3. | Address of Operand ; 0 o| 4 1 | Operand Date LDA ORA 4 | Op Code Address +3 oa 0 1 © | Next Op Code SBC SUB ‘STA 7 ‘Op Code Address +1 rr oe a Destination Address (MSB) 4 2 | Op Code Address+2 4 ° 1 1 | Destination Address (LSB) 3 | Destination Address 0) 1 ° 1 | Accumulator Data 4 | Op Code Address +3 1 ° 1 0 __|_Next Op Code ODD ~ T | Op Code Address+1 7 OT 1 | T_T Kadress of Operand (MSB) cPX LOD 2 | Op Code Address+2 1 off 1 | Address of Operand (LSB) LDS LDx 5 3 | Address of Operand 1 oj; 1 | Operand Data (MSB) suBD 4 | Address of Operand+1 | 1 o.4 1) Operand Data (LSB) 5_| Op Code Address +3 1 ° 1 © | Next Op Code “Std sts “| 1 [Op Code Adaress# TF o 1 |1 Destination Address (MSB)_ STX 2 | Op Code Address +2 loa of} 1 | Destination Address (LSB) 5 3 | Destination Address ° 1 C) 1 | Register Data (MSB) 4 | Destination Address +1 0 1 ° 1 | Register Data (LSB)

5 Op Code Address +3 1 i) 1 i) Next Op Code

rs a ‘Y “| Op Code Address + 7~ rn a “Jump Address (MSB) 2 | Op Code Address +2 1 ° 1 1 | Jump Address (LS8) 6 3 | FFFF jo4 1 1 1 Restart Address (LSB) 4 | Stack Pointer o 1 ° 1 | Return Address (LSB) 5 | Stack Pomnter—1 0 1 ° 1 | Return Address (MSB) 6 | Jump Address 1 0 1 0_| First Subroutine Op Code ASL ASR ‘Op Code Address+1 rn a a Address of Operand (MSB) COM DEC Op Code Address+2 1 ° ’ 1 Address of Operand (LSB) INC LSR Address of Operand ;? ° 1 1 | Operand Date NEG = ROL FFFF 1 1 1 1 | Restart Address (LSB) ROR Address of Operand ° 1 | ° 1 | New Operand Data Op Code Address +3 1 ol. © | Next Op Code CLR 1 Op Code Address +1 T 6 T Address of Operand (MSB) 2 | Op Code Address +2 jo o | 4 Address of Operand (LS@) 3 | Address of Operand 1 oj Operand Data 4 | Address of Operand 9 1 0 00 §__| Op Code Adgress+3 1 0) . Next Op Code (Continued) @HITACHI 166 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

a HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y ‘Address Mode Cycle W Tr IMPLIED ABA ABX 1 ‘Op Code Address +1 1 ° 1 0 [Next Op Code ASL ASLD ASR CBA | ciel | | cLuR CLV | COM EC | | DES DEX INC INS | | | INX —LSR 1 LSAD ROL | ROR NOP | SBA SEC SEI SEV TAB TAP | TBA TPA | TST TSX TXS _ — DAA XGDX Op Code Address +1 y | 0 Next Op Code | 2 | FFF 1 1 Lo | Restart Address (LSB) PULA PULB Op Code Address +1 1 C) Next Op Code FRFF 1 1 Restart Address (LSB) Stack Pointer +1 1 oO Data from Stack PSHA PSHB Op Code Address+1 1 0 Next Op Code FRFE 1 1 Restart Address (LSB) ‘Stack Pointer 0 | 1 Accumulator Data Op Code Address +1 1 oO Next Op Code PULX Op Code Address +1 Next Op Code FFE Restart Address (LSB) Stack Pointer +1 Data from Stack (MSB) Stack Pointer +2 Data from Stack (LS8) ~PSHX Op Code Address +7 6 Next Op Code FRE 1 Restart Address (LSB) ; 5 Stack Pointer ° Index Register (LSB) | Stack Pointer -1 | 0 Index Register (MSB) : Op Code Address +1 1 Next Op Code RTS Op Code Address+1 1 oO 1 7 jext Op Code FFFF 1 1 1, U4 Restart Address (LSB) Stack Pointer +1 1 ° 1 1 | Return Address (MSB) Stack Pointer +2 1 ° 1 1 | Return Address (LSB) Return Address 1 i) 1 ° First Op Code of Return Routine wut” Op Code Address+1 T 7 5 Next Op Code FRFF 1 1 1 Restart Address (LSB) FFFF 1 1 1 | Restart Address (LSB) FFFF 1 1 1 | Restart Address (LSB) FFFF 1 1 1 Restart Address (LSB) FREE 1 1 1 Restart Address (LSB) FFFF 1 1 1_|_ Restart Address (LS8) (Continued) @ HITACHI Hitachi America, Ltd. » Hitachi Plaza ¢ 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 © (415) 589-8300 167 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HD63CO3Y fee Pe) eee ee ae IMPLIED WAI 1] Op Code Address +1 7 6 T T__] Next Op Code

2 FFFF 1 1 1 1 Restart Address (LSB)

1. | Stack Pointer 0 1 0 | 1 | Return Address (LSB) 4 | Stack Pointer-1 o 3 ° 1 | Return Address {MSB) i 9 5 | Stack Pointer ~2 ° 1 0 1 | Index Register (LSB)

6 Stack Pomter~3 ° 1 o 1 | Index Register (MSB)

7 | Stack Pointer—4 oj} 1 ° 1 | Accumulator A 8 | Stack Ponter—5 o} 1 ° 1 | Accumutator 9 | Stack Pointer~6 0 1 ° 1_| Conditional Code Register AT i T__| Op Code Address +1 7 0 7 T | Next Op Code | 2 (| FFFF 1 | 1 1 1 | Restart Address (LSB) 3. | Stack Pomnter+1 1 ° 1 1 | Conditional Code Register 4 | Stack Pointer +2 1 ° 1 1 Accumulator B | 49 | 8 | Stack Pointer+3 ’ 0 1 1 | Accumulator A 6 | Stack Pomter+4 1 ° 1 1 | Index Register (MSB) 7 | Stack Pomter+5 1 0 1 1 | Index Register (LSB) 8 | Stack Pointer +6 1 ° 1 1 | Return Address (MSB) 9 | Stack Pomter +7 1 oj4 1 Return Address (LSB) |..10 | Return Address 1 | 0 1 ° First Op Code of Return Routine wi 1 | Op Code Address +1 a) T T | Next Op Code

52 FRFF 1 14 1 1 Restart Address (LSB)

3 | Stack Pointer oj} 4 ° 1 | Return Address (LSB) 4 | Stack Pointer—1 ° 1 ° 1 | Return Address (MSB) 5 | Stack Pointer—2 0 1 ° 1 Index Register (LSB) 12. | & | Stack Pointer—3 oj; 4 ° 1 | Index Register (MSB) | 7 | Stack Pointer~4 o} 1 Q 1 Accumulator A 8 | Stack Ponter-5 0; 1 ° 1 | Accumulator B 9 | Stack Pointer -6 0 1 0 1 | Conditional Code Register 10 | Vector Address FFFA 1 | oO 1 1 | Address of SW! Routine (MSB) 11 | Vector Address FFFB 1 C) 1 1 | Address of SW! Rouune (LSB) [12_| Address of SWI Routine 1 oj4 © _| Furst Op Code of SW! Routine SiP 7 | Op Code Address +1 7 0 7 1 | Next Op Code | 2. | FFFF 1 1 1 1 | Restart Address (LSB)

4 Sleep \\ | i

i {| sob fe F | 3. | Free 1 14 1 | Restart Address (LSB) [4 | Op Code Address +1 1 0 1 © | Next Op Code RELATIVE Bcc ecs T jp Code Address +7 1 0 1 T Branch Offset BEQ —BGE 3 | 2. | FFF r44 1 | 1 | Restart Address (LSB) SGT BHI 13 (Branch Address Test="1 1 ° 1 First Op Code of Branch Routine BLE BLS | | Op Code Address +1 Test="0 | © | Next Op Code BLT BMT | BNE BPL i { | 1 BRA BRN | i j BVC BVS i oe BSR ot ry Op Code Address +1 ae 1) 1) Offset — | i 2 FFEF ot hr a | Restart Address iL SB) [si 3 | Stack Pointer jol4 © | 1 | Return Address (LSB) | 4 | Stack Pointer ~1 ° 1 0 1 | Return Address (MS8) 5 | Branch Address 1, OF} Ff oO Furst Op Code of Subroutine @ HITACHI 168 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 © (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.

When designing a board, note that crosstalk may disturb the EZ D in this area. to the HD6303Y as possible. Z cy YZ . Do not use this kind of printed-circuit board design. Figure 31. Warning concerning board design www.chipdocs.com Be sure to visit ChipDocs web site for more information.

HD6303Y, HD63A03Y, HD63B03Y, HDE63CO3Y eee eee eee Ome = WARNING CONCERNING WAI INSTRUCTION If the HALT signal is accepted by the MCU while the WAI in- . struction is executing, the CPU will not operate correctly after — toe HALT mode is canceled. MALT input WAI is a instruction which waits for an interrupt. The cor- waiting for responding interrupt routine is executed after an interrupt intercupt P) occurs. {interrupt occurs However, during the execution of the WAI instruction, wrong vector address oy HALT input makes the CPU malfunction and fetch an abnormal (aa | 4 interrupt vectoring address. vector fetch for interrupt In HALT mode, the CPU operates correctly without the WAI | instruction, and WAI is executed correctly without HALT input. tT Therefore, if HALT input is necessary, make interrupts wait } during the loop routine, as shown in Figure 33. . interrupt routine . | IS WRITE-ONLY REGISTER When the CPU reads a write-only register, the read data is always Figure 33 MAC function during WAI SFF, regardless of the value in the write-only register. Therefore, be careful of the results of instructions which read write-only register ° and perform an arithmetic or logical operation on its contents, such : ‘ as AIM, ADD, or ROL. is executed, because the arithmetic or logical operation is always done with the data SFF. In particulars, Loop don’t use the AIM, OIM or EIM instruction to manipulate the DDR bit of PORT. : : : 5 {@ WARNING CONCERNING POWER START-UP. i) MAL function a) Recommended method RES must be held low for at teast 20 ms when the power starts up. - In this case, the internal reset function is not effective until the Figure 34 Program to wait for interrupt oscillation begins at power-on. The RES signal is input to the LSI in synchronism with the internal clock @ (shown in Figure 35.) Therefore, after power starts up, the LSI conditions such as its 1/ ~ ports and operating mode. are unstable. Fix the level of 1/O ports ust ¢ $ by means of an external circuit ta determine the level for system operation during the oscillator stabilization time __ > P 4 E interes! reaet RES pin: 3) signal Figure 35 AES circuit @HITACHi 170 Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300 . www.chipdocs.com Be sure to visit ChipDocs web site for more information.