HD61603 Datasheet | DigiCamel IC Datasheet

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HD61602 HITACHI

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 37

Technical content

Features

Wide-range operating voltage — Operates in a wide range of supply voltage: 2.2V to 5.5V — Compatible with TTL interface at 4.5V to 5.5V ¢ Low current consumption — Can run from a battery power supply (100 A max. at 5 V) — Standby input enables standby operation at lower current consumption (5 WA max. on SV) ¢ Internal power supply circuit for liquid crystal display driver (HD61602) — Internal power supply circuit for liquid crystal display driver facilitates the connection to a microprocessor system 1230

Ordering Information

Type No. Package HD61602R 80-pin plastic QFP (FP-80) HD61602RH 80-pin plastic QFP (FP-80A) HD61603R 80-pin plastic QFP (FP-80) Versatile Segment Driving Capacity Display Frame Freq. (Hz) Type No. Driving Method Segments Example of Use atf..=100kHz Package HD61602 Static 51 8 segments x 6 digits + 3 marks 33 80-pin plastic 1/2 bi QFP (FP-80, jas 1/2 duty 102 8 segments x 12 digits +6 marks 65 rpBOA 1/3 bias 1/3duty 153 9 segments x 17 digits 208 TFP-80) 1/4duty 204 8 segments x 25 digits + 4 marks 223 HD61603 Static 64 8 segments x 8 digits 33 80-pin plastic QFP. (FP-80) 1231 HITACHI

HD61602R HD61603R° RECs w_)SeG17 REL> @SeGi7 oe Bee oe. Bee Ei Tee cot roast (FP-80) (FP-80) HD61602RH BeRReSaT Teg IE gages QIOOOIDIOONODIODOO osc ww seGis wo w seas Ea Besse pind soeee Ea cose 35923995 3388583 EERE REREEE EERE EE EE (FP-80A) (Top view) 1232 HITACHI

“ iy L LGD driving rad generator Common}, Commen output FA (tines) = a © i contol ting gonetstor ParaleV serial Data laton [ Pastas | [Segment|—s, Segment output 00-07 —) ‘abt x2 converter Display |p| ariver [yy (St lines) ie cata RAM —_ decoder doting EE Operation iaict FE moge vi LCD exiving Driving votago voltage generator | V3 selection | oo a | ail 2 Tovon JT iT 061603 SYNC l LOD driving gonerator common} . =. RAM write WES 5L_controtlor (st timing generator Data latch Pavalleseral 0-03 v| Abts 4 PL sonveror oispiay | |, |segmont data RAM) driver ‘Segment output (64 lines) _ 0c08er seting inion va 1233

HD61602 Terminal Functions Terminal No. of Name Lines Input/Output Connected to Function VDD 1 Power supply Positive power supply. READY 1 NMOS open MCU While data is being set in the display data RAM drain output and mode setting latch in the LSI after data transfer, low is output from the READY terminal to inhibit the next data input. There are two modes: one in which low is output only when both of CS and RE are low, and the other in which low is output regardless of CS and RE. cs 1 Input MCU Chip select input. Data can be written only when this terminal is low. WE 1 Input MCU Write enable input. Input data of DO to D7 is latched at the rising edge of WE. RE 1 Input MCU Resets the input data byte counter. After both CS and RE are low, the first data is recognized as the ist byte data. SB 1 Input MCU High level input stops LSI operations. 1. Stops oscillation and clock input. 2. Stops LCD driver. 3. Stops writing data into display RAM. DO-D7 8 Input MCU Data input terminal for 8-bit x 2-byte data. vss 1 Power supply Negative power supply. VREF1 1 Output External R Reference voltage output. Generates LCD driving voltage. VREF2 1 Input External R Divides the reference voltage of VREF1 with external R to determine LCD driving voltage. VREF2 = V1. vc1, VC2 2 Output External C Connection terminals for boosting C of LCD driving voltage generator. An external C is connected between VC1 and VC2. Vi,V2,V3. 3 Output (Input) External LCD driving voltage outputs. An extemal C is connected to each terminal. COMO-COM3 4 Output LCD LCD common (backplate) driving output. SEGO-SEG50 51 Output LCD LCD segment driving output. SYNC 1 Input MCU Synchronous input for 2 or more chips applications. LCD driver timing circuit is reset by high input. LCD is off. osc1 2 Input External R Attach external R to these terminals for osc2 Output oscillation. An external clock (100 kHz) can be input to OSC1. Note: Logic polarity is positive. 1 = high = active. 1234 HITACHI

HD61603 Terminal Functions Terminal No. of Name Lines Input/Output Connected to Function VDD 1 Power supply Positive power supply. READY 1 NMOS open MCU While data is being set in the display data RAM drain output and mode setting latch in the LSI after data transfer, low is output from the READY terminal to inhibit the next data input. There are two modes: one in which low is output only when both of CS and RE are low, and the other in which low is output regardless of CS and RE. cs 1 Input MCU Chip select input. Data can be written only when this terminal is low. WE 1 Input MCU Write enable input. Input data of DO to D3 is latched at the rising edge of WE. RE 1 Input MCU Resets the input data byte counter. After both of CS and RE are low, the first data is recognized as the 1st byte data. 1. Stops oscillation and clock input. 2. Stops LCD driver. 3. Stops writing data into display RAM. Do-D3 4 Input MCU Data input terminal from where 4-bit x 4 data are ‘input. vss 1 Power supply Negative power supply. v3 1 Input Power supply Power supply input for LCD drive. Voltage between VDD and V3 is used as driving voltage. COMO 1 Output Leb LCD common (backplate) driving output. SEGO-SEG63 64 Output LCD LCD segment driving output. SYNC 1 Input MCU Synchronous input for 2 or more chips applications. LCD driver timing circuit is reset by high input. LCD is off. Osc 2 Input External R Attach external R to these terminals for Osc2 Output oscillation. An external clock (100 kHz) can be input to Osc,. Note: Logic polarity is positive. 1 = high = active. 1235 HITACHI

The HD61602 has an internal display RAM shown in Figure 1. Display data is stored in the RAM, or is read according to the LCD driving timing to display on the LCD. One bit of the RAM corresponds to 1 segment of the LCD. Note that some bits of the RAM cannot be displayed depending on LCD driving mode. ‘Common address (COMo-COMs) | : 51 bits ‘Segment address (SEGO-SEG50) Figure 1 Display RAM 1236 HITACHI

Figure 11 Bit Assignment in an Adn (HD61603) 1243 HITACHI

The HD61602 has the following operating modes: 1. LCD drive mode Determines the LCD driving method. a. Static drive mode LCD is driven statically. b. 1/2 duty cycle drive mode LCD is driven at 1/2 duty cycle and 1/2 bias. c. 1/3 duty cycle drive mode LCD is driven at 1/3 duty cycle and 1/3 bias. d. 1/4 duty cycle drive mode LCD is driven at 1/4 duty cycle and 1/3 bias. 2. Data display mode Determines how to write display data into the data RAM. a. Static display mode 8-bit data is written into the display RAM according to the digit in static drive. b. 1/2 duty cycle display mode 8-bit data is written into the display RAM according to the digit in 1/2 duty cycle drive. c. 1/3 duty cycle display mode 8-bit data is written into the display RAM according to the digit in 1/3 duty cycle drive. d. 1/4 duty cycle display mode 8-bit data is written into the display RAM according to the digit in 1/4 duty cycle drive. 3. READY output mode Determines the READY output timing. After a data set is transferred, the data is processed internally. The next data cannot be acknowledged during the processing period. The READY output reports the period to the MPU. The timing when the READY is output can be selected from the following two modes: a. READY is mode always available (Figure 12). b. READY is mode available by CS and RE (Figure 13). 4, LCD OFF mode In this mode, the HD61602 stops driving LCD and turns it off. 5. External driving voltage mode A mode for using external driving voltage (V1, V2, and V3). The above 5 modes are specified by mode setting data. The modes are independent of each other and can be used in any combination. Bit manipulation is independent of data display mode and can be used regardless of it. 1244 HITACHI

HD61602 Input Data Formats Input data is composed of 8 bits x 2. Input them as 2-byte data after READY output changes from low to high or low pulse is entered into RE terminal. 1. Display data (updates display on an 8-segment basis) 1stoyte Le[o|x| daria 7 6 8 4 8 2 1 0 2nd byte 7 6 8 «4 8 2 7 0 a. Display address Digit address Adn in accordance with display mode b. Display data Pattern data that is written into the display RAM according to display mode and the address 2. Bit manipulation data (updates display on a segment basis) istbyte [Le] + pool = [>] | itt | 7 6 8 4 8 2 1 0 2nd byte 7 6 5 4 8 @ 7 0 a. Display data Data that is written into 1 bit of the specified display RAM. b. COM address Common address of display RAM c. SEG address Segment address of display RAM 1247 HITACHI

Mode setting data 2nd byt [x [= || x | fr) 7 6 8 4 3 2 1 0 a. Display mode bits 00: Static display mode Ol: 1/2 duty cycle display mode 10: 1/3 duty cycle display mode ll: 1/4 duty cycle display mode b. OFF/ON bit I: LCD off (set to 1 when SYNC is entered) 0: LCD on c. Drive mode bits 00: Static drive Ol: 1/2 duty cycle drive 10: 1/3 duty cycle drive ll: 1/4 duty cycle drive d. READY bit 0: READY bus mode; READY outputs 0 only while CS and RE are 0. (reset to 0 when SYNC is entered) 1: READY port mode; READY outputs 0 regardless of CS and RE. e. External power supply bit 0: Driving voltage is generated internally. 1: Driving voltage is supplied externally. (Set to 1 when SYNC is entered.) 4, 1-byte instruction Astbyto 7 6 8 «@ 3 2 7 0 The first data (first byte) is ignored when bit 6 and bit 7 in the byte are 1. 1248 HITACHI

HD61603 Input Data Formats Input data is composed of 4 bits x 4. Input them as four 4-bit data after READY output changes from low to high or low pulse is entered into RE terminal. 1. Display data (updates display on an 8-segment basis) tistbyte 2nd byte 32 7 0 8 2 7 0 3rdbyte ain byte e765. 4] |ens, 21, 0 32 1 0 8 2 1 0 a. Display address Digit address Adn shown in Figure 10. b. Display data Pattern data that is written into the display RAM as shown in Figure 11, 2. Bit manipulation data (updates display on a segment basis) tstbyto 2nd byte 32 1 0 8 @ 1 0 Srdbyte ain byte sits, 4 | (era, 2. 1, 0 32 t 0 $s 2 1 0 a. Display data Data that is written into 1 bit of the specified display RAM. b. SEG address Segment address of display RAM (segment output) 1249 HITACHI

Mode setting data istoye 2nd byte 3 2 1 0 8 2 7 0 aid byte 4th byte ye 1 0 8 2 1 0 a. OFF/ON bit I: LCD off (set to 1 when SYNC is entered.) 0: LCD on b. READY bits 0: READY bus mode; READY outputs 0 only while CS and RE are 0. (reset to 0 when SYNC is entered.) 1: READY port mode; READY outputs 0 regardless of CS and RE. 4, 1-byte instruction tstoyto > 2 TO The first data (4 bits) is ignored when bit 3 and 2 in the data are 1. 1250 HITACHI

Input data is composed of 8 bits x 2. Take care that the data transfer is not interrupted, because the first 8-bit data is distinguished from the second one by the sequence only. If data transfer is interrupted, or at power on, the following two methods can be used to reset the count of the number of bytes (count of the first and second bytes): 1. Set CS and RE inputs low (no display data changes). 2. Input 2 or more “1-byte instruction” data in which bit 7 and 6 are 1 (display data may change). The data input method via data input terminals (CS, WE, DO to D7) is similar to that of static RAM such as HM6116. An access of the LSI can be made through the same bus line as ROM and RAM. When output ports of a microprocessor are used for an access, refer to the timing specifications and Figure 16. Power on TS fT NN SNS WE TNT TFT Fa RE 5 SNS READY £000 TF ' % 8 5 ‘SYNC J V2 00-07 ———{()— Gk XE Xen Fst Xen Mode setting data Mode setting data Display data Notes: 1. READY output is indefinite during 12 clocks after the oscillation start at power on (clock: OSC2 clock). 2. High pulse should be applied to SYNC terminal when using two or more chips synchronously. 3. Inthe mode in which READY is always available, READY output is in definite while SYNC is high. 4. Reset the byte counter after power on. 5. READY output period is within 3.5 clocks in the mode setting operation and bit manipulation or within 10.5 clocks when the display data (8 bits) is updated. 6. Connect a pull-up resister if WE or RE may be floating. 7. Itis not always necessary to follow this example. Figure 16 Example of Data Transfer Sequence 1251 HITACHI

Input data is composed of 4 bits x 4. Take care that data transfer is not interrupted, because the first 4-bit data to the fourth 4-bit data are distinguished from each other by the sequence only. If data transfer is interrupted, or at power on, the following two methods can be used to reset the count of the number of data (count of the first 4-bit data to the fourth 4-bit data): 1. Set CS and RE low. 2. Input 4 or more “1-byte instruction” data (4-bit data) in which bit 3 and 2 are 1 (display data may change). The data input method via data input terminals (CS, WE, DO to D3) is similar to that of static RAM such as HM6116. An access of the LSI can be made through the same bus line as ROM and RAM. When output ports of a microprocessor are used for an access, refer to the timing specifications and Figure 17. Power on a a a oe a WE TFT TFA AATF RE fg NS READY 60007 TF" PNT * 6 “3 *5 6 SYNC) 4, 0-03. —— + GX EXE FER Mode setting data Mode setting data Display data Notes: 1. READY output is indefinite during 12 clocks after the oscillation start at power on (clock: OSC2 clock). 2. High pulse should be applied to SYNC terminal when using two or more chips synchronously. 3. Inthe mode in which READY is always available, READY output is in definite while SYNC is high. 4. Reset the 4-bit data counter after power on. 5. READY output period is within 3.5 clocks in the mode setting operation and bit manipulation or within 10.5 clocks when the display data (8 bits) is updated. 6. Connect a pull-up resister it WE or RE may be floating. 7. tis not always necessary to follow this example. Figure 17 Example of Data Transfer Sequence 1252 HITACHI

Note that the READY output will be unsettled during 1.5 clocks (max) after inputting the first 2-byte data for setting the mode after turning the power on. This is because the READY bit data of mode setting latches and the mode of READY pin (READY bus or port mode) are unsettled until the completion of mode setting. There are two kinds of the READY output waveforms depending of the modes: 1. READY bus mode (READY bit = 0) 2. READY port mode (READY bit = 1) However, if you input SYNC before mode setting, waveform will be determined; when you choose READY bus mode, (1) a in Figure 18 will be output, and when you choose READY port mode, (2) a will be output. The figures can be applied both to HD61602 and HD61603. Power on t fd WE 00-07 <ist X_2nd_> Mode sting data ZH; =~ READY output is unsettled (2-byte data) daowe (max) Mode setting latch is unsettled. 4 Mode setting data are Power on latched. VE RE a READY a ae) Note: CS = low a 1.5 clocks (max) (1) READY Bus Mode Power on We a READY Kes Note: TS = low, FE = high Ps ciocs fran 3.5 clocks (max) (2) READY Port Mode Figure 18 READY Output According to Modes 1253 HITACHI

Standby operation with low power consumption can be activated when pin SB is used. Normal operation of the LSI is activated when pin SB is low level, and the LSI goes into the standby state when pin SB is high level. The standby state of the LSI is as follows: 1. LCD driver is stopped (LCD is off). 2. Display data and operating mode are held. 3. The operation is suspended while display changes (while READY is outputting low.) In this case, READY outputs high within 10.5 clocks or 3.5 clocks after release from the standby mode. 4. Oscillation is stopped. When this mode is not used, connect pin SB to VSS. Multichip Operation When an LCD is driven with two or more chips, the driving timing of the LCD must be synchronized. In this case, the chips are synchronized with each other by using SYNC input. If SYNC input is high, the LCD driver timing circuit is reset. Apply high pulse to the SYNC input after the operating mode is set. A high pulse to the SYNC input changes the mode setting data. (The OFF/ON bit is set and the READY bit is reset. See 3. Mode Setting Data in “Input Data Formats”.) Transfer the mode setting data into the LSI after every SYNC operation. If a power on reset signal is applied to the SYNC pin, the LCD can be off-state when the power is turned on. When SYNC input is not used, connect pin SYNC to VSS. When SB input is used, after standby mode is released, a high pulse must be applied to the SYNC input, and mode setting data must be set again. Restriction on Usage Minimize the noise by inserting a noise by-pass capacitor (2 1 uF) between VDD and VSS pins. (Insert one as near chip as possible.) 1254 HITACHI

Liquid Crystal Display Drive Voltage Circuit (HD61602) What is LCD Voltage? HD61602 drives liquid crystal display using four levels of voltages (Figure 19); VDD, V1, V2, and V3 (VDD is the highest and V3 is the lowest). The voltage between VDD and V3 is called VLCD and it is necessary to apply the appropriate VLCD according to the liquid crystal display. V3 always needs to be supplied regardless of the display duty ratio since it supplies the voltage to the LCD drive circuit of HD61602. voo Myf [mee J vs av ve Figure 19 LCD Output Waveform and Output Levels 1255 HITACHI

Power supply voltage* VDD, V1, V2, V3 0.3 to +7.0 Vv Terminal voltage* VT -0.3 to VDD +0.3 Vv Operating temperature Tose —20 to +75 °c Storage temperature Tey 55 to +125 °c * Value referenced to VSS = OV. Note: IfLSIs are used above absolute maximum ratings, they may be permanently destroyed. Using them within electrical characteristics limits is strongly recommended for normal operation. Use beyond these conditions will cause malfunction and poor reliability. Recommended Operating Conditions Limit Item Symbol Min Typ Max Unit Power supply voltage VDD 22 - 5.5 Vv V1, V2, V3 0 — VDD 7 Terminal voltage* VT i) _ VDD Vv Operating temperature Toe -20 = 75 °C * Value referenced to VSS = OV. 1260 HITACHI

Electrical Characteristics

DC Characteristics (1) (VSS = 0V, VDD = 4.5 to 5.5V, Ta = -20 to +75°C, unless otherwise noted) Limit Item Symbol Min’ Typ Max Unit Test Condition ‘Inputhigh voltage OSCi ss VIKi_—s's«sOBVDD — VDD V ‘Inputlowvoltage OSCt —VIL1_—sisiéOststi‘<‘— 2S CRM! Ohes viz oO — oO8 V ‘Outputleakage = READY =, — — 5 HA VO=VDD | current ‘Outputlowvoltage READY VOL — — O04 VV [,=04mA ‘Inputleakage —sInputterminal ‘,, 1.0. — (1.0 pA VIN=O-VDD current Vil OC”S~<a”SNSC«WN=VDD-VB™” vaV3 oi, COCO ‘LCD driver voltage COMO-COM3 Vdt — — 03 V dld=3yAToreach drop COM, V3 = VDD-3V ‘SEGO-SEGS5O Vd2 — =3=9— 06 V did=3yAToreach SEG, V3 = VDD-3V Powersupply Sig SSCS A Cringcisplay™ = current Rocco = 360 KQ Te SOA Atstandby ‘Internal driving V1, V2,V3.—=C«WNTR ss —)—S—(iC~SOiKSC«Ss«UREF2=VDD-1'V, voltage drop C1-C4 = 0.3 pF, RL =3MQ ‘Notes: 1. V1,V2:appyonlytoHD61602,—“C*“‘ ;]UDW#*“‘CSSNSNNNNOO 2. Except the transfer operation of display data and bit data. 1261 HITACHI

DC Characteristics (2) (VSS = OV, VDD = 2.2 to 3.8V, Ta = —20 to +75°C, unless otherwise noted) Limit Item Symbol Min Typ Max Unit Test Condition Input high voltage VIH 08VDD — VDD Vv Input low voltage VIL O _— 0.1VDD V Output leakage READY IOH _ - 5 yA =VIN=VDD current Output low voltage READY VOL. — — 0.1VDD V IOL = 0.04 mA Input leakage Input terminal 1, -1.0 0 1.0 yA -VIN=0-VDD current! vi le =20 — 20 yA VIN= VDD-V3 V2, V3 ls 5.0 — 50 pA LCD driver voltage COMO-COM3_ Vd1 al - 03 Vv tld = 3 pA for each drop COM, V3 = VDD-3V SEGO-SEG50. Vd2 - — 06 Vv tid = 3 pA for each SEG, V3 = VDD-3V Power supply leg _ - 50 HA During display** current Roge = 330 kQ leg — — 5 HA At standby Internal driving V1, V2, V3 VIR - _- 0.4 Vv VREF2 = VDD-1V, voltage drop C1-C4 = 0.3 uF, RL =3MQ, VDD =3-3.8 V Notes: 1. V1, V2: apply only to HD61602. 2. Except the transfer operation of display data and bit data. 1262 HITACHI

AC Characteristics (1) (VSS = 0V, VDD = 4.5 to 5.5V, Ta = -20 to +75°C, unless otherwise noted) Limit Item Symbol Min Typ Max Unit Test Condition ‘Oscillation frequency OSC2 if, = 70.~—=S—«d100.:«st30.~S*é«iwZ:«CWwR = GOK” ‘Externalclock frequency OSCi sf, 70S 100:«130,”—~*téi«iw SS ‘Externalclockduty --OSC1_—séDuy, — 40——<“COwSC i SsC—<“<sisSCS 4% 0 -— — ms ©... hw 30 — — ms t} 40 — — ms |. te (400 — — ms mw Os Figurest tj 40 — — ms |. ‘ben 95S ~S«STS) Clock Fordisplay data transfer ton 25)~C”~SC«S'SSSCCdocK For bitand mode data transfer ‘Input signalrise time andfalltme t,t — — 2 ms 1263 HITACHI

AC Characteristics (2) (VSS = 0V, VDD = 2.2 to 3.8V, Ta = -20 to +75°C, unless otherwise noted) Limit Item Symbol Min Typ Max Unit Test Condition ‘Oscillation frequency OSC2 ff, 70.~=~=«100.:«130.~*é‘iRHZ:=C‘w«C = BOK ‘Externalclock frequency OSCT ff, 70.~—=”*=«‘SCSHstéi‘iaKHSSStS~S VOsignaltimng (titi SSS i wT SCS uw -— — 20 4s Figues2 i ‘% 20 -— — wp tbe SC«TS~——Clock ‘Fordisplay data transfer ‘be =—o25S*s=C«CS*«SSS*«CCdock Forbitand mode data transfer ‘Input signalrise time andfalltime tt — — 2 ms 1264 HITACHI

Selected Specification

Hitachi Semiconductor HD61603 overview.

Summary

SEGMENT TYPE LCD DRIVER

Description

SEGMENT TYPE LCD DRIVER

Source title HD61603 Datasheet(PDF) - Hitachi Semiconductor

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