HD614121P

HD404240S HITACHI

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 67

Technical content

Description = The HMCS412/414/424 Series are HMCS400 + Package Series CMOS 4-bit single-chip microcomputers, —Standard 42-pin dual-inline plastic package Each device incorporates a ROM, RAM, I/O, serial (DP-42) interface, and timer/counter, including high-voltage —42-pin shrink dual-inline plastic package V/O pins with high-current output pins to directly (DP-42S) drive a fluorescent display. —44-pin flat plastic package (FP-44A) eee Features Ordering Information + 2048-word x 10-bit ROM (HMCS412) Series Product Name Model Name Package 4096-word x 10-bit ROM (HMCS414/424) HMCS412 HMCS412C ——«HD614121P__DP-42 * 160-digit x 4-bit RAM (HMCS412/414) HD614121S_—__OP-42S 256-digit x 4-bit RAM (HMCS424) HD614121H_ —_—FP-44A, + 36 1/0 pins including 24 high-voltage 1/0 pins HIMCS412CL__HDe14126P P42 (40 V max.) ‘HD6141265 __DP-425_ * Timer/counters HD614126H __FP-44A — B-bit x 1 (HMCS412/414) HMCS412AC -HD614129P_—_—DP-42 — 8-bit x 2 (HMCS424) Hpe141208~—CO Pao * Clock-synchronous 8-bit serial _ interface Hosre1295_OF 428 _ (HMCS424 only) HD614129H__FP-44A + Five interupt sources HMCS414 HMCS414C —-HD614141P__DP-42 — Two by external sources (HMCS412, 414) HOSI4I41S __OP-425_ — One by internal source (HMCS412, 414) HD614141H FP-44A — Two by external sources (HMCS424) HMCS414CL—-HD614146P__DP-42 — Three by internal sources (HMCS424) HD614146S —_ DP-42S. + Subroutine stack up to 16 levels including inter- HD614146H__FP-44A Tupts HMCS414AC HD614149P__DP-42 + Low-power dissipation modes 06141498 DP-425 — Standby mode HD614149H —_FP-44A, . Onahy ostilator HMCS424 HMCS424C——«HD404240P__DP-42 —Crystal or ceramic oscillator HO4042405 _DP-42S _ —Resistor (HMCS412C/414C) ——__HD404240H__FP-44A_ —External clock input HMCS424CL — HD40L4240P__DP-42 C-type: 5-V operation version HD40L4240S _OP-428 _ CL-type: 3-V operation version HD40L4240H ~—FP-44A AC-type: high speed operation version HMCS424AC = HD40A4240P_ —DP-42. HD40A42408 _DP-425_ HD40A4240H _FP-44A $$$ HOM 40 FP AGA M™@ 4496204 0047232 684 Me 301 Hitachi ee

HMCS412 Series/HMCS414 Series/HMCS424 Series eee or ee eee eee eres Pin Arrangement HMCS412, HMCS414 fy | D2 C10 aD, Ps Da «FD. éédddasae , panels sae ANANAnANANN ' Foy Cs sa)D; mcf eee aaa easy, Roy L je sh} D, Ro, Cz 2bJ Ds Rol? ba Ro, Cl» ay Fo, tl hd. Rip Ls 20-1 Ds Boh imi Rty fs 29]; Bigg, P42 Sep Riel FP-44A »Eo, Riz} a2f]D, le RigC yi DP-42S «Fj, Ris 27] Dp Fe 3 x0[-] GND Re) Cs 26] GND Re, Cu alos, Re, Clo 2s]08¢, Re, Cs osc, Re, C}10 Else, Ra C} aL }TESt PO}. oy eenesen th ae ele coh COU FAA, [ bal Lio fake ssiiz Roy, Cl 2p ee aE Vee Cf 2 PI} Pty NC: No connection Top view HMCS424 Oe Efro aly Pe ook: choo éédddasas aaa sae pnnonoAnAn Ro, Cs «Jp, pol 2 FPR RHR RTL Ro, tye aL IDs Ro, C2 21D, Ro. bd LIDS Ro; Cs EID, Ro, Fs s[Jo. Rig Ce sof] D5 Rigo up, Ro}. =Be Rife pp-42 B40: ai, Cle FP-44A abl, Rill" pp.gas SED and nel, Aig C2 311] Dp 3 Re) ]s0 x[]GND R29 Cle z= L]GND Re, C4 2[-J OSC, Re, Cle asJose, Ro, Css (jose, Re, C}10 aL Josc, Ra, Le aL Test PAO vee ee ree an spn be seer UUWUUUUoO Ra, je 2) | R4y SKE Bk 5 RSp/INT [he af) PASO dae 3 z5B RayART, C]= 2s) RaySt z Fi Voc C2" al] RagSCR 2 NC: No connection Top view ME 4494204 0047233 710 Ml 302 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series Pin Functions GND, Voc+ Vaisp (Power): GND, Voc and Vyisn _R0p to R05, Rip to R13, R2p to R23, R3p to R35, are the power supply pins for the MCU. Connect 4g to R43, RA, (R Ports): RO to R4 are 4-bit GND to ground (0 V) and apply the Voc power _ ports. RA is a 1-bit port. RO is an output port, RA is supply voltage to the Vcc pin. The Vgisp pin an input port, and R1 to R4 are 1/0 ports. RO, R1, (multiplexed with RA,) is a power supply for high- 2, and RA are high-voltage ports, and R3 and R4 voltage 1/O pins with maximum voltage of 40 V are standard ports. Each pin has a mask option (Voc - 40 V). For details, see the InpuyOutput which selects its circuit type. The pins R32 and section. R3, are multiplexed with INTg and INT). For HMCS424C/CL/AC, pins R4p, R4,, and R4p are TEST (Test): TEST is for test purposes only. — multiplexed with SCK, SI, and SO, respectively. Connect it to Voc. For details, see the Input/Output section. RESET (Reset): RESET resets the MCU. For INT, INT; (Interrupts): INT) and INT, are details, see the Reset section, external interrupts for the MCU. INT; can be used . as an external event input pin for timer B. INTo and OSC, OSC, (Oscillator Connections): OSC, and INT, are multiplexed with R3, and R3,, respec- OSC, are input pins for the internal oscillator tively. For details, see the Interrupt section. circuit. They can be connected to a crystal, ceramic, or external oscillator circuit. For details, §CK, SI, SO: Only applicable to the see the Internal Oscillator Circuit section. HMCS424C/CL/AC. The transmit clock I/O pin . (SCK), serial data input pin (SI), and serial data Dg to Dyg (D Port): The D port is an input/output output pin (SO) are used for serial interface. SCK, Port addressed by the bit. These 15 pins are all 1, and SO are multiplexed with R4g, R4y, and input/output pins. Do to Dy are standard and D4 to 4, respectively. For details, see the Serial Dyg are high-voltage pins. The circuit type foreach Interface section, pin can be selected using a mask option, For details, see the Input/Output section. MM 44956204 0047234 657 me 308 Hitachi OOOO eee

HMCS412 Series/HMCS414 Series/HMCS424 Series Block Diagram ‘Do Dy = D: a238° et | we re Dr tre k no —= SD | ai ose, i ro Daa | H : ret—4§ iz. ae RESET [3s B TT Ret [e ed agi; =. peta Hi Pesce HES 8) 2: | fora! - Be | 33 = Bie Fd | PEER Ry R4y/SO a 3 Ray/SI /SCK rag | =I: jo) Foner 3 fy Tt Reso § mF fi 5 Li g ME 4496204 0047235 593 mm 304 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series Oe i rer ecoc—oOoroo—r——ooowrereveveee’s Memory Map ROM Memory Map subroutines. The CAL instruction branches to these subroutines. The MCU contains the following ROM size shown in table 1. The ROM is described in the following Pattern Area paragraphs with the ROM memory map in figure 1. $0000 to $07FF (HMCS412C/CL/AC); $0000 to SOFFF (HMCS414C/CL/AC, HMCS424C/CL/ EE Vector Address Area ($0000 to $000F): AC): These locations can be used for ROM data. Locations $0000 through $000F can be used for The P instruction allows reference to the ROM data JMPL instructions to branch to the starting address as a pattern. of the initialization program and the interrupt programs. After reset or an interrupt, the program Program Area is executed from the vector address. $0000 to $07FF (HMCS412C/CL/AC); $0000 to SOFFF (HMCS414C/CL/AC, HMCS424C/CL/ Zero-Page Subroutine Area ($0000 to $003F): AC): These locations can be used for program Locations $0000 through $003F can be used for code. Table 1 ROM Size Table 2. RAM Size Series Name ROM Size Series Name RAM Size HMCS412C/CL/AC 2048-word x 10-bit HMCS412C/CL/AC. 160-digit x 4-bit HMCS414C/CLIAC 4096-word x 10-bit HMCS414C/CLIAC - HMCS424C/CLIAC HMCS424C/CL/AC 256-digit x 4-bit ° [$0000 0 MPL instruction }$0000 Vector address 1 (ump to reset routine) $0001 15 $000F 2) JMPL instruction $0002 16 0010 3 (jump to INT) routine) $0003 Zero-page subroutine 4 JMPL instruction $0004 (64 words) 5| Gump to INT; routine $0005 6 $003F. 6 JMPL instruction® $0006 64 $0040 7 (jump to timer A routine) $0007 Program pattern bold Soabo 9[ Gump totimer routine) —~) go009 woe (4086 words ore tof s000 4008 $1000 ny T s0008

12 MPL instruction* $0006

13, (jump to serial routine) $0000 Note: * Only applicable for the HMCS424C/CLIAC. Figure 1 ROM Memory Map ME 4496204 0047236 42T 905 Haach! a

HMCS412 Series/HMCS414 Series/HMCS424 Series RAM Memory Map registers cannot be accessed by RAM bit manipula- tion instructions. The MCU also contains the following RAM size shown in table 2 as the data and stack area. In Data Area ($020 to $07F (HMCS412C/CL/AC, addition to these areas, interrupt control bits and = HMCS414C/CL/AC); $020 to SODF (HMCS424C/ special function registers are also mapped on the © CL/AC)): The 16 digits of $020 through $02F are RAM memory space. The RAM memory map called memory registers (MR) and are accessible | (figure 2) is described in the following paragraphs. by the LAMR and XMRA instructions (figure 4). Interrupt Control Bits Area ($000 to $003): The Stack Area ($3C0 to $3FF): Locations $3CO interrupt control bits area (figure 3) is used for through $3FF are reserved for LIFO stacks to save interrupt control. It is accessible only by RAM bit _ the contents of the program counter (PC), status manipulation instructions. However, the interrupt flag (ST), and carry flag (CA) when subroutine request flag cannot be set by software. The RSP bit calls (CAL or CALL instruction) and interrupts are is used only to reset the stack pointer. processed. This area can be used as a 16-level nest- ing stack in which one level requires 4 digits. Special Function Registers Area ($004 to $00B): Figure 4 shows the save condition. The program ‘The special function registers are the mode or data__counter is restored by the RTN and RTNI instruc- Tegisters for the external interrupt, the serial inter- tions, The status flag and carry flag are restored face, and the timer/counters. These registers are only by the RTNI instruction. This area, when not classified into three types: write-only, read-only, used for a stack, is available as a data area. and read/write, as shown in figure 2, These ° [$000 0 's000 FAM-mapped registers 1 | $001 31 so1F 2 Interrupt control bits area $002 32 ; ‘$020 3 $003 a7}, Memon aes MF fsuar 4 soos Be S«d 5 $005 630i) 6 sos 127 so7F 7 $007 128 080 8 $008 (182 ds o [Ter mode regter Bw) W_| soo9 z ie | sere" resin ae 224 soFo " (TCBUMTLRU) ; RAW] $008 - a Stack

1023 S3FF

Notes: 1. Only applicable for the HMCS424C/CL/AC. 2. Two registers are mapped on the same address. . Timer counter Blower: Timer load ter B lower | RW: Read/write tg | Timerload a Figure 2 RAM Memory Map ME 4496204 0047237 3bb

306 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series —_—W reir en HE erie s'HMCS424 Series Bit3 Bit 2 Bit Bito

0 Imo IFO RSP Ie $000

(IM of INTs) (IF of INTo) (Reset SP bit) | (Interrupt enable tlag)

1 IMTA* IFTAS Mt Ft $001

(IM of timer A) (IF of timer A) (IM of INT;) (IF of INT;) IMTB IFTS ,

2 Not used Not used (IM of timer 8) (IF oftimerB) | $002

IMs* IFs* IF: Interrupt request flag IM: Interrupt mask IE: Interrupt enable flag SP: Stack pointer Note: Each bit of the interrupt control bits area is set by the SEM/SEMD instruction, reset by the REM/REMD instruction, and tested by the TM/TMD instruction. It is not affected by other instructions. Furthermore, the interrupt request flag is not affected by the SEM/SEMD instruction. The value of the status flag becomes invalid when the RSP bit or the unusable bits are tested by the TM or TMD instruction. * Only applicable for the HMCS424C/CLIAC. Figure 3 Configuration of Interrupt Control Bits Area Memory registers Stack area 33['MR (1) }$021 34[ MR (2) |$022 35[ MR (3) | $023 36] MR (4) |$024 37[ MR (5) |$025 38] MR (6) |$026 39| MR (7) |$027 Bits Bit2 _—-Bit1 _—Bito 40] MR (8) |$028 a a ee

41 MA(9) |$029 1920] ST | PCy PCr PCy | $arc

43 $028 1021] PCio PCs; PC, PC; | $3FD 44[ MR (12) |$020 a a ee 45{MA (33) |$020 1022} CA | PCs; PC; PC, | $aFE 46] MR (14) |$02E = a es | S 47[MR (15) |s02F 1023 sore 1028] POs PCa | PC: | POs | Sarr PCy3 to PCo: Program counter ST: Status flag CA: Carry tlag Notes: 1. Since HMCS412C/CLIAC have 2 k ROM, PC;;, POya, and PC;g are not used. 2. Since HMCS414C/CLIAC and HMCS424C/CLIAC have 4 k ROM, PC;2 and PO, are not used. Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position ME 4456204 0047238 2eTo 307 Hitachi ee

a HMCS412 Series/HMCS414 Series/HMCS424 Series Functional Description Registers and Flags overflow from the ALU generated by an arithmetic operation. It is also affected by the SEC, REC, The MCU has nine registers and two flags for the = ROTL, and ROTR instructions. CPU operations (figure 5). During an interrupt, the carry flag is pushed onto | | Accumulator (A), B Register (B): The 4-bit the stack. It is restored by the RTNI instruction, but accumulator and B register hold the results of the not by the RTN instruction. | arithmetic logic unit (ALU), and transfer data . to/from memory, I/O, and other registers. Status Flag (ST): The status flag (ST) holds the ALU overflow, ALU non-zero, and the results of a W Register (W), X Register (X), Y Register (Y): bit test instruction for the arithmetic or compare ‘The 2-bit write-only W register, and the 4-bit X instructions. It is a branch condition of the BR, and Y registers are used for indirect addressing of | BRL, CAL, or CALL instruction. The value of the RAM. The Y register is also used for D port — status flag remains unchanged until the next addressing. arithmetic, compare, or bit test instruction is exe- . . cuted. The status flag becomes a 1 after the BR, SPX Register (SPX), SPY Register (SPY): The BRL, CAL, or CALL instruction is executed or not. 4bit registers SPX and SPY are used to assist the uring an interrupt, the status flag is pushed onto X and Y registers, respectively. the stack and restored back from the stack by the RTNI i ion, but not TN instruction. Carry Flag (CA): The carry flag (CA) stores the instruction, but by the RTN instruction. a 3 ° A peta 3 ) 1 i) [ae] wear 3 o 3 0 Y register

3 L')

‘Status flag 13. 0

2 EI Q

(TTT 6] sai Figure 5 Registers and Flags me 4496204 0047239 135 308 Hitachi eee

executed, of HMCS412C/CL/AC and HMCS414C/CL/AC. $3FF. It is decremented by 4 when data is Pushed vided to control and maintain the interrupt request. testored from it. The stack can only be used up to interrupt operations. Table 3. Vector Addresses and Interrupt Priority Note: * Only applicable for the HMCS424C/CLIAC.

HMCS412 Series/HMCS414 Series/HMCS424 Series ae Figure 6 is a block diagram of the interrupt control _—_ chart. If an interrupt is requested, the instruction circuit, Table 3 shows the interrupt priority and being executed finishes in the first cycle. The IE is vector addresses, and table 4 shows the interrupt _reset in the second cycle. In the second and third conditions corresponding to each interrupt source. cycles, the carry flag, status flag, and program . . . counter are pushed onto the stack. In the third ‘The interrupt request is generated when the IF is set cycle, the instruction is re-executed after jumping to 1 and IM is 0. If the IE is | at this time, the inter- (0 the vector address. | rupt will be activated and vector addresses will be generated from the priority PLA corresponding to _In each vector address, program the JMPL instruc- the interrupt sources. tion to branch to the starting address of the inter- . . Tupt program. The IF which caused the interrupt Figure 7 shows the interrupt processing sequence, —_ must be reset by software in the interrupt program. and figure 8 shows the interrupt processing flow- we so008 Sequence control [} [>] bush Pores + Reset IE + Jump to vector address sons (\\ IH $0003 d [wo] OY | Vector | Priory control address ic seo. [| in $001.4 4d) — a BO i a ft i [wl Fr naicates only applicable for HMCS424C/CL/AG. Note: $m, nis RAM address $m, bit number n. Figure 6 Interrupt Control Circuit Block diagram ME 4496204 0047241 697 a

310 Hitachi

4.44...

HMCS412 Series/HMCS414 Series/HMCS424 Series EE rigs TE et Series IMCS 424 Series oe 1 2 3 4 5 6 ‘execution Stacking; \\ ‘Stacking; ‘on the vector address Instruction execution at of the interrupt routine Figure7 Interrupt Processing Sequence Me 44596204 OO47e4e2 723 311 Hitachi Ee

HMCS412 Series/HMCS414 Series/HMCS424 Series No | | Yes eS Yes ‘Stack — (PC) Stack < (CA) Stack « (ST) os ‘No i PC + $0006 i “<> . interrupt? No F777 Indicates only applicable S77 P Tre erenererrenrrennsesennasessnnnsssensaeenseseesay 1... forthe HMCSA24C/CLIAG, | i i (serial itorupt) Figure 8 Interrupt Processing Flowchart Mm 4496204 0047243 bbT 312 Hitachi a

—— SSSSSSSSSSSSSSSSSSSSSS HMCS412 Series/HMCS414 Series/HMCS424 Series Interrupt Enable Flag (IE: $000, Bit 0): The timer B external event input, the external interrupt interrupt enable flag enables/disables interrupt mask (IM1) has to be set so that the INT, interrupt Tequests as shown in table 5. It is reset by an inter- request will not be accepted (table 7). Tupt and set by the RTNI instruction. External Interrupt Request Flags (IFO: $000, External Interrupts (INTo, INT}): The external —_ Bit 2; IF1: $001, Bit 0): The external interrupt interrupt request inputs (INTo, INT}) can be select- request flags (IFO, IF1) are set at the falling edge of ed by the port mode register (PMR: $004). Setting the INT, and INT; inputs, respectively. , bit 3_and bit 2 of PMR causes R3/INT) and R3,/INTp pins to be used as INT, and INT, External Interrupt Masks (IMO: $000, Bit 3; respectively. IM1: $001, Bit 1): The external interrupt masks mask the external interrupt requests. The external interrupt request flags (IFO, IF1) are . . set at the falling edge of INTy and INT, inputs Port Mode Register (PMR: $004): The 4-bit (table 6). write-only port mode register controls the R3,/INTo, R3,/INT;, R4,/SI, and R42/SO pins as The INT, input can be used as a clock signal input shown in table 8, The port mode register will be to timer B, in which timer B counts up at each initialized to $0 by MCU reset. These pins are falling edge of the INT, input. When using INT, as _ therefore initially used as ports. Table 5 Interrupt Enable Flag Table 8 Port Mode Register te Interrupt Enabled/Disabled PMR3 R3,/INT, Pin f) Disabled 0 Used as R33 port inputoutput pin

1 Enabled 1 Used as INT; input pin

Table 6 External Interrupt Request Flags PMR2 R3,/INTo Pin IFO, 1F1 Interrupt Requests 0 ___Usedas R3zpor inpuvvoutput pin

2 No 1 Used as INT, input pin

TT R4,/SI Pin sed as RA, Table7 External Interrupt Masks O___Usedias Ry port inputioutput pin

1 Used as SI input pin

) Enabled PMRO R4/SO Pin

1 Disabled (masked) C) Used as R42 port input/output pin

1 Used as SO output pin

Note: PMRO and PMR1 can be only used by the HMCS424C/CLIAC. M@@ 4456204 0047244 STL 313 Hitachi eee

HMCS412 Series/HMCS414 Series/HMCS424 Series Serial Interface Only applicable for the HMCS424C/CL/AC. The _— write-only serial mode register controls the serial interface is used to transmit/receive 8-bit data. R4g/SCK, prescaler divide ratio, and transmit clock serially. It consists of the serial data register, the source, as shown in table 9. The write signal to the serial mode register, the octal counter, and the serial mode register controls the operating state of multiplexer, as illustrated in figure 9. Pin R4g/SCK _ the serial interface. | and the transmit clock signal are controlled by the oo . . serial mode register. The contents of the serial data The write signal to the serial mode register stops register can be written into or read out by software. the serial data register and octal counter from The data in the serial data register can be shifted applying the transmit clock, and it also resets the synchronously with the transmit clock signal. octal counter to $0 simultaneously. Therefore, when the serial interface is in the transfer state, the The STS instruction initiates serial interface opera- _ write signal causes the serial mode register to cease tions and resets the octal counter to $0. The counter the data transfer and to set the serial interrupt Starts to count at the falling edge of the transmit —_request flag. clock signals (SCK) and increments by one at the ; . rising edge of the SCK. When the octal counter is | The contents of the serial mode register will be reset to $0 after eight transmit clock signals, or changed on the second instruction cycle after writ- when a transmit/receive operation is discontinued _ing into the serial mode register. Therefore, it is by resetting the octal counter, the serial interrupt Necessary to execute the STS instruction after the Tequest flag will be set. data in the serial mode register has been changed completely. The serial mode register will be reset Serial Mode Register (SMR: $005): The 4-bit to $0 by MCU reset. System! OC (3 bits) |SROF ook Prescaler (11 bits) Octal counter IFS a Interrupt request flag glaiole of serial Deki interface ri +2 bel MPX scK fafa SR (8 bits) Serial data register SMR (4 bits) PMR (4 bits) | | [Serial mode register| Port mode register mee |_| R4,/SI R4,/SO port port port | Figure 9 Serial Interface Block Diagram ME 4496204 0047245 432 314 Hitachi a

a HMCS412 Series/HMCS414 Series/HMCS424 Series SS eee eS Serial Data Register (SRL: $006, SRU: $007): to the serial data register, to MSB first, synchro- The 8-bit read/write serial data register consists of __ nously with the rising edge of the transmit clock. a low-order digit (SRL: $006) and a high-order —_ Figure 10 shows the I/O timing chart for the trans- digit (SRU: $007). mit clock signal and the data. ‘The data in the serial data register will be output The read/write operations of the serial data register from the SO pin, from LSB to MSB, synchronously should be performed after the completion of data with the falling edge of the transmit clock signal. _transmit/receive. Otherwise the data may not be At the same time, external data will be input SI pin —_ guaranteed. Table 9 Serial Mode Register SMR3 R4g/SCK

0 Used as Ry port input/output pin

1 Used as SCK input/output pin

SMR2_ SMR1 = SMRO R4y/SCK Port Clock Source Divide Ratio —_ Divide Ratio i) 0 0 5CK output Prescaler +2048 + 4096 0 0 1 SCK output Prascaler +512 +1024 0 1 0 SCK output Prescaler +128 _ +256 | 0 1 1 ‘SCK output Prescaler +32 +64 1 0 0 SCK output Prescaler +8 +16 1 0 1 ‘SCK output Prescaler +2 +4 1 1 tC) SCK output ‘System clock - +1 1 1 1 SCK input External clock - = Transmit clock 1 2 3 4.5 6 7 8 Va) VVepY¥yYy iy wiser Jol [ [| fo A A A {\\ A A A i Serial input data latch timing Figure 10 Serial Interface I/O Timing WM 4456204 0047246 379 315 Hitachi Ne

HMCS412 Series/HMCS414 Series/HMCS424 Series Serial Interrupt Request Flag (IFS: $003, Bit 0): —_In transmit wait state the falling edge of the first The serial interrupt request flag will be set when —_ transmit clock causes the serial interface to shift to the octal counter counts eight transmit clock the transfer state, while the octal counter counts up signals, or when data transfer is discontinued by and the serial data register shifts simultaneously. If resetting the octal counter. Refer to table 10. the clock continuous output mode is selected, however, the serial interface stays in the transmit Serial Interrupt Mask (IMS: $003, Bit 1): The clock wait state while the transmit clock outputs | serial interrupt mask masks the interrupt request. continuously. Refer to table 11. The octal counter becomes 000 again after 8 Selection and Change of the Operation Mode: transmit clocks or by the execution of the STS Table 12 shows the serial interface operation instruction, so that the serial interface returns to the modes which are determined by a combination of transmit clock wait state, and the serial interrupt the value in the port mode register and that in the request flag is set simultaneously. serial mode register. Initialize the serial interface by the write signal to the serial mode register when When the internal transmit clock is selected, the the operation mode is changed. transmit clock output is triggered by the execution of the STS instruction, and stops after 8 clock. Operating State of Serial Interface: The serial interface has three operating states: the STS wait- Example of Transmit Clock Error Detection: ing state, transmit clock wait state, and transfer ‘The serial interface functions abnormally when the state, as shown in figure 11. transmit clock is disturbed by external noise. In this case, transmit clock errors can be detected by the The STS waiting state is the initialization state of procedure shown in figure 12. the serial interface internal state. The serial interface is put into this state in one of two ways: If more than 8 transmit clock are applied in the either by changing the operation mode through a _ transmit clock wait state, the state of the serial data change in the port mode register, or by writing _interface shifts in the following sequence: transfer data into the serial mode register. In this state, the _ state, transmit clock wait state, and transfer state serial interface does not operate even if the transmit again. The serial interrupt flag should be reset clock is applied. If the STS instruction is executed, _ before entering into the STS state by writing data to the serial interface shifts to the transmit clock wait | SMR. This procedure causes the serial interface state. request flag to be set again. Table 10 Serial Interrupt Request Flag Table 12 Serial Interface Operation Mode IFS Interrupt Request Serial Interface 0.\\No:~C*«SSMR_ PMR. PMR2._ Operating Mode 7. ve 1 ° 0 Clock continuous output

1 Yes mode

Table 11 Serial Interrupt Mask TO 1 1 0 Receive mode Ms Interrupt Request 1 1 1 Transmit/receive mode ° Enabled

1 Disabled (masked)

ME 4496204 0047247 205 Me 316 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series $$ Ee Sires ES Serics/HMCS424 Series STS waiting state (aoe! counter = 000 .) ransmit clock disabl . Change PMR’ . Write to Change PMR SMR Pe Waite to SMA STs (FS <1) | instruction \\ yy Transmit clock Transmit clock wait state Transfer state (octal counter = 000) 8 transmit clocks, {octal counter # 000) STS instruction (IFS —1) Note: * Implies the change of operation mode as shown below. Clock + Transmit mode continuous + Receive mode output mode + Transmit/receive mode Figure 11 Serial Interface Operation State Transmit/receive (IFS <1) Interrupt disable FS 0 Yes Transmit clock error processing No Table 12 Example of Transmit Clock Error Detection M@ 4496204 0047248 141 a 317 Hitachi a

timer mode register A (TMA), timer mode register occurring. B (TMB), and the serial mode register (SMR).

2 FEET ETTS interrupt

Note: * Timer A only applicable for the HMCS424C/CLIAC. Figure 13. Timer Block Diagram

The timer mode register A is initialized to $0 by low-order digit first, and then the high-order digit. Timer Mode Register B (TMB: $009): 4-bit to $00 by the MCU reset. table 14. Timer mode register B is initialized to $0 high-order digit first, and then the low-order digit. the time when the high-order digit is read.

HMCS412 Series/HMCS414 Series/HMCS424 Series —eee PMR: $004 ‘SMR: $005 Poe] [oe —_— | + transmit clock selection | R40/SCK pin mode selection | R42/SO pin mode selection R4,/SI pin mode selection R3,/INTo pin mode selection R3,/INT, pin mode selection TMA: $008 TMB: $009 freee] fre ven TMA2|TMA1 'TMB1 | TMBO ma i SS + __rimer-8 input clock selection ‘Auto-reload function selection Timer-A input clock selection Figure 14 Mode Register Configuration and Function ME 4496204 0047251 73b 320 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series Timer A Interrupt Request Flag (IFTA: $001, Timer B Interrupt Request Flag (IFTB: $002, Bit 2): The timer A interrupt request flag is set by _ Bit 0): The timer B interrupt request flag is set by the timer A overflow output (table 15). the overflow output of timer B (table 17). Timer A Interrupt Mask (IMTA: $001, Bit 3): Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer A interrupt mask prevents an interrupt The timer B interrupt mask prevents an interrupt request from being generated by the timer A inter- request from being generated by the timer B inter- Tupt request flag (table 16). Tupt request flag (table 18). Table 15 Timer A Interrupt Request Flag Table 17. Timer B Interrupt Request Flag IFTA Interrupt Request IFTB Interrupt Request rs a a

1 Yes 1 Yes

Table 16 Timer A Interrupt Mask Table 18 Timer B Interrupt Mask IMTA Interrupt Request IMTB Interrupt Request

0 Enabled _ o Enabled

1 Disabled (masked) 1 Disabled (masked)

Mm 4456204 O047eSe b?e 321 Hitachi a

HMCS412 Series/HMCS414 Series/HMCS424 Series eee Input/Output The MCU has 36 I/O pins, 12 standard and 24 high —_R Ports: The six R ports are composed of 16 /O voltage. One of three circuit types can be selected _ pins, 4 output-only pins, and 1 input-only pin. Data by the mask option for each standard pin: CMOS, _ is input through the LAR and LBR instructions, with pull-up MOS, and without pull-up MOS and output through the LRA and LRB instructions. (NMOS open drain). One of two circuit types can The MCU will not be affected by writing into the | be selected for each high-voltage pin: with pull- _input-only and/or non-existing port, while invalid down MOS and without pull-down MOS (PMOS data will be read from the output-only and/or non- open drain). Since the pull-down MOS is connect- _ existing ports. ed to the internal Vip line, the RA,/Vgisp Pin must | . be selected as Vgisp via the mask option when at The R32, R33, R4g, R4y, and R4, pins are multi- least one high-voltage pin is selected as with pull- _ plexed with the INTo, INT; SCK, SI, and SO pins, down MOS. See table 19 for I/O pin circuit types. respectively. See table 19 as for the classification of standard pins, high-voltage pins, and selectable ‘When every input/output pin is used as an input circuit types of these W/O pins. pin, the mask option and output data must be selected as specified in table 20. Unused I/O Pins: If unused I/O pins are left floating, the LSI may malfunction due to noise. Output Circuit Operation of With Pull-Up MOS __ The I/O pins should be fixed as follows to prevent Standard Pins: In the standard pin option with malfunction. pull-up MOS, the circuit shown in figure 15 is used to shorten the rise time of output. High-voltage pins: Select without pull-down MOS (PMOS open drain) via the mask option and When the MCU executes an output instruction, it connect to Voc on the printed circuit board. generates a write pulse to the R port addressed by this instruction. This pulse will switch the PMOS Standard pins: Select without pull-up MOS (B) on and shorten the rise time. The write pulse © (NMOS open drain) via the mask option and keeps PMOS in the on state for one-eighth of the connect to GND on the printed circuit board, instruction cycle time. While the write pulse is 0, a — high output level is maintained by the pull-up R4o/SCK and R42/SO should be set to Ray and R4 MOS (C). by the serial mode register and port mode register, Tespectively. When the HLT signal become 0 in the stop mode, MOS (A), (B), and (C) turn off. Reset D Port: The /O D port has 15 discrete 1/0 pins, Setting the RESET pin high resets the MCU. At each of which can be addressed independently. It Power-on or when cancelling the stop mode, the can be set/reset through the SED/RED and ‘eset must satisfy tac for the oscillator to stabilize, SEDD/REDD instructions, and can be tested 0 all other cases, at least two instruction cycles are | through the TD and TDD instructions. See table 19 Teduired for the MCU to be reset. as for the classification of the standard pin, high-rate 21 shows the components initialized by voltage pin, and the 1/O pin circuit types. MCU reset, and the status of each. Table 22 shows how registers recover from the stop mode. Me 4496204 0047253 505 322 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series eee te DertesHMCS424 Series Table 19 1/O Pin Circuit Types Standard Pins eee Without Pull-Up MOS With Pull-Up MOS (NMOS Open Drain) (A) (B) CMOS (Cc) Pins reer SS MOS (C) Ping vo ALT aT Input Do to Dg, common e--L >~ Get TD ota FT D> et F3p to RBs, pins Vee) Ve ite Vee Rap to R4g , . _ —. oto oO aia Gas Output High Voltage Pins ae Without Pull-Down MOS (PMOS Open Drain) (D) With Pull-Down MOS (E) Pins errr) With Pull-Down MOS(E) Pins vO Veo Yoo D, to Djs, common _ Rig to R1. < CT oo pins Ootout tert R2q to R23, data ’ data eon RCT Veep aT i! Ir it ALT put HLT Gata eee Output Voc ROp to ROg pins Veo FLT ot tout aaa Veow Vasp eee Input RA, pins __ Oo put data SSS ME 4496204 0047254 445 mm 328 Hitachi Neen nnn

———— HMCS412 Series/HMCS414 Series/HMCS424 Series Table 19 I/O Pin Circuit Types (cont) Standard Pins Without Pull-Up MOS (NMOS Open Drain) or CMOS (A or C) With Pull-Up MOS (B) Pins | common ne sok HLT oe pins T Vv vi TF mode) Neo _ CT + mode select ¢ |e Hoa sleet | cals internal SCK internal SCK Output so* pins Veo Vee | Veo Shel . so so Input INTo, pins inte Input ti sit, a Oe a SCR HUT HLT (input Le Note: In the stop mode, HLT is 0, HLT is 1, and I/O pins are in high impedance. * Only applicable for the HMCS424C/CLIAC. If the MCU is interrupted by the serial interface in the external clock input mode, the SCK terminal becomes input only. ME 4496204 0047255 381 324 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series eeeaeeeeEeseeeeses ertes Table 20 Data Input from Common Input/Output Pins VO Pin Circuit Type Input Possible Input Pin State SS put in State Standard pins cmos No _ = Without pull-up MOS. Yes 1 (NMOS ‘open drain) _ _ _ _ With pull-up MOS Yes" 41 - , High voltage pins Without pull-down MOS Yes 0 (PMOS open drain) _ . _. With pull-down MOS Yes 0 ee Veo Veg ~~] MN Write pulse { (output f | PMOS @) instruction) Pull-up MOS (C)| E ACT | | O NMOS (A) Ll [ } - Data On-Resistance Value HMCS412C, HMCS412AC HMCS412CL HMCS414C, HMCS414AC = HMCS414CL MOS Buffer HMCS424C, HMCS424AC HMCS424CL A Approx. 250 2 Approx. 1k B Approx. 1k Approx. 1.7 k2 _ Cc Approx. 30 kQ to 160 kQ Approx. 60 kQ to 1 MQ (Veg = 3 V) (Voc = 5 V) Approx. 30 kQ to 160 k® (Vec = 5 V) $c PRON, SO IE 10 160 KS? (Vee = SV) 1 instruction cycle Write pulse ee Oe ee Figure 15 Output Circuit Operation of With Pull-Up MOS Standard Pins ME 4496204 OO4725b 218 a 325 Hitachi —— ee

HMCS412 Series/HMCS414 Series/HMCS424 Series | Table 21 Initial Values after MCU Reset | Item Initial Value Contents Program counter (PC) $0000 Execute program from the top of | ROM address ) | branch instructions | ‘Stack pointer (SP) $3FF Stack level is 0 ; VO pins, Standard Without pull-up 1 Oo ~ Enable input a output register pins MOS With pultup 1 “Enable input MOS CMOS tl ™—CS High voitage Without pul- 0 = Enableinput’ = pins down MOS: down MOS: interrupt flags __ Interrupt enable flag (IE) ° Inhibit all interrupts and mask Interrupt request flag (IF) ° No interrupt request Interrupt mask (IM) 1 Mask interrupt request Mode registers Posrt mode register (PMR) ‘0000 See Port Mode Register section Serial mode register* (SMR) 0000 See Serial Mode Register section Timer mode register A* (TMA) 000 "See Timer t Mode Register A section Timer mode register B (TMB) 0000 See Timer Mode Register B section Timer/counters Prescaler $000 - Timer counter A* (TCA) $00 - Timer counter B (TCB) $00 = Timerloadregister(TLA) $00, — TT Octal counter* 000 - Note: * Only applicable for the HMCS424C/CLIAC. Wm™ 4496204 0047257 154 a 326 Hitachi

—SSSSSSSSSSSSSSSSSSSSSSSSs HMCS412 Series/HMCS414 Series/HMCS424 Series SSS eeeeEee———e—eeeeeeew ets Table 22 Initial Values after Cancelling Stop and Other Modes by Reset After MCU Reset to Recover After MCU Reset to Recover ttem from Stop Mode from Other Modes mir om Dor Motes Carry flag (ca) The contents of the items before The contents of the items before ‘Accumulator —(A).~—~*S*«*«CU rset re not retained MCU reset are not retained. ——______________ tis necessary to initialize them _It is necessary to initialize them B register (8) by software. by software, , W register (Ww) X/SPX registers (X/SPX) Y/SPY registers (Y/SPY) Serial data registers (SR) RAM The contents of RAM before The contents of RAM before MCU reset (just before STOP MCU reset are not retained. instruction) are retained. ttis necessary to initialize them by software. Note: * Only applicable for the HMCS424C/CLIAC. ME 4456204 0047258 O40 me 327 Hitachi Neen

$$ a SSSSSSSSSSSSSSSSSSSSSseee HMCS412 Series/HMCS414 Series/HMCS424 Series SSeS eee eee eee Serres Table 24 Examples of Oscillator Circuits Circuit Constants Circuit Configuration HMCS424C HMCS424CL HMCS424AC ———— O00 eee eee One External ‘Oscillator clock lose, operation a pen — asce Ceramic < Ceramic oscillator Ceramic oscillator “Ceramic oscillator oscillator f lose, CSA 4.00MG CSA 2.000MK CSA 4.00MG ‘Ceramic ! CSA 2.000MK (Murata) (Murata) ecto (Murata) Re 1MQ£20% Re 1 MQ. 420% losc, Re 1MQ420% = Cy: 30 pF 420% Cy: 30 pF #20% cae Cy:30 pF +20% Cx: 30 pF+20% Cp 30 pF 420% Co: 30 pF 20% Crystal Re 1MQ420% = — Ry: 1 M2.420% oscillator cy, Cy: 10 pF to 22 pF C,: 10 pF to 22 pF cota J 420% #20% Fe C2: 10 pF to 22 pF Co: 10 pF to 22 pF lose, £20% 420% Ce a Crystal: Equivalent Crystal: Equivalent GNo circuit shown at circuit shown at Rroaparel bottom left bottom left ieee Co: 7 pF max. Co: 7 pF max. osc.=f TERT feosc, Re: 100.2 max. Rg: 100 O max. & f: 1.0 MHz to f: 1,0 MHz to 4.5 MHz 4.5 MHz - Ry 2MQ420%

3 S Cy: 10 pF to 22 pF

crystal jose 420% Ry Co: 10 pF to 22 pF lose, 420% fF Crystal: Equivalent ON circuit shown at reuse bottom left omy 27 pF max, osci=f TE AS pose. Re: 100 © max. Co f: 1.0 MHz to

2.25 MHz

Resistor Ry 18kQ 41% - = oscillator jose fr Josc. Notes: 1. The circuit parameters written above are recommended by the crystal or ceramic oscillator manufacture. The circuit parameters are affected by the crystal, ceramic resonator, and the floating capacitance when designing the board. When using the resonator, consult with the crystal or ceramic oscillator manutacture to determine the circuit parameters. 2. Wiring among OSC,, OSCz, and other elements should be as short as possible, and avoid crossing other wires. Refer to the recommended layout of the crystal and ceramic oscillator (figure 17). 3. Resistor oscillator can be used for HMCS412C and HMCS414C MB 4456204 OO472b0 749 Me 329 Hitachi a

HMCS412 Series/HMCS414 Series/HMCS424 Series Operating Modes The MCU has two low-power dissipation modes, _the oscillator circuit is active, and the interrupts and standby mode and stop mode (table 25). Figure 18 _timer/counters remain working, On the other hand, is a mode transition diagram for these modes. the CPU stops since the clock related to the instruc- tion execution stops. Registers, RAM, and I/O pins Standby Mode: Executing the SBY instruction retain the states they were in just before the MCU | puts the MCU into standby mode. In standby mode, went into standby mode. Table 25 Low-Power Dissipation Modes Function Timer! Low-Power Inpuy Counters, Dissipation Osclitstor Instruction Registers, Interrupts Output Serial Cancellation Mode Instruction Circuit Execution Flags. Function RAM Pins Interface Method Standby SBY ‘Active Stop Retained Active ‘Retained Retained’? Active RESET mode Instruction input, interrupt tet Stop mode STOP ‘Stop Stop Reset"! — Stop Retained High Stop RESET instruction impedance’? input Notes: 1. The MCU recovers from the stop mode by RESET input. Refer to table 21 for the contents of the flag and registers. 2. A high-voltage pin of with pull-down MOS is tied to the Veisp Power supply through the pull-down MOS. With pull-down: MOS on, a pull-down current flows when a difference between the pin voltage and the Vege, voltage exists. This is in addition to the current dissipation in the stop mode (Iso). 3. When an VO circuit is active, an VO current may flow, depending on the state of the 1/0 pin in standby mode. This is in adkition to the current dissipation in standby mode. Active mode SBY STOP instruction instruction Interrupt request Standby Stop mode RESET =1 mode RESET =1 RESET =1 Figure 18 MCU Operation Mode Transition @™ 4456204 0047261 bas a 330 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series FE ee SEES Standby mode may be cancelled by inputting asserted, the interrupt is executed, while if it is 0, RESET or by asserting an interrupt request. In the the interrupt request is put on hold and normal former case the MCU is reset. In the later case, the _ instruction execution continues, MCU becomes active and executes the next . instruction following the SBY instruction. If the Figure 19 shows the flowchart of the standby interrupt enable flag is 1 when an interrupt request. Mode. Oscillator: Active Peripheral clocks: Active All other clocks: Stop Yes <-> No Yes i : No! i Yes | : : No! Yes | <-> Restart Restart processor clocks| processor clocks| instruction “ S £7777") indicates only applicable for Yes tes.3 the HMCS424C/CUAC, Execute ed Figure 19 MCU Operating Flowchart in Standby Mode ME 44956204 OO472b2 S11 ml 331 Hitachi Neen

HMCS412 Series/HMCS414 Series/HMCS424 Series Stop Mode: Executing the STOP instruction bring stabilize. (Refer to AC Characteristics table.) After the MCU into stop mode, in which the oscillator _ the stop mode is cancelled, RAM retains the state it circuit and every function of the MCU stop. was in just before the MCU went into stop mode, but the accumulator, B register, W register Y/SPY Stop mode may be cancelled by resetting the MCU. registers, and carry flag will not retain their At this time, as shown in figure 20, RESET input contents, "| must be applied for at least tac for oscillation to Stop mode oscar TTT __, AIM Internal clock RESET STOP instruction tres 2 tac (stabilization time) execution Figure 20 Timing of Stop Mode Cancellation Mm 4496204 0047263 458 ml 392 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series Addressing Modes RAM Addressing Modes When the BR instruction is on a page boundary (256n + 255) (figure 23), executing it transfer the As shown in figure 21, the MCU has three RAM PC contents to the next page according to the hard- addressing modes: register indirect addressing, ware architecture. Consequently, the program direct addressing, and memory register addressing. branches to the next page when the BR instruction | is used on a page boundary. The HMCS400 series Register Indirect Addressing Mode: The W cross macroassembler has an automatic paging register, X register, and Y register contents (10 bits facility for ROM pages. total) are used as the RAM address. | . , . Zero-Page Addressing Mode: By executing the Direct Addressing Mode: A direct addressing CAL instruction, the program can branch to the instruction consists of two words, with the world zero-page subroutine area, which is located at (10 bits) following the opcode used as the RAM $9900 to $003F. When the CAL instruction is exe- address. cuted, 6-bits of immediate data are placed in the . . low-order six bits of the program counter (PCs to Memory Register Addressing Mode: The and 0s are placed in the high-order eight bits memory registers (16 digits from $020 to $02F) are (PC 3 to PC). accessed by executing the LAMR and XMRA 13 6 instructions. Table Data Addressing Mode: By executing the ‘ . TBR instruction, the program can branch to the ROM Addressing Modes and the PInstruction a sarass determined by the contents of the 4-bits The MCU has four ROM addressing modes as immediate data, accumulator, and B register. shown in figure 22, P Instruction: ROM data addressed by table data i addressing can be referenced by the P instruction Direct Addressing Mode: The program can Ss retere " ° branch to any address in ROM memory space by Core 24). When bit 8 in the ROM data is 18 bi executing the JMPL, BRL, or CALL instruction. ‘OM Gave are wren ne, the wOM dee bits (PC3 to PCo) with 14-bit immediate data When both bits 8 and 9 are 1, ROM data are writ Current Page Addressing Mode: The MCU has 8 = ten. into the accumulator and B Tegister, and also to pages of ROM with 256 words per page. By exe- the R1 and R2 port output registers at the same cuting the BR instruction, the program can branch time. to an address on the current page. This instruction : ff replaces the low-order eight bits of the program The P instruction has no effect on the program counter (PC, to PCy) with 8-bit immediate data. counter. M@™ 4496204 0047264 354 333 Hitachi OOOO

HMCS412 Series/HMCS414 Series/HMCS424 Series —— eEmemee W register X register Y register — FT [ws] wo] x0 [x2] x [>] ve] ve] [vo] = rains sree rear Register Indirect Addressing Instruction 1st word Instruction 2nd word naan foie slo ar ar or Direct Addressing Instruction [__oveede ms [me] [| 0 00010 ae ranaseos araraarie pee ed Memory Register Addressing Figure 21 RAM Addressing Modes

HMCS412 Series/HMCS414 Series/HMCS424 Series SO A ene rere eee SE eee ee eres: [UMPL] [BRL (CAL) instruction 1st word Instruction 2nd word oO eee Opcode Ps Pe P; Po|dg de dp dg ds dy dy dp 6, do Program counter |PC,3 PC, PC, ,PC jg PCy PCy PC, PC, PCs PC, PC, PC, PC, PCy Direct Addressing Instruction Program counter |PC,gPC;2PC,;PC;)PCg PC PC, PC, PC; PC, PC3 PC» PC, PC, Current Page Addressing Instruction oo Program counter |PC,3PC; PC, ;PC,gPC, PC, PC, PC, PC; PC, PCy PC PC, PC, Zero Page Addressing Instruction B register Accumulator A if PETTITT | Program counter |PC,3PC;2PC,;PC;> PCy PC PC, PC, PCs PC, PCy PC PC, PCy Table Data Addressing Figure 22 ROM Addressing Modes ME 4456204 0047266 1b? 335 Hitachi Cenc nncnenee ee

HMCS412 Series/HMCS414 Series/HMCS424 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage Veco 0.3 to +7.0 Vv Pin voltage vt 0.3 to Veg + 0.3 Vv 1 Veo - 45 to Veg +0.3 v 2 Total permissible input current Ilo 25 (25) mA 3 p Maximum input current lo 15 (15) mA 5,6 Maximum output current lo 4(2) mA 6,7, 10 6 (3) mA 7, 8,10 30 (15) mA 7,9,10 Total permissible output current -Zly 85 (100) mA 4,10 Operating temperature Tope 20 to +75 °c Storage temperature Tog 55 to +125 °c Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation should be under the conditions of the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. All voltages are with respect to GND. 1. Standard pins. 2. High-voltage pins. 3. Total permissible input current is the total sum of input currents which flow in from all I/O pins to GND simultaneously. 4. Total permissible output current is the total sum of the output currents which flow out from Veg to all /O pins simultaneously. 5. Maximum output current is the maximum amount of input current from each I/O pin to GND. 6. Do to Dg, R3, and RA. 7. Maximum output current is the maximum amount of output current from Vgc to each VO pin. 8. ROto R2. 9. Dg to Diy. 10. -Zlp = 100 mA if -Ip is equal to or less than 2 MA, 3 mA, or 15 mA. Me 4456204 CO47ebs TIT 337 Hitachi ee

HIMCS412 Series HMCS414 GeriecHMC&ADa dais ————— HMCS412 Series/HMCS414 Series/HMCS424 Series eS HMCS412C/CL/AC Electrical Characteristics DC Characteristics (GND = 0 V, Vuiep = Voc -— 40 V to Vcc, T, = -20°C to +75°C, HMCS412C: Voc = 3.5 V to 6 V, HMCS412CL: Vcc = 2.5 V to 6 V, HMCS4I12AC: Vcc = 4.5 V to 6 V) item Symbol Pin Min Max Unit Test Condition Notes + OOO—— Test Concition _Notes | Input high Vig RESET, 0.8Vcg 9 Veg +0.3 -V | voltage R3p/INTp, R3,/INT, osc, Vec-90.5 Voc+0.3 V —_HMCS412C/AC Voo-0.3 Vec+03 V HMCS412CL Input low Vie RESET, 03 0.2Veg OV voltage R3,/INTo, RayiNTs osc, 03 0.5 V___HMCS412C/AC 0.3 0.3 Vv HMCS412CL {nputoutput | I, | RESET, — 1 HA Vin = 0 Vito Veg, 1 leakage R3,/INTo, current R3y/iNT,, Osc, hed Current lec Veo =— 1.8 MA HMCS412C: Veg =5V; 2,5 dissipation fosc = 4 MHz, + 8, or in active fose = 2 MHz, +4 mode = 2.2 mA HMCS412C: Veg =5V; 2,5 Ry = 18 KO 41%, +8 - 0.8 MA HMCS412CL: Veg =3V; 2,5 foge = 4 MHz, + 16, or fosc = 2 MHz, +8 . - 3.0 MA HMCS412AC: Veg = 5V; 2,5 fosc = 4 MHz, + 4 Current Isey Voc = 1.0 mA HMCS412C:Vgg =5V; 3,5 dissipation fosc = 4 MHz, + 8, or in standby fosc = 2 MHz, +4 | mode . " - 1.3 MA HMCS412C:Vog#5V; 3,5 Ry = 18kQ 41%, + 8 - 0.5 MA HMCS412CL: Veg =3V; 3,5 fosc = 4 MHz, + 16, or fosc = 2 MHz, +8 = 1.4 mA HMCS412AC: Veg =5V; 3,5 foso = 4 MHz, +4 Current Istop Veo _ 10 WA VintEST) = Veo -0.3Vto 4 dissipation in Veci Vee: Vin(RESET) = ‘stop mode OVt0O.3V Stopmode Vgtop Voc 2 - Vv retaining voltage MB 4496204 0047269 97b 338 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series ee vee re eee Notes: 1. Excluding pull-up MOS current and output buffer current. 2. The MCU is in the reset state. InpuVoutput current does not flow. + MCU in reset state, operation mode + RESET, TEST: Vo + Do to D3, R3, R4: Vog + Dg to Dy4, RO to R2, RAY: Viiep 3. The timer/counter operates with the fastest clock. Input/output current does not flow. * MCU in standby mode + Inpuvoutput in reset state , + RESET: GND + TEST: Vog + Doto Dg, R3, R4: Veg, + Dg to Dy4, RO to R2, RAs: Vis 4. Excluding pull-down MOS current. 5. When fosc = x MHZ, estimate the current dissipation as follows: HMCS412C/AC: Maximum value at x MHz = (x/4) x (max. value at 4 MHz) HMCS412CL: Maximum value at x MHz = (x/2) x (max. value at 2 MHz) Input/Output Characteristics for Standard Pins (GND = 0 V, Vgisp = Voc ~ 40 V to Vcc, Ta = -20°C to +75°C, HMCS412C: Voc = 3.5 V to 6 V, HMCS412CL: Vcc = 2.5 V to 6 V, HMCS412AC: Vec =

4.5 V to 6 V)

Item Symbol Pin Min Typ Max Unit Test Condition Note Input high Vig Doto Ds, 0.7Ve¢ _ Veo +0.3 V voltage R3p, R3;, Input low Vit DotoDs, 0.3 - 03V¢g VV voltage R3p, R3,, Output high Voy DotoD3, Veo-10 — ~ Vv -HMCS412C/AC: 1 voltage R3p, R3;, slow = 1.0 mA DotoD3, Vgc-05 — = Vv -HMCS412C/AC: 1 F3p, R3;, low = 0.5 mA R4 HMCS412CL: lop = 0.3 mA Outputlow Voy. DotoD3, — = 0.4 Vs HMCS412C/AC: voltage R3p, R3y, lon = 1.6 mA R4 HMCS412CL: _ _ lon = 0.4 mA Inputfoutput | hy, | DotoD3s, — - 1 WA Vine OVt0Vog 2 leakage R3q, R3,, current R4 Pull-up MOS —Ipy DotoDs, 30 60 150 HA Voc =5V, 3 current R3p, R3;, Vin =0V Ra DotoD3, 3 15 50 HA HMCS412CL 3 R3p, R3,, only: Vgg = 3 V, R4 Vin = 0V Notes: 1. Applied to V/O pins selected as CMOS output by mask option. 2. Pull-up MOS current and output buffer current are excluded, 3. Applied to /O pins selected as with pull-up MOS by mask option. WM 4456204 0047270 658 Me 339 Hitachi Nene nnn n nnn

HMCS412 Series/HMCS414 Series/HMCS424 Series Input/Output Characteristics for High-Voltage Pins (GND = 0 V, Vaigp = Voc - 40 V to Voc. Ta =-20°C to +75°C, HMCS412C: Voc = 3.5 V to 6 V, HMCS412CL: Vcc = 2.5 V to6 V, HMCS412AC: Vcc = 4.5 V to 6 V) lem Symbol Pin Min Typ Max Unit Test Condition Note Input high Vy Dg toDy4, 0.7Veg — Veco +0.3 V voltage Rt, R2, __ a Input low Vit DytoDi4, Voo-40 — 0.3Vog.—OV voltage Rt, R2, RAY Output high Voy DstoDyy Voc-3.0 — = V loy= 15mA, voltage HMCS412C/CL: Voc = 5 V + 20% HMCS412AC: Voc = 4.5 V to 6 V Vec-2.0 — = Vo =lo = 10 mA, HMCS412C/CL: Voc = 5 V 420% HMCS412AC: Voc =4.5V to6V Voo-10 — = v HMCS412C/AC: vlog = 4 mA HMCS412CL: -loy = 2.5 mA ROtoR2 Voc-3.0 — = V loy=3 mA, HMCS412C/CL: Vog = 5 V #20% HMCS412AC: Voc #45 V106V Voeo-20 — = V lou=2 mA, HMCS412C/CL: Voc = 5 V £20% HMCS412AC: Voc = 4.5 V to 6 V Veo-1.0 — - v HMCS412C/AC: lox = 0.8 MA HMCS412CL: _ lon = 0.5 mA Output low = Voy DgtoDy4, — — Veo-37 Vi Veisp = 1 voltage RO to R2 Voc - 40V DytoDy4, — _— Vec-37 V 150 kQ at 2 RO to R2 Voc - 40 V | Inpuvoutput | I | DytoDy4, — - 20 WA Vin=Vog-40V 3 leakage RO to R2, to Voc current RA, Pulldown pp DgtoDy4, 125 250 600 HA Viisp = 1 , MOS current RO to R2, Voc - 35 V, RA, Vin = Voc | Notes: 1. Applied to /O pins selected as with pull-down MOS by mask option. 2. Applied to VO pins selected as without pull-down MOS (PMOS open drain) by mask option. 3. Pulldown MOS current and output buffer current are excluded. ME 4496204 OO47271 52h Ml 340 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series AC Characteristics (GND = 0 V, Vaisp = Voc - 40 V to Vcc, Ta = -20°C to +75°C, HMCS412C: ' Voc = 3.5 V to 6 V, HMCS412CL: Voc = 2.5 V to 6 V, HMCS412AC: Voc = 4.5 V to 6 V) tem Symbol = Pin Min Typ Max Unit Test Condition Note Crystalor Oscillation fos¢ Osc, 04 4 45 MHz HMCS412C: ceramic frequency OSC divide-by-8 oscillator 02 2 225 MHz HMCS412C: dvidedy-4 | 08 4 45 MHz HMCS412CL: divide-by-16 04 2 2.25 MHz HMCS412CL: divide-by-8 02 4 45 MHz HMCS412AC: divide-by-4 Instruction — teye 1.78 2 20 us HMCS412C, cycle time 3.55 4 20 ps HMCS412CL 0.89 1 20 us HMCS412AC Oscillator tac Osc, — — 20 ms HMCS412C/AC 1 stabilization Osc, time — — 60 ms _HMCSsi2cL Ss Resistor Oscillation fosc Osc, 15° 3 45 MHz HMCS412C: oscillator frequency OSC2 Ry = 18kQ41% Instruction — teye 1.78 266 533 us HMCS412C: cycle Ry = 18 kQ+1% time Oscillator tac Osc, — _ 0.5 ms HMCS412C: 1 stabilization OSC, Ry = 18kQ 41% time Between Cry osc, — = 1 pF HMCS412C pin OSC, capacitance External clock high top osc, 92 — — ns HMCS4120: 2 and low widths top. divide-by-8 HMCS412CL: divide-by-16 HMCS412AC: divide-by-4 203 - _ ns HMCS412C: 2 divide-by-4 HMCS412CL: divide-by-8 Mm 4496204 OO47e72 4EO mm 341. Hitachi a

HMCS412 Series/HMCS414 Series/HMCS424 Series OO AC Characteristics (GND = 0 V, Vdisp = Vcc - 40 V to Voc, Ta = -20°C to +75°C, HMCS412C: Voc = 3.5 V to 6 V, HMCS412CL: Vc = 2.5 V to 6 V, HMCS412AC: Voc = 4.5 V to 6 V) (cont) tem Symbol Pin Min Typ Max Unit ‘TestCondition Note TOO Oost Koncition Note External clock rise topr osc; — =- 20 ns 2 time a _ External clock fall tort osc; — —- 2 ns 2 time . ee INTo high width ty INTo 2 arte INT low width te INT 2 - - toye 3 INT, high width tit INT; 2 - _ lye 3 INT; low width te INT, 2 - - teye 3 tye RESET high width tasty RESET 2 =_- =_ bye 4 Input capacitance Cin Allpins —~ - 15 pF t=1 MHz, Vin = OV Nin OV RESET fall time tastt = = 20 ms HMCS412C/AC 4 _ - 15 ms HMCS412CL 4 SII Notes: 1. The oscillator stabilization time is period from when Voc reaches its minimum allowable voltage (HMCS412C: 3.5 V, HMCS412CL: 2.5 V, HMCS412AC: 4.5 V) at power-on until when the oscillator stabilizes, or after RESET goes high. At power-on or recovering from stop mode, apply the RESET input for more than tac to meet the necessary time for oscillator stabilization. Since tac depends on the crystal or ceramic circuit constant and stray capacitance, consult with the crystal or ceramic oscillator manufacturer when designing the reset circuit. (See figure 25.) 2. See figure 26. 3. See figure 27. 4. See figure 28. WM 4456204 0047273 3T? 342 Hitachi

a HMCS412 Series/HMCS414 Series/HMCS424 Series HM 2 Series MCS44 Series IM CS424 Series HMCS412C/CL/AC Option List a Please check off the appropriate applications and enter | customer fT Ni 1. VO option A: Without pull-up MOS (NMOS open drain) B: With pull-up MOS C: CMOS (cannot be used as input) D: Without pull-down MOS (PMOS open drain) E: With pull-down MOS: Note: /O options masked by [J are not available. pm |e beter = | bee] | | [0 pa az|s[vo fee TT | =a : oo R20 [0 a [res |e (vo | | | fie es fre} [uo [TT fre | [vo | || fe | i Use checklist RA1/Vdisp [ra | nar /2fs| 1 [Use cheokit pass MB 4456204 0047276 OOL 345 Hitachi a

HMCS412 Series/HMCS414 Series/HMCS424 Series 2. RAINdisp 3. Divider (Div) CO RAI: Without pull-down MOS (D) Divider | 3 | ww | Note: If even one high-voltage pin is selected with umesaiecl fe oOo | a | VO option E, pin RA1/Vdisp must be [HMcs4i2Ac | wepewemeerse! a selected to function as Vdisp. Hmcssizac | OEE ee ea 4, ROM code media Please specity the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version) C EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are OC EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 5. Oscillator (CPG option) CHMCS412C QHMCS412CL GHMcs412AC (5-V operation) (3-V operation) (high speed operation) Cl Resistor (Rf = 18 kQ 41%, + 8) f Ceramic oscillator O Ceramic oscillator Ci crystal oscillator CO crystal oscillator 6. Stop mode 7. Package 0 bp-4as mm 4u9b204 0047277 THe 346 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series OOOO eon 0 ae C.Ree>? ETT EOTOT—r rcv oes HMCS414C/CL/AC Electrical Characteristics DC Characteristics (GND = 0 V, Vaisp = Voc - 40 V to Voc, Ty = -20°C to +75°C, HMCS414C: Voc = 3.5 V to 6 V, HMCS414CL: Veg = 2.5 V to 6 V, HMCS414AC: Voc = 4.5 V to 6 V) tem Symbol Pin Min Max Unit Test Condition Notes Input high Vy RESET, 0.8Vcg Voc +03 -V voltage R32/INTo, ROyINTy osc, Voc-0.5 Voc+0.3 V HMCS414C/AC Veco-0.3 Voco+0.3 V HMCS414CL Input low Vit RESET, -03 02Vcc OV voltage R32/INTo, R3y/iNT; Osc, 40.3 0.5 Vv HMCS414C/AC 0.3 0.3 Vv HMCS414CL Inputoutput | fi. | RESET, — 1 HA Vin = 0 V0 Veg. 1 leakage R3z/INTo, current R3,/INTy, OSC, Current lec Voc _ 1.8 mA HMCS412C:Vog=5V; 2,5 dissipation fosc = 4 MHz, + 8, or in active foc = 2MHz, + 4 mode = 22 MA HMCS412C:Vog=5V; 2,5 Ry = 18kQ 41%, +8 - 08 mA HMCS414CL: Veg =3V; 2,5 fogc = 4 MHz, + 16, or fos = 2 MHz, +8 = 3.0 MA HMCS414AC: Voc =5V; 2,5 fosc = 4 MHz, + 4 Current Isay Voce - 1.0 mA HMCS412C:Vog=5V; 3,5 dissipation fosc = 4 MHz, + 8, or in standby fosc = 2 MHz, + 4 mode = 13 MA HMCS412C:Vog=5V; 3,5 Ry = 18kQ41%, +8 - 0s MA —HMCS414CL: Veg =3V; 3,5 fose = 4 MHz, + 16, or fosc = 2MHz, +8 ad 1.4 mA HMCS414AC: Voc =5V; 3,5 - fos = 4 MHz, + 4 Current Istop Vee = 10 WA Vintes=Vec-0.3Vto 4 dissipation in Voc: Vcc: Vin(ReseT) = stop mode OVtoO3V Stopmode Vstop Voc 2 = v retaining voltage WM 4456204 0047278 989 347 Hitachi a

HMCS412 Series/HMCS414 Series/HMCS424 Series Notes: 1. Excluding pull-up MOS current and output buffer current. 2. The MCU is in the reset state. Input/output current does not flow. + MCU in reset state, operation mode + RESET, TEST: Voc *+ Do to Dg, R3, R4: Veg + Dg to Dy4, RO to R2, Ay: Vein 3. The timer/counter operates with the fastest clock. Input/output current does not flow. * MCU in standby mode + Input/output in reset state + RESET: GND + TEST: Veg + Do to D3, R3, R4: Veo, + Dg to Dy4, RO to R2, RAs: Vaisp 4. Excluding pull-down MOS current. 5. When fos = x MHZ, estimate the current dissipation as follows: HMCS414C/AC; Maximum value at x MHz = (x/4) x (max. value at 4 MHz) HMCS414CL; Maximum value at x MHz = (x/2) x (max. value at 2 MHz) Input/Output Characteristics for Standard Pins (GND = 0 V, Vaisp = Voc - 40 V to Voc, Ta = -20°C to +75°C, HMCS414C: Voc = 3.5 V to 6 V, HMCS4I4CL: Voc = 2.5 V to 6 V, HMCS414AC: Voc = item Symbol Pin Min Typ ‘Max Unit Test Condition Note Input high Vy Do toD3, 0.7Veq _ Voc +0.3 V voltage R3p, R3;, Input low Vi Do toDs, -0.3 - 0.3Veg voltage R3p, R3,, Re 7 Output high Voy DotoD3, Veg-10 — - v HMCS414C/AC: 1 voltage R3p, R3;, lon = 1.0 mA R4 ee _ DotoDs, Voo-05 — - Vv -HMCS414C/AC: 1 R3p, R3,, loy = 0.5 mA; R4 HMCS414CL: 7 toy = 0.3 mA Output low Vo. Dp toDs, — - 0.4 Vv HMCS414C/AC: voltage R3p, R3;, lo = 1.6 mA R4 HMCS414CL: loy = 0.4 mA inputoutput | ly. | Dg toD3, — _ 1 WA Vig OVtOVeg 2 leakage R3p, R3;, current R4 Pull-up MOS = —Ipy DotoDs, 30 60 150 HA Veg =5V, 3 current R3p, R3,, Vin = OV DotoDs, 3 15 50 HA HMCS414CL 3 R3p, R3,, only: Veg = 3 V, R4 Vin = OV Notes: 1. Applied to I/O pins selected as CMOS output by mask option. 2. Pull-up MOS current and output butfer current are excluded. 3. Applied to /O pins selected as with pull-up MOS by mask option. | ME 4496204 0047279 615 348 Hitachi |

HMCS412 Series/HMCS414 Series/HMCS424 Series Input/Output Characteristics for High-Voltage Pins (GND = 0 V, Vgisp = Voc - 40 V to Vc, Ta =-20°C to +75°C, HMCS414C: Voc = 3.5 V to 6 V, HMCS414CL: Voc = 2.5 V to 6 V, HMCS414AC: Vcc = 4.5 V to 6 V) item Symbol Pin Min Typ Max Unit TestCondition Note Input high Vin DgtoDy4, 0.7Veg = Voc +0.3 V voltage Ri, R2, RA, Inputlow Vy. DytoDy4, Veo-40. — 0.3Vc¢ =O voltage Ri, R2, a Output high Vow DstoDi4 Voo-3.0 — =_ Vv “lon = 15 mA, voltage HMCS414C/CL: Vog = 5 V + 20% HMCS414AC: Voc = 4.5 V to 6 V Voo-20 — = Vo =lon = 10 mA, HMCS414C/CL: Voc = 5 V 420% HMCS414AC: Voc = 4.5 V to 6 V Veoe-1.0 — _ v HMCS414C/AC: slow = 4 mA HMCS414CL: wloy = 2.5 mA ROtoR2 Voo-30 — = Von =3mA, HMCS414C/CL: Voc = 5 V £20% HMCS414AC: _ Veg =4.5V 106 V Voo-20 — = Vo -lon=2 mA, HMCS414C/CL: Voc = 5 V £20% HMCS414AC: Voc = 4.5 V 10 6V Veo-10 — = V_HMCSA414C/AC: lo = 0.8 mA HMCS414CL: _ lop = 0.5 mA Output iow Vou Dg toDy4, — = Voo-37 V Vasp= 1 voltage RO to R2 __ Veco - 40 V Dato Dig, — = Vec-37 V‘150kQat 2 RO to R2 Voc - 40 V Inpuvoutput | Ii. | O4t0 Dig, — _ 20 HA Vin=Vec-40V 3 leakage RO to R2, to Voc current RA, Pul-down pp DgtoDy4, 125 250 600 WA Veisp = 1 MOS current RO to R2, Veo -35V, RA, Vin = Voo Notes: 1. Applied to /O pins selected as with pulldown MOS by mask option 2. Applied to /O pins selected as without pull-down MOS (PMOS open drain) by mask option. 3. Pull-down MOS current and output buffer current are excluded. WM 4496204 0047280 S37 349 Hitachi a

HMCS412 Series/HMCS414 Series/HMCS424 Series AC Characteristics (GND = 0 V, Vaisy = Voc - 40 V to Voc, Ta = ~20°C to +75°C, HMCS414C: Voc = 3.5 V to 6 V, HMCS414CL: Vcc = 2.5 V to 6 V, HMCS414AC: Vcc = 4.5 V to 6 V) tem Symbol Pin Min Typ Max Unit TestCondition Note Crystalor Oscillation tose OSC; 04 4 45 MHz HMCS414C: ceramic frequency OSCp divide-by-8 oscillator 02 2 225 MHz HMCS414c: 08 4 45 = MHz HMCS414CL: divide-by-16 0.4 2 2.25 MHz HMCS414CL: divide-by-8 0.2 4 45 MHz HMCS414AC: divide-by-4 Instruction — tec 1.78 2 20 us HMCS414C cycle time 355 4 20 us HMCS414CL 089 1 20° us HMCS414AC Oscillator tac Osc, — — 20 ms HMCS414C/AC 1 stabilization OSC time = 60. ms HwcsaiacL _ _ 60 ms HMCS414CL 1 Resistor Oscillation tos Osc, 15 3 45 MHz HMCS414C: oscillator frequency OSC, Ry = 18 KO41% Instruction —teyc 1.78 266 533 us HMCS414C: cycle y= 18 kK 41% time Oscillator — tag osc, — - 05 ms HMCS414C: 1 stabilization OSC2 Ry = 18 kQ 41% time Between Cry Osc, — = 1 pF HMCS414C. pin OSC capacitance External clock high top Osc, 92 - = ns HMCS414C: 2 and low widths tort divide-by-8 HMCS414CL: divide-by-16 HMCS414AC: divide-by-4 203 - al ns HMCS414C: 2 divide-by-4 HMCS414CL: divide-by-8 WM 4496204 0047261 473 ml 350 Hitachi

=. SS HMCS412 Series/HMCS414 Series/HMCS424 Series Ee eeeeeeeeeeeeaeaerereasaes AC Characteristics (GND = 0 V, Vdisp = Vcc - 40 V to Vcc, Ta = -20°C to + 75°C, HMCS414C: Voc = 3.5 V to 6 V, HMCS414CL: Vcc = 2.5 V to 6 V, HMCS414AC: Voc = 4.5 V to 6 V) (cont) ttem Symbol Pin Min Typ Max Unit Test Condition Note $$. Oe Test Condition Note External clock rise top, osc; — _ 20 ns 2 time _ _ External clock fall tort osc; — — 2 os 2 INTo high width ty INTo 2 = tye 3 INTo low width te INTs = 2 _ - toe 3 INT; high width ti INT; 2 — = _tee 3 a a INT; low width ti. int; 2 - = tye 3 RESET high width tasty RESET 2 = = te 4 Input capacitance Cin Allping — — 15. pF f=1 MHz, Vig = OV ee RESET fall time tastt = _ 20 _ms__HMCS414C/AC 4 _ _ 15 ms HMCS414CL 4 NF Notes: 1. The oscillator stabilization time is period from when Veg reaches its minimum allowable voltage (HMCS414C: 3.5 V, HMCS414CL: 2.5 V, HMCS414AC: 4.5 V) at power-on until when the oscillator stabilizes, or after RESET goes high. At power-on or recovering from stop mode, apply the RESET input for more than tac to meet the necessary time for oscillator stabilization. Since tac depends on the crystal or ceramic circuit constant and stray capacitance, consult with the Crystal or ceramic oscillator manufacturer when designing the reset circuit. (See figure 29.) 2. See figure 30. 3. See figure 31. 4. See figure 32. M@™ 4456204 0047282 30T 351. Hitachi Cnn nn nn nnn

HMCS412 Series/HMCS414 Series/HMCS424 Series HMCS414C/CL/AC Option List oe Please check off the appropriate applications and enter | -CUS*O™e” po the necessary information, | Deparment | i a " | Rowe name LBltype number , [inate | 1. VO option A: Without pull-up MOS (NMOS open drain) B: With pull-up MOS C: CMOS (cannot be used as input) D: Without pull-down MOS (PMOS open drain) E: With pull-down MOS Note: 1/O options masked by [ij are not available. fm | © bette] = | Gatti patetefole late |clole| po jet lt | | ee ym) fo bey | | os | [vo pe fee 8 coe || [Ral rai [Pfs] mm u4ugb204 0047285 O19 a ase tach

HMCS412 Series/HMCS414 Series/HMCS424 Series 2. RA1Ndisp 3. Divider (Div) CiRArwiteu paldowwos() | [ower [« [8 | w_] Note: It even one high-voltage pinis selected with [HMcsaiacL [ee O | a | VO option E, pin RA1/Vdisp must be [Hcsaraac| O [auis a ea ape selected to function as Vdisp. eee ee 4. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). C EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are C EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 5. System oscillator (OSC1 and OSC2) OHMCS414C OHMCS414CL OHMCS414AC (5-V operation) (3-V operation) (high speed operation) Ci Resistor (Rt = 18 k0+1%, + 8) [eee pe ee eT Ceramic oscitator C1 Coramieoscilator 6. Stop mode 7. Package D Used _ oO OP-42 O Not used C FP-42S D FP-44A Mi 4496204 0047286 TSS 355 Hitachi a

HMCS412 Series/HMCS414 Series/HMCS424 Series ESS HMCS424C/CL/AC Electrical Characteristics DC Characteristics (GND = 0 V, Vaisp = Voc - 40 V to Vcc, T, = -20°C to +75°C, HMCS424C: Voc = 3.5 V to 6 V, HMCS424CL: Voc = 2.5 V to 6 V, HMCS424AC: Voc = 4.5 V to 6 V) ttem Symbol Pin Min Max Unit _ Test Condition Notes —$__ at tonetition CNH Input high Vy RESET, 0.8Vcg Veg +03 -V is CK, | R32/INTo, RSSINT; sl 0.7Ve¢ Veg +03 V osc, Vec-05 Veg +03 V__HMCS424C/AC Voc-0.3 Veg +03 Vi HMCS424CL Input low Vie RESET, -0.3 0.2Vco OV voltage SCK,__ RaAlNT, R3,/INT, ae si 0.3 03V¢o OV osc, 0.3 05 Vv HMCS424C/AC 0.3 03 V___HMCS424CL Output high Voy SCK, Veo-1.0 — Vv HMCS424C/AC: voltage so lon = 1.0 mA Veco-0.5 — Vs HMCS424C/AC: lon = 0.5 mA; HMCS424CL: _ toy = 0.3 mA Output low = Vo, SCK, - 0.4 Vv _-HMCS424C/AC: voltage so lo. = 1.6 mA; HMCS424CL: lon = 0.4 mA $e OMA Inpuvoutput | hy | RESET, — 1 HA Vin = 0 V to Veg 1 leakage SCK, current R32/INTo, R3,/INT;, SI, SO, - Osc, a Current lec Voc _ 2 mA HMCS424C:Vog=5V; 2,5 dissipation fosc = 4 MHz, + 8, or in active tose = 2 MHz, +4 mode : . - 0.7 MA HMCS424CL:Vog=3V; 2,5 fos¢ = 2 MHz, +4 = 3.2 mA HMCS424AC:Voc=5V; 2,5 | fosc = 4 MHz, +4 } —.—— rr aa mm 4496204 0047287 79) 956 Hach

ee eeeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSSsseF HMCS412 Series/HMCS414 Series/HMCS424 Series DC Characteristics (GND = 0 V, Vaisp = Vcc - 40 V to Voc, Ty = -20°C to +75°C, HMCS424C: Voc =3.5 V to 6 V, HMCS424CL: Voc = 2.5 V to 6 V, HMCS424AC: Vic = 4.5 V to 6 V) (cont) ttem Symbol Pin Min Max Unit Test Condition Notes | Current Igay Veo = 1.2 mA HMCS424C:Vog=5V; 3,5 dissipation fogc = 4 MHz, + 8, or in standby fosc = 2 MHz, + 4 mode = 05 mA HMCS424CL:Vog=3V; 3,5 Se fosc = 2 MHz, + 8 - 17 MA HMCS424AC: Veg =5V; 3,5 fose = 4 MHz, +4 Current Istop Veo — 10 WA — HMCS424C/AC: 4 dissipation in VingTEST) = Voc - 0.3 V to stop mode Voc: Vineset) = 0 V t00.3V HMCS424CL: Vin(TEST) = Voc — 0.3 V to Voc: VinreseT) = 0 V 1o0.2V Stopmode Vstop Voc 2 = v retaining voltage Notes: 1. Excluding pull up MOS current and output buffer current. 2. The MCU is in the reset state. Input/output current does not flow. + MCU in reset state, operation mode + RESET, TEST: Voc * Do to D3, R3, R4: Vog + Dg to Dy4, RO to R2, RAY: Veien 3. The timer/counter operates with the fastest clock. input/output current does not flow. + MCU in standby mode * Input/output in reset state + Serial interface: Stop + RESET: GND + TEST: Voc * Do to Dg, R3, R4: Veg + Dg to Dy4, RO to R2, RAY: Vajisp 4. Excluding pull-down MOS current. 5. When fogc = x MHZ, estimate the current dissipation as follows: HMCS424C/AC: Maximum value at x MHz = (x/4) x (max. value at 4 MHz) HMCS424CL: Maximum value at x MHz = (x/2) x (max. value at 2 MHz) ME 4496204 0047268 625 357 Hitachi ee

HMCS412 Series/HMCS414 Series/HMCS424 Series Input/Output Characteristics for Standard Pins (GND = 0 V, Vaiep = Voc - 40 V to Vcc, Ta = -20°C to +75°C, HMCS424C: Vcc = 3.5 V to 6 V, HMCS424CL: Voc = 2.5 V to 6 V, HMCS424AC: Voc =

4.5 V to6V)

tem Symbol Pin Min Typ Max Unit Test Condition Note Input high Vy DotoDs, O.7Vco — Veo +0.3 V voltage RS, R4 7 7 | Inputiow Vy. DotoDs, -0.3 - 0.3Veg OV voltage R3, R4 _ _ Output high Voy Dy toD3, Vog-1.0 — - Vv -HMCS424C/AC: 1 voltage R3, R4 lon = 1.0 mA DptoDs, Vog-05 — = V-HMCS424C/AC: 1 R3, R4 ~loy = 0.5 mA; HMCS424CL: Alon = 0.3 mA Output low Voy. Dy toDs, — = 0.4 Vv -HMCS424C/AC: voltage R3, R4 lo, = 1.6 mA HMCS424CL: . lo, = 0.4 mA Inpuvoutput | hy | Do toDs, — - 1 HA Vinz OVtOVeg 2 leakage R3, R4 current Pultup MOS —Ipy DotoDs, 30 60 150 HA Voc =5V, 3 current R3, R4 Vin = OV DotoDs, 3 16 50 HA HMCS424CL 3 R3, R4 only: Veg = 3 V, Vin = 0V een ON Notes: 1. Applied to /O pins selected as CMOS output by mask option. 2. Pull-up MOS current and output buffer current are excluded. 3. Applied to /O pins selected as with pull-up MOS by mask option. MM! 4496204 0047289 7b4 ml 358 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series Input/Output Characteristics for High-Voltage Pins (GND = 0 V, Vaisp = Vcc ~ 40 V to Vcc, Ta =-20°C to +75°C, HMCS424C: Voc = 3.5 V to 6 V, HMCS424CL: Voc = 2.5 V to 6 V, HMCS424AC: Voc = 4.5 V to 6 V) Hem Symbol Pin Min Typ Max Unit Test Condition Note Input high Vig DgtoDy4, 0.7Veg - Veo +0.3 V voltage Rt, R2, RA, Input low Vu DytoDy4, Voo-40 — 0.3V¢g OV voltage Rt, R2, RAy Output high Von DstoDig Voo-30 — _ Vo -loy= 15 mA, voltage HMCS424C/CL: Voc = 5 V + 20%; HMCS424AC: Voc = 4.5 V to 6.0 V Veo-20 — = V low = 10 mA, HMCS424C/CL: Voc = 5 V 420%; HMCS424AC: Voc = 4.5 V to 6.0 V Veo-10 — = V_-HMCS424C/AC: =loy = 4 mA: HMCS424CL: wloy = 2.5 mA ROtoR2 Veo-30 — - Vo =loy = 3 mA, HMCS424C/CL: Voc = 5 V 420% HMCS424AC: Veo = 4.5 V to 6.0 V Voo-20. — = Vo low = 2 mA, HMCS424C/CL: Vog = 5 V #20%; HMCS424AC: Voc = 4.5 V 10 6.0 V Veo-1.0 — _ Vv HMCS424C/AC: —loy = 0.8 mA HMCS424CL: _ lo} = 0.5 mA Output iow Vo. D4to Dis, — = Vec-37 V Vaisp= 1 voltage RO to R2 Voc - 40V DytoDi4, — — Voc-37 V 150 kQ at 2 RO to R2 Voc - 40 V Inpuvoutput — | hy | DytoDig, — _ 20 WA Vin=Vog-40V 3 leakage RO to R2, to Veo current RA; Pulldown pp Dgto Dig, 125 250 600 BA Vaisp = 1 MOS current RO to R2, Voc - 35V, RA, Vin = Veo Notes: 1. Applied to I/O pins selected as with pull-down MOS by mask option. 2. Applied to VO pins selected as without pull-down MOS (PMOS open drain) by mask option. 3. Pull-down MOS current and output buffer current are excluded. WB 4496204 0047290 4ab 359 Hitachi a

HMCS412 Series/HMCS414 Series/HMCS424 Series sss AC Characteristics (GND = 0 V, Vgisp = Voc - 40 V to Voc, Ta = -20°C to +75°C, HMCS424C: Voc = 3.5 V to 6 V, HMCS424CL: Vcc = 2.5 V to 6 V, HMCS424AC: Voc = 4.5 V to 6 V) tem Symbol Pin Min Typ Max Unit TestCondition Note — $$ oj aquwuw—eem—omortondlon Note Oscillation frequency fosc OSC,, 0.4 4 45 MHz HMCS424C: OSC divide-by-8 02 2 225 MHz HMCS424C: 0.4 2 2.25 MHz HMCS424CL: 02 4 45 MHz HMCS424AC: __ divide-by-4 _ Instruction cycle time heye 178 2 20 us HMCS424C 355 4 20 HS HMCS424CL 0.89 1 20 Hus HMCS424AC a ch ccd Oscillator stabilization tac osc,, — - 20 ms HMCS424C/AC 1 time OSC - - 60 ms HMCS424CL 1 SO External clock high topH. osc; 92 — — ns HMCS424C: 2 and low widths top divide-by-8 HMCS424AC: divide-by-4 203 - - ns HMCS424C: 2 divide-by-4 HMCS424CL: divide-by-8 $$ eeSSS EY ME 4496204 0047291 312 a 360 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series AC Characteristics (GND = 0 V, Vgisp = Voc - 40 V to Vcc, Ta = -20°C to +75°C, HMCS424C: Voc = 3.5 V to 6 V, HMCS424CL: Voc = 2.5 V to 6 V, HMCS424AC: Voc = 4.5 V to 6 V) (cont) tem Symboi Pin Min Typ Max Unit‘ Test Condition Note External clock rise topr osc, — — 2 os 2 time External clock fall topt osc; — - 20 ns 2 time INTo high width tin INTo 2 - tye 3 INTo low width te INTo 2 _ - toc 3 INT, high width tea INT, 2 = — eye 3 INT; low width tie INT, 2 - - tye 3 RESET high width tasTH RESET 2 -_- tye 4 Input capacitance Cin Allpins — - 15 pF f=1 MHz, Via =0V RESET fall time tastt — = 20 —ms_HMCSa24c/AC 4 - =_ 15 ms: HMCS424CL 4 Notes: 1. The oscillator stabilization time is period from when Vcc reaches its minimum allowable voltage (HMCS424C: 3.5 V, HMCS424CL: 2.5 V, HMCS424AC: 4.5 V) at power-on until when the oscillator stabilizes, or after RESET goes high. At power-on or recovering from stop mode, apply the RESET input for more than tac to meet the necessary time for oscillator stabilization. Since | tac depends on the crystal or ceramic circuit constant and stray capacitance, consult with the crystal or ceramic oscillator manufacturer when designing the reset circuit. 2. See figure 33. 3. See figure 34. 4. See figure 35. Me 4456204 0047292 255 361 Hitachi a

HMCS412 Series/HMCS414 Series/HMCS424 Series Serial Interface Timing Characteristics (GND = 0 V, Vaisy = Voc - 40 V to Voc, Ta = -20°C to +75°C, HMCS424C: Vcc = 3.5 V to 6 V, HMCS424CL: Voc = 2.5 V to 6 V, HMCS424AC: Vcc = 4.5 V to 6 V) During Transmit Clock Output ttem Symbol Pin __Min_‘Typ Max Unit‘ Test Condition Notes ——__ symbol Min typ _Max__Unit__ Test Condition Notes | Transmit clock cycle _tgaye SCK 1 — = tye 1,2 time we Transmit clock high tgcxH: SCK 05 - - tgeye 1,2 and low widths tgcxt amorowwens Nc Transmit clock rise tsckr SK — - 100 ons HMCS424C/AC 1,2 and fall times tgcxt — = 300 ns HMCSA24CL_—s4,2 8s HMC ARAL 1,2 Serial output data toso sO — — 300 ns HMCS424C 1,2 delay time = = 600 ns HMCSA24CL st, ens HIMCSA24AC 12 Serial input data tes: si 500 — — ns HMCS42aC 1 Setup time 1000 — — ns HMCS424CL 1 Ss CSAC Serial input data tis! sl 150 — — ns HMCS424C/AC 1 hold time 500 — — ns HMCSA24CL_ 1 $$ ns ANCL Notes: 1. See figure 36. 2. See figure 37. we 4496204 0047293 195 mm 362 Hitachi

HMCS412 Series/HMCS414 Series/HMCS424 Series Serial Interface Timing Characteristics (GND = 0 V, Vgisp = Vcc - 40 V to Voc, Ta = -20°C to +75°C, HMCS424C: Vcc = 3.5 V to 6 V, HMCS424CL: Vcc = 2.5 V to 6 V, HMCS424AC: Voc = 45 V to 6 V) During Transmit Clock Input Item Symbol Pin Min Typ Max Unit TestCondition Notes Transmit clock cycle tscye SCK 1 - - teye 1 time Transmit clock high ts «= SCK OOS tgoye 1 and low widths tgcxt Transmit clock rise tgckr: SCK — - 100 ns HMCS424C/AC 1 | and fall times tscxt : - - 300 ns HMCS424CL_—t Serial output data toso so - - 300 ins HMCS424C 1,2 delay time — = 600 ns -HMCS424CL_ 1,2 = _ 250 ns HMCS424AC 1,2 Serial input data tgs) sl 500 — — ns HMCS424C 1 setup time 4000 — — ns HMCS424CL_ 1 300 =- =- ns HMCS424AC 1 Serial input data tusi si 150 _ - ns HMCS424C/AC 1 hold time 500 — — ns HMCS424CL 1 Notes: 1. See figure 36. 2. See figure 37. Me 4496204 0047294 O21 363 Hitachi ee

Please check of the appropri applications and ene femme the necessary information. Department po ee " Cr iweemane [oaticmmy | 1, VO option A: Without pull-up MOS (NMOS open drain) B: With pull-up MOS C: CMOS (cannot be used as input) D: Without pull-down MOS (PMOS open drain) E: With pull-down MOS Note: /O options masked by [i are not available. pm | © bier] |e Eee lajelclole| [aye[clole| [oo te 720 | | | age [reo To] a as saeco || [rs| {vo | | Pee [ee | Do i [ae] & fo | | | , rae] [vol |_| fe , tee | [wo] || flee [ma rat [fe] 1 [Use cecnisr Rava] | M™ 4496204 0047297 830 i 866 Hitech! | MB

HMCS412 Series/HMCS414 Series/HMCS424 Series COO vv _OF OwWm_—E—eueEeEeeO 2. RA1/Vdisp 3. Divider (Div) (RA: Wout pu-down MOS 0) [over a

0 Vaisp Hmcsazac | oO |

Note: If even one high-voltage pin is selected with HMesazact [EE ETE VO option E, pin RA1/Vdisp must be selected aera to function as Vdisp. Hwcsa24ac | Ol eas ee = 4. ROM code media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). C EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are O EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are pro- grammed to different EPROMS. 5. System oscillator (OSC1 and OSC2) DOHMCS424C OOHMCS424CL OOHMCS424AC (5-V operation) (3-V operation) 7 (high speed operation) O Ceramic oscillator O Ceramic oscillator O Ceramic oscillator O Crystal oscillator Crystal oscillator __ | OCrystal oscillator OCExternal clock O External clock C1 External clock 6. Stop mode 7. Package O Used oO DP-42 O Not used © oP-42s OD FP-44A MB 4456204 0047298 777 367 Hitachi ee