HD61203U_1 HITACHI
Document overview
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- PDF pages: 29
Technical content
Features
- Dot matrix liquid crystal graphic display common driver with low impedance
- Low impedance: 1.5 kΩ max
- Internal liquid crystal display driver circuit: 64 circuits
- Internal dynamic display timing generator circuit
- Display duty cycle When used with the column driver HD61202U: 1/48, 1/64, 1/96, 1/128 When used with the controller HD61830: Selectable out of 1/32 to 1/128
- Low power dissipation: During displays: 5 mW
- Power supplies: VCC : 2.7~5.5V
- Power supply voltage for liquid crystal display drive: 8V to 16V
- CMOS process
- 100-pin plastic QFP, 100-pin plastic TQFP, chip
Ordering Information
Type No. Package HD61203UFS 100-pin plastic QFP (FP-100A) HD61203UTE 100-pin thin plastic QFP (TFP-100B) HCD61203U Chip
V EE V6R V5R V2R V1R TH CL2 CL1 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X22 X21 X20 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 V EE V6L V5L V2L V1L V CC DL FS DS1 DS2 C NC R NC CR STB SHL GND NC M/S NC FRM M NC FCS DR (Top view) HD61203UFS (FP-100A)
V EE V6R V5R V2R V1R X20 X21 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X43 X44 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 V EE V6L V5L V2L V1L V CC DL FS DS1 DS2 C NC R NC CR STB SHL GND NC M/S NC FRM M NC FCS DR CL1 CL2 TH (Top view) HD61203UTFIA (TFP-100B)
Chip Size : 3.40 × 4.08 µm 2 Coordinate : Pad Center Origin : Chip center Pad Size : 90 × 90 µm No.1 No.29 NO.28 TYPE CODE HD61203U NO.2 No.52 NO.79 NO.54 NO.78 PAD Name Coordinate XY Coordinate XY Coordinate XY PAD Name PAD Name 100 X21 X20 X19 X18 X17 X16 X15 X14 X50 X49 X48 X47 X22 X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X43 X44 X45 X46 –1513 1712 1544 1385 1238 1091 952 822 692 562 432 302 172 –88 –218 –349 –479 –609 –739 –869 –999 –1129 –1259 –1389 –1527 –1665 –1821 –1853 –1853 –1828 –1213 –976 –846 –716 –586 –456 –196 –65 195 325 455 585 715 853 1407 –1828 –1522 –1374 –1236 –1097 –967 –837 –707 –577 –447 –317 –187 –57 203 333 463 593 723 853 983 1122 1261 1399 1513 1513 1513 1513 1513 1546 1693 1853 1853 1470 1304 1170 1040 910 779 649 519 –131 –261 –391 –521 –651 –781 –911 –1041 –1171 –1301 –1479 1513 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1853 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 1513 –1513 –1513 –1375 –1828 –1828 –1828 –1828 –1828 –1828 –1828 –1828 –1828 –1828 –1828 –1828 –1828 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 –1513 PAD No. PAD No. PAD No. X13 X12 X11 X10 V6L V5L V2L V1L DL FS DS1 DS2 C R CR SHL GND M/S PHI2 PHI1 FRM M FCS DR CL2 V1R V2R V5R V6R X64 X63 X62 X61 X60 X59 X58 X57 X56 X55 X54 X53 X52 X51 389 259 129 1853 1853 1853 VEE1 VCC VEE2 Pad Location Coordinates
Timing generation circuitOscillator DR FCS M CL2 FRM V CC GND VEE CL1 TH DL SHL STB RC R R f C f C M/S FS DS1 DS2 ø1 ø2 V1L V5L X1 X2 V2L V6L X62 X63 X64 V1R V2R V5R V6R
The timing generator circuit generates display timing and operating clock for the HD61202U. This circuit is required when the HD61203U is used with the HD61202U. Connect terminal M/S to high level (master mode). It is not necessary when the display timing signal is supplied from other circuits, for example, from HD61830. In this case connect the terminals FS, DS1, and DS2 to high level and M/S to low level (slave mode). Bidirectional Shift Register A 64-bit bidirectional shift register. The data is shifted from DL to DR when SHL is at high level and from DR to DL when SHL is at low level. In this case, CL2 is used as shift clock. The lowest order bit of the bidirectional shift register, which is on the DL side, corresponds to X1 and the highest order bit on the DR side corresponds to X64. Liquid Crystal Display Driver Circuit The combination of the data from the shift register with the M signal allows one of the four liquid crystal display driver levels V1, V2, V5 and V6 to be transferred to the output terminals (Table 1). Table 1 Output Levels Data from the Shift Register M Output Level
11 V 2
01 V 6
10 V 1
00 V 5
HD61203U Terminal Functions Terminal Name Number of Terminals I/O Connected to Functions VCC GND VEE Power supply V CC –GND: Power supply for internal logic. VCC –VEE : Power supply for driver circuit logic. V1L, V2L V5L, V6L V1R, V2R V5R, V6R 8 Power supply Liquid crystal display driver level power supply. V1L (V1R), V2L (V2R): Selected level V5L (V5R), V6L (V6R): Non-selected level Voltages of the level power supplies connected to V1L and V1R should be the same. (This applies to the combination of V2L & V2R, V5L & V5R and V6L & V6R respectively.) M/S 1 I V CC or GND Selects master/slave.
- M/S = VCC : Master mode When the HD61203U is used with the HD61202U, timing generation circuit operates to supply display timing signals and operation clock to the HD61202U. Each of I/O common terminals DL, DR, CL2, and M is in the output state.
- M/S = GND: Slave mode The timing operation circuit stops operating. The HD61203U is used in this mode when combined with the HD61830. Even if combined with the HD61202U, this mode is used when display timing signals (M, data, CL2, etc.) are supplied by another HD61203U in the master mode. Terminals M and CL2 are in the input state. When SHL is V CC , DL is in the input state and DR is in the output state. When SHL is GND, DL is in the output state and DR is in the input state. FCS 1 I V CC or GND Selects shift clock phase.
- FCS = VCC Shift register operates at the rising edge of CL2. Select this condition when HD61203U is used with HD61202U or when MA of the HD61830 connects to CL2 in combination with the HD61830.
- FCS = GND Shift register operates at the fall of CL2. Select this condition when CL1 of HD61830 connects to CL2 in combination with the HD61830.
Terminals I/O Connected to Functions FS 1 I V CC or GND Selects frequency. When the frame frequency is 70 Hz, the oscillation frequency should be: fOSC = 430 kHz at FCS = VCC fOSC = 215 kHz at FCS = GND This terminal is active only in the master mode. Connect it to VCC in the slave mode. DS1, DS2 2 I V CC or GND Selects display duty factor. Display Duty Factor 1/48 1/64 1/96 1/128 DS1 GND GND V CC VCC DS2 GND V CC GND V CC These terminals are valid only in the master mode. Connect them to VCC in the slave mode. /G36/G37/G25 TH CL1 IV CC or GND Input terminal for testing Connect to /G36/G37/G25 VCC . Connect TH and CL1 to GND. CR, R, C 3 Oscillator In the master mode, use these terminals as shown below: RC RC RC RC Rf Cf Open Open External clock Internal oscillation External clock In the slave mode, stop the oscillator as shown below: RC RC Open OpenVCC ø1, ø2 2 O HD61202U Operating clock output terminals for the HD61202U
- Master mode Connect these terminals to terminals ø1 and ø2 of the HD61202U respectively.
- Slave mode Don’t connect any lines to these terminals.
Terminals I/O Connected to Functions FRM 1 O HD61202U Frame signal
- Master mode Connect this terminal to terminal FRM of the HD61202U.
- Slave mode Don’t connect any lines to this terminal. M 1 I/O MB of HD61830 or M of HD61202U Signal to convert LCD driver signal into AC
- Master mode: Output terminal Connect this terminal to terminal M of the HD61202U.
- Slave mode: Input terminal Connect this terminal to terminal MB of the HD61830. CL2 1 I/O CL1 or MA of HD61830 or CL of HD61202U Shift clock
- Master mode: Output terminal Connect this terminal to terminal CL of the HD61202U.
- Slave mode: Input terminal Connect this terminal to terminal CL1 or MA of the HD61830. DL, DR 2 I/O Open or FLM of HD61830 Data I/O terminals of bidirectional shift register DL corresponds to X1’s side and DR to X64’s side.
- Master mode Output common scanning signal. Don’t connect any lines to these terminals normally.
- Slave mode Connect terminal FLM of the HD61830 to DL (when SHL = V CC ) or DR (when SHL = GND). M/S V CC GND SHL V CC GND V CC GND DL Output Output Input Output DR Output Output Output Input NC 5 Open Not used. Don’t connect any lines to this terminal. SHL 1 I V CC or GND Selects shift direction of bidirectional shift register. SHL Shift Direction Common Scanning Direction VCC DL → DR X1 → X64 GND DL ← DR X1 ← X64
Terminals I/O Connected to Functions X1–X64 64 O Liquid crystal display Liquid crystal display driver output Output one of the four liquid crystal display driver M Data Output level 1010 V2 V6 V1 V5 When SHL is VCC , X1 corresponds to COM1 and X64 corresponds to COM64. When SHL is GND, X64 corresponds to COM1 and X1 corresponds to COM64.
M/S TH CL1 FCS FS DS1 DS2 STB CR R C ø1 ø2 FRM M CL2 SHL DL DR X1–X64 ALLLL HHHHH— —— — — F rom MB of From CL1 of H From FLM of — COM1–COM64 HD61830 HD61830 HD61830 L — From FLM of COM64–COM1 HD61830 BL L L HHHHHH— —— — — F rom MB of From MA of H From FLM of To DL/DR of COM1–COM64 HD61830 HD61830 HD61830 HD61203U No. 2 L To DL/DR From FLM of COM64–COM1 of HD61203U HD61830 No. 2 CL L L HHHHHH— —— — — F rom MB of From MA of H From DL/DR — COM65–COM128 HD61830 HD61830 of HD61203U No. 1 L — From DL/DR COM128–COM65 of HD61203U No. 1 D H L L H H L L H Rf Rf Cf To ø1 of To ø2 of To FRM of To M of To CL of H — — COM1–COM64 or HD61202U HD61202U HD61202U HD61202U HD61202U LH C f L — — COM64–COM1 E H L L H H L L H Rf Rf Cf To ø1 of To ø2 of To FRM of To M of To CL of H — To DL/DR COM1–COM64 or HD61202U HD61202U HD61202U HD61202U HD61202U of HD61203U L H Cf HD61203U To CL2 of No. 2 HD61203U L To DL/DR — COM64–COM1 of HD61203U No. 2 FL L L HHHHHH— —— — — F rom M of From CL2 of H From DL/DR — COM1–COM64 HD61203U HD61203U of HD61203U No. 1 No. 1 No. 1 L — From DL/DR COM64–COM1 of HD61203U No. 1 Notes: H: VCC }FixedL: GND Rf: Oscillation resister Cf: Oscillation capacitor
Outline of HD61203U System Configuration Use with HD61830 1. When display duty ratio of LCD is 1/64 No. 1 COM1 COM64 LCD No. 1 HD61830 HD61830 LCD No. 1 HD61830 No. 2 COM1 COM64 COM1 COM64 Upper Lower COM1 COM64 COM1 COM64 Lower Upper LCD One HD61203U drives common signals. Refer to Connection List A. One HD61203U drives common signals for upper and lower panels. Refer to Connection List A. Two HD61203Us drive upper and lower panels separately to ensure the quality of display. No. 1 and No. 2 operate in parallel. For both of No. 1 and No. 2, refer to Connection List A. 2. When display duty ratio of LCD is from 1/65 to 1/128 No. 1 COM1 COM128 LCD HD61830 No. 2 No. 1 HD61830 COM1 COM128 COM1 COM128 Upper Lower LCD No. 2 COM1 COM128 COM1 COM128 Upper Lower LCD No. 1 No. 2 No. 3 No. 4 HD61830 Two HD61203Us connected serially drive common signals. Refer to Connection List B for No. 1. Refer to Connection List C for No. 2. Two HD61203Us connected serially drive upper and lower panels in parallel. Refer to Connection List B for No. 1. Refer to Connection List C for No. 2. Two sets of HD61203Us connected serially drive upper and lower panels in parallel to ensure the quality of display. Refer to Connection List B for No. 1 and 3. Refer to Connection List C for No. 2 and 4.
Use with HD61202 (1/64 Duty Ratio) No. 1 COM1 COM64 LCD HD61202U LCD COM1 COM64 COM1 COM64 Upper Lower COM1 COM64 COM1 COM64 Lower Upper LCD One HD61203U drives common signals and supplies timing signals to the HD61202Us. Refer to Connection List D. One HD61203U drives upper and lower panels and supplies timing signals to the HD61202Us. Refer to Connection List D. Two HD61203Us drive upper and lower panels in parallel to ensure the quality of display. No. 1 supplies timing signals to No. 2 and the HD61202Us. Refer to Connection List E for No. 1. Refer to Connection List F for No. 2. No. 1 HD61202U HD61202U No. 1 HD61202U HD61202U No. 2
Use with HD61202U (RAM Type Segment Driver) 1. 1/64 duty ratio (see Connection List D) R3 V1 R3 V6 R3 V3 R3 V4 R3 V5 R3 V2 VEE Contrast Open Open VCC +5V (VCC ) –10V (X64) M CL2 FRM X64 (X1) SHL DS1 DS2 TH CL1 FS M/S FCS STB C CR R Cf Rf V CC V1L, V1R V6L, V6R V5L, V5R V2L, V2R VEE GND DL DR R3 = 15 Ω ( ) is at SHL = Low COM1 COM64 LCD panel HD61203U M CL FRM HD61202U V1L, V1R V3L, V3R V4L, V4R V2L, V2R V CC GND V EE V CC GND VEE Note: The values of R1 and R2 vary with the LCD panel used. When bias factor is 1/9, the values of R1 and R2 should satisfy 4R1 + R2 = 1 For example, R1 = 3 kΩ , R2 = 15 kΩ Figure 3 Example 1
(DR) C CL2 FRM DL (DR) DR (DL) M (X64) (X63) 1 2 3 63 64 1 2 3 63 64 1 1 frame1 frame V6 V5 123 47 48 49 ( ): at SHL = Low Note: * Phase difference between DL (DR) and CL2 Figure 4 Example 1 Waveform (RAM Type, 1/64 Duty Cycle)
Use with HD61830 (Display Controller) 1. 1/64 duty ratio (see Connection List A) Open VCC Open VCC VEE GND Open Open Open See connection example VCC Open (X64) M CL2 DL (DR) DR (DL) X64 (X1) SHL DS1 DS2 TH CL1 FS M/S FCS STB COM1 COM64 LCD panel HD61203U M CL1 FLM HD61830 (Display controller) C CR R V CC V1L, V1R V6L, V6R V5L, V5R V2L, V2R VEE GND FRM ( ) is at SHL = Low Figure 5 Example 2 (1/64 Duty Ratio)
( ): at SHL = Low MB FLM CL1 (X64) (X63) X64 (X1)V6 From HD61830 Figure 6 Example 2 Waveform (1/64 Duty Ratio)
- 1/100 duty ratio (see Connection List B, C) VCC VCC COM1 COM64 COM65 COM100 LCD panel SHL DS1 DS2 TH CL1 FS M/S FCS STB (X64) X64 (X1) (X64) X36 (X29) SHL DS1 DS2 TH CL1 FS M/S FCS STB V CC V1L, V1R V6L, V6R V5L, V5R V2L, V2R V EE GND VCC OpenOpen R CR C M CL2 DL (DR) DR (DL) HD61203U (master) No. 1 M CL2 DL (DR) DR (DL) OpenHD61203U (slave) No. 2 VCC V1L, V1R V6L, V6R V5L, V5R V2L, V2R V EE GND C CR R Open Open VCC FLM MA MB HD61830 Display controller See Connection Example 1 VCC VEE GND Note: ( ) is at SHL = Low Figure 7 Example 2 (1/100 Duty Ratio)
12100 36 4 6 5 6 6 100 123 6 4 6 5 6 6 100 12 V6 V1 V5V2 MB FLM MA DR(DL) HD61203U No. 1 (X64) X64 (X1) (X64) X36 (X29) HD61830 HD61203U No. 1 HD61203U No. 2 Figure 8 Example 2 Waveform (1/100 Duty Ratio)
Item Symbol Limit Unit Notes Power supply voltage (1) V CC –0.3 to +7.0 V 2 Power supply voltage (2) V EE VCC – 17.0 to VCC + 0.3 V 5 Terminal voltage (1) V T1 –0.3 to VCC + 0.3 V 2, 3 Terminal voltage (2) V T2 VEE – 0.3 to VCC + 0.3 V 4, 5 Operating temperature T opr –20 to +75 °C Storage temperature T stg –55 to +125 °C Notes: 1. If LSIs are used beyond absolute maximum ratings, they may be permanently destroyed. We strongly recommend you to use the LSI within electrical characteristic limits for normal operation, because use beyond these conditions will cause malfunction and poor reliability. 2. Based on GND = 0V. 3. Applies to input terminals (except V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R) and I/O terminals at high impedance. 4. Applies to V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R. 5. Apply the same value of voltages to V1L and V1R, V2L and V2R, V5L and V5R, V6L and V6R, V EE (23 pin) and VEE (58 pin) respectively. Maintain VCC ≥ V1L = V1R ≥ V6L = V6R ≥ V5L = V5R ≥ V2L = V2R ≥ VEE
Electrical Characteristics
DC Characteristics (VCC = 2.7V to 5.5V, GND = 0V, VCC –V EE = 8.0 to 16.0V, Ta = –20 to +75°C) Specifications Test Item Symbol Min Typ Max Unit Test Conditions Notes Input high voltage VIH 0.7 × VCC —V CC V1 Input low voltage V IL GND — 0.3 × VCC V1 Output high voltage VOH VCC – 0.4 — — V I OH = –0.4 mA 2 Output low voltage VOL — — 0.4 V I OL = 0.4 mA 2 Vi–Xj on resistance RON — — 1.5 k Ω VCC –VEE = 10V Load current ±150 µA Input leakage current IIL1 –1.0 — 1.0 µA Vin = 0 to V CC 3 Input leakage current IIL2 –2.0 — 2.0 µA Vin = V EE to VCC 4 Operating frequency fopr1 50 — 600 kHz In master mode external clock operation Operating frequency fopr2 0.5 — 1500 kHz In slave mode shift register Oscillation frequency fosc 315 450 585 kHz Cf = 20 pF ± 5% Rf = 47 kΩ ± 2% 7, 12 Dissipation current (1) IGG1 — — 1.0 mA In master mode 1/128 duty cycle Cf = 20 pF Rf = 47 kΩ 8, 9 Dissipation current (2) IGG2 — — 200 µA In slave mode 1/128 duty cycle 8, 10 Dissipation current IEE — — 100 µA In master mode 1/128 duty cycle 8, 11 Notes: 1. Applies to input terminals FS, DS1, DS2, CR, SHL, M/S, and FCS and I/O terminals DL, M, DR and CL2 in the input state. 2. Applies to output terminals, ø1, ø2, and FRM and I/O common terminals DL, M, DR, and CL2 in the output status. 3. Applies to input terminals FS, DS1, DS2, CR, /G36/G37/G25 , SHL, M/S, FCS, CL1, and TH, I/O terminals DL, M, DR, and CL2 in the input state and NC terminals. 4. Applies to V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R. Don’t connect any lines to X1 to X64.
- External clock is as follows. TH TL tfcptrcp
0.7 VCC
0.5 VCC
0.3 VCC
Duty cycle = TH TH + TL × 100% 6. Applies to the shift register in the slave mode. For details, refer to AC characteristics. 7. Connect oscillation resistor (Rf) and oscillation capacitance (Cf) as shown in this figure. Oscillation frequency (fOSC ) is twice as much as the frequency (fø) at ø1 or ø2. Cf Rf CR R C ø1, ø2 Cf = 20 pF Rf = 47 kΩ fOSC = 2 × fø 8. No lines are connected to output terminals and current flowing through the input circuit is excluded. This value is specified at VIH = VCC and VIL = GND. 9. This value is specified for current flowing through GND in the following conditions: Internal oscillation circuit is used. Each terminal of DS1, DS2, FS, SHL, M/S, /G36/G37/G25 , and FCS is connected to VCC and each of CL1 and TH to GND. Oscillator is set as/ described in note 7. 10. This value is specified for current flowing through GND under the following conditions: Each terminals of DS1, DS2, FS, SHL, /G36/G37/G25 , FCS and CR is connected to VCC , CL1, TH, and M/S to GND and the terminals CL2, M, and DL are respectively connected to terminals CL2, M, and DL of the HD61203U under the condition described in note 9. 11. This value is specified for current flowing through V EE under the condition described in note 9. Don’t connect any lines to terminal V. 12. This figure shows a typical relation among oscillation frequency, Rf and Cf. Oscillation frequency may vary with the mounting conditions. C f = 20 pF 50 100 R f (kΩ ) 600 400 200 fOSC (kHz)
- Resistance between terminal X and terminal V (one of V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R) when load current flows through one of the terminals X1 to X64. This value is specified under the following conditions: Terminal X (X1 to X64) V1L, V1R V6L, V6R V5L, V5R V2L, V2R RON VCC –VEE = 10V V1L = V1R, V6L = V6R = VCC – 1/7 (VCC –VEE ) V2L = V2R, V5L = V5R = VEE + 1/7 (VCC –VEE ) Connect one of the lines The following is a description of the range of power supply voltage for liquid crystal display drive. Apply positive voltage to V1L = V1R and V6L = V6R and negative voltage to V2L = V2R and V5L = V5R within the ÆV range. This range allows stable impedance on driver output (RON). Notice that ÆV depends on power supply voltage V CC –VEE . /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 ΔV ΔV VCC V1 (V1L = V1R) V6 (V6L = V6R) V5 (V5L = V5R) V2 (V2L = V2R) VEE 3.5 ΔV (V) 81 6 VCC –VEE (V) Range of power supply voltage for liquid crystal display drive Correlation between driver output waveform and power supply voltage for liquid crystal display drive Correlation between power supply voltage V CC –VEE and ΔV
Applicable terminals: CR, M/S, SHL, FCS, DS1, DS2, FS Applicable terminals: DL, DR, CL2, MI/O Terminal Input Terminal PMOS NMOS VCC Output Terminal VCC PMOS V1L, V1R VCC PMOS V6L, V6R VEE NMOS V5L, V5R VEE NMOS V2L, V2R Applicable terminals: X1 to X64 PMOS VCC NMOS (Input circuit) Enable Data Output circuit (tristate) Output Terminal PMOS NMOS VCC Applicable terminals: ø1, ø2, FRM
AC Characteristics (VCC = 2.7V to 5.5V, GND = 0V, Ta = –20 to +75°C) In the Slave Mode (M/S = GND) (FCS = GND) (Shift clock) CL2 (FCS = V CC ) (Shift clock) DL (SHL = VCC ) DR (SHL = GND) Input data DR (SHL = V CC ) DL (SHL = GND) Output data Item Symbol Min Typ Max Unit Note CL2 low level width (FCS = GND) tWLCL2L 450 — — ns CL2 high level width (FCS = GND) tWLCL2H 150 — — ns CL2 low level width (FCS = VCC )t WHCL2L 150 — — ns CL2 high level width (FCS = VCC )t WHCL2H 450 — — ns Data setup time t DS 100 — — ns Data hold time t DH 100 — — ns Data delay time t DD — — 200 ns 1 Data hold time t DHW 1 0 ——n s CL2 rise time t r —— 3 0 n s CL2 fall time t f —— 3 0 n s Notes: 1. The following load circuit is connected for specification. 30 pF (includes jig capacitance) Output terminal
- In the master mode (M/S = VCC , FCS = VCC , Cf = 20 pF, Rf = 47 kΩ )
tWø1Htrtf tWø2Ltf tr tWø2H tD21tD12tWø1L 0.3 V CC CL2 DL (SHL = VCC ) DR (SHL = GND) DR (SHL = VCC ) DL (SHL = GND) FRM M
Item Symbol Min Typ Max Unit Data setup time t DS 2 0——µ s Data hold time t DH 4 0——µ s Data delay time t DD 5 ——µ s FRM delay time t DFRM –2 — +2 µs M delay time t DM –2 — +2 µs CL2 low level width t WCL2L 3 5——µ s CL2 high level width t WCL2H 3 5——µ s ø1 low level width t Wø1L 700 — — ns ø2 low level width t Wø2L 700 — — ns ø1 high level width t Wø1H 2100 — — ns ø2 high level width t Wø2H 2100 — — ns ø1–ø2 phase difference t D12 700 — — ns ø2–ø1 phase difference t D21 700 — — ns ø1, ø2 rise time t r — — 150 ns ø1, ø2 fall time t f — — 150 ns