HD61202 HITACHI

Document overview

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Technical content

Features

  • Dot matrix liquid crystal graphic display column driver incorporating display RAM
  • RAM data direct display by internal display RAM — RAM bit data 1: On — RAM bit data 0: Off
  • Internal display RAM address counter preset, increment
  • Display RAM capacity: 512 bytes (4096 bits)
  • 8-bit parallel interface
  • Internal liquid crystal display driver circuit: 64
  • Display duty cycle Drives liquid crystal panels with 1/32–1/64 duty cycle multiplexing
  • Wide range of instruction function Display data read/write, display on/off, set address, set display start line, read status
  • Lower power dissipation: during display 2 mW max
  • Power supply: V CC : 5 V ± 10%
  • Liquid crystal display driving voltage: 8 V to 17 V
  • CMOS process

Ordering Information

Type No. Package HD61202 100-pin plastic QFP (FP-100) HD61202TFIA 100-pin thin plastic QFP (TFP-100B) HD61202D Chip

V EE1 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 FRM E CL D/I R/W RST CS1 CS2 CS3 NC NC NC DB7 DB6 DB5 DB4 DB3 DB2 ADC M VCC V4R V3R V2R V1R V EE2 Y64 Y63 Y62 Y61 Y60 Y59 Y58 Y57 Y56 Y55 Y54 Y53 Y52 Y51 Y50 Y49 Y48 Y47 Y46 Y45 Y44 Y43 Y42 Y41 Y40 Y39 Y38 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 Y25 Y24 Y23 (Top view) HD61202 (FP-100)

V EE1 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 M ADC FRM E CL D/I R/W RST NC CS1 NC CS2 CS3 NC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 GND VCC V4R V3R V2R V1R V EE2 Y64 Y63 Y62 Y61 Y60 Y59 Y58 Y57 Y56 Y55 Y54 Y53 Y52 Y51 Y50 Y49 Y48 Y47 Y46 Y45 Y44 Y43 Y42 Y41 Y40 Y39 Y38 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21 (Top view) HD61202TFIA (TFP-100B)

flagOutput registerInput register Instruction register I/O buffer Interface control CS1, CS2, CS3 R/W D/I E DB0–DB7 CL FRM VCC GND VEE1 VEE2 ADC M RST

Terminal Number of Connected Name Terminals I/O to Functions VCC 2 Power supply Power supply for internal logic. GND Recommended voltage is: GND = 0 V VCC = 5 V ± 10% VEE1 2 Power supply Power supply for liquid crystal display drive circuit. VEE2 Recommended power supply voltage is VCC – VEE = 8 to 17 V. Connect the same power supply to VEE1 and VEE2 . VEE1 and VEE2 are not connected each other in the LSI. V1L, V1R 8 Power supply Power supply for liquid crystal display drive. V2L, V2R Apply the voltage specified depending on liquid V3L, V3R crystals within the limit of VEE through VCC .V4L, V4R V1L (V1R), V2L (V2R): Selection level V3L (V3R), V4L (V4R): Non-selection level Power supplies connected with V1L and V1R (V2L & V2R, V3L & V3R, V4L & V4R) should have the same voltages. CS1 3 I MPU Chip selection. CS2 Data can be input or output when the terminals are CS3 in the following conditions: Terminal name CS1 CS2 CS3 Condition L L H E 1 I MPU Enable. At write (R/W = low): Data of DB0 to DB7 is latched at the fall of E. At read (R/W = high): Data appears at DB0 to DB7 while E is at high level. R/W 1 I MPU Read/write. R/W = High: Data appears at DB0 to DB7 and can be read by the MPU. When E = high, CS1, CS2 = low and CS3 = high. R/W = Low: DB0 to DB7 can accept at fall of E when CS1, CS2 = low and CS3 = high. D/I 1 I MPU Data/instruction. D/I = High: Indicates that the data of DB0 to DB7 is display data. D/I = Low: Indicates that the data of DB0 to DB7 is display control data. 770 HD61202

Terminal Number of Connected Name Terminals I/O to Functions ADC 1 I V CC /GND Address control signal to determine the relation between Y address of display RAM and terminals from which the data is output. ADC = High: Y1: $0, Y64: $63 ACD = Low: Y64: $0, Y1: $63 DB1–DB7 8 I/O MPU Data bus, three-state I/O common terminal. M 1 I HD61203 Switch signal to convert liquid crystal drive waveform into AC. FRM 1 I HD61203 Display synchronous signal (frame signal). Presets the 6-bit display line counter and synchronizes the common signal with the frame timing when the FRM signal becomes high. CL 1 I HD61203 Synchronous signal to latch display data. The rising CL signal increments the display output address counter and latches the display data. ø1, ø2 2 I HD61203 2-phase clock signal for internal operation. The ø1 and ø2 clocks are used to perform operations (I/O of display data and execution of instructions) other than display. Y1–Y64 64 O Liquid crystal Liquid crystal display column (segment) drive output. display The outputs at these pins are at the light-on level when the display RAM data is 1, and at the light-off level when the display RAM data is 0. Relation among output level, M, and display data (D) is as follows: RST 1 I MPU or The following registers can be initialized by setting external CR the RST signal to low level. 1. On/off register 0 set (display off) 2. Display start line register line 0 set (displays from line 0) After releasing reset, this condition can be changed only by instruction. NC 3 Open Unused terminals. Don’t connect any lines to these terminals. Note: 1 corresponds to high level in positive logic. HD61202 771 M D Output level 1010 V1 V3 V2 V4

I/O Buffer: Data is transferred through 8 data bus lines (DB0–DB7). DB7: MSB (most significant bit) DB0: LSB (least significant bit) Data can neither be input nor output unless CS1 to CS3 are in the active mode. Therefore, when CS1 to CS3 are not in active mode it is useless to switch the signals of input terminals except RST and ADC; that is namely, the internal state is maintained and no instruction excutes. Besides, pay attention to RST and ADC which operate irrespectively of CS1 to CS3. Register: Both input register and output register are provided to interface to an MPU whose speed is different from that of internal operation. The selection of these registers depend on the combina- tion of R/W and D/I signals (table 1). 1. Input register The input register is used to store data temporarily before writing it into display data RAM. The data from MPU is written into input register, then into display data RAM auto- matically by internal operation. When CS1 to CS3 are in the active mode and D/I and R/W select the input register as shown in table 1, data is latched at the fall of the E signal. 2. Output register The output register is used to store data temporarily that is read from display data RAM. To read out the data from the output register, CS1 to CS3 should be in the active mode and both D/I and R/W should be 1. With the read display data instruction, data stored in the output register is output while E is high level. Then, at the fall of E, the display data at the indicated address is latched into the output register and the address is increased by 1. The contents in the output register are rewrit- ten by the read display data instruction, but are held by address set instruction, etc. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address is set, but can be output at the second read of data. That is to say, one dummy read is necessary. Figure 1 shows the MPU read timing. Table 1 Register Selection D/I R/W Operation 1 1 Reads data out of output register as internal operation (display data RAM fi output register) 1 0 Writes data into input register as internal operation (input register fi display data RAM) 0 1 Busy check. Read of status data. 0 0 Instruction

The display on/off flip/flop selects one of two states, on state and off state of segments Y1 to Y64. In on state, the display data corresponding to that in RAM is output to the segments. On the other hand, the display data at all segments disappear in off state independent of the data in RAM. It is controlled by display on/off instruction. RST signal = 0 sets the segments in off state. The status of the flip/flop is output to DB5 by status read instruction. Display on/off instruction does not influence data in RAM. To control display data latch by this flip/flop, CL signal (display syn- chronous signal) should be input correctly. Display Start Line Register The display start line register specifies the line in RAM which corresponds to the top line of LCD panel, when displaying contents in display data RAM on the LCD panel. It is used for scrolling of the screen. 6-bit display start line information is written into this register by the display start line set instruction. When high level of the FRM signal starts the display, the information in this register is transferred to the Z address counter, which controls the display address, presetting the Z address counter. X, Y Address Counter A 9-bit counter which designates addresses of the internal display data RAM. X address counter (upper 3 bits) and Y address counter (lower 6 bits) should be set to each address by the respective instructions. 1. X address counter Ordinary register with no count functions. An address is set by instruction. 2. Y address counter An Address is set by instruction and is increased by 1 automatically by R/W opera- tions of display data. The Y address counter loops the values of 0 to 63 to count. Display Data RAM Stores dot data for display. 1-bit data of this RAM corresponds to light on (data = 1) and light off (data = 0) of 1 dot in the display panel. The correspondence between Y addresses of RAM and segment pins can be reversed by ADC signal. As the ADC signal controls the Y address counter, reversing of the signal during the operation causes malfunction and destruction of the contents of register and data of RAM. Therefore, never fail to connect ADC pin to V CC or GND when using. Figure 3 shows the relations between Y address of RAM and segment pins in the cases of ADC = 1 and ADC = 0 (display start line = 0, 1/64 duty cycle).

Figure 3 Relation between RAM Data and Display COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM62 COM63 COM64 DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB) 01234 6 1 6 2 6 3 ADC = 1 (connected to V CC ) LCD display pattern Display RAM data (HD61203 X1) (HD61203 X2) (HD61203 X3) (HD61203 X4) (HD61203 X5) (HD61203 X6) (HD61203 X7) (HD61203 X8) (HD61203 X9) (HD61203 X62) (HD61203 X63) (HD61203 X64) Y1 Y2Y3 Y4 Y6 Y

63 Y64

Line 2X = 1 X = 7 Line 62 Line 63 X = 0 HD61202 pin name RAM Y address Y

Figure 3 Relation between RAM Data and Display (cont) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM62 COM63 COM64 DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 (MSB) 01234 6 1 6 2 6 3 ADC = 0 (connected to GND) LCD display pattern Display RAM data (HD61203 X1) (HD61203 X2) (HD61203 X3) (HD61203 X4) (HD61203 X5) (HD61203 X6) (HD61203 X7) (HD61203 X8) (HD61203 X9) (HD61203 X62) (HD61203 X63) (HD61203 X64) Y Y Y Y Y

59 Y3Y2 Y1

Line 2X = 1 X = 7 Line 62 Line 63 X = 0 HD61202 pin name RAM Y address5

The Z address counter generates addresses for outputting the display data synchronized with the common signal. This counter consists of 6 bits and counts up at the fall of the CL signal. At the high level of FRM, the contents of the display start line register is present at the Z counter. Display Data Latch The display data latch stores the display data temporarily that is output from display data RAM to the liquid crystal driving circuit. Data is latched at the rise of the CL signal. The display on/off instruction controls the data in this latch and does not influence data in display data RAM. Liquid Crystal Display Driver Circuit The combination of latched display data and M signal causes one of the 4 liquid crystal driver levels, V1, V2, V3, and V4 to be output. Reset The system can be initialized by setting RST terminal at low level when turning power on. 1. Display off 2. Set display start line register line 0. While RST is low level, no instruction except status read can be accepted. Therefore, execute other instructions after making sure that DB4 = 0 (clear RESET) and DB7 = 0 (ready) by status read instruction. The conditions of power supply at initial power up are shown in table 2. Table 2 Power Supply Initial Conditions Item Symbol Min Typ Max Unit Reset time t RST 1.0 — — µs Rise time t r — — 200 ns Do not fail to set the system again because RESET during operation may destroy the data in all the registers except on/off register and in RAM. VCC RST tRST tr

0.7 VCC

0.3 VCC

4.5 V

Display Control Instructions Outline Table 3 shows the instructions. Read/write (R/W) signal, data/instruction (D/I) signal, and data bus signals (DB0 to DB7) are also called instructions because the internal operation depends on the signals from the MPU. These explanations are detailed in the following pages. Generally, there are following three kinds of instructions: 1. Instruction to set addresses in the internal RAM 2. Instruction to transfer data from/to the internal RAM 3. Other instructions In general use, the second type of instruction is used most frequently. Since Y address of the internal RAM is increased by 1 automatically after writing (reading) data, the program can be shortened. During the execution of an instruction, the system cannot accept instructions other than status read instruction. Send instructions from MPU after making sure that the busy flag is 0, which is proof that an instruction is not being executed.

Instructions R/W D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Functions Display on/off 0000111111 / 0 Controls display on/off. RAM data and internal status are not affected. 1: on, 0: off. Display start line 0011 Display start line (0–63) Specifies the RAM line displayed at the top of the screen. Set page (X address)0010111 Page (0–7) Sets the page (X address) of RAM at the page (X address) register. Set Y address 0001Y address (0–63) Sets the Y address in the Y address counter. Status read 1 0 Busy 0 ON/ Reset 0000 Reads the status. OFF RESET 1: Reset 0: Normal ON/OFF 1: Display off 0: Display on Busy 1: Internal operation 0: Ready Write display data 0 1 Write data Writes data DB0 (LSB) Has access to the to DB7 (MSB) on the address of the display data bus into display RAM specified in RAM. advance. After the Read display data 1 1 Read data Reads data DB0 (LSB) access, Y address is to DB7 (MSB) from the increased by 1. display RAM to the data bus. Note: Busy time varies with the frequency (fCLK ) of ø1, and ø2. (1/fCLK ≤ TBUSY ≤ 3/fCLK )

The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing D = 0 into D = 1. Display Start Line Z address AAAAAA (binary) of the display data RAM is set in the display start line register and displayed at the top of the screen. Figure 4 shows examples of display (1/64 duty cycle) when the start line = 0–3. When the display duty cycle is 1/64 or more (ex. 1/32, 1/24 etc.), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed. Set Page (X Address) X address AAA (binary) of the display data RAM is set in the X address register. After that, writing or reading to or from MPU is executed in this specified page until the next page is set. See figure Set Y Address Y address AAAAAA (binary) of the display data RAM is set in the Y address counter. After that, Y address counter is increased by 1 every time the data is written or read to or from MPU. Status Read

  • Busy When busy is 1, the LSI is executing internal operations. No instructions are accepted while busy is 1, so you should make sure that busy is 0 before writing the next instruction.
  • ON/OFF Shows the liquid crystal display conditions: on condition or off condition. When on/off is 1, the display is in off condition. When on/off is 0, the display is in on condition.
  • RESET RESET = 1 shows that the system is being initialized. In this condition, no instructions except status read can be accepted. RESET = 0 shows that initializing has finished and the system is in the usual operation condition. Code 000011111D R/W D/I DB7 DB0 MSB LSB Code 0011 AAAAAA R/W D/I DB7 DB0 MSB LSB Code 0010111AAA R/W D/I DB7 DB0 MSB LSB Code 0001 AAAAAA R/W D/I DB7 DB0 MSB LSB Code 1 0 Busy 0 ON/ OFF RESET 0000 R/W D/I DB7 DB0 MSB LSB

Figure 4 Relation between Start Line and Display HD61202 781 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM60 COM61 COM62 COM63 COM64 Start line = 0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM60 COM61 COM62 COM63 COM64 Start line = 1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM60 COM61 COM62 COM63 COM64 Start line = 2 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM60 COM61 COM62 COM63 COM64 Start line = 3

Writes 8-bit data DDDDDDDD (binary) into the display data RAM. Then Y address is increased by 1 automatically. Read Display Data Reads out 8-bit data DDDDDDDD (binary) from the display data RAM. Then Y address is increased by 1 automatically. One dummy read is necessary right after the address setting. For details, refer to the explanation of output register in “Function of Each Block”. Code 0 1DD DDDD R/W D/I DB7 DB0 MSB LSB DD Code 1 1DD DDDD R/W D/I DB7 DB0 MSB LSB DD Figure 5 Address Configuration of Display Data RAM X = 0 X = 1 DB0 to DB7 DB0 to DB7 Page 0 Page 1 012 6 16 26 3 Y address X = 6 X = 7 DB0 to DB7 DB0 to DB7 Page 6 Page 7

Interface with HD61203 (1/64 Duty Cycle) HD61202 783 RC RC VCC V1L, V1R V6L, V6R V5L, V5R V2L, V2R V EE GND HD61203 SHL DS1 DS2 TH CL1 FS M/S FCS STB V CC V EE VCC X64 DL DR Open Open M CL2 FRM M CL FRM V CC ADC RST External CR MPU Power supply circuit +5 V (VCC ) R3 V1 R3 V6 R3 V3 R3 V4 R3 V5 R3 V2 VEE Contrast –10 V R3 = 15 Ω HD61202 R f C f COM1 COM64 Y1 Y64 VCC V1L, V1R V2L, V2R V3L, V3R V4L, V4R V EE1 , VEE2 GND VCC V EE CS1 CS2 CS3 R/W D/I E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 SEG1 SEG64 LCD panel 64 × 64 dots

Figure 6 LCD Driver Timing Chart (1/64 Duty Cycle) 784 HD61202 CL FRM M X64 Y64 12 3 4 8 4 9 64 1 2 3 64 1 2 3 64 1 1 frame 1 frame The waveforms of Y1 to Y64 outputs vary with the display data. In this example, the top line of the panel lights up and other dots do not. Selected Input COM SEG Non-selected

  1. Example of Connection with HD6800 In this decoder, addresses of HD61202 in the address area of HD6800 are: Read/write of the display data $FFFF Write of display instruction $FFFE Read out of status $FFFE Therefore, you can control HD61202 by reading/ writing the data at these addresses. Figure 7 Example of Connection with HD6800 Series A15 to VMA R/W to RES HD6800 Decoder VCC CS1 CS2 CS3 D/I R/W E DB0 to DB7 RST HD61202 V CC
  1. Example of Connection with HD6801
  • Set HD6801 to mode 5. P10 to P14 are used as the output port and P30 to P37 as the data bus.
  • 74LS154 4-to-16 decoder generates chip select signal to make specified HD61202 active after decoding 4 bits of P10 to P13.
  • Therefore, after enabling the operation by P10 to P13 and specifying D/I signal by P14, read/write from/to the external memory area ($0100 to $01FE) to control HD61202. In this case, IOS signal is output from SC1 and R/W signal from SC2.
  • For details of HD6800 and HD6801, refer to their manuals. Figure 8 Examples of Connection with HD6801 A B C D Y15 G1 G2 74LS154 P10 P11 P12 P13 (IOS) (SC1) (R/W) (SC2) P14 E P30 P31 P37 HD6801 (Data bus) CS1 CS2 CS3 R/W D/I E DB0 DB1 DB7 HD61202 No. 1 VCC

In this example, two HD61203s output the equivalent waveforms. So, stand-alone operation is possible. In this case, connect COM1 and COM65 to X1, COM2 and COM66 to X2, ..., and COM64 and COM128 to X64. However, for the large screen display, it is better to drive in 2 rows as in this example to guarantee the display quality. Figure 9 Application Example HD61203 (master) X64 HD61203 (slave) HD61202 No. 1 Y1 Y64 HD61202 No. 2 Y1 Y64 HD61202 No. 8 Y1 Y32 COM1 COM2 LCD panel 128 × 480 dots HD61202 No. 9 Y1 Y64 HD61202 No. 10 Y1 Y64 HD61202 No. 16 Y1 Y32 COM3 X64 COM65 COM66 COM67 COM128 COM64

Item Symbol Value Unit Note Supply voltage V CC –0.3 to +7.0 V 2 VEE1 VCC – 19.0 to VCC + 0.3 V 3 VEE2 Terminal voltage (1) V T1 VEE – 0.3 to VCC + 0.3 V 4 Terminal voltage (2) V T2 –0.3 to VCC + 0.3 V 2, 5 Operating temperature T opr –20 to +75 °C Storage temperature T stg –55 to +125 °C Notes: 1. LSIs may be destroyed if they are used beyond the absolute maximum ratings. In ordinary operation, it is desirable to use them within the recommended operation conditions. Useing them beyond these conditions may cause malfunction and poor reliability. 2. All voltage values are referenced to GND = 0 V. 3. Apply the same supply voltage to V EE1 and VEE2 . 4. Applies to V1L, V2L, V3L, V4L, V1R, V2R, V3R, and V4R. Maintain VCC ‡ V1L = V1R ‡ V3L = V3R ‡ V4L = V4R ‡ V2L = V2R ‡ VEE 5. Applies to M, FRM, CL, RST, ADC, ø1, ø2, CS1, CS2, CS3, E, R/W, D/I, and DB0–DB7. 788 HD61202

Electrical Characteristics (GND = 0 V , VCC = 4.5 to 5.5 V , VCC – VEE = 8 to 17.0 V , Ta = –20 to +75°C) Limit Item Symbol Min Typ Max Unit Test Condition Notes Input high voltage V IHC 0.7 · VCC —V CC V1 VIHT 2.0 — V CC V2 Input low voltage V ILC 0 — 0.3 · VCC V1 VILT 0 — 0.8 V 2 Output high voltage VOH 2.4 — — V I OH = –205 µA 3 Output low voltage V OL — — 0.4 V I OL = 1.6 mA 3 Input leakage current IIL –1.0 — +1.0 µA Vin = GND – V CC 4 Three-state (off) I TSL –5.0 — +5.0 µA Vin = GND – V CC 5 input current Liquid crystal supply I LSL –2.0 — +2.0 µA Vin = V EE – VCC 6 leakage current Driver on resistance R ON — — 7.5 k Ω VCC – VEE = 15 V 8 ±ILOAD = 0.1 mA Dissipation current ICC (1) — — 100 µA During display 7 ICC (2) — — 500 µA During access 7 access cycle = 1 MHz Notes: 1. Applies to M, FRM, CL, RST, ø1, and ø2. 2. Applies to CS1, CS2, CS3, E, R/W, D/I, and DB0–DB7. 3. Applies to DB0–DB7. 4. Applies to terminals except for DB0–DB7. 5. Applies to DB0–DB7 at high impedance. 6. Applies to V1L–V4L and V1R–V4R. 7. Specified when liquid crystal display is in 1/64 duty cycle mode. Operation frequency: f CLK = 250 kHz (ø1 and ø2 frequency) Frame frequency: f M = 70 Hz (FRM frequency) Specified in the state of Output terminal: Not loaded Input level: V IH = VCC (V) VIL= GND (V) Measured at VCC terminal HD61202 789

  1. Resistance between terminal Y and terminal V (one of V1L, V1R, V2L, V2R, V3L, V3R, V4L, and V4R) when load current flows through one of the terminals Y1 to Y64. This value is specified under the following condition: The following is a description of the range of power supply voltage for liquid crystal display drive. Apply positive voltage to V1L = V1R and V3L = V3R and negative voltage to V2L = V2R and V4L = V4R within the DV range. This range allows stable impedance on driver output (RON). Notice that DV depends on power supply voltage V CC –V EE . 790 HD61202 Terminal Y (Y1–Y64) V1L, V1R V3L, V3R V4L, V4R V2L, V2R RON VCC – VEE = 15.0 V V1L = V1R , V3L = V3R = VCC – 2/7 (VCC – VEE ) V2L = V2R , V4L = V4R = VCC + 2/7 (VCC – VEE ) /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 /n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00/n00 ΔV ΔV VCC V1 (V1L = V1R ) V3 (V3L = V3R ) V4 (V4L = V4R ) V2 (V2L = V2R ) VEE 5.0 ΔV (V) 8 17.0 VCC – VEE (V) Range of power supply voltage for liquid crystal display drive Correlation between driver output waveform and power supply voltages for liquid crystal display drive Correlation between power supply voltage V CC – VEE and ΔV

Applicable terminals: M, FRM, CL, RST, ø1, ø2, CS1, CS2, CS3, E, R/W, D/I, ADC Applicable terminals: DB0–DB7 Input/Output Terminal Input Terminal PMOS NMOS VCC Output Terminal VCC PMOS V1L, V1R VCC PMOS V3L, V3R VEE NMOS V4L, V4R VEE NMOS V2L, V2R Applicable terminals: Y1–Y64 PMOS VCC NMOS (Input circuit) Enable Data (Output circuit) [three state]

Interface AC Characteristics MPU Interface (GND = 0 V , VCC = 4.5 to 5.5 V , Ta = –20 to +75°C) Item Symbol Min Typ Max Unit Note E cycle time t CYC 1000 — — ns Fig. 10, Fig. 11 E high level width P WEH 450 — — ns E low level width P WEL 450 — — ns E rise time t r — — 25 ns E fall time t f — — 25 ns Address setup time t AS 140 — — ns Address hold time t AH 10 — — ns Data setup time t DSW 200 — — ns Fig. 10 Data delay time t DDR — — 320 ns Fig. 11, Fig. 12 Data hold time (write) t DHW 10 — — ns Fig. 10 Data hold time (read) t DHR 20 — — ns Fig. 11 Figure 10 MPU Write Timing 792 HD61202 2.0 V 0.8 V 2.0 V 0.8 V 2.0 V 0.8 V tCYC PWEL PWEH tr tAS tAS tAH tAH tf 2.0 V 0.8 V tDSW tDHW E R/W CS1–CS3 D/I DB0–DB7

Clock Timing(GND = 0 V , VCC = 4.5 to 5.5 V , Ta = –20 to +75°C) Limit Item Symbol Min Typ Max Unit Test Condition ø1, ø2 cycle time t cyc 2.5 — 20 µs Fig. 13 ø1 low level width t WLø1 625 — — ns ø2 low level width t WLø2 625 — — ns ø1 high level width t WHø1 1875 — — ns ø2 high level width t WHø2 1875 — — ns ø1—ø2 phase difference t D12 625 — — ns ø2—ø1 phase difference t D21 625 — — ns ø1, ø2 rise time t r — — 150 ns ø1, ø2 fall time t f — — 150 ns Figure 13 External Clock Waveform 794 HD61202 tWHø1trtf tWLø1 tD12 tD21 tWHø2 tWLø2 trtf tcyc

Display Control Timing(GND = 0 V , VCC = 4.5 to 5.5 V , Ta = –20 to +75°C) Limit Item Symbol Min Typ Max Unit Test Condition FRM delay time t DFRM –2 — +2 µs Fig. 14 M delay time t DM –2 — +2 µs CL low level width t WLCL 35 — — µs CL high level width t WHCL 35 — — µs Figure 14 Display Control Signal Waveform HD61202 795 CL FRM M