HD404328FS

HD404328 HITACHI

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Technical content

(JAN 13 ae HD404328, HD4074329 4-Bit Single-Chip Microcomputer © HITACHI Description HD404328S, HD4074329S The HD404328 and HD4074329 are HMCS400-series microcomputers designed to increase program productivity and also incorporate large-capacity memory. Each micro- RN computer has an LCD driver/controller, A/D converter, siti zero-crossing detection circuit, and 32-kHz oscillator for aN clock. atl The HD4074329, which includes PROM, is a ZTAT micro- < aN N computer that can dramatically shorten system development ~ will Y periods and smooth the process from debugging to mass aN ye production. ee DP-64S Features HD404328FS, HD4074329FS * 8,192-word x 10-bit ROM (HD404328) ~ 16,384-word x 10-bit PROM (HD4074329) ; (ZTAT versions are 27256-compatible) 4 aff © 256-digit x 4-bit RAM (HD404328) @ ff! 512-digit x 4-bit RAM (HD4074329) cil * 35 .1/0 pins iil — 2 input pins AN \\ — 33 input/output pins, including 8 large-current pins RR, | (15 mA, max) and 16 pins multiplexed with LCD seg- i 1 fi ment pins © Three timer/counters * Clock-synchronous 8-bit serial interface FP-64B * A/D converter (8-bit x 4-channel) HD4074329C © 12-digit LCD driver — Static, V4, '", Vs Duty Cycle ; © Zero-crossing detection circuit (optional) © Eight interrupt sources ° S — Two external sources, including one double-edge funetion DC-648 — Six internal sources © Subroutine stack ¢ Instruction cycle time: 2 ys (fosc=4 MHz) — Up to 16 levels, including interrupts © Two operating modes © Four low-power dissipation modes — MCU mode — Subactive mode (optional) — PROM mode (HD4074329 only) : — Standby mode © Built-in oscillator - — Crystal or ceramic filter (external clock also Support Tools enabled) © Macro assembler for H68/H680SD series ¢ Emulator for AS microcomputers (with realtime trace function) { — Anemulator unit, target probe, and user cable are not included. Any emulator unit designed for the HMCS400 series can be used.

HD404328, HD4074329

Ordering Information

Type Product Name ROM (Words) Package Comment Mask ROM HD404328S 8,192 DP-64S HD404328FS FP-64B ZTAT HD4074329S 16,384 DP-64S HD4074329FS FP-64B HD4074329C Dc-64s Window Pin Arrangement v,010 6417) Vee x val]2 63{_]coma ae) gggs88 vol] 3 62 [coms Bezes53338355 AN] 4 1 icone NONAAAANONNNN ANoL]5 60 [_]COM1 64 63 62 61 60 59 58 57 56 55 54 53 52 aN, C]6 59|_]seG24 ANoL_|1 51[_JsEG22 ANZ 7 58 |_]SEG23 AN3CJ2 50 JsEG21 | ANC] 8 87 |_] SEG22 AVss(]3 49|"}sEG20 AVes(_] 9 56 [_]SEG21 TestL4 48[_]seci9 Test LJ 10 55 [_]SEG20 osc, C]5 47(secis ose, 11 54|_]sEG19 osceL]|6 46(_]seG17 osca[_] 12 s3(_]seGia RESET (_|7 45[_]R5,/SEGI6| RESET C] 13 52(_Jseci7 xif]s 44[7]Rs2/Sects| xif} 14 siLIRSyseGis § —x2_]9 43[_JR5 /SEG14] xe[] 15 s0[JR5Q/SEG15 GNDL]10 42{JR5y/SEG13} eno] 16 49[]R5,/SEGI4 == DoL_]11 41 R4yseci2| OL] 17 4a(Jrsysecis 0, L]12 4o[JR4y/SEG11 oC] 19 4s(Dragseai1 aL] 14 38[_IR4g/SEG9 Dz] 20 45 [_] R4,/SEG10 o,C)15 37[_]R34/SEG8 o,C Jat 44[TR4gSEGO = Os L] 16 36[_]R3,/SEG7 Os] 22 43[JR3/SEG8 = gL_]17 35[_JR3 /SEG6 DL] 23 42(Jraseq7 = 0 L]18 34[_JR3y/SeGs 0,L] 24 41 [1R3, SEG “1Ch19 33[JR2q/SEG4 Cas 40 [_Jraysees 20 21 22 23 24 25 26 27 28 29 30 31 32 Do/NTo (| 26 39 |_| R29/SEG4 QUUUUUQUUOUDU DroANT; C] 27 38 Clr2,/seos Eseeeepeahsag ROg(_] 28 37 (_]R2,/SEG2 ee BE SERLD Ro, CL] 29 96 |_] R2q/SEG1 a z edgag Ro2[_| 30 35 [_] Rig/BUZZ coe R03(_| 31 34] P1280 oe IRtg/SCKC] 32 33 RNS 1: Oy /2COEVENT DP-64s FP-64B Dc-64s (top view) (top view) | Note: For packaging details, see page 87. I 2 @ HITACHI

HD404328, HD4074329 Pin Description Pin Number DP-64S FP-64B Item Symbol DC-64S VO Function Power supply = Vcc 64 58 Applies power voltage GND 16 10 Connected to ground Test TEST 10 4 1 Used for factory testing only: connect this pin to Veg Reset RESET 13 7 i Resets the MCU Oscillator osc, 11 5 ii Input/output pins for the internal oscillator ‘OSC. 12 6 © Circuit: connect them to a crystal, ceramic 2 filter, or external oscillator circuit x1 14 8 i Used for a 32.768-kHz crystal for clock X2 15 9 © Purposes: if not used, fix X1 to Voc and leave X2 open Port Do~Dg 17-25 11-19 VO Input/output ports addressed by individual bits; pins DoD, are large-current pins that can each supply up to 15 mA Do, Dio 26,27 20,21 | Input ports addressable by individual bits RO9-R53 28-51 22-45 VO _ Inpuvoutput ports addressable in 4-bit units Interrupt INTo, INT, 26,27 20, 21 | _ Input pins for external interrupts Serial SCK 32 26 VO __ SCI clock input/output pin si 33 27 | SCI receive data input pin sO 34 28 O SCI transmit data output pin Buzzer BUZZ 35 29 O Buzzer signal output pin LCD Vi. Vo. V3 1-3 59-61 Power pins for LCD driver; can be left open in operation because they are connected by internal voltage division resistors Voltage conditions are: Voc 2 V1 2 V2 2 V3 2 GND COM1-COM4 60-63 54-57 © Common signal pins for LCD SEG1-SEG24 36-59 30-53 © — Segment signal pins for LCD. AD converter = AVoco 4 62 Power pin for A/D converter: connect it to the same potential as Voc, as close physi- cally as possible to the power source AVss 9 3 Ground for AVcc: connect it to the same potential as GND, as close physically as possible to the power source ‘ANo-ANg 5-8 63, 64, 1,2 | Analog input pins for 4-channel A/D converter Zero-crossing ZCD 25 19 1 Zero-crossing detection input pin detection Counter EVENT 25 19 I Event count input pin @HITACHI 3

HD404328, HD4074329 Block Diagram 3— as re ge ES a | 5 ies | S gos Ss é4|fe, ee iB

38 Bs zit ss ule 3

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8888 S8858858 855555555558 88 88

BRRRRBR RBH RRR RRR H BY BB 4 @HITACHI

HD404328, HD4074329 Memory Map ROM Memory Map Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. The ROM memory map is shown in figure 1 and described below. Program Area (HD404328: $0000-$1FFF, HD4074329: $0000-$3FFF): Used for program Vector Address Area ($0000-$000F): Reserved coding. for JMPL instructions that branch to the start addresses of the reset and interrupt service rou- RAM Memory Map tines. After MCU reset or an interrupt routine is . . . serviced, program execution continues from the The MCU contains a 256-digit x 4-bit (HD404328) vector address. or 512-digit x 4-bit (HD4074329) RAM area con- sisting of a data area and a stack area. In addition, Zero-Page Subroutine Area ($0000-$003F): interrupt control bits and special registers are Reserved for subroutines. The program branches mapped onto the same RAM memory space out- to a subroutine in this area in response to the CAL _ side this area. The RAM memory map is shown in instruction. figure 2 and described below. 0 $0000 0 JMPL instruction $0000 ‘6 Vector address s000F 1 [Gump to RESET routine) | $0001 Zero-page subroutine 3 (jump to INTo routine) $0003 (64 words) 4 JMPL instruction $0004 63 soso 5{ (jump toINT; routine) $0005 Pattern 7|_ (jump to TIMER-A routine) $0007 (4096 words) 8 JMPL instruction $0008 4095 $OFFF 9 lump to TIMER-B routine! $0009 4096 $1000 10 JMPL instruction $000A "1 jump to TIMER-C routine} $000B HD404328 program 12 JMPL instruction $000C (8192 words) 13 jump to ZCD routine! $000D

14 JMPL instruction $000E

8191 S1FFF 15) ti

a192 $2000 lump to A/D, SERIAL routine) | $000F HD4074329 program (16384 words) 16383 $3FFF @ HITACHI 5

HD404328, HD4074329 Interrupt Control Bit Area and Register Flag —_ segments as display data. Data 1 lights the corre- Area ($000-$003, $020-$023): Used for interrupt sponding LCD segment; data 0 extinguishes it. control bits and the bit register (figure 3). This area can be accessed only by RAM bit manipula. Data Area (HD404328: $040-$04F and tion instructions. In addition, note that the inter- | $070-$11F, HD4074329: $070-$21F): The Tupt request flag cannot be set by software, the memory register (MR), which is 16 digits RSP bit is used only to reset the stack pointer, and ($040-$04F) long, can be accessed by the LAMR the WDON flag can be set only by the SEM and and XMRA instructions. Its structure is shown in SEMD instructions. figure 4. Special Function Register Area ($004-$01F, | Stack Area ($3C0-$3FF): Used for saving the $024-$03F): Used as mode registers for external contents of the program counter (PC), status (ST), interrupts, serial interface, and timer/counters, and and carry (CA) at subroutine call (CAL, CALL) as data registers and as data control registers for and interrupt servicing. This area can be used as a Y/O ports. As shown in figure 2, these registers can 16-nesting-level subroutine stack in which one be classified into three types: write-only, read- _ level requires four digits. The data to be saved and only, and read/write. The SEM, SEMD, REM, and __ the save conditions are shown in figure 4. REMD instructions can be used for the LCD con- . . trol register (LCR), but RAM bit manipulation The program counter is restored by either the RTN instructions cannot be used for other registers. or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any LCD Data Area ($050-$067): Used for storing unused space in this area is used for data storage. LCD data which is automatically output to LCD 6 © HITACHI

HD404328, HD4074329 3000 ° RAM-mapped registers s ° bee 63 (64 digits) $03F 2 Interrupt control bit area $002 64 $040 3 $003 Memon oe 4 [Port mode register A __(PMRA)! W_| $004 79 9 $04F 5 [ Serial mode register (SMR) | W_| $005 80 i $050 6 $006 aarvete hie \\ 7 | Serial data register, upper (SRU) | RWW | $007 103 $067 8 $008 104 $068 9 | Timer mode register B iB) ;_ W_| $009 Not used \\ 10 | timer B (TCBL/TLRL) ‘RW | $O0A 111 $06F 1 CBU/TLRU) | RW | $00B 112 Data $070 12 | Miscellaneous register MIS) ;_W_| $00C. (176 digits) \\ 13 | Timer mode register C «_W_| $00D 287 9 S11F 14 | timer 6 CCUTCRL) +R | $00E 200 || $120 15 ‘CCU/TCRU) : RW | SooF | Data 16 [ Interrupt mode register IMR): W_ | $010 | (2s6digis) | 17 | Port mode register B___(PMRB) ; W_| $011 543} ee ie $21F 18 | Port mode registerC ___(PMRC) + W_| $012 544 $220 19 $013 20 | LCD mode register (LMR) | W_| $014 Notused 21 $015 959 $3BF 22 | A/D mode register (AMR) ;_W_| $016 960 $3C0 23 | A/D data register, lower (ADRL): R_] $017 fact 24 | A/D data register, upper_(ADRU) + R_| $018 (64 digits)

1023 SOFF Not used

Shaded area can only be 35 eatster lag area $023 48 $030 49 | PortR1 DCR (DCR1) ; W_| $031 50 | PortR2 DCR (DCR2) | W_| $032 51 $033 52 | PortR4 DCR (DCR4) | W_| $034 Ri Read only 53 | Port R5 DCR (CRs) - W_| $035 RW: ReadMrite 59 | Port Do-D3 DCR (DCRB) + W_| $03B * Two registers mapped on the same area 60 | Port De-D7 DCR DCRC) | W_| $o3c 61 | Port DgDCR (DCRD) | W_| $03D 62) $03E Timer/event counter B, lower Timer load register B, lower + TCBL) iR LAL) W | Soa Timer/event counter B, upper ‘ R Timer load register B, upper : w|$ooB | CBU, ‘ U) ‘ | ‘Timer/counter C, lower oR Timer load register C, lower: Timer/counter C, upper R Timer load register C, upper | OCU) : RU LW | S00F Figure 2, RAM Memory Map @HITACHI 7

HD404328, HD4074329 Bit 3 Bit 2 Bit 1 Bito

9 IM of INT, IF of INT Reset SP bit) _ | (Interrupt enable flag) | $00

1) (Mof timer A) IF of timer A) __(IM of INT; IF of ING) | $001 IMTC IFTC IMTB IFTB

2 IM of timer C IF of timer C) __(IM of timer B) IF of timer B $002

3 IM of A/D IF of A/D IM of ZCD} IF of ZCD $003

32 | Direct transfer on flag (A/D start flag (Watchdog on flag Low speed on flag) | $020 33) | so21 Reserved 34 $022 IMS [IFS 35| (1M of serial interface) | (IF of serial trace) . 8023 IF: Interrupt request flag IM: Interrupt mask VE: Interrupt enable flag SP: Stack pointer Note: Bits in the interrupt control bit area and register flag area are set by the SEM or SEMD instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction. Other instructions have no effect. However, note that the IF cannot be set by the SEM or SEMD instruction. If the RSP bit or a non-existent bit is tested by the TM or TMD instruction, its status is undefined. The WDON flag can only be used by the SEM or SEMD instruction (it is reset only by MCU reset). Figure 3 Configuration of Interrupt Control Bit and Register Flag Area Memory registers Stack area 65 | MR (1) | $041 Level 15 66 | MR (2) | $042 67 | MR (3) | $043 Level 13 68 | MR (4) | $044 69 | MR (5) | $045 Level 11 70 [MR (6) | $046 Level 10 7 $047 Bit Bit2 Bit1 Bito 73 {MR (9) | $049 1020 | ST | PCis | PCi2 | PCi | $3FC 75 [MR (11)] $04B 1021 | PCio | PCy | PCs | PC; | $3FD

7 Pe a $04D Level 3 1022 | CA | PCs | PCs | PCy | $3FE

78 $04E oa. | Fal pa |e 79 [ma (15)} $04F 1028 sorF 1028 SFF PC3-PCp: Program counter ST: Status CA: Carry Figure 4 Configuration of Memory Register and Stack Area, and Stack Position 8 @ HITACHI

HD404328, HD4074329 Functional Description Registers and Flags for indirect RAM addressing. The Y register is also used for D-port addressing. The MCU has nine registers and two flags for CPU operations. They are shown in figure 5 and SPX Register (SPX), SPY Register (SPY): Four- described below. bit registers used to supplement the X and Y registers. Accumulator (A), B Register (B): Four-bit regis- ters used to hold results from the arithmetic logic © Carry (CA): One-bit flag that stores any ALU unit (ALU) and transfer data between memory, _ overflow generated by an arithmetic operation. CA J/O, and other registers. is affected by the SEC, REC, ROTL, and ROTR . instructions. A carry is pushed onto the stack dur- W Register (W), X Register (X), Y Register (Y): ing interrupt servicing and popped from the stack Two-bit (W) and four-bit (X and Y) registers used by the RTNI instruction—but not by the RTN instruction. 3 i} 3 0 1 i [w ] W register 3 i) 3 0 3 oO 3 i) Status 13 9 9 5 i} PTT J spon Figure 5 Registersand Flags @ HITACHI 9

HD404328, HD4074329 Status (ST): One-bit flag that latches any over- _An interrupt request flag (IF), interrupt mask (IM), flow generated by an arithmetic or compare _and vector address are provided for each interrupt instruction, not-zero decision from the ALU, or source, and an interrupt enable flag (I/E) controls result of a bit test. ST is used as a branch condi- _ the entire interrupt process. tion of the BR, BRL, CAL, and CALL instruc- tions. The contents of ST remain unchanged until Vector addresses are shared by serial interface and the next arithmetic, compare, or bit test instruction A/D converter interrupt causes, so software must is executed, but become 1 after a BR, BRL, CAL, _ first check which type of request has occurred. or CALL instruction is read, regardless of whether . ae the instruction is executed or skipped. ‘The con- Interrupt Control Bits and Interrupt Servicing: tents of ST are pushed onto the stack during inter- Locations $000 to $003 and $020 to $023 in RAM rupt servicing and popped from the stack by the are reserved for the interrupt control bits which can RTNI instruction—but not by the RTN instruction. be accessed by RAM bit manipulation instructions. Program Counter (PC): 14-bit counter that The interrupt request flag (IF) cannot be set by points to the ROM address of the instruction being software. MCU reset initializes the interrupt executed. enable flag (I/E) and the IF to 0 and the interrupt mask (IM) to 1. Stack Pointer (SP): Ten-bit pointer that contains . . co the address of the stack area to be used next. The 4 block diagram of the interrupt control circuit is SP is initialized to $3FF by MCU reset, is Shown in figure 6, interrupt priorities and vector decremented by 4 when data is pushed onto the ddresses are listed in table 2, and interrupt pro- stack, and is incremented by 4 when data is popped &SSing conditions for the eight interrupt sources from the stack. Since the top four bits of the SP 2€ listed in table 3. are fixed at 1111, a stack of up to 16 levels can be Ay interrupt request occurs when the IF is set to 1 . and the IM is set to 0. If the I/E is 1 at that point, ‘The SP can be initialized to $3FF in another way: __ the interrupt is serviced. A priority programmable by resetting the RSP bit with the REM or REMD logic array (PLA) generates the vector address instruction. assigned to that interrupt source. Reset The interrupt processing sequence is shown in fig- ure 7 and an interrupt processing flowchart is ‘The MCU is reset by inputting a high-level voltage Shown in figure 8. After an interrupt is acknowl- to the RESET pin. At power-on and when stop edged, the previous instruction is completed in the mode is canceled, RESET must be high for at least first cycle. The I/E is reset in the second cycle, the ‘one tac to enable the oscillator to stabilize. During Carry, Status, and program counter values are operation, RESET must be high for at least two _ Pushed onto the stack during the second and third instruction cycles. cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Initial values after MCU reset are shown in table 1. Program a JMPL instruction at each vector Interrupts address, to branch the program to the start address of the interrupt service program, and reset the IF The MCU has eight interrupt sources: two exter- by a software instruction within the interrupt ser- nal signals (INTo and INT}), three timer/counters —_yice program. (timer A, timer B, and timer C), serial interface (SERIAL), zero-crossing detection, and A/D converter, 10 @ HITACHI

HD404328, HD4074329 Table 1 Initial Values After MCU Reset Initial tem Abbr. Value __ Contents Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status 61) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt Interrupt enable flag ___(VE)___O Inhibits all interrupts flags/mask Interrupt request flag _(IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests. vo Port data register (PDR) _Allbits 1 Enables output at level 1 Data control register (OCR) Allbits 0 Turns output buffer off (to high impedance) Port mode register A (PMRA) 0000 Refer to description of port mode register A Port mode register B (PMRB) 0000 Refer to description of port mode register B Port mode register C __(PMRC) 0000 __ Refer to description of port mode register C Interrupt mode register (IMR) 0000 Refer to description of interrupt mode register Timer/ Timer mode register A (TMA) 0000 Refer to description of timer mode register A counters. Timer mode registerB (TMB) 0000 _ Refer to description of timer mode register B interface Timer mode registerC (TMC) 0000 Refer to description of timer mode register C Serial mode register (SMR) 0000 _ Refer to description of serial mode register Prescaler S $000 _ Prescaler W $00 = Timer/counter A (TCA) $00 _ Timer/counter B (TCB) $00 _— Timer/counter C (TCC) $00 _ Timer load registerB (TLR) $00. — OT Timer load registerC (TCR) $00 = Octal counter 000 = AD A/D mode register (AMR) _ 0000 Refer to description of A/D mode register LCD LCD control register (LCR) 000 Refer to description of LCD control register LCD mode register (CMR) 0000 Refer to description of LCD duty cycle/clock control register LCD output register (LOR) 0000 Refer to description of LCD output register Bit register Low speed on flag (LSON) 0 Refer to description of low-power dissipation modes Watchdog timer on flag_(WDON) 0 Refer to description of timer C AD start flag (ADSF) 0 Refer to description of A/D converter Direct transfer on flag __(DTON) 0 Refer to description of low-power dissipation modes Miscellaneous register (MIS) 0000 __ Refer to description of miscellaneous register Note: The statuses of other registers and flags after MCU reset are as follows: Status After Cancellation of Status After all Other Types of Item Abbr. Stop Mode by MCU Reset Reset Carry (CA) Pre-MCU-reset values are not = Pre-MCU-reset values are not Accumulator (A) guaranteed: values must be ini- guaranteed: values must be ini- Bregister (8) tialized by program alized by program W register (W) X/SPX register (X/SPX) YISPY register__(Y/SPY) Serial data register (SR) AUD data register (ADRL, ADRU) RAM Pre-MCU-reset (pre-STOP- instruction) values are retained @ HITACHI nN

HD404328, HD4074329 $000, 0 Sequence control + Push PC/CAST |) + Reset VE + Jump to vector address ety >To O ee [——— Vector sn FEE [renee ” t+ + Priority control PLA $001, 0 {| $001, 1 d ) Lim: ] $001, 2 $001, 3 d ) $002, 0 am >) $002, 2 $002.3 5 |) $003, 0 $003, 1 d ) $003, 2 (\\ $023, 2 $003, 3 d ) C 023, 3 [imap] LIMs |] Figure 6 Block Diagram of Interrupt Control Circuit Table 2 Vector Addresses and Interrupt Priorities Reset, Interrupt Priority Vector Address RESET $0000 INTa 1 $0002 INT, 2 $0004 Timer A 3 $0006 Timer B 4 $0008 Timer C 5 $000A zcD 6 $000C AD, Serial 7 $000E 12 @ HITACHI

HD404328, HD4074329 Instruction cycles 1 2 3 4 5 6 Instruction execution Interrupt Stacking, piacking, (dress! acceptance VE reset generation Execution of JMPL instruction at vector address Execution of instruction at start address The stack is accessed and the I/E reset after the instruction of Interrupt is executed, even if it is a two-cycle instruction. routine Figure 7 Interrupt Processing Sequence Table3 —_—s Interrupt Processing and Activation Conditions Interrupt ——IniterruptCause Control Bit INTo INT, TimerA TimerB TimerC ZCD AUD, Seriai VE 1 1 1 1 1 1 1 IFO -IMO 1 ) i} 0 i) i} 0 1F1-IM1 . 1 t) tf) 0 t) ) IFTA:IMTA . . 1 0 ie) 9 0 (FTB-IMTB . . . 1 i) ie) 0 IFZC -IMZC * . * . . 1 i} +1FS-IMS Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. @ HITACHI 13

HD404328, HD4074329 No Yes Interrupt Yes Yes VEO PC ¢ (PC) +1 Stack — (PC) Stack < (CA) Stack < (ST) Yes INTo PC < $0002 interrupt? No INT; No Timer A No Timer B No Timer C No ZcD PC « $000 No (A/D, serial interrupt) Figure 8 Interrupt Processing Flowchart 14 @ HITACHI

HD404328, HD4074329 Interrupt Enable Flag (/E: $000, 0): Controls IFO is set at the falling edge of signals input to the entire interrupt process. It is reset by the inter- INT, and IFI is set at the rising and falling edges Tupt processing and set by the RTNI instruction, as _of signals input to INT. The INT, interrupt edge shown in table 4. is selected by the interrupt mode register (IMR: $010), as shown in figure 9. External Interrupts (INTp, INT): Specified by port mode register A (PMRA: $004). External Interrupt Masks (IMO: $000, 3; IM1: $001, 1): Prevent (mask) interrupt requests caused External Interrupt Request Flags (IFO: $000,2; by the corresponding external interrupt request IF1: $001, 0): Set at the rising or falling edges of _flags, as shown in table 6. the INTo and INT; inputs, as shown in table 5. Table 4 Interrupt Enable Flag Table 6 External Interrupt Masks Interrupt Enable Flag Interrupt External Interrupt (VE) Enabled/Disabled Mask (IMO, IM1) Interrupt Request tC) Disabled tC) Enabled

1 Enabled 1 Disabled (masked)

Table 5 External Interrupt Request Flags External Interrupt Request Flag (IFO, IF1) interrupt Request 0 No

1 Yes

interrupt mode register (IMR): $010 (eet fe) INT; detection edge selection ZCD detection edge selection aes trary | 20P etctone6pe | | wr, otction eae [0 | Noseiecion [0 | Neasecion [ 1 | Falling-edge detection Falling-edge detection + [2 | Rising-edge detection 1 | 0 _| Rising-edge detection [|_ 1] Doubie-eage detection | |_ 1 | Doubie-edge detection Figure 9 Interrupt Mode Register @ HITACHI 15

HD404328, HD4074329 Timer A Interrupt Request Flag (IFTA: $001, 2): Set by overflow output from timer C, as shown. 2): Set by overflow output from timer A, as shown _in table 11. in table 7. Timer C Interrupt Mask (IMTC: $002, 3): Pre- Timer A Interrupt Mask (IMTA: $001, 3): Pre- vents (masks) an interrupt request caused by the vents (masks) an interrupt request caused by the __ timer C interrupt request flag, as shown in table 12. timer A interrupt request flag, as shown in table 8. Zero-Crossing Interrupt Request Flag (IFZC: Timer B Interrupt Request Flag (IFTB: $002, $003, 0): Set by a zero crossing of an AC input 0): Set by overflow output from timer B, as shown _ signal, as shown in table 13. The interrupt edge is in table 9. selected by the interrupt mode register (IMR: $010), as shown in figure 9. Timer B Interrupt Mask (IMTB: $002, 1): Pre- vents (masks) an interrupt request caused by the Zero-Crossing Interrupt Mask (IMZC: $003, timer B interrupt request flag, as shown in table 10. 1): Prevents (masks) an interrupt request caused by the zero-crossing interrupt request flag, as Timer C Interrupt Request Flag (IFTC: $002, — shown in table 14. Table 7 Timer A Interrupt Request Flag Table 11 Timer C Interrupt Request Flag Timer A Interrupt Timer C Interrupt Request Flag (IFTA) Interrupt Request Request Flag (IFTC) Interrupt Request

0 No 0 No

1 Yes 1 Yes

Table 8 Timer A Interrupt Mask Table 12 Timer C Interrupt Mask Timer A Interrupt Timer C Interrupt Mask (IMTA) Interrupt Request Mask (IMTC) Interrupt Request

0 Enabled i) Enabled

1 Disabled (masked) 1 Disabled (masked)

Table 9 Timer B Interrupt Request Flag Table 13 Zero-Crossing Interrupt Request Flag Timer B Interrupt Zero-Crossing Interrupt Request Flag (IFTB) Interrupt Request Request Flag (IFZC) Interrupt Request (o} No oO No Table 10 Timer B Interrupt Mask Table 14 Zero-Crossing Interrupt Mask Timer B interrupt Zero-Crossing Interrupt Mask (IMTB) Interrupt Request Mask (IMZC) Interrupt Request ° Enabled ° Enabled 16 @ HITACHI

a HD404328, HD4074329 A/D Interrupt Request Flag (IFAD: $003, 2): Serial Interrupt Request Flag (IFS: $023, 2): Set at the completion of A/D conversion, as shown —_ Set when the octal counter counts the eighth trans- in table 15. fer clock signal or when data transfer is discontin- ued by resetting the octal counter (table 17). A/D Interrupt Mask (IMAD: $003, 3): Prevents (masks) an interrupt request caused by the A/D Serial Interrupt Mask (IMS: $023, 3): Prevents interrupt request flag, as shown in table 16. (masks) an interrupt request caused by the serial interrupt request flag, as shown in table 18. Table 15 A/D Interrupt Request Flag Table 17 Serial Interrupt Request Flag AJD Interrupt Serial Interrupt Request Flag (IFAD) Interrupt Request Request Flag (IFS) Interrupt Request Table 16 A/D Interrupt Mask Table 18 Serial Interrupt Mask A/D Interrupt Serial Interrupt Mask (IMAD) Interrupt Request Mask (IMS) Interrupt Request

0 Enabled 0 Enabled

@ HITACHI 7

HD404328, HD4074329 Operating Modes The MCU has five operating modes that are speci- Active Mode: The MCU operates according to fied by how the clock is used. The functions avail- _ the clock generated by the system oscillators OSC, able in each mode are listed in table 19, and opera- and OSC, tions are shown in table 20. Transitions between ‘operating modes are shown in figure 10. Table 19 Functions Available in Each Operating Mode Mode Name Active Standby Stop Watch Subactive4 Activation method RESET SBY STOP TMA = 1 INTo or timer A cancellation, instruction instruction STOP interrupt request interrupt instruction from watch request mode Status System oscillator Operating Operating Stopped Stopped Stopped Subsystem Operating Operating Operating’ Operating Operating oscillator Instruction Operating Stopped Stopped Stopped Operating execution (Dopy) Interrupt function Operating Operating Stopped Stopped Operating interrupt (®pep) Clock function Operating Operating Stopped Operating? Operating? interrupt (®¢. x) RAM Operating Retained Retained Retained Operating Registers/lags Operating Retained Reset® Retained Retained/ operating vo Operating Retained Reset? Retained Operating Cancellation method RESET input, RESET input, RESET input RESET input, RESET input, STOP/SBY interrupt INT or timer A STOP/SBY instruction request interrupt instruction request Notes: 1. To reduce current dissipation, stop all oscillation in external circuits. 2. Refer to the Interrupt Frame section for details. 3. Output pins are at high impedance. 4. Subactive mode is an optional function: specify it on the function option list. 5. The A/D converter does not operate. 6. Port mode register B retains the contents it had in active mode. System Clock (®cpy) Operating Stopped Non-Timebase Peripheral Operating Active mode Standby mode Function Clock (®per) ‘Subactive mode Stopped - Watch mode (TMA3 = 1) Watch mode (TMA3 = 0) 18 @HITACHI

HD404328, HD4074329 Standby Mode: The MCU enters standby mode = Stop mode is terminated by a RESET input as when a SBY instruction is executed from active shown in figure 12, RESET must be high for at mode. In this mode, the oscillators, interrupts, _ least one tgc to stabilize oscillation (refer to the timer/counters, and serial interface continue to AC Characteristics section). When the MCU operate, but all instruction execution-related clocks _restarts after stop mode is canceled, all RAM con- stop. The stopping of these clocks stops the CPU, _ tents are retained, but the accuracy of the contents retaining all RAM and register contents and main- _ of the accumulator, B register, W register, X/SPX taining the current I/O pin status. register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET | Watch Mode: The MCU enters watch mode if a input, the MCU is reset as well. After an interrupt | STOP instruction is executed in active mode when request, the MCU enters active mode and resumes, © TMA3 = 1, or if a STOP or SBY instruction is exe- executing the next instruction after the SBY _ cuted in subactive mode. instruction. If the interrupt enable flag is 1, that . . - interrupt is then processed; if it is 0, the interrupt Watch mode is terminated by a RESET input or a request is left pending and normal instruction exe- timer A/INTp interrupt request. For details of cution continues. A flowchart of operation in RESET input, refer to the Stop Mode section. standby mode is shown in figure 11. When terminated by a timer A/INTo interrupt request, the MCU enters active mode if LSON is 0, Stop Mode: The MCU enters stop mode if a or subactive mode if LSON is 1. Any interrupt STOP instruction is executed in active mode when _ request generated during the transition to active TMA3 = 0. In this mode, the system oscillator mode is delayed for half the interrupt frame period stops, which stops all MCU functions as well. (tac), to give the oscillation time to stabilize, as - shown in figure 13. Table 20 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode? CPU Reset Retained Retained | RAM Retained Retained Retained ee Timer A Reset ee Timer C Reset Stopped —— eee Serial interface Reset Stopped* r—“‘“‘“ (‘CI Leo Reset Ce vo Reset? Retained Retained a AD Reset Stopped stopped Zero-crossing Stopped$ Stopped® a ——eee detection ( ——OC—s Notes: 1. Output pins are at high impedance. 2. Shading means operating. 3. Subactive mode is an optional function specified on the function option list. 4. Transmission/reception is activated if a clock is input in external clock mode. (However, interrupts stop.) 5. The bias circuits still operate when the D8/ZCD/EVENT pin is set to ZCD. @ HITACHI 19

HD404328, HD4074329 Operation during mode transition is the same as Subactive mode is an optional function that the that at standby mode cancellation (figure 11). user must specify on the function option list. Subactive Mode: The CPU operates with a clock = Interrupt Frame: In watch and subactive modes, generated by the X1 and X2 oscillation circuits. timer A and INTo interrupts are generated in syn- Functions that can operate in subactive mode are —chronism with the interrupt frame. Three interrupt listed in table 21. When the STOP or SBY instruc- _frame lengths (T) can be selected by settings of the tion is executed in subactive mode, the MCU __ miscellaneous register, as shown in figure 14. The enters cither watch or active mode, depending on —_time from an interrupt strobe to interrupt request the statuses of LSON and DTON. The DTON flag _— generation is the oscillation stabilization period can only be set in subactive mode; it is automati- —_(igc), as shown in figure 13. cally reset after a transition to active mode. | re | Standby mode Active mode ‘Stop mode pyle poe (TMAS = 0) ‘| fesc: Operating | ‘spy ¢ ‘| osc: Operating |: fosc: Stopped i | fe Operating fx: Operating |: STOP fc Operating t] @axc = foe Pax: = foe : ax: Stopped P| pen: = fore y Interrupt] pen: = foe ; ren: Stopped : : : IA3 = 0) : : : : (TMA = 1) (IMAG = 1, LSON = 0): 1] _ tc Operating fx: Operating [: iNTo, : fx: Operating | : 1 | @eu: Stopped EE es 1 time-base')! | @cru: Stopped |: 1) oe: = tae gov cise fe ee ee 1] Oren = foe : Interrupt i] Gren: = foe —— : ne) aK a : Subactive mode Stop _: (TMAS = 1, LSON = 1): fosc: Main oscillation frequency oe —_ 2} foc: Stopped |: fc Suboscillation frequency, + Operating INTo. : me on rating : for time-base dan = time-base") : Pou: epped : foe: fosc/8 oes @ax: = fou : fous: 1x/8 - = tae STOP/SBY rer: Stopped : ax: Clock for time-base functions Notes: 1. Interrupt source LSON: Low speed on flag 2. STOP/SBY (DTON = 1, LSON = 0) DTON: Direct transfer on flag 3. STOP/SBY (DTON = 0, LSON = 0) Figure 10 MCU Status Transitions 20 @HITACHI

0428, 1104074529 << No <oT eer Ga EEE, SEK. SL EK Gn PEE EK. a ees Yes 7s | Ss (sav (sav (sav (sev (sev hes om ony) ony) ony) oniy) onty) =e | fie processor clocks Yes Figure 11 MCU Operation Flowchart @HITACHI Py

HD404328, HD4074329 MCU operation cycle <9 > - Yes Yes Spy, STOP VE « 0; stack < (PC), instruction? (CA), (ST) anneal j Low power mode; PC < next location PC < vector address 1_ Speration cyeie | IF: Interrupt request flag IM: Interrupt mask VE: Interrupt enabke flag PC: Program counter CA: Cany ‘ST: Status Figure 16 MCU Operating Sequence (MCU operation cycle) 24 @ HITACHI

—_— HD404328, HD4074329 Low power mode operation cycle sm ~ Yes oo

2 Note

. Hardware NOP Hardware NOP execution execution MCU operation Note: For iF and IM operation, refer to figure 11. cycle Figure 17 MCU Operating Sequence (low-power mode operation) @ HITACHI 25

HD404328, HD4074329 cs — bod be it Ss RS {| x2 | 4 | | OSCe TA — ro a = GND Figure 20 Typical Layouts of Crystal and Ceramic Filters @ HITACHI 7

HD404328, HD4074329 Table 21 Oscillator Circuit Examples Circuit Configuration Circuit Constants > eer roron— Ero costas External Clock External Le} ti Open OSC2 Ceramic Filter G — Ceramic titer: CSA4.00MG Oscillator OSC; (Murata) (OSC, OSC2) Ceramic => Rr=1MQ+20% filter C1 = C2 = 30 pF + 20% OSCy GND Crystal Oscillator Cc Rr: TBD (O8C1, 08C2) osc; Ci =Ce=TBD C Crystal: Equivalent to circuit shown rystal CO Co=7 pF, max O8Ce Rg = 100 2, max Ca f= 1.010 4.5 MHz GND AT cut parallel resonance crystal ose <{ Pee osc Co Crystal Oscillator C Cy =Co=15 pF+5% (X1, X2) x1 Crystal: 32.768 kHz, MX38T (Nippon Denpa) Crystal C3 Co=1.5pF, typ x2 Rs =14kQ, typ C GND " <f he e Co ee Notes: 1. Circuit constants differ with different types of crystal and ceramic filter oscillator, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC; and OSC, pins (X1 and X2 pins) and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 20. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to tc and leave the X2 pin open. 28 @ HITACHI

HD404328, HD4074329 Input/Output The MCU has 2 input pins and 33 input/output —The output buffer is tumed on and off by the data Pins, 8 of the input/output pins being large-current —_control register (DCR) during input through an pins (15 mA, max). A program-controlled pull-up —_input/output pin. MOS transistor is provided for each input/output oo. . pin. 1/0 pin circuit types are shown in table 22. Table 22 Circuit Configurations of I/O Pins W/O Pin Type Circuit Applicable Pins Common I/O \\ Pull-up control signal | Do-Dg. Pin (with oO et | ROo-RO3 pull-up mos chy <I] {DCR} Rto-Ri1s ransistor) R20-R2 “<] oe a Output data R3q-R33 ARCO {PDR} R4o-R43 R5o0-R53 [ » Input data Input control: Voc C] Pull-up control signal | SCK Voc fh EH | a | ir au Output data Sox (internal) Output Pin feo -———— Pul-up control signal | SO (with pull-up i wt] BUZZ Mos. transistor) | 4 CT] | @ of | rr aa Output data 56. Byzz InputPin OO iNT | SI © Nh | EVENT es | De | Dio | Input control: AGinutsion? zed put Signal & Zero-crossing | detection circuit | External capacitor Note: For details of the Rt, /SO pin, refer to note 2 of table 23. @HITACHI 29

HD404328, HD4074329 D Ports (Dg-Dj9): Consist of 9 input/output pins mode register (SMR), bits 1 and 0 of port mode and 2 input pins. Ports Do—D7 are large-current I/O _ register A (PMRA), and bit 2 of port mode register ports, Dg is an ordinary input/output port, and Dy C (PMRC), as shown in figure 21. and Djo are input-only ports. These ports are set by SED and SEDD instructions, reset by RED and Pins R2-R5 are multiplexed with SEG1-SEG16. REDD instructions, and tested by TD and TDD The functions of these pins must be specified by the instructions. LCD output register (LOR: $015). The operating modes of ports Dg-Djo are set by Pull-up MOS Transistor Control: A program- bits 2 and 3 of port mode register A (PMRA) and controlled pull-up MOS transistor is provided for bits 0 and 1 of port mode register B (PMRB), as each input/output pin. The on/off status of all these shown in figure 21. The on/off status of the output transistors is controlled by bit 3 of port mode regis- buffer is controlled by D port data control registers ter C (PMRC), and the on/off status of an individual (DCRB, DCRC, and DCRD) that are mapped to transistor can also be controlled by the port data memory addresses. register of the corresponding pin—enabling on/off control of that pin alone. R Ports: Accessed in 4-bit units. Data is input to these ports by LAR and LBR instructions and out- The configuration of the I/O buffer is shown in fig- put from them by LRA and LRB instructions. The ure 22, and the configurations of various program- on/off status of the output buffers of the R ports are controlled I/O circuits are given in table 23. controlled by R port data control registers . . . (DCRO-DCRS) that are mapped to memory How to Deal with Unused I/O Pins: 1/O pins that addresses. are not needed by the user system (floating) must be connected to Vcc to prevent LSI malfunctions Pins R1g-R13 are multiplexed with pins SCK, SI, due to noise. These pins must cither be pulled up to SO, and BUZZ, respectively. The operating modes Vcc by their pull-up MOS transistors or by resis- of these pins are controlled by bit 3 of the serial tors of about 100 kQ. 30 @ HITACHI

HD404328, HD4074329 Serial mode register (SMR): $005 [> tet: ]e | Rio/SCK pin mode selection ae Port mode register A (PMRA): $004 Ri2/SO pin mode selection R1,/SI pin mode selection Dy/INTo pin mode selection Dio/INT; pin mode selection [ PMRA | pot | PMRA | pot | PMRA | | PMRA | Port | Bits | Selection] Bit2 | Selection! Bit1 | | Bito | Selection a Port mode register B (PMRB): $011 } Ds/ZCD/EVENT pin mode selection } Not used Pon | 0 | ZCD (low sensitivity) [1 _|ZCD (high sensitivity)” an EVENT * Becomes low sensitivity in subactive mode. Figure 21 I/O Switching Mode Registers @HITACHI 31

_.. $$ HD404328, HD4074329 Port mode register C (PMRC): $012 } BUZZ output frequency selection Rt13/BUZZ pin mode selection Pull-up MOS transistor on/off selection [ Pmrc | Pull-up MOS | Pmac | | Bits | Owotf Selection! Bit2 | Los fon | azz | LCD output register (LOR): $015 R2/SEG1-SEG4 pin mode selection R3/SEG5-SEG8 pin mode selection R4/SEGS-SEG12 pin mode selection RS5/SEG13-SEG16 pin mode selection | Bits | Selection | Bit 2 | | Bit 1 | Selection | Bito | Selection pof ons [of im [ol wm [ol wm | Li |secis-secie| 1 [secs-secia] 1 [seas-secs| 1 [seai-sece| Figure 21 1/O Switching Mode Registers (cont) 32 @HITACHI

HD404328, HD4074329 Vee O PMRC3 Voc O Pull-up ; MOS. PMOS (A) transistor Ib DCR €3) NMOS (B) x POR Input control BD: Input data Figure 22 I/O Buffer Configuration Table 23 Programmable I/O Circuits PMRC, Bit 3 [') 7 __ 1 DCR O 1 i} 1 PDR 0 1 0 1 0 1 0 1 CMOS PMOS(A) Off Off Off On Off Off Off On Buffer “NMOS (B) Of Of On Of Of Of On off Pull-up MOS Transistor Off Off Off Off Off On Off On Notes: 1. Various /O methods can be selected by different combinations of settings of the above mode registers (PMRC3, DCR, PDR). 2. The PMOS (A) transistor of the Rp /SO pin can be turned off by setting bit 2 of the miscellaneous register (MIS) to 1. Ri, /SO Pin [ ocr | sits | eitz | ens | sito | PMOS (A) DcRo | Ao, FO [of on | bert | Rts Ato 3. The relationships between DCRs and pins| DCR3_ | R33 | R32 | _R3, Ro are as shown on the right. DCR4 Réy | Rap | Ray Ray DCR5 | A5s_| R52 | RS: R5o pera | | be | or | De ocrD | — oT = Ds @ HITACHI 33

HD404328, HD4074329 Timers The MCU has two prescalers (S and W) and three Timer A: Eight-bit timer that can be used as a timer/counters (A, B, and C), clock time-base (figure 23). It is initialized to $00 . . and incremented at each input clock. If an input Prescaler S: Eleven-bit counter that inputs a sys- clock is applied to timer A after it has reached $FF, tem clock signal. After being initialized to $000 _an overflow that sets the timer A interrupt request by MCU reset, prescaler S divides the system flag (IFTA: $001, 2) is generated, and timer A clock. Prescaler S keeps counting, except in watch _restarts from $00. and stop modes, and at MCU reset. Of the prescaler S outputs, timer A input clock, timer B Timer A is used to generate regular interrupts input clock, timer C input clock, and serial inter- | (every 256 clocks) for measuring times between face transmit clock are selected by timer mode reg- _ events. It can also be used as a clock time-base ister A (TMA), timer mode register B (TMB), when bit 3 of timer mode register A (TMA) is set timer mode register C (TMC), and the serial mode to 1. The timer is driven by the 32-kHz oscillator register (SMR). clock frequency divided by prescaler W, and the clock input to timer A is controlled by TMA. In Prescaler W: Five-bit counter that inputs the X1 this case, prescaler W and timer A can be initial- input clock signal divided by eight. Prescaler W _ ized to $00 by software. output can be selected as a timer A input clock by timer mode register A (TMA). (tube) Prescaler W (5 bits) wvaaed 7 |; Ny +t] 0} O Timer A MPX2 32-kHz crystal . = Timer mode register A K Timer/counter A IFTA (TMA, 4 bits) TN (TCA, 8 bits) Timer A's On: TMAS = 0 interrupt request oy] 8) S18) ou} | 0] OB] S] i] FS +] ot) a] ete] et ele System | (to) i clock Prescaler S (11 bits) Figure 23 Block Diagram of Timer A 34 @ HITACHI

—.. SS HD404328, HD4074329 EEE TEE Timer B (TCBL and TLRL: $00A, TCBU and The auto-reload function and prescaler division TLRU: $00B): Eight-bit write-only timer load _ ratio of timer C depend on the state of timer mode register (TLRL and TLRU) and read-only register C (TMC). Timer C is initialized to the timer/counter (TCBL and TCBU) located at the _ value set in TMC by software, then is incremented same addresses. The eight-bit configuration con- _ by one at each clock input. If an input is applied to sists of lower and upper digits located at sequential _timer C after it has reached SFF, an overflow is addresses. A block diagram of timer B (and timer _ generated. In this case, if the auto-reload function C) is shown in figure 24, is enabled, timer C is initialized to its initial value; if auto-reload is disabled, the timer is initialized to The timer/counter is initialized by writing to timer $00, The overflow sets the timer C interrupt load register B (TLR). In this case, the lower nib- request flag (IFTC: $002, 2). ble must be written to first. The contents of TLR are loaded into the timer/counter at the same time Timer C also functions as a watchdog timer. If a the upper nibble is written to, initializing the program routine runs out of control and an over- timer/counter. TLR is initialized to $00 by MCU __flow is generated while the watchdog on (WDON) reset. flag is set, the MCU is reset. This error can be detected by having the program contro! timer C The count of timer B is obtained by reading the reset before timer C reaches $FF. timer/counter. In this case, the upper digit must be read first; the count is latched when the upper nib- © The WDON can only have 1 written to it; it is ble is read. cleared to 0 only by MCU reset. An auto-reload function, input clock source, and Timer Mode Register A (TMA: $008): Four-bit prescaler division ratio of timer B depend on the —_write-only register that controls timer A as shown - state of timer mode register B (TMB). When an in table 24. external event input is used as the input clock source of TMB, the Ds/ZCD/EVENT pin must be Timer Mode Register B (TMB: $009): Four-bit set to function as the ZCD or EVENT pin by _write-only register that selects the auto-reload setting port mode register B (PMRB: $011). function, input clock source, and the prescaler divi- sion ratio as shown in table 25. It is initialized to Timer B is initialized to the value set in TMB by $0 by MCU reset. software, and is then incremented by one by each clock input. If an input is applied to timer B after Writing to this register is valid from the second it has reached $FF, an overflow is generated. In __ instruction execution cycle. Timer B initialization this case, if the auto-reload function is enabled, set by writing to TMB must be done after a mode timer B is initialized to its initial value; if auto- change becomes valid. reload is disabled, the timer is initialized to $00. . . . The overflow sets the timer B interrupt request flag Timer Mode Register C (TMC: $00D): Four-bit (IFTB: $002, 0). write-only register that selects the auto-reload function and prescaler division ratio as shown in Timer C (TCCL and TCRL: $00E, TCCU and _ table 26. It is initialized to $0 by MCU reset. TCRU: $00F): Eight-bit write-only timer load we . an . register (TCRL and TCRU) and read-only Writing to this register is valid from the second timer/counter (TCCL and TCCU) located at the instruction execution cycle. Timer C initialization same addresses. The eight-bit configuration Set by writing to TMC must be done after a mode consists of lower and upper digits located at Change becomes valid. sequential addresses. The operation of timer C is basically the same as that of timer B. @ HITACHI 35

———— SSeS HD404328, HD4074329 y 4 Timer mode register B (TMB, 4 bits) Timer latch register B (TLB, 4 bits) ——_ Timer/counter B EVENTI Timer B MPX (TCB, 8 bits) (Refer to L, S 4 Timer B's figure 37.) interrupt Timer load register B request (TLR, 8 bits) flag algig| ‘ , oe] 0] 8] S| io & 4 +128 | | Pure _ ape Le + Sa stem Prescaler S (11 bits) clock

4 Timer C's

gs) 8) 2 Timer latch register C| request al +] 0) 8] SF] ] =) & (TLC, 4 bits) flag IFTC MPX| Timer/counter C ° 1 Ti bed haved imer load register Wate reset Timer mode register © (TCR, 8 bits) (Watchdog) (TMC, 4 bits) Internal bus line (S2) $020, 1 (Set only) Figure 24 Block Diagram of Timers B and C 36 @ HITACHI

HD404328, HD4074329 Table 24 Timer Mode Register A TMA Bits Bit2 Bit1 Bito Source Prescaler, Input Clock Period, Operating Mode 0 0 0 0 PSS,2048ty, ‘TimerAmode

1 PSS, 1024 toe

1 0 PSS, 512 teye

1 PSS, 128 teye

1 0 ) PSS, 32 teye

1 PSS, 8 teye

1 0 PSS, 4 teye

1 PSS”

1 PSW, 16 tsuBoye

1 0 PSW, 8 tgupeye “1 PSW2tguye 1 0 0) PSW, 122 tuBcyc

1 Do not use

~ “T0 ~-PSW,TCArestt S~™S Notes: 1. tguBeyc = 244.14 us (when 32.768-kHz crystal oscillator is used) 2. teyc = 1.9074 1s (when 4.1943-MHz crystal oscillator is used) 3. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 4. If PSW or TCA reset is selected while the LCD is operating, LCD operation halts (power switch goes off and all SEG and COM pins are grounded). When an LCD is connected for display, the PSW and TCA reset periods must be set in the pro- gram to the minimum. @ HITACHI 37

HD404328, HD4074329 Pulse Output The MCU has a built-in pulse output function © C (PMRC: $012), as shown in table 27. The duty called BUZZ. The pulse frequency can be selected —_cycle of the pulse output is fixed at 50%. When from the prescaler S's outputs, and the output fre- the pulse output function is used, the R13/BUZZ quency depends on the state of port mode register pin must be specified as BUZZ by PMRC. a Serial Interface The MCU has a clock-synchronous serial interface as shown in figure 25. The Rlo/SCK pin and the which transmits and receives 8-bit data. transmit clock are controlled by writing data to the SMR. The transmit clock shifts the contents of the The serial interface consists of a serial data register §R, which can be read and written to by software, (SR), serial mode register (SMR), port mode _ pefore transmission starts between two MCUs. register A (PMRA), octal counter, and multiplexers, a Table 25 Timer Mode Register B Table 26 Timer Mode Register C TMB TMC Bit3 Auto Reload Function Bit3 Auto Reload Function to) Disabled 0 Disabled

1 Enabled 1 Enabled

_TMB __ Input Clock Period/ _TMC_ Bit2 Bit Bito Input Clock Source Bit2 Bit1 BitO —_ Input Clock Period 0 0 0 2048 teye 0 0 0 2048 eye 1 512 teye 1 1024 teye 1 0 128 teyc 1 0 512 teye 1 32 teye 1 128 teyo 1 0 0 Btoye 1 0 ) 32 teye

1 A teye 1 8 teye

1 ZCD/EVENT (external 1 2 tye

event input) OF Table 27 Port Mode Register C PMRC Bit1 _BitQ _ Prescaler Division Ratio 0 0 + 1024 1 +512 1 0 + 256 1 +128 38 @HITACHI

HD404328, HD4074329 $eeeeSSFFSFFFSFFSSEEEE RO) Eee The serial interface is activated by the STS instruc- A write signal input to the serial mode register dis- tion. The octal counter is reset to 000 by this continues the input of the transmit clock to the instruction, it starts counting at the falling edge of serial data register and octal counter. Therefore, if the transmit clock (SCK), and it increments at the —_a write is performed during data transmission, the rising edge of the clock. A serial interrupt request _ octal counter is reset to 000 to stop transmission, flag is set when the eighth transmit clock signal is and, at the same time, the serial interrupt request input (the serial interface is reset) or when serial _ flag is set. transmission is discontinued (the octal counter is reset). Write operations are valid from the second instruc- tion execution cycle, so the STS instruction must Serial Mode Register (SMR: $005): Four-bit be executed after at least two cycles have been write-only register that controls the Rlg/SCK pin, executed. The serial mode register is initialized to transmit clock, and prescaler division ratio as_ $0 by MCU reset. shown in figure 26. Writing to this register initial- izes the serial interface. System Octal counter | SROF clock Prescaler (11 bits) (OC, 3 bits) IFS elses sana wl isl S interface's n O| =) 5] & interrupt * +) F] tl + request flag Serial MPX Internal bus line (S1) my va 7 SCK Serial data register (SR, 8 bits) register register A (SMR, 4 bits) (PMRA, 4 bits) internal bus line (S2) Internal bus line (S2) Miscellaneous register (MIS, 4 bits) | ressox ee al | Prior | to Ea port SCK sl so Figure 25 Block Diagram of Serial Interface @ HITACHI 39

HD404328, HD4074329 Serial Data Register (SRL: $006, SRU: $007): modes are provided for the serial interface; transi- Eight-bit read/write register separated into upper _ tions between them are shown in figure 28. and lower digits located at sequential addresses. . oo. Data in this register is output from the SO pin, In STS wait state, the serial interface is initialized LSB first, in synchronism with the falling edge of and the transmit clock is ignored. If the STS the transmit clock; and data is input, LSB first, instruction is then executed, the serial interface through the SI pin at the rising edge of the transmit —_ enters transmit clock wait state. In transmit clock wait state, input of the transmit Data cannot be read or written during serial data Clock increments the octal clock, shifts the serial transmission. If a read/write occurs during trans- Clock register, and activates serial transmission. mission, the accuracy of the resultant data cannot However, note that if clock output mode is be guaranteed. selected, the transmit clock is continuously output but data is not transmitted. Selecting and Changing Operating Mode: Table . so . . 28 lists the serial interface's operating modes. To During transmission, the input of eight clocks or select an operating mode, use one of these combi- the execution of the STS instruction sets the octal nations of PMR and SMR settings; to change the Counter to 000, and the serial interface enters trans- operating mode, always initialize the serial inter- _ mit clock wait state. If the state changes from face internally by writing data to the SMR. transmit to another state, the serial interrupt request flag is set by the octal counter reaching Serial Interface Operation: Three operating 000. Serial mode register (SMR): $005 BonG —— —— Riy/SCK Pin r Jock select | o | Rio port input pin ransmit clock selection —7 . SCK input or output pin R10/SCK pin mode selection = p pe [swe iSCK Pi Prescaler Division Transmit Clock [pi 2 [en [eno] Rip/SCKPin | Clock Source! patio | Period | © | Sckouput | Proscater | +128 | 258tye | SCK output +32 64 toye [0 | ScKoutput_| Prescaler | 1 | ScKoutput_| Proscaier [i [scKinour [ewernatcick] — Note: teye = 1.9074 us (with 4.1943-MHz crystal oscillator used at 1/8 division ratio) Figure 26 Serial Mode Register 40 @HITACHI

HD404328, HD4074329 CSE Oe ET In this state, if the internal clock has been selected, _ figure 29. the transmit clock is output in answer to the execution of the STS instruction, but serial trans- If more than eight transmit clocks are input in mission is inhibited after the eighth clock is output. _ transmit clock wait state, the serial interface's state changes to transmission, uansmit clock wait, then If port mode register A (PMRA) is written to in _ back to transmission. transmit clock wait state or during transmission, . the serial mode register (SMR) must be written to, __ If the serial interface is set to STS wait state by to initialize the serial interface. The serial inter- writing data to the SMR after the serial interrupt face then enters STS wait state. request flag has been reset, the flag is set again. If the serial interface shifts from transmission state Note on Use: The serial interrupt request flag to another state, the octal counter returns to 000, —_— Might not be set if the status is changed from trans- setting the serial interrupt request flag. fer by the execution of an SMR write or STS . instruction during the first period that the transmit Transmit Clock Error Detection: The serial clock is low. To prevent this, program a check that interface will malfunction if a spurious pulse the SCK pin is at 1 (by executing an input instruc- caused by external noise conflicts with a normal tion for the R1 port) before the execution of an transmit clock during transmission. A transmit SMR write or STS instruction, to ensure that the clock error of this type can be detected as shown in serial interrupt request flag is set. ———SSSFSSSSSSSSSSSSsssSsssSSee Transmit clock | | | | 1 2 3 4 5 6 7 8 y ae eT TT TTL ih i A i i i i i Serial input data latch timing Figure 27 Timing of Serial Interface Output Table 28 Serial Interface Operating Modes SMR PMRA Bit3 Bit1 BitO Operating Mode 1 i+) i) Continuous clock output mode

1 Transmit mode

1 i) Receive mode

1 Transmit/receive mode

@ HITACHI 41

7 HD404328, HD4074329

The MCU has a built-in A/D converter that usesa Note: Use the SEM and SEMD instructions to sequential comparison method with a resistor lad- write data to the ADSF, but make sure that der. It can measure four analog inputs with an the ADSF is not written to during A/D cight-bit resolution. As shown in the block dia- conversion. gram of figure 30, the A/D converter has a four-bit . A/D mode register, a one-bit A/D start flag, anda A/D Data Register (ADRL: $017, ADRU: four-bit plus four-bit A/D data register. $018): Eight-bit read-only register that is not cleared by a reset. Note that data read from this A/D Mode Registcr (AMR: $016): Four-bit register during A/D conversion cannot be guaran- write-only register which selects the A/D conver- teed. After the completion of A/D conversion, the sion period and indicates analog input pin informa- _resultant eight-bit data is held in this register, as tion. Bit 0 of the AMR selects the A/D conversion shown in figure 32, until the start of the next period, and bits 2 and 3 select a channel, as shown —_—conversion. in figure 31. Note on Use: The contents of the A/D data regis- A/D Start Flag (ADSF: $020, 2): One-bit flag ter are not guaranteed during A/D conversion. To that initiates A/D conversion when 1 is written to ensure that the A/D converter operates stably, do it. At the completion of A/D conversion, the con- not execute port output instructions during A/D verted data is stored in the A/D data register and conversion. the ADSF is cleared. Refer to figure 31. Internal bus line (S2) Internal bus line (S1) A/D mode register AD start flag (DAL son (AMR: $016) 2 7 ’ ( $016) (ADSF: $020) ADRU: $018) 2 1 ANo O IFAD AN: O MPx AN2 O ANs O Comparator AVss O Figure 30 Block Diagram of A/D Converter @ HITACHI 43

a] ee HD404328, HD4074329 7] ES err Or Liquid-Crystal Display (LCD) The MCU has an LCD controller and driver which Four duty cycles and the LCD clock are program- drive four common signal pins and 24 segment _ controllable, and a built-in dual-port RAM ensures pins. The controller consists of a RAM area in that display data can be automatically transmitted which display data is stored, a display control reg- to the segment signal pins without program ister (LCR), and a duty cycle/clock control register intervention. If a 32-kHz oscillation clock is (LMR), as shown in figures 33 and 34. selected as the LCD clock source, the LCD can be used even in watch mode, in which the system clock stops. eS ’ Power switch . f

9 COM2

3 | driver [7 COMB V2 > LCD © COM4 power control LCD clock V3 0 circuit = | LCD output ~ register GND 4 Display on/ott (LOR: $015) 1 2 ? SEG1/R29 | | Display control |g SEG1/R2;

4 Segment’

(LCR: $013) $050 7 F Displays Po Itiot E area | Lop multiplexer 4 segment © SEG16/R53 $067 Duty cycle/LCD| L clock control register cK) 6 SEG24 (LMR: $014)

2 RAM area LCD clock

Clock selection aN clock output ! Divided 32-kHz clock output LCD: Liquid crystal display Figure 33 Block Diagram of Liquid Crystal Display @HITACHI 45

HD404328, HD4074329 LCD Data Area and Segment Data ($050-$067): | LCD Control Register (LCR: $013): Three-bit As shown in figure 35, each bit of the storage area —_write-only register which controls LCD blanking, corresponds to one of four duty cycles. If data is the turning on and off of the liquid-crystal display's written to an area corresponding to a certain duty power supply division resistor, and display in cycle, it is automatically output to the correspond- watch and subactive modes, as shown in table 29. ing segments as display data. LCD control register (LCR): $013 >It te | Z™“ Blank/display Power switch on/off Display on/off in watch mode or subactive mode (Not used) LCD mode register (LMR): $014 Pe ted: fe | _ ; _| Input clock selection LCD output register (LOR): $015 feted: fe] ——-——— R2/SEG1-SEG4 pin mode selection ——— R3/SEG5-SEG8 pin mode selection == R4/SEG9-SEG12 pin mode selection SSS _RS/SEG1 3-SEG 16 pin mode selection — Figure34 LOD Registers 46 @ HITACHI

HD404328, HD4074329 + Blank/display LCD Output Register (LOR: $015): Write-only Blank: Segment signals are turned off, register used to specify that ports R2-RS act as regardless of LCD RAM data setting. pins SEG1-SEG16, as shown in table 32. Display: LCD RAM data is output as segment signals. Large Liquid-Crystal Panel Drive and Vi.cp: To drive a large-capacity LCD, decrease the resis- + Power switch on/off tance of the built-in division resistors by attaching Off: The power switch is off. external resistors in parallel, as shown in figure 36. On: The power switch is on and V; is Voc. The size of these resistors cannot be simply calcu- + Watch/subactive mode display lated from the LCD load capacitance because the Off: In watch and subactive modes, all common matrix configuration of the LCD complicates the and segment pins are grounded and the _ paths of charge/discharge currents flowing through liquid-crystal power switch is turned off. the capacitors—and the resistance will also vary On: In watch and subactive modes, LCD RAM with lighting conditions. This size must be deter- data is output as segment signals. mined by wial-and-error, taking into account the ; power dissipation of the device using the LCD, but LCD Duty Cycle/Clock Control Register (LMR: a resistance of 1 to 10 kQ would usually be suit- $014): Four-bit write-only register which selects able. (Another effective method is to attach capac- the display duty cycle and LCD clock source, as _ tors of 0.1 to 0.3 UF.) shown in table 30. The dependence of frame fre- quency on duty cycle is shown in table 31. Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid-crystal drive voltage (Vi.cp)- Bit3 Bit2 Bit1 Bito Bit 3 Bit 2 Bit1 BitO 80 sei | SEG1 | SEGt | $050 92 [SEG13 | SEG13 |SEG13 | SEG13 | $05C 81 | SEG2 | seG2 | seG2 | SEG2 | $051 93 SEG14 |SEG14 | $05D 82 | SEG3 | SEG3 | SEG3 | SEG3 | $052 94 | SEG15 | SEG15 | SEG15 | SEG15 | $05E 83 $053 95 | SEG16 | SEG16 | SEG16 | SEG16 | $05F 84 | SEGS | SEGS | SEGS | SEGS | $054 96 | SEG17 | SEG17 | SEG17 | SEG17 | $060 85 | SEG6 | SEG6 | SEG6 | SEG6 | $055 97 |SEG18 | SEG18 | SEG18 | SEG18 | $061 86 | SEG7 SEG7 |$056 98 |SEG19|SEG19 | SEG19|SEGT9 | 062 87 | SEG8 | SEG8 | SEG8 | SEGS | $057 99 | SEG20 | SEG20 | SEG20 | SEG20 | $063 88 | SEG9 | SEG9 | SEG9 | SEG9 | $058 100 | SEG21 | SEG21 | SEG21 | SEG21 | $064 89 | SEG10 | SEG10 | SEG10 | SEG10 | $059 101 | SEG22 | SEG22 | SEG22 | SEG22 | $065

90 SEG SEG11|$05A 102 | SEG23 | SEG23 | SEG23 | SEG23 | $066

91 |SeG12|SEG12|SEG12|SEG12|$05B 103 | SEG24 | SEG24 SEG24 | $067 COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 “Figure 35. Configuration of LCD RAM Area (for dual-port RAM) @ HITACHI 47

HD404328, HD4074329 Table 29 LCD Control Register LCR Display in Watch Mode CR Power Switch SCR Bit2 or Subactive Mode Bit1 On/Oft Bito Blank/Display

0 Off 0 Off 0 Blank

1 On 1 On 1 Display

Note: When using an LCD in watch mode or subactive mode, use the divided output of a 32-kHz oscillator as the LCD clock and set bit 2 of the LCR to 1. if using the divided output of the system clock as the LCD clock, always set bit 2 of the LCR to 0. Table 30 LCD Duty Cycle/Clock Control Register LMR Bit3 BR2 Bit1 Bito Duty Setection/Input Clock Selection a - 0 t) 1/4 duty cycle 1 1/8 duty cycle

1 O 1/2 duty cycle

1 Static

bY) 0 _- - CLO (32.768/64 kHz when using 32.768-kHz oscillator)

1 CLI (leyc/258)

1 O cL2 Mey 2048)

a CLS (refer to table 31) Note: foye is the divided system clock output. 48 @ HITACHI

HD404328, HD4074329 Table 31 LCD Frame Periods for Different Duty Cycles Static Duty Cycle LMR ‘BRS Bit2 Bits Bit2 BS B2 BRS BR2 0 0 O 1 1 0 1 1 Instruction Cycle Time cLo cli cL2 CL3Note 2us 512 Hz 1953 Hz 244 Hz 122 H2z/64 Hz 1/2 Duty Cycle LMR Bits Bit2 Bit3 Bit2 Bits Bit2 Bits Bit2 0 0 0 1 1 0 1 1 Instruction Cycle Time cLo Cli cL2 CL3Note 2us 256 Hz 976.5 Hz 122 Hz 61 Hz/32 Hz 1/3 Duty Cycle LMR ~ Bit3 Bit2 Bit3 Bit2 Bits Bit2 Bit3 Bit2 0 0 0 1 1 0 1 1 Instruction Cycle Time cLo cli cL2 CL3Note 2us 170.6 Hz 651 Hz 81.3 Hz 40.6 Hz/21.3 Hz 1/4 Duty Cycle LMR Bits Bit2 Bits Bit2 Bits Bit2 Bis Bit2 0 0 0 1 1 oO 1 1 Instruction Cycle Time CLO cli CL2 CLgNote 2us 128 Hz 488.2 Hz 61 Hz 30.5 Hz/16 Hz Note: The division ratio depends on the value of bit 3 of timer mode register A (TMA): the first value is for TMAS = 0 and the second is for TMA3 = 1. When TMAS = 0, CL3 = f,y,/4096. When TMAS = 1, CL3 = 32.768 kHz/512. Table 32 LCD Output Register Lon Lon Lon, ton, Bit3 Port Selection Bit2 Port Selection Bit1 Port Selection BitO Port Selection O RS i) R4 oO R3 0 R2

1 SEG16-SEG13__ 1 SEG12-SEG9 1 SEG8-SEGS 1 SEG4-SEG1

@ HITACHI 49

HD404328, HD4074329 rm | Vee (V1) En | Vee (V1) V2 V2 aA | or aR | ele ca cx GND GND 1 — Veo com1 Vy Hy 3-digit LCD Vee Ly, Li. Vico SEG1 GND SEG24 Static drive com |_2 = Veco Vv com2 L/ 6-digit LCD ' Ll Veo V2 —— Vico [| Ve SEG1 to GND SEG24 1/2 duty cycle, 1/2 bias drive 3 — Voc V1 H 8-digit LCD Veco V2 —— Vico SEG1 V3 to GND SEG24 1/3 duty cycle, 1/3 bias drive com |_4 om vee to L/ 12-digit LCD Vi Ig! COM4 L]/ Veco V2 —_ Vico SEG! V3 to GND SEG24 7 Veo Vico 2 GND 1/4 duty cycle, 1/3 bias drive Figure 36 LCD Connection Examples 50 @ HITACHI

. HD404328, HD4074329 Zero-Crossing Detection Circuit The MCU has a zero-crossing detection circuit that _ setting the input clock source of timer mode regis- generates a digital signal in synchronism with an _ ter B (TMB: $009) for external event input. AC signal input to the ZCD pin through an exter- . nal capacitor. A block diagram of the zero-cross- Note: After MCU reset, the Dg/ZCD/EVENT pin ing detection circuit is shown in figure 37. is set to ZCD. With this setting, a supply current (bias current) always flows because The zero-crossing detection circuit has two modes a bias circuit within the zero-crossing circuit (low sensitivity mode and high sensitivity mode) is still operating. This current flows in all which are set by port mode register B (PMRB: MCU operation modes, but it is particularly $011) as shown in table 33. critical in stop mode because the MCU is more affected by bias current since the other A digital signal generated by the zero-crossing circuits of the LSI are not dissipating much detection circuit sets the zero-crossing interrupt current. If the zero-crossing detection func- request flag (IFZC). The interrupt edge is selected tion is not being used, use port mode regis- by the interrupt mode register (IMR: $010). This ter B to set this pin to Dg or EVENT. This signal can be made the input clock of timer B by prevents the bias current from flowing. Dg port input EVENTI De/ZCDy (Refer to AC input EVENT pin figure 24.) signal | Zero-crossing ‘s} MPX detection circuit \\F2c External capacitor 2 2 Port mode register B Interrupt mode register Figure 37 Block Diagram of Zero-Crossing Detection Circuit Table 33 Port Mode Register B PMRB 1 0 Port Selection °O 0 ZCD (low sensitivity mode)

1 ZCD (high sensitivity mode)”

1 EVENT

• Becomes low sensitivity in subactive mode. @ HITACHI 51

HD404328, HD4074329 Table 34 Registers in Special Register Area Name Address RW Bit Description PMRA $004 Ww 0 R1/SO pin mode selection

1 R1,/SI pin mode selection

2 Do/INTo pin mode selection

3 D,o/INT, pin mode selection

SMR $005 WwW 2-0 Serial transfer clock speed selection

3 Rt9/SCK pin mode selection

SRL $006 RW 3-0 SCI data register, lower 4 bits SRU $007 RW 3-0 SCI data register, upper 4 bits TMA $008 Ww 2-0 Input clock selection (timer A)

3 Timer Atime-base mode selection

TMB $009 Ww 2-0 Input clock selection (timer B)

3 Auto reload function selection

TCBL/TLRL $00A RW 3-0 Timer counterfimer load register (timer B), lower 4 bits TCBU/TLRU $00B RW 3-0 Timer counterfimer load register (timer B), upper 4 bits MIS $00C Ww 1,0 Interrupt frame period selection

2 R12/SO PMOS off

3 Changeover to setting by system oscillator frequency

TMC $00D WwW 2-0 Input clock selection (timer C) TCCL/TCRL $00E RW 3-0 Timer counterfimer load register (timer C), lower 4 bits TCCU/TCRU $00F RW 3-0 Timer counterfimer load register (timer C), upper 4 bits IMR $010 Ww 1,0 INT, detection edge selection 3,2 Zero-crossing detection edge selection PMRB $011 WwW 1,0 Dg/ZCD/EVENT pin mode selection 3,2 Do not use PMRC $012 w 1,0 Buzzer frequency selection

2 R1,/ BUZZ pin mode selection

3 Pull-up MOS transistor on/off selection

LCR $013 Ww ) LCD display selection

1 LCD power switch on/off selection

2 LCD display selection during watch mode

3 Do not use

LMR $014 Ww 1,0 LCD duty cycle selection 3,2 LCD input clock selection 52 @ HITACHI

HD404328, HD4074329 Table 34 Registers in Special Register Area (cont) Name Address R/W Bit Description LOR $015 Ww Ly R2/SEG1-SEG4 pin mode selection

1 R3/SEG5-SEG8 pin mode selection

2 R4/SEG9-SEG12 pin mode selection

3 R5/SEG13-SEG16 pin mode selection

AMR $016 w ) Conversion timing selection (A/D)

1 Dontuse

3,2 Analog input selection (A/D) ADRL $017 R 30 A/D data register, lower 4 bits ADRU $018 R 30 A/D data register, upper 4 bits DCRO $030 Ww 3-0 Data control register for port RO DCR1 $031 Ww 3-0 Data control register for port R1 DCR2 $032 Ww 3-0 Data contro} register for port R2 DCR3 $033 Ww 3-0 Data control register for port R3 DCR4 $034 Ww 3-0 Data control register for port R4 DCRS $035 Ww wn Data contro! register for port RS DCRB $03B w 3-0 Data control register for port Dp-D3 DCRC $03C Ww 3-0 Data control register for port D4-D7 DCRD $03D Ww 0 Data control register for port Dg

31 Do not use

@HITACHI 53

HD404328, HD4074329 PROM Mode Description Programming the Built-in ROM Since an HMCS400-series instruction is ten bits long, the HMCS$400-series MCU has a built-in The MCU's built-in ROM is programmed in conversion circuit to enable use of a general- PROM mode in which the pins are arranged as purpose PROM programmer. This circuit splits shown in figure 38. PROM mode is set by pulling each instruction into a lower five bits and an upper TEST, Mo, and M, low and RESET high as shown _ five bits that are read from or written to consecu- in figure 39. In PROM mode, the MCU does not _ tive addresses. This means that if, for example, 16 operate, but it can be programmed in the same way —_kwords of built-in PROM are to be programmed as any other commercial 27256-type EPROM by a general-purpose PROM programmer, a 32- using a standard PROM programmer and a 64-to- byte address space ($0000-$7FFF) must be 28-pin socket adapter. Recommended PROM specified. programmers and socket adapters are listed in table 35. C10 64 {Vcc Cle 63{-] — Cis 62{_] Mo M1 Voc Vee. Vee [=] 4 61] DOONAN Mo C15 60h] 64 63 62 61 60 59 58 57 56 55 54 53 52 um, Cle sof] Vec 1 si) Vee C47 58h] Vee [] 2 50[7] Vee J 8 57[_] no CIs af] eno E19 s6{o] Test4 48) est C1 10 55{—) Vec C15 47) Vee [J 11 s4f] Cié et E412 sat] Reset (]7 45{] Reset C] 13 s2{_] GND = “eS _ 43[] OE GND - 4 3 5 np (] 10 HD4074329F 42|] CE ano C]16 HD40743298 49 [] OE ati aT] Ag A, C17 H04074329¢ ag] cE Aa] 12 40|_ As Ae LJ 18 47a Aol 13 sof] Ae Ao C119 46, Aa Aw C414 38[] Ay Aw C120 45{o) Ad An C15 37[_] 07 Ay Chat 44 Ay An Ci 16 36|-] Os Ar C]22 43[5J 07 an C17 35/1 Os Avy L123 42(-] 06 Au C18 34[] O4 Aw te autos 50.21 20 23 24 25.26 27 28 29.90.31 39°[ as C126 solo, OUUUOUUUUOUU Ve Clr alos AaVppAs Ag 040302010 0Vec0001 O2 As CL] 28 37(_Jo, As L290 36{] Oo Note: Externally connect pins of the same name. This is not 04 20 35 |] Vee necessary if one of the sockets listed in table 36 is used. 03) 31 34[] Oo O2C] 32 s3[_ Jor Figure 38 Pin Arrangement in PROM Mode 54 @ HITACHI

HD404328, HD4074329 Voc oo Vee RESET tle 0 My, | Data to ie Kon, Vpp A ° KT Address Vee N Ao-Ara Ais OE cE GND Figure 39 PROM Mode Connections Table 35 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Model name Package Manufacturer Model Name DATA V/O Corp. 29B DP-64S Hitachi TBD DC-64S FP-64B Hitachi TBD AVAL Data Corp. PKW-1000 DP-64S Hitachi TBD DC-64S TBD FP-64B Hitachi TBD Table 36 PROM Moée Selection Pin Mode CE OE Vpp Qp-07 Programming Low High Vpp Data input Verification High Low Vpp Data output Programming inhibited High High Vpp High impedance @ HITACHI 55

HD404328, HD4074329 Warnings 3. PROM programmers have two voltages (Vpp): 12.5 V and 21 V. Remember that ZTAT 1. Always specify addresses $0000 to $7FFF devices require a Vpp of 12.5 V—the 21-V set- when programming with a PROM programmer. ting will damage them. 12.5 V is the Intel If address $8000 or higher is accessed, the 27256 setting. PROM may not be programmed or verified cor- rectly. Set all data in unused addresses to $FF. Programming and Verification: The built-in PROM of the MCU can be programmed at high Note that the plastic-package version cannot be speed without risk of voltage stress or damage to erased and reprogrammed, but the ceramic win- data reliability. dow-package version can be reprogrammed after being exposed to ultraviolet light. Programming and verification modes are selected as shown in table 36, the memory map in PROM 2. Make sure that the PROM programmer, socket mode is shown in figure 40, the programming adapter, and LSI are aligned correctly (their pin flowchart is shown in figure 41, and a timing chart 1 positions match), otherwise overcurrents may —_ of PROM programming and verification is shown damage the LSI. Before starting programming, _ jn figure 42. make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly For details of PROM programming, refer to the fixed in the programmer. Notes on PROM Programming section. soooo [T]T 11, 1, 1 Bit 4,Bit 3,Bit 2,Bit 1,Bit o] Lower 5 bits MPL instruction $0000 sooot [TTT 11. 1, 1 :Bit 9. 8,Bit 7,Bi 6.8 5] Upper 5 bits f °° $0001 Kies eo a Soon 0 (ump to INT routine)" } $0003 (64 words) (ump to INT; routine) _| $0005 $007F $003F JMPL instruction $0006 = 0 | vert san Pattern jump to TIMER-B routine) _| $0009 SIFFF SOFFF' jump to TIMER-C routine)_| $0008 “ ia Rare jump to ZCD routine) $0000 Program JMPL instruction $000E (16384 words) Huan $000F $7FFF . $3FFF Upper 3 bits are not to be used (fill them with 111). Figure 40 Memory Map in PROM Mode 56 @ HITACHI

HD404328, HD4074329 Erasure (Window Package) 2-3 cm away from an ultraviolet lamp with a rat- ing of 12,000 4.W/cm? for about 20 minutes. After Data in the PROM is erased by exposing the LSI to erasure, all PROM bits are set to 1. ultraviolet light of a wavelength of 2537 A for an integrated dose of at least 15 W.s/cm2. These con- For details of packages with windows, refer to the ditions can be satisfied by placing the LSI about —_ Notes on Window Packages section. Start Set programming/verification mode Vpp = 12.54 0.3 V, Voc = 6.0 + 0.25 V Address = 0 n=0 Ne Ye es n= 25? Program tpy = 1 ms +t 5% No sei | — Address + 1 > address Yes <C> Yes Set read mode | Voc = 5.00.5 V, Vpp = Veg 0.6 V No—“ All addresses read? Yes Fail Cena) Figure 41 Flowchart of High-Speed Programming @ HITACHI 57

HD404328, HD4074329 Programming Electrical Characteristics DC Characteristics during Programming/ Verification (Vcc = 6.0 V + 0.25 V, Vpp = 12.5 V 0.3 V, Vgg = 0.0 V, Ta = 25°C + 5°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Conditions Input high Vin Qg-On, Ag Ara, 2.2 = Vec+03 V voltage OE, CE Input low Viv Qo-O7, Ap Aig, 0.3 _ 0.8 Vv voltage OE, CE Output high Von Qp-O7 24 - = Vv Toy = -200 pA voltage Output low Vou Q-O7 - — 04 v lo, = 1.6 mA voltage Input leakage ly | Op-O7, Ao -Ara, — — 2 HA Vin = 5.25 V/O.5V OE, CE Voc current loc _ - 30 mA Vpp current Ipp — — 40 mA Input pulse level: 0.8 V to 2.2V Input rise/fall time: < 20 ns Input timing reference levels: 1 V, 2 V Output timing reference levels: 0.8 V, 2 V Programming ' Verification OO Vee + Vee tves. Vv Veo We GND tyes. ne oe LLtoew, | Figure 42 PROM Programming/Verification Timing 58 @ HITACHI

HD404328, HD4074329 AC Characteristics during Programming/Verification (Vcc = 6.0 V + 0.25 V, Vpp = 12.5 V0.3 V, Ta = 25°C + 5°C, unless otherwise specified) Item Symbol Min Typ Max Unit Test Conditions Address setup time tas 2 - - us OE setup time toes 2 _- - ys Data setup time tos 2 - ad us Address hold time tay 0 = — bs Data hold time tou 2 _ _- BS Data output disable time tppNote - 130 ns Vpp setup time tyes 2 - - ps Program pulse width tpw 0.95 1.0 1.05 ms CE pulse width during overprogram —topw 2.85 =- 78.75 ms Voc setup time tves 2 _ - us Data output delay time toe 0 = 500 ns ‘Note: tp¢ is defined at the point where the output level can no longer be referenced after output is released. DC Characteristics during Read (Vcc = 5.0 V + 10%, Vpp = Voc + 0.6 V, Ta= 25°C + 5°C, unless otherwise specified) Item Symbol Min Typ Max Unit Test Conditions Input leakage current lu fd - 1 pA Voc = 5.5 V, Vin = GND to Voc Output leakage current lo - -—- 1 HA Voc = 5.5 V, Vout = GND to Veg Program pin current lbp —- 1 100 HA Vpp = Voc + 0.6 V Power current in operation IgcNole = — _ 30 mA — t=1MHz, loy=OmA Input voltage Vi -03 — 0.8 Vv Vid 22 — Voco+03 V Output voltage Vou _- _ 0.4 Vv Io, = 1.6 mA Vou 24. — Vv lon = -200 pA Note: Excluding input through current. AC Characteristics during Read (Vcc = 5.0 V + 10%, Vpp = Voc + 0.6 V, Ta = 25°C + 5°C, unless otherwise specified) Item Symbol Min Max Unit Test Conditions Access time tace = 500 ns CE = OF = Vi. CE output delay time toe = 500 ns OE = Vy. ‘OE output delay time toe 10. —«*150 ns CE = Vy. Output disable delay time topNote 0 105 ns CE = Vi Data output hold time tou i} _- ns CE =OE = Viv Note: tpg is defined at the point where the output level can no longer be referenced after output is released. @ HITACHI 59

Figure 43. PROM Read Timing

HD404328, HD4074329 Notes on PROM Programming PROM Programming: EPROM memory cells must be programmed under specific voltage and Principles of Programming/Erasure: A memory timing conditions. The higher the programming cell in a ZTAT microcomputer is the same as an —_yoltage Vpp and the longer the programming pulse EPROM cell: it is programmed by applying a high _,,,, is applied, the more electrons are injected into voltage between its control gate and drain to inject the floating gates. However, if Vpp exceeds speci- hot electrons into its floating gate. These electrons fications, the p-n junctions may be permanently are stable, surrounded by an energy barrier formed damaged. Pay particular attention to overshooting by an SiO; film. The change in threshold voltage —_ in the PROM programmer. In addition, note that of a memory cell with a charged floating gate negative voltage noise will produce a parasitic makes the corresponding bit appear as 0; a cell transistor effect that may reduce breakdown whose floating gate is not charged appears as a 1 voltages. bit (figure 44), The ZTAT microcomputer is electrically connected The charge in a memory cell may decrease with to the PROM programmer by a socket adapter. time. This decrease is usually due to one of the Therefore, note the following points: following causes: + Check that the socket adapter is firmly mounted * Ultraviolet light excites electrons, allowing them on the PROM programmer. to escape. This effect is the basis of the erasure — « Do not touch the socket adapter or the LSI dur- principle. ing the programming. Touching them may affect + Heat excites trapped electrons, allowing them to the quality of the contacts, which will cause pro- escape. gramming errors. + High voltages between control gate and drain may erase electrons. PROM Reliability after Programming: In gen- eral, semiconductor devices retain their reliability, If the oxide film covering a floating gate is defec- provided that some initial defects can be excluded. tive, the electron erasure rate will be greater. How- These initial defects can be detected and rejected ever, electron erasure does not often occur because by screening. Baking devices under high-tempera- defective devices are detected and removed at the ture conditions is one method of screening that can testing stage. rapidly eliminate data-hold defects in memory cells. (Refer to the Principles of Programming/ Erasure section.) SE Control gate Control gate CK Ca SiOz Floating gate SiO2 Floating gate Se \\ QQOSS2 Lf Source \\ [LN] aa res Write (0) Erasure (1) Figure 44 Cross-Sections through EPROM Cell @HITACHI 61

HD404328, HD4074329 ZTAT microcomputer devices are extremely reli- _ Ultraviolet-Proof Label: If the LSI is exposed to able because they have been subjected to such a _ fluorescent light or sunlight, its memory contents screening method during the wafer fabrication pro- may be erased by the small proportion of ultravio- cess, but Hitachi recommends that each device is _let light present in such sources. In strong light, exposed to 150°C at one atmosphere for at least 48 the MCU may even be damaged by photocurrents hours after it is programmed, to ensure its best per- generated in it. To prevent such problems, Hitachi formance. The recommended screening process is | recommends that an ultraviolet-proof label is shown in figure 45. placed over the erasure window after the PROM is programmed. Notes on Window Packages Special labels containing metal to absorb ultravio- Glass Erasure Window: If the glass window let light are sold for this purpose. When choosing comes into contact with plastic or something carry- —_Jabels, bear the following characteristics in mind: ing a static charge, electrostatic charge on the win- dow may make the LSI malfunction. If this + Adhesion (mechanical strength): Reuse and occurs, expose the LSI to ultraviolet light for a few dust reduce adhesion, and peeling off a label minutes to neutralize the charge and restore the may generate static electricity. Therefore it is LSI to normal operation. Unfortunately, this will best to erase and reprogram the PROM after also reduce the magnitude of charges stored in the peeling off its label. Rather than remove an old floating gates, so reprogramming is recommended. label, it is better to stick a new label over it. Build-up of electrostatic charge on the window is + Allowable temperature range: Check the per- the main cause of malfunctions, so follow these missible environmental temperature range of the basic rules for preventing electrostatic build-up: label. If used under conditions outside this range, the gum of the label may stiffen or adhere + Everybody handling LSIs must either be permanently to the window, even after the label grounded or wearing gloves. is removed. + Never allow plastic to rub across the window. * Be careful when using coolant sprays—they + Moisture resistance: Check the permissible often contain ions. humidity range and environmental conditions of + Cover the window with an ultraviolet-proof the label. It is currently difficult to find a ultra- label (preferably one that contains a conductive violet-proof label suitable for all conditions, so material)—it's an effective way of neutralizing select a label that is appropriate for the condi- charge. tions under which the MCU will operate. Exposure to high temperature, without power 150°C + 10°C, 48 n + en No Program read check Voc = 4.5 V or 5.5 V Note: Exposure time is measured from when the temperature in the heater reaches 150°C. Figure 45 Recommended Screening Flow 62 @ HITACHI

———. HD404328, HD4074329 Addressing Modes RAM Addressing Modes Direct Addressing Mode: A direct addressing instruction consists of two words. The first word The MCU has three RAM addressing modes, as _contains the opcode, and the contents of the second shown in figure 46 and described below. word (10 bits) are used as a RAM address. Register Indirect Addressing Mode: The con- Memory Register Addressing Mode: The mem- tents of the W, X, and Y registers (10 bits in total) ory register (MR), which consists of 16 addresses are used as a RAM address. from $040 to $04F, is accessed with the LAMR and XMRA instructions. W register X register Y register RAM address Register Indirect Addressing st word of instruction __ ____ 2nd word of instruction _ RAM address Direct Addressing Instruction __ _ | i i j i Hii RAM address Memory Register Addressing Figure 46 RAM Addressing Modes @HITACHI 63

HD404328, HD4074329 ROM Addressing Modes and the P Instruction --_Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at The MCU has four ROM addressing modes, 23 $000-$003F by executing the CAL instruction. shown in figure 47 and described below. When the CAL instruction is executed, 6 bits of . . immediate data are placed in the six low-order bits canst tides anne ROM money pace by exe, of the program counter (PCs-PCo), and Os are any address in memory space by exe- i 5 i i cuting the JMPL, BRL, or CALL instruction, Each P2°%# in the eight high-order bits (PC)3-PCe). of these instructions replaces the 14 program — Table Data Addressing Mode: A program can counter bits (PC}3~PCo) with 14-bit immediate —_pranch to an address determined by the contents of data. four-bit immediate data, the accumulator, and the Current Page Addressing Mode: The MCU has Bregister by executing the TBR : 64 pages of ROM with 256 words per page. AP Instraction: ROM data addressed in table data Program can branch to any address in the current addressing mode can be referenced with the P page by executing the BR instruction. This instruction as shown in figure 48. If bit 8 of the instruction replaces the eight low-order bits of the — ROM data is 1, eight bits of ROM data are written Program counter (PC7-PCo) with cight-bit imme- 19 the accumulator and the B register. If bit 9 is 1, diate data. If the BR instruction is on a page _eight bits of ROM data are written to the RO and boundary (address 256n + 255), executing that RI port output register. If both bits 8 and 9 are 1, instruction transfers the PC contents to the next ROM data is written to the accumulator and the B physical page, as shown in figure 49. This means _register and also to the RO and RI port output reg- that the execution of a BR instruction on a page _ister al the same time. boundary will make the program branch to the next page. The P instruction has no effect on the program counter. Note that the HMCS400-series cross macro assem- bler has an automatic paging feature for ROM Pages. 64 @xurracn

HD404328, HD4074329 ASSOC EAP rere 1st word of instruction 2nd word of instruction (BRL Program counter Direct Addressing Instruction wy Program counter Current Page Addressing toa [~~ opae [os es a a2 #1 20] i i i i i i i i Sanne Program courte Zero Page Addressing wor) (“ors Te) say ) pad B register Accumulator ——— oF Program counter Table Data Addressing Figure 47 ROM Addressing Modes @xHmacni 65

HD404328, HD4074329 Instruction Set The HD404328 and HD4074329 each have 101 instructions, classified into the following 10 groups: + Immediate instructions + Register-to-register instructions + RAM address instructions + RAM register instructions + Arithmetic instructions + Compare instructions + RAM bit manipulation instructions + ROM address instructions + Input/output instructions + Control instructions The functions of these instructions are listed in tables 38 to 47, and an opcode map is shown in table 48. Table 38 Immediate Instructions ~ Words/ Operation Mnemonic Operation Code Function Status Cycles Load Afrom immediate LAli 100011 ig ip iy ip i>A 1 Load B from immediate LBIi 1000008 ig is pb iB Ww Load memory from LMIDi,d 01101 0 ig ip iy ip iM 22 immediate dg dg dy de ds dy dg dy dy do Load memory from LMIlyi 101001 ig ip iy 9) i5MY+13Y NZ 1/4 immediate, increment Y Table 39 Register-Register Instructions Words/ Operation Mnemonic Operation Code Function Status Cycles Load A from B LAB 0001001000 BoA Ww Load B from A LBA 0011001000 A+B Ww” Load A from W LAW 0100000000 W-+A 2/2Nore 0000000000 Load A from Y LAY 00101011141 YoA Mal Load A from SPX LASPX 0001101000 £SPX+A Ww Load A from SPY LASPY 0001011000 SPY>A 1” Load A from MR LAMRm 1001 1 1 mgmmm MR(m) >A Ww Exchange MRandA = XMRAm 10 1 1 1 1 mgmmmy MR(m)oA 1 Note: The assembler automatically provides an operand for the second word of the LAW instruction. @HITACHI 67

HD404328, HD4074329 Table 40 RAM Address Instructions Words/ Operation Mnemonic Operation Code Function Status Cycles Load W from immediate LWIi 00111100i% ioW 1 Load X from immediate LXli 100010%% i i ix al Load Y from immediate _LYti 100001 Ri i>Y al Load W from A LWA 0100010000 AoW 2/2Now a COCKCOCOO Load X from A LXA 0011101000 A-+X 1 Load Y from A LYA 0011011000 Aw+~Y 1 Increment Y Vv 0001011100 Y+ri-+Y NZ aal Decrement Y DY oo110 171411 Y-13Y NB 1” Add Ato Y AYY 0001010100 Y+A>Y OVF 14 ‘Subtract A from Y SYY 0011010100 Y-A+Y NB 1 Exchange X and SPX XSPX oo0o00000001 Xe SPX 1 Exchange Yand SPY _XSPY 0000000010 Y «> SPY 1” Exchange X and SPX, XSPXY ooo0o0000011 Xe SPXY @ SPY w Nenspy Note: The assembler automatically provides an operand for the second word of the LWA instruction. 68 @HITACHI

HD404328, HD4074329 —s <$OOn—nr ee rer Table 41 RAM Register Instructions Words/ Operation Mnemonic Operation Code Function Status Cycles ————OOOOOOoOrSEEOEO er AO OS Load Afrom memory LAMY) 00100100yx MA 1 (Xe SPX, Y © SPY) Load A from memory LAMDd 0110010000 M>A 22 dy de dy dg ds dy by de dy do Load Bfrommemory LBM(XY) 00010000yx M>B wm (X SPX, Yo SPY) eS ON Load memory fromA = LMA(XY) 00100101yx A+M 1A ( @ SPX, Ye SPY) See OO Load memory from A = LMADd 0110010100 A+M 22 dy dg dy dg ds dy G3 bo dy do Load memory from A, LMAIV(X) 000101000x A>+MY+13Y wa increment Y (K @ SPX) NZ Load memory from A, LMADYX) 001101000x A»+MY-1>Y ya decrement Y (Ko SPX) NB Exchange memory XMAIXY) 00100000yx MeoA in and A (X & SPX, Y & SPY) Exchange memory XMADd 0110000000 MeA 22 and A dy dg d7 dg ds dy dy dp dy do Exchange memory XMBXY) 00110000yx MoB 1A and B (Xe SPX, Y @ SPY) Note: The meanings of (XY) and (X) are as follows: Each instruction marked with (XY) has 4 mnemonics, each with different object codes. For exam- ple, different values of x and y of the opcode of the LAM(CY) instruction are given below. Mnemonic Y x Function LAM 0 oO ‘None LAMX 0 1 Xe SPX LAMY 1 0 Yeo SPY LAMXY 1 1 X «9 SPX, Yeo SPY different values of x of the opcode of the LMAIY(X) instruction are given below. Mnemonic x Function LMAIY oO None LMAIYX 1 X «> SPX @HITACHI 6

HD404328, HD4074329 Table 42 Arithmetic Instructions Words/ Operation Mnemonic Operation Code Function Status Cycles Add immediate to A Ali 101000 ig in iy pb AtindA OVF 1/1 Increment B IB 0001001100 B+13B NZ 1/t Decrement B DB 0011001111 B-13B NBO 1/1 Decimal adjust for DAA 0010100110 1” addition Decimal adjust for DAS 0010101010 WW subtraction Negate A NEGA 0001100000 A+i A 1 Complement B COMB 0101000000 B-3B 1" Rotate right A with carry ROTR 0010100000 1" Rotate left A with carry =ROTL 0010100001 7 Set carry SEC 0011101414141 150A I Reset carry REC 0011101100 0-CA 1 Test carry Tc ooo11011i1 CA 1 Add A to memory AM 0000001000 M+A3A OVF 1/1 Add A to memory AMDd 0100001000 M+A>A OVF 2/2 dg dg d7 de ds de dg dp di do Add Ato memory with AMC 0000011000 M+A+CA+A OVF 1/1 carry OVF > CA Add Ato memory with AMCDd 0100011000 M+A+CA+A OVF 22 carry dy dg dy dg ds dg dy dz d; dg OVF—>CA Subtract A from memory SMC 0010011000 M-A-CA>A NB 1/4 with carry NB CA Subtract Afrom memory SMCDd 0110011000 M-A-CA+A NB 22 with carry dg dg dz de dg dy dg dod, do NB-»CA OR A and B OR 0101000100 AUBOA WW AND memory with A ANM 0010011100 AnM>A NZ Ww AND memorywithA ANMDd 0110011100 AnM>A NZ 22 dy dg d7 de ds dg dg dp d do OR memory with A ORM 0000001100 AUM>A NZ 1 OR memory with A ORMDd 0100001100 AUM>A NZ 22 dg dg dy dg ds dg ds dz ds do EOR memory wihA EORM 0000011100 A®M>A NZ 1M EOR memory withA EORMDd 0100011100 A®M>A NZ 22 dg dg d7 de ds dy dg dod, do 70 @ HITACHI

Table 43. Compare Instructions

HD404328, HD4074329 Table 45 ROM Address Instructions Words/ Operation Mnemonic Operation Code Function Status Cycles Branch on status 1 BRb 1 1 by bg bs by by by by by 1 1 Long branch on status 1. BRLu 0101 1 1 pg PrP; Po 1 2 dg dg d7 de ds de ds do ds do Long jump JMPLu 0 101 0 1 pg PoP; Po 2 unconditionally dg dg dy dg ds dg dy do dy do Subroutine jump on CALa 0 1 1 1 a5 a ag ag a; ay 1 Wz status 1 Long subroutine jump = CALLu 0101 1 0 pgpyp; po 1 2 on status 1 dg dg dy dg ds dy dy do dy do Table branch TBRp 00101 1 pg pop; Po Ww” Return from subroutine RTN 0000010000 18 Retum from interrupt. — RTNI 0000010001 1-—>1€,cary sT 18 restored Table 46 Input/Output Instructions Words/ Operation Mnemonic Operation Code Function Status Cycles Set discrete I/O latch SED oo11100100 1 D(Y) Ww Set discrete I/O latch SEDDm 10111 0 mmmm 13D (m) Ww direct Reset discrete /O latch RED 0001100100 0>D(Y) Ww Reset discrete VO latch REDDm 1001 1 0 mmmm 0>D(m) i" direct Test discrete VO latch TD 0011100000 D(Y) 14 Test discrete /O latch TDDm 10101 0 mmmm D(m) 1/1 direct Load A from R-port LARm 100101 mmmm Rim)oA Ww register Load B from R-port LBRm 100100 mmmm R(m 3B iN register Load R-port register. LRAm 101101 mmmm A>R(m) 77) from A Load R-port register. LRBm 101100 mmmm B—>R(m) 1M from B Pattern generation Pp 011.01 1 pg pep; Po 172 72 @ HITACHI

HD404328, HD4074329 EEE Oy TILT Table 47 Control Instructions Words/ Operation Mnemonic Operation Code Function Status Cycles $$ Smee yes No operation NOP 0000000000 1 a ec Start serial STS 0101001000 WA EE Standby mode/watch modeNote SBY 0101001100 Ww" Sa Stop mode/watch mode STOP 0101001101 1 a leat Note: Only after a transition from subactive mode. @HITACHI 73

HD404328, HD4074329 Table 48 Opcode Map a SREP EDE EEE EEE Ep | |Wor parsers So = mi fF Oho CLD —“ te Pew err [. [on a i Pep Rn i = nCOCCUrUm™m™m™mhmCUmD Le [ro oof fo fcc ce] Pp we ee a a a a a | 2 | Al i(4) 0 | [a | ALE! i(4) pepo seo ms OT (2-word/2-cycle) 74 @ HITACHI

a HD404328, HD4074329 Table 48 Opcode Map (cont) SOO a Ee pe ct ee a a ES a (6) Le | [2 | + | | 2 | [+ | ls | |e | BR b(8) Hy [a | [8 | |» | Le | (2-word/2-cycle) @ HITACHI 75

HD404328, HD4074329 Absolute Maximum Ratings Item Symbol Value Unit Note Power voltage Voc —0.3 to +7.0 Vv Programming voltage Vpp 0.3 to +14.0 Vv 2 Pin voltage Vr ~0.3 to (Voc + 0.3) v Total permissible input current Zh 100 mA 3 Total permissible output current ly 50 mA 4 Maximum input current I, 4 mA 5,6 30 mA 5,7 Maximum output current ly 4 mA 8,9 Operating temperature Topr 20 10 +75 °C Storage temperature Tstg -55 to +125 °C Storage temperature (bias) Thias ~25 to +80 °C Notes: 1. Permanent damage may occur if absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the Electrical Characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 2. Dio (Vpp) of the HD4074329. 3. The total permissible input current is the total of input currents simultaneously flowing in from all the VO pins to ground. 4, The total permissible output current is the total of output currents simultaneously flowing out from Veg to all I/O pins. 5. The maximum input current is the maximum current flowing from any I/O pin to ground. 6. Applies to Dg, RO-RS. 7. Applies to Do-D,. 8. The maximum output current is the maximum current flowing from Ve¢ to any I/O pin. 9. Applies to Dp—Dg, RO-R5. 76 @ HITACHI

st sssSSSSSSSSSSSSSSSSSSSSS— HD404328, HD4074329 $s ELT

Electrical Characteristics

Ta = -20°C to +75°C; unless otherwise specified) Item Symbo! Pin(s) Min Typ Max Unit Test Conditions Notes ss Input high Vin RESET, SCK, 0.8Vgc¢ =— Voc+0.3 V Voc=3.5t06.0V voltage INT, INT}, St§__ARpAAap$ppAa EVENT 0.9Vco — Voot+03 V ee osc, Veo-0.5 — Voc+0.3 V Vog=3.5t06.0V ee TOSS Veo-0.3 — Voct03 V SF sSISTFar vn Perera ae Input low Vie RESET, SCK, -0.3 — 02V¢¢ Vi Voc = 3.510 6.0V voltage INT, INT;, ——- EVENTS} -0.3 — 01Ve¢e Vv a osc, 03 — 0s Vi Veg = 3.510 6.0 V ee TOON 0.3 — o3 Vv una rneneeeeee Output high Vou SCK, SO, Veo-1.0 — — Vi =loyy = 0.5 mA voltage BUZZ Sse rors Output low Vo. SCK, SO, _ — 04 Vv lo, = 0.4 mA voltage BUZZ So VO leakage l,l RESET, SCK, — — 10 BA Viq = Oto Veg 1 current INTo, INT,, SI SO, OSC,, BUZZ SSE ner eee Current lec Veco - 3 6 mA Voc =5.0V, 2,4 dissipation in fose = 4 MHz active mode SSS Current Ispy Veo - 06 15 mA Vcc =3.0V, 3,4 dissipation in LCD on standby mode eee Current IsuB Veo _- 70 100 HA Voc = 3.0 V, dissipation in ee LCD on — subactive mode _- 50 70 5 a Current Iwrer Veo = 4°15 HA Veo = 3.0V, 6 dissipation in LCD off watch mode (1) ee Current Wwree Veco _ 15 35 HA Voge = 3.0V, 6 dissipation in LCD on watch mode (2) ooo SSS Current Istop Veo = 1 10 HA Veg = 3.0V, 6 dissipation in Xt = Veo stop mode eee Stop mode Vstop Veco 2 - = Vv No 32-kHz oscillator 7 retain voltage oS Notes on next page @HITACHI 77

—— SSS HD404328, HD4074329 Notes: 1. Output buffer current is excluded. 2. leg is the source current when no VO current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST, Do-Dy, Dg, Dio, RO-RS at Voc Dg open 3. Iggy is the source current when no V/O current is flowing while the MCU timer is in operation. Test conditions: MCU: V/O reset Serial interface stopped Standby mode Pins: RESET at GND TEST, Do-Dy, Dg, Dio, RO-RS at Voc Dg open 4. The power dissipation while the MCU is operating or is in standby mode is in proportion to foc. The value of the dissipation current when fos = x MHz is given by the following equation: Maximum value (fos = X MHz) = x/4 x maximum value (fos¢ = 4 MHz) 5. Applies to HD404328 only. 6. Dj is connected to Veg in the HD4074329. 7. RAM data retention 1/O Characteristics for Standard Pins (HD404328: Vcc = 2.7 to 6.0 V, HD4074329: Vcc = 3.0 to 5.5 V; GND = 0.0 V; Ta = -20°C to +75°C; unless otherwise specified) item Symbol Pin(s) Min Typ Max Unit Test Conditions Notes Input high Vit Ds-Dro. 07Veo — Voc+03 V voltage RO~R5 Input low Vit Ds—Dio. -0.3 — 03Vc¢e Vv voltage Ro-RS Output high Vou Dg, RO-RS— Vgc-1.0 — — Vo Aly = 0.5 mA voltage Output low Vo. Dg, RO-RS5 — 04 Vo Iq =0.4mA voltage VO leakage In! Dg, Ds, = — 10 HA Vin = 0 to Voc 1 current RO-RS Dio — — 20.0 nA Pull-up MOS = -Ip Dg, RO-R5 5 25 90 BA Voc = 3.0V, Vin = 0.0V current Note: 1. Output buffer current is excluded. 78 @ HITACHI

HD404328, HD4074329 V/O Characteristics for Large-Current Pins (HD404328: Voc = 2.7 to 6.0 V, HD4074329: Vcc = 3.0 to 5.5 V; GND = 0.0 V; Ta = ~20°C to +75°C; unless otherwise specified) item Symbol Pin(s) Min Typ Max Unit Test Conditions Notes Input high Vie Do-D7 O7Vco — Vec+03 V voltage Input low Vit Do-D7 0.3 — 03Veo V voltage Outputhigh Voy Dg-Dy Veo-1.0 — — Vo low = 0.5 mA voltage Output low Vor Do-D = — 04 Vly =0.4mA voltage = = 20 V lg=15mA Voc = 4.5 to 6.0 V VO leakage Iu! Do-Dy — — 10 BA Vin = 0 to Veg 1 current Pull-up MOS —Ip Do-D7 5 25 90 BA Veg = 3.0, Vin = 0 current Note: 1. Output buffer current is excluded. LCD Circuit Characteristics (HD404328: Vcc = 2.7 to 6.0 V, HD4074329: Vcc = 3.0 t0 5.5 V; GND =

0.0 V; Ta = -20°C to +75°C; unless otherwise specified)

Item Symbol Pin(s) Min Typ Max Unit Test Conditions Notes Segment driver Vas SEG1-SEG24 — - 0.6 Vv Ig=3.0 pA 1 voltage drop Common driver Vgc COM1-COM4 — - 0.3 Vv Ig=3.0pA 1 voltage drop LCD power Rwen 100 300 900 kQ Between V, and supply division GND, V, = Voc resistor LCD voltage Vico Vy 3.0 _ Vee Vv 23 Notes: 1. Vys and Vy, are the voltage drops from power supply pins V,, V2, and V3, and GND to each segment pin and each common pin. 2. When Vi cp is supplied from an external source, the following relations must be retained: Voc 2 V; 2 V2 2 V3 2 GND 3. The minimum value of Vi¢p in the HD404328 is 2.7 V. @ HITACHI 79

HD404328, HD4074329 A/D Converter Characteristics (Vcc = 5.0 V + 10%, AVsg = 0.0 V, Ta = 0°C to +70°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit TestConditions Notes Analog power Acc AVec Vec-0.3 Voc Voec+0.3 V voltage Analog input AVin —ANo-AN3 AVsg Nec Vv voltage Current between = lap, - - 50 — BA Voe = AVec = 5.0 V AVoc and AVgg Analog input CA, ANo-AN3 — TaD — pF capacitance Resolution 8 8 8 Bit Number of inputs. } — 4 Channel Absolute accuracy _ — +20 LSB Ta = 25°C 1 fosc = 1.0-4.5 MHz Conversion period 34 _- 67 tye Analog input ANo-ANg 1 _ _ MQ. f= 1 MHz, Vi, = 0.0V impedance Note: 1. Operating frequency of A/D conversion "fgg" is from 1 (MHz) to 4.5 (MHz). Zero-Crossing Detection Circuit Characteristics Ta = 0°C to +70°C; unless otherwise specified) Item Symbol = Pin Min Typ Max Unit TestConditions Notes Zero-crossing Vze zcD 20 — 3.0 Vp.p AC connection, detection input C=0.1 pF voltage Zero-crossing Vaze _ _ +750 mV {zc = 50 Hz Refer to detection accuracy (sine wave) Figure 50 fosc = 4 MHz Voc = 5.0 V Zero-crossing tao 45. — 250 Hz detection input frequency 80 @HITACHI

HD404328, HD4074329 High Sensitivity Mode (Vcc = 5.0 V + 10%, GND = 0.0 V, Ta = 0°C to +70°C, unless otherwise specified) Item Symbol Pin Min’ Typ = Max = Unit Test Conditions Notes ——_____ oa roe EO et wonanions Notes Zero-crossing Vze ZCD 1.0 — 3.0 Vpp~ ACconnection, detection input C=0.1 pF voltage Zero-crossing Vazo - - £100 mV fz¢ = 50 Hz Refer to detection accuracy (sine wave) Figure 50 fosc = 4 MHz Voc = 5.0 V detection input frequency i \\ | \\ ' ' in ih u in " H ' in ' 1 Internal CPU signal i Note: The internal CPU signal is shown lagging behind the original waveform in the figure, but this is not fixed—it could actually lead. Figure 50 Zero-Crossing Detection @ HITACHI 81

HD404328, HD4074329 Ta = -20°C to +75°C; unless otherwise specified) Item Symbol _Pin(s) Min Typ Max Unit Test Conditions Notes Clock oscillation fggc_ OSC,,OSC, 0.4 4.0 45 MHz ‘/8division,32. 1 frequency _ kHz used 0.4 4.0 45 MHz 1/8 division used,

8 Kz nts

X1, X2 = 32.768 — kHz Instruction cycle eye = 2 = us fosc = 4 MHz time Oscillation tac OSC,,OSC, — = 40 ms Voc =3.5106.0V 2 stabilization time _— — 60 ms 2 (crystal) Oscillation tre OSC,,OSC, — — 20 ms“ Vog=3.5t06.0V 2 stabilization time _ _ 60 ms 2 (ceramic filter) Oscillation tro X1, X2 _— — 3 s 3 stabilization time External clock topy osc, 90 - _ ns 4 high width External clock top, OSC; 90 — ns 4 low width External clock top, osc, _ - 20 ns 4 rise time External clock topr osc, Sd _ 20 ns 4 fall time INTo, INT,, EVENT ty, INTo INT, 2 = = tye! 5,6 high width EVENT tsuBeye INTo, INT;, EVENT. ti. INTp, INT; 2 = = teyc! 5,6 width EVENT tsuBeye RESET high width tasty _ RESET 2 — = fee 7 RESET fall time tasty RESET = = 20 ms 7 Input capacitance Ci, Dro = = TBD pF t = 1 MHz, Vi, = 0.0 V All pins except — — 15. pF. f=1MHz,V,=0.0V Dio, ANo~ANg, Notes: 1. If fogc¢ = 0.4 to 1.0 MHz, bit 3 of the miscellaneous register (MIS: $00C) must be set to 1; if oscillation. 2. The oscillation stabilization time is the time required for the oscillator to stabilize after Voc RESET input goes high after stop mode is canceled. At power-on and when stop mode is can- celed, RESET must be input for at least tac to ensure the oscillation stabilization time. If using acrystal oscillator or a ceramic filter oscillator, contact its manufacturer to determine what sta- bilization time is required, since it will depend on the circuit constants and stray capacitances. 3. The oscillation stabilization time is the time required for the oscillator to stabilize after Voc reaches 2.7 V (3.0 V for the HD4074329) at power-on—at least tac must be ensured. If using a 32.768 kHz crystal oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. 4. Refer to figure 51. 5. Refer to figure 52. The tcye unit applies when the MCU is in standby or active mode. 6. Refer to figure 52. The tsugcyc unit applies when the MCU is in watch or subactive mode. tgupcyc = 244.14 ps (32.768-KHz crystal) 7. Refer to figure 53. 82 @ HITACHI

HD404328, HD4074329 Serial Interface Timing Characteristics (HD404328: Vcc = 2.7 to 6.0 V, HD4074329: Voc = 3.0 to 5.5 V; GND = 0.0 V; Ta = -20°C to +75°C; unless otherwise specified) During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Conditions Notes Transmit clock cycle time tseye SCK 10 — _ tye _ Load shown in figure 551, 2 Transmit clock high width tscxy SCK 0.3. — —— _teye Load shown in figure 55 1,2 Transmit clock low width tscx, __ SCK 0.3. — —— __tgcye__Load shown in figure 55_ 1,2 Transmit clock rise time tgcx,y SCK — — 100 ns Voc=3.5t06.0V, 1,2 load shown in figure 55 ol - 200 ns Load shown in figure 55 1,2 Transmit clock fall time tgoxt sckK — - 100 ns Voc = 3.5 to 6.0 V, 1,2 load shown in figure 55 — = 200 ns _Loadshowninfigure55 1,2 _ Serial output data tpso so - _- 300 ons Voc = 3.5 to 6.0 V, 1,2 delay time load shown in figure 55 = = 500 ns Load shown in figure 55 1,2 Serial input data tgs Ss! 200 — — ns Voc=3.5t06.0V 1 setup time 300 — — os 1 Serial input data tusi sl 150° — - ns Voc = 3.5 to 6.0 V 1 hold time 300. — _ ns 1 During Transmit Clock Input Item Symbol Pin Min Typ Max Unit Test Conditions Notes Transmit clock cycle time tse SCK 1.0 — —— _taye 1 Transmit clock high width tgcxy SCK 03 — _ tgeye 1 Transmit clock low width tscx, SCK_ 03° — — __tecye 1 Transmit clock rise time tgcxy = SCK — — 100 ns Voc=3.5t06.0V 1 = _ 200 ns 1 Transmit clock fall time tscxrp «= SCK. — = — 100 ns Voo=3.5106.0V 1 _ _- 200 ns 1 Serial output data tpso SO — — 300 ns Vog=3.5to6.0V, 1,2 delay time load shown in figure 55 _- _ 500 ns Load shown in figure 55 1,2 Serial input data tgs sl 200 — — ns Voc=3.5106.0V 1 setup time 300 — _ ns 1 Serial input data tus! SI 150 — - ns Voc = 3.5 to 6.0 V 1 hold time 300 — — ns 1 Notes: 1. Refer to figure 54. 2. Refer to figure 55. @HITACHI 83

HD404328, HD4074329 Vee = 3.5 V to 6.0 V (HD404328) Voc = 3.5 V to 5.5 V (HD4074329) Mop top Osc, O5V ‘ot topr topr Voc = 2.7 V to 3.5 V (HD404328) Voc = 3.0 V to 3.5 V (HD4074329) Mop top osc, 0.3V a, tepr tort Figure 51 Oscillator Stabilization Time Voc = 3.5 V to 6.0 V (HD404328) Vec = 3.5 V to 5.5 V (HD4074329) — 0.8 \\ INTo, INT, ve tu

0.2 Voc

Voc = 2.7 V to 3.5 V (HD404328) Voc = 3.0 V to 3.5 V (HD4074329) — 0.9 INT, , INT, Nec te!

0.1 Voc

Figure 52 Interrupt Timing Voc = 3.5 V to 6.0 V (HD404328) Veo = 3.5 V to 5.5 V (HD4074329) 0.8 \\ Voc = 2.7 V to 3.5 V (HD404328) Voc = 3.0 V to 3.5 V (HD4074329)

0.9 Veo

RESET tasty _ |

0.1 Voce

Tast Figure 53 Reset Timing 84 @ HITACHI

HD404328, HD4074329 HD404328 Option List Please enter check marks (If, x, or %) in boxes by applicable items. Packages

3 DPSS

[ousiomer [SS [ Deparment’ [i ROM code name [_——*d LSI number (to be filled in by Hitachi) Optional Functions ROM Code Media ( With 32-kHz CPU operation O EPROM: Emulator type (0 Without 32-kHz CPU operation, with time-base for clock) (0 HD4074329 ( Without 32-kHz CPU operation, without time-base © With zero-crossing detection function © Without zero-crossing detection function Usage Conditions Check Oscillator for OSC) and OSC. © Ceramic fitter Oscillator for X1 and X2 Crystal [to Notvsed | — ——+d G External clock [t= MHz | Package Dimensions Unit: mm (inch) DP-64S nil Sh i . 7.6.26) ee ait Banna) val 6 33 a) 1¢ RN i ANY giz ~s aN as ~ ll i | 2 1 i} R vt VT F3R .m20.25 | owl = 3 LL assess 86 @ HITACHI

~ HD404328, HD4074329 Package Dimensions Unit mm (inch) FP-64B 20.0(0.787) FNM ATTEN S aa S&S SS |S z)4 Ee fF ° Sid gS E |S . =r —) — = a 20 a

2 TUT Zoe

1 | is wag Hat2U [0.15(0. 006) | nals Nr olm | ° SIMnnnnhhn | fom) ~ |= 1,240.2 _| DC-64S ih Aan . il I! 57.32. GA AY} feo a a mR aft “aN y! | ok ff | 2 " 7 rere * dal pase . @HITACHI 87