HD404304P

Hitachi Semiconductor

CMOS 4-BIT SINGLE-CHIP MICROCOMPUTER

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HD404304 HITACHI

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Description

The HD404304 Series is a CMOS 4-bit single-chip + Two timer/counters microcomputer basically equivalent to the — 11-bit prescaler HMCS400 series, providing high programming —8-bit timer (free-running timer/watchdog Productivity, high speed operation, and low power timer) dissipation. It incorporates ROM, RAM, I/O, A/D — 8-bit timer (auto-reload timer/event counter) converter, two timer/counters, including high + Five interrupt sources voltage 1/0 pins to drive fluorescent display tubes — Two by external sources directly. — Two by timer/counters — One by A/D converter ‘The HD404304 Series includes three chips: the . 4-channel x 8-bit A/D converter HD404302R with 2 k-word ROM, the HD404304 «Two tone generator outputs with 4 k-word ROM and the HD4074308 with . Subroutine stack, up to 16 levels including inter- 8 k-word PROM. The HD4074308, which includes rupts PROM, is ZTAT™ microcomputer that can dra- Two low-power dissipation modes matically shorten system development periods and —Standby mode smooth the process from debugging to mass — Stop mode Production. (The PROM program specifications are On-chip oscillator the same as for the 27256.) — Crystal or ceramic oscillator —External clock —42-pin plastic DIP (DP-42) Features —42-pin ceramic DIP with window (DC-42)* . A — 42-pin plastic shrink DIP (DP-42S) . 1 R . * ‘ 2048 word x 10-bit ROM (mask ROM version, — Sé-pin flat plastic package (FP-54) 4096-word x 10-bit ROM (HD404304) * Instruction cycle time: 2 Hs (fosc = 4 MHz) 8192-word x 10-bit PROM (ZTAT™ version) Note: * Availabl , + 160-digitx 4-bit RAM lote: * Available as a sample + 33 1/0 pins, including 25 high-voltage I/O pins (40 V max.) SSS

Ordering Information

Type Product Name Model Name ROM (Words) Package Orono ROM (Words) Package Mask ROM HD404302R HD404302RP 2,048 DP-42 HD404302RS OP-42S HD404302RF FP-54 —— ee HD404304 HD404304P 4,096 OP-42 HD404304S DP-42S HD404304F FP-54 ZTAT™ HD4074308 HD4074308P 8,192 DP-42 HD4074308S DP-42S HD4074308C* DC-42* HD4074308F FP-54 ON Note: * Available as a sample

579 Hitachi

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Sv | Pin Arrangement Dw C10 21 JD, TGyD1s 2 [De TGyDy2 C3 «0; Vaig/RAs C14 sof] De Ro, C45 wf Ds Ro; Cs wo RO, C17 36[_] Dy ; Ro; Cle sd: | Rig Lo ss] Dy Ri, OP-42 l_}D, Rip) DP-428 sel] Veo. RtsCj 0C-42 sf Jose, R25 C19 sf] OSC, Re, CI] 2o{_) TEST Re, Cis ze[_] RESET Rag Ce 27 AVes R3, C17 26{_] R4y/ANg, rs, Ce 25[) R&g/ANe INTyR3, C19 24[] RAVAN, INT YRS. Jeo 237] Rég/ANo @np Cla 2E1 AVeg ! Top view gig 2 éssésgs Non Mol OO wea aa e ne(_]7 «[JNc nels {_]Ne ro, (| {D4 Ro, [_}10 +s[_]03 R03} «(1b2 Riol 12 «(J Dy ri, ]3 «e\\_] D9 RizL|« FP-54 411} Veo rts s 40{_osce Rep (_|16 so{_Josc, Re, Loh sol] TesT R2g[_]19 26[_] AVss No [_]20 as{_ NC ne] sno nclf#, 3 ep ep 8 8 8 5 a%}INC UUUUU UUUUU feees £2222 ae zai? Top view m445b204 0048439 5953 mf 580 Hitachi

SC‘; -HD404304 Series Pin Description Pin Number Pin Number DP-42, DP-42, DP-428, DP-428, DC-42 FP-54 Pin Name vo DC-42 FP-54 Pin Name vo 1 1 Dio vO 28 7 RESET 1 2 2 D,,/TGy vO 29 38 i-c ee 3 3 Dig, 1 30 39 Osc, 1 4 4 “RAG 8h 40 OSC, ° 5 5 RO, vo 32 41 Voc 6 9 RO, vo 3 42 Do vo 7 10 RO. v0 34 a dD 8 14 FO; vO 3 44 Dp vo 9 12 “Rio “vO 6 45 Ds vO 10 13 Ri, vo 37 46 Da vo "1 14 Rip vo 38 50 Ds vO 12 15 Rig vo 39 51 De _ vo 13 16 R2o vo @ 82 Db a) = 14 17 R2, vO 4 53 Ds vO 15 18 R2, vo 42 54 Dy vo 16 19 R23 vo - 6 NC 17 23 R3p vo = 7 NC. _ 18 24 R3, vo — 6 NC 19 25 RANT, vo 20 NC 20 26 Ray/iNT, vo 21 NC 21 27 GND - 22 NC 22 28 AVeo = 3 NC 23 29 R4g/ANo vo = 34 NC 24 30 R4,/AN, il) — 35 NC 25 31 Raa/AN> vo _- 47 NC 26 32 R4y/ANg vo - 48 NC . 27 36 AVsg = 49 NC NC:Noconnecion—~SCSCSCSCS M4496204 OO4S44O LOT mm set Hitachi I

Power Supply be selected using a mask option. For details, see the | Input/Output section. Voc: Apply power supply voltage to this pin. Rp to R03, Rip to R13, R2 to R23, R3p to R33, | GND: Connect to ground. Rap to R43, RAy (R Ports): RO to R4 are 4-bit /O | Vaisp? This pin, multiplexed with RAj, is for the tg R2 and RAy are high-voltage pins, and the pins power supply of the high-voltage output pins witha of R3 to R4 are standard pins. R3, and R33 are maximum voltage of Vcc—40 V. For details, see multiplexed with INTp and INT}, respectively. For the Input/Output section. details, see the Input/Output section. AVccy AVss: Power supply pins for the A/D Interrupts | converter, __ | — . _ INT , INT,: External interrupt pins. INT; can be | TEST: Non-user pin. Connect this pin to Vcc. used as an external event input pin for timer B. . F . INTo and INT; are multiplexed with R32 and R33, RESET: MCU reset pin. For details, see the Reset rasrectively, For details, see the Interrupt section. Oscillators Tone Generator . A TGpo, TG,: Tone generator output pins. These pins OSC}, OSC,: Inpuyoutput pins for the internal are ‘hi eh- voltage pins multiplexed with Dy, and | oscillator circuit. They can be connected to a crys- D1, respectivel: tal, ceramic, of external oscillator circuit, For 712 TesPectively. details, see the Internal Oscillator Circuit section. AID Converter Ports ANo to AN; (AN Port): A/D converter input port. ANp to AN3 are multiplexed with R4y to R43, Dp to Dj, (D Port): Input/output port addressed by respectively. For deuile wwe the WD Conver its bits. These 13 pins are all high-voltage ign input/output pins. The circuit type for each pin can . ME 4456204 OO48441 SUL mt 582 Hitachi

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ROM Memory Map subroutines. The CAL instruction branches to these subroutines, The ROM is described in the following paragraphs with the ROM memory map in figure 1. Pattern Area ($0000 to $07FF: HD404302R; $0000 to SOFFF: HD404304, HD4074308): Vector Address Area ($0000 to $000F): — Locations $0000 through $07FF or $0FFF are Locations $0000 through $000F are reserved for reserved for ROM data. The P instruction allows JMPL instructions to branch to the starting address reference to ROM data as a pattern. of the initialization program and the interrupt programs. After a reset or an interrupt, program Program Area ($0000 to $07FF: HD404302R; execution continues from the vector address. $0000 to $OFFF: HD404304; $0000 to $IFFF: HD4074308): Locations from $0000 to $1FFF can Zero-Page Subroutine Area ($0000 to $003F): be used for program code. Locations $0000 through $003F are reserved for 9 $0000 0 JMPL instruction $0000 Vector address 1 (jump to reset routine) $0001 15| SOOOF 2 MPL instruction ‘$0002 16| —_|$0010 3 jump to INTo routine) $0003 Zero-page subroutine \\ 4 MPL instruction $0004 6a (64 words) stor 8 Jump to INT; routine) $0005 64 soos 8 JMPL instruction $0006 7 (jump to timer A routine) $0007

8 JMPL instruction $0008

reeae mands) " 9 {jump to timer B routine) $0009 2047 For HO404302R|$07FF \\"! jump to A/D routine) $0008 2048 gosoo V2; | $000 13[ $0000 Program pattern 14 [$000 (4096 words) {$000 4095) For HD404304 | $OFFF 4096| $1000 Program (8192 words)

8191 For HD4074308 | $1FFF |

8192 $2000 Not used 16383| $3FFF Figure 1 ROM Memory Map mm 4496204 0048443 319

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RAM Memory Map shown in figure 2. These registers cannot be accessed by RAM bit manipulation instructions. The MCU contains a 160-digit x 4-bit RAM as the However, WDON ($020) can be accessed only by data and stack area. In addition to these areas, inter- those bit instructions, Tupt control bits and special function registers are also mapped on the RAM memory space, The Data Area ($040 to $09F): The 16 digits of $040 RAM memory map (figure 2) is described in the through $04F are called memory registers (MR) following paragraphs. and are accessible by the LAMR and XMRA instructions (figure 4). Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for Stack Area ($3CO to $3FF): Locations $3CO interrupt control. It is accessible only by RAM bit through $3FF are reserved for the stack area to save manipulation instructions. However, the interrupt the contents of the Program counter (PC), status request flag cannot be set by software. The RSP bit flag (ST), and carry flag (CA) when subroutine is used only to reset the stack pointer. calls (CAL and CALL instructions) and interrupts are processed. This area can be used as a 16-level Special Function Registers Area ($004 to $034): nesting stack in which one level requires 4 digits. The special function registers are the mode or data Figure 4 shows the save condition. The program registers for extemal interrupt, A/D conversion, counter is restored by the RTN and RTNI instruc. and the timer/counters, and are the I/O port data tions. The status and carry flags are restored only control registers. These registers are classified into by the RTNI instruction. This area, when not used three types: write-only, read-only, and read/write as. as q stack, is available as a data area. a Mm 445be04 OO48444 255 585 Hitachi ee

9 [$000 0 $000 RAM-mapped registers S09 } Interrupt control bits area been (16 digits) $o4F 4[ Port mode register A_(PMRA) | _W_|$004 {$050 5| Port mode register B_ (PMB) | W__|$005 Data (80 digits) \\ 6 $006 S09F 7[_~ Noted $007 [$0A0 | Timer mode register A__ (rma) | w_|$008 9[ Timer mode register 8 (TMB) | w_|$009 12 $000 S3BF 13] A/D data register lower (ADAL) | _R_|$00D | $39 14[ AD data register upper (ADRU) | _R_|$00E | Stack (64 digits) \\ 15] AD port select register (ADPR) |W _|S00F “ _ : ee oe Not used \\ 31 SO1F | 32] $020 y so2t | Special flag bits area so2 35 'so23 36] $024 Not used 50] 032 53] $035 Notes: * Two registers are mapped on the same address. TCBL: Timer counter B lower TCBU: Timer counter B upper TLRL: Timer load register B lower Not used ‘TLRU: Timer load registr B upper W: Write only R: Read only RM: ReadWrite 63 SosF Figure 2, RAM Memory Map Mi 4456204 OO48445 15] 586 Hitachi

AEN OWS DlerriesS: Bit 3 Bit 2 Bit 1 Bito

0 IMO IFO RSP IE $000

(1M of INTo) (IF of INTo) (Reset SP bit) _|(Interrupt enable flag

1 IMTA IFTA M1 iF $001

(IM of timer A) (IF of timer A) (IM of INT;) (IF of INT;)

2 IMAD IFAD IMTB IFTB $002

(IM of A/D) (IF of A/D) (IM of timer B) (IF of timer B) s[neone | tns [Ue | IF: Interrupt request flag 1M: Interrupt mask JE: Interrupt enable flag SP: Stack pointer Note: Each bit in the interrupt control bits area is set by the SEM/SEMD instruction, reset by the REMREND instruction, and tested by the TM/TMD instruction. Other instructions have no effect. Furthermore, the interrupt request flag is not affected by the SEM/SEMD instruction. The contents of the status flag become invalid when unusable bits and the RSP bit are tested by the TM or TMD instruction. Bit3 Bit 2 Bit 1 Bito | WDON ADSE 2 $021 Reserved $022 $023 Note: The WDON flag can be used by the SEW/SEMD instruction, and reset by MCU reset. ADSF stays high during A/D conversion and becomes low after A/D conversion. Figure 3 Configuration of Interrupt Control Bits Area mm 4496204 oO4a44b Oe 587 Hitachi NNER nnn

a HD404304 Series Memory registers Stack area 64[ MR (0) ]$040 960 $3Co 65 $041 66| MR (2) |$042 67[ MR (3) |$043 68 $044 69| MR (5) |$045 70{ MR (6) |$046 71|_MR (7) |$047 Bits _Bit2 _—Bit1 _Bito

72 MR (8) |$048 oa | onl oe

73{ MR (9) |$049 1020} ST | Py | PCy2 | PCr | $3FC 7 $04B 1021] PCy | PCy | PCg | PC; | $3FD 76| MR (12) |$04C ao | oe 77 [M3 |s040 se2e| ca | Pos | Pos | PO, | sore | 78 $04E se | a | ow | we 7alMA(15) |$04F 1023 eakF 1023] PC; | PC, | PC; | PCo | S3FF , PCjg to PCo: Program counter | ST: Status flag CA: Carry tlag | | Notes: 1. Since the HD404302R has a 2-kword ROM, PC;;, PC;2, and PC;g are not used. 2. Since the HD404304 has a 4-kword ROM, PC;2 and PC;3 are not used. 3. Since the HD4074308 has a 8-kword ROM, PC; is not used. | Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position M™ 4496204 0048447 TLY 588 Hitachi

Registers and Flags overflow generated from the ALU during arith- metic operation. It is also affected by the SEC, The MCU has nine registers and two flags forCPU REC, ROTL, and ROTR instructions. A carry is operations. The following paragraphs describe the pushed onto the stack during an interrupt, and registers and flags shown in figure 5 in detail. Popped off the stack by the RTNI instruction. This . flag is not affected by the RTN instruction. Accumulator (A), B Register (B): The 4-bit accu- mulator and B register hold the results from the Status Flag (ST): The status flag (ST) indicates an arithmetic logic unit (ALU) as well as the transfer ALU overflow and ALU non-zero during arith- data between memory, I/O, and other registers, metic or compare instructions, and the result of a . bit test instruction. Moreover, the status flag con- W Register (W), X Register (X), ¥ Register (Y): trois branching caused by the BR, BRL, CAL, or The 2-bit W register and the 4-bit X and Y registers. Cal y instruction, Whether these instructions are indirectly address the RAM, The Y register is also executed or skipped, the status flag is always set to used for D-port addressing. 1, The state of this flag remains unchanged until . the next arithmetic, compare, bit test, or branch en et Si SPY Revise (SPY): the instruction is executed. During an interrupt, ST is Xond Yaen wesivel are used to assist pushed onto the stack, and popped off the stack by registers, respectively. the RTNI instruction. This flag is not affected by Carry Flag (CA): The carry flag (CA) indicates an the RTN instruction. 3 Q We] wept 3 0 3 0 CO) SPY ie Carry tlag Status tlag 1: oO 9 ) [TET] se} sak omer Figure 5 Registers and Flags myydb204 OO4844s STO me 589 Hitachi

—_—SSSSeSSSSSSSSSSSSSSeeSeSeSeeeeSeeeSSSSSSSSSSSSSSsSsssssssseseseses HD404304 Series Program Counter (PC): The program counter isa and maintain the interrupt request. The interrupt 14-bit binary counter which holds the address of enable flag (IE) is also used to control interrupt the next program instruction to be executed. operations. Stack Pointer (SP): The stack pointer (SP) is a _ Interrupt Control Bits and Interrupt Service: 10-bit register which indicates the next stack The interrupt control bits are mapped on $000 address. This pointer, which is initialized to $3FF, through $003 of the RAM space. They are acces- is decremented by 4 when data is pushed onto the sible by RAM bit manipulation instructions. stack, and is incremented by 4 when data is popped However, the interrupt request flag (IF) cannot be off the stack. The highest four bits are fixed to set by software. The interrupt enable flag (IE) and 1111, which allows the pointer to indicate up to 16 _IF are cleared to 0, and the interrupt mask (IM) is levels of subroutines. The stack pointer is initial- set to 1 after MCU reset. ized when the MCU is reset or the RSP bit ($000, ; , . bit 1) is reset by the REM or REMD instruction. Figure 6 is a block diagram of the interrupt control circuit. Table 1 shows the interrupt priority and Interrupts vector addresses, and table 2 shows the interrupt conditions corresponding to each interrupt source. Five interrupt sources are available on the MCU: The interrupt request is generated when the IF is set extemal requests (INTo, INT), timer/counters to 1 and IMis 0, If the IE is 1 at this time, the inter- (timer A, timer B), and A/D. For each source, the —_rupt will be activated and vector addresses will be interrupt request flag (IF), interrupt mask (IM), and generated from the priority PLA corresponding to interrupt vector addresses are provided to control _the interrupt sources. ee Table 1 Vector Addresses and Interrupt Priority Reset/Interrupt Priority Vector Addresses | RESET SOO NT 1 $0002 NT, 2 $0004 Timer A 3 $0006 Timer 8 4 $0008 AD 5 $000A Table 2 Interrupt Conditions Interrupt Control Bit INT INT, Timer A Timer B AD IE 1 1 1 1 1 IFO - IMO. 1 0 ° ° ° 1F1 - IMT * 1 Y) 0 0 IFTA - IMTA + + 1 0 0 IFTB - IMTS ‘ * * 1 0 WFAD TIMAD Note: * Don't care 4496204 0048449 637 590 Hitachi

WHT 1+) execution ‘Stacking; | Interrupt Stacking; on the vector address ‘execution at starting address | of the interrupt routine | Figure 7 Interrupt Processing Sequence | M™445b204 OO48451 495 me 592 Hitachi

request? No <> Yes Stack « (PO) ; Stack « (CA) Stack « (ST) No PC « so004 No Yes ~~ timer A No PC « $0008 Yes <~ Timer B interrupt? ‘No (AD interrupt) Figure 8 Interrupt Processing Flowchart mm 445b204 O04845e 32] 593 Hitachi cae nneeeeeeeeeee

Interrupt Enable Flag (IE: $000, Bit 0): The Port Mode Register A (PMRA: $004): Port mode interrupt enable flag enables/disables interrupt register A is a 4-bit write-only register which con- requests. It is reset by an interrupt and set by the __trols the R3,/INTg pin and R33/INT, pin as shown ' RTNI instruction. in figure 10, Port mode register A will be initial- — ized to $0 by MCU reset. External Interrupts (INT, INT;): The external | interrupt request inputs (INTo, INT,) can be Timer A Interrupt Request Flag (IFTA: $001, selected by port mode register A (PMRA: $004) _Bit 2): The timer A interrupt request flag (figure 9) (figure 10). is set when an overflow occurs in timer A. The external interrupt request flags (IFO, IF1) Timer A Interrupt Mask (IMTA: 001, Bit 3): | are set at the falling edge of INTp and INT, inputs, The timer A interrupt mask bit (figure 9) masks an respectively. interrupt request caused by the timer A interrupt | __ request flag. The INT, input can be used as a clock signal input | to time B. Timer B is incremented at each falling Timer B Interrupt Request Flag (IFTB: $002, | edge of the INT;. When using INT; as the timer B__ Bit 0): The timer B interrupt request flag (figure 9) extemal event input, the external interrupt mask is set when an overflow occurs in timer B. | (IM1) must be set so that the interrupt request by ' INT, will not be accepted. Figure 9 shows the Timer B Interrupt Mask (IMTB: $002, Bit 1): | interrupt mode register. The timer B interrupt mask bit (figure 9) masks an interrupt request caused by the timer B interrupt External Interrupt Request Flags (IFO: $000, — request flag. | Bit 2; IF1: $001, Bit 0): The external interrupt request flags (IFO, IF1) (figure 9) are set at the A/D Interrupt Request Flag (IFAD: $002, Bit 2): falling edge of the INT and INT; inputs, respec- The A/D interrupt request flag (figure 9) is set | tively. when an A/D conversion is completed. External Interrupt Masks (IMO: $000, Bit 3; A/D Interrupt Mask (IMAD: $002, Bit 3): The IM1: $001, Bit 1): The external interrupt mask bits A/D interrupt mask bit (figure 9) masks an inter- (figure 9) mask an interrupt request caused by the Tupt request caused by the A/D interrupt request external interrupt request flags. flag. mi 449b204 0048453 ebo ml 504 Hitach!

a HD404304 Series Timers The MCU contains a prescaler and two timer/ ight different clock signals, divided by the counters (timers A and B) as shown by the block _prescaler, can be used as an input clock. The clock diagram in figure 11. input signals to timer A are selected by timer mode register A. When the next clock signal is applied Prescaler: The input to the prescaler is the system after timer A becomes $FF, an overflow is clock signal. The prescaler is initialized to $000 by generated and timer A is reset to $00. This MCU reset or by setting bit 3 of timer mode overflow causes the timer A interrupt request flag register A (TMA: $008) when the watchdog timer —_(JFTA $001, bit 2) to go to 1. ‘on flag (WDON: $020, bit 1) is 0, after which the prescaler starts to divide the system clock. It This timer can function as a watchdog timer to continues operation until MCU reset or stop mode _ detect a runaway program. The MCU is reset when occurs. an overflow output is generated from a timer counter that cannot be controlled due to a runaway ‘The pulse frequency of timer A input clock, timer program while the watchdog timer on flag B input clock, and the tone generator outputs (TGp, — (WDON) is 1. TG)) are selected among prescaler outputs by timer mode register A (TMA: $008), timer mode register Timer B Operation: Timer mode register B B (TMB: $009), and port mode register B(PMRB: — (TMB: $009) selects the auto-reload function input $005), respectively. clock source, and the prescaler divide ratio for timer B. When an external event input is used as an ‘After MCU reset, WDON is 0. Thus, when timer A input clock signal to timer B, select R33/INT; as | is reset by setting bit 3 of timer mode register A INT, by setting port mode register A (PMRA: (TMA) when the watchdog timer is off, the $004), and set the external interrupt mask (IM1) prescaler is also reset, which affects the operation to prevent an external interrupt request from of timer B and the tone generator outputs (TGo, —_ occurring. . TG,). Consequently, the program should control these conditions. Timer B is initialized according to data written into / timer load register B by software. Timer B is incre- | Timer A Operation: Timer A is an 8-bit interval mented at every clock input signal. When the next timer which can be used also as a watchdog timer. —_clock signal is applied to timer B after it is set to The prescaler divide ratio of timer A is selected by $F, it will generate an overflow output. In this timer mode register A (TMA: $008). case, if the auto-reload function is selected, timer B is initialized according to the value of timer load After timer A is initialized to $00 by MCU reset or register B. If it is not selected, timer B is reset to setting bit 3 of timer mode register A (TMA: $00, The timer B interrupt request flag (IFTB: $008), it is incremented at every clock input signal. _ $002, bit 0) will be set at this overflow output. m4ysb204 0048455 030 mM

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NN SET7?_ Ct ee HD404304 Series SO _ HD 404304 Series System Watchdog timer on flag Gi Timer mode © — | ee ee rm) Interrupt L) request flag of timer A System reset awa, U g Prescaler (11 bits) Zz CI +1024 | VieCuc [128] V/\\ ®)re, Internal bus line (S1)

2 TL (4 bits) 4

iNT, TCB (8 bits) TBOF CS Timer B MPX Timer unt) B Ga)

8 Interrupt

TLR (8 bits) ir Tiner meae ottmerB register B internal bus line (S2) |! Figure 11 Timers A and B Block Diagram OO484sh 177 = 4uabeou 597 Hitachi ee

Timer Mode Register A (TMA: $008): Timer 0, the prescaler is also reset. Bit 3 retains a 1 for mode register A is a 4-bit write-only register. Bits 0 only one instruction cycle. to 2 of TMA control the prescaler divide ratio of . . the timer counter A clock input, as shown in figure Timer mode register A can be modified from the 12. Bit 3 resets timer A when set to 1; if WDON = second instruction cycle of the write instruction. a Timer mode register A (TMA: $008) [ers [ome [ses [or [Bit2 | Bit | Bit 0 | Prescaler divide ratio | [° pee es | [7 48 [a1 [sz | fo [332 | [of 4 | eee WOON] BS] Function 1 | Timer counter A and prescaler are reset __ lt | 1 | Timer counter A is reset X<D< frees os |ADSF| Special flag bit ($020) > Special flag bit ($020) : Not used WDON: Watchdog on flag ADSF : A/D start flag Figure 12, Timer Mode Register A Configuration wm 4y5b204 0048457 403 =

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selects the auto-teload function, the prescaler digit (TCBU: $00B, TLRU: $00B). low-order digit first, and then the high-order digit. register B is written to, The initialization of timer B to $00 by MCU reset. by a write to the timer load register should be . $00A, TLRU: $00B): Timer B consists of an 8-bit the high-order digit is read. Figure 13. Timer Mode Register B Configuration

Timer A Interrupt Request Flag (IFTA: $001, A interrupt request flag. Bit 2): The timer A interrupt request flag (figure 14) is set by the overflow output of timer A. When Timer B Interrupt Request Flag (IFTB: $002, the watchdog timer function is selected, the timer Bit 0): The timer B interrupt request flag (figure interrupt request flag is not set since the MCU is _14) is set by the overflow output of timer B. t by rfl It. reset By an overflow output ‘Timer B Interrupt Mask (IMTB: $002, Bit 1): Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer B interrupt mask (figure 14) prevents an The timer A interrupt mask (figure 14) prevents an _ interrupt request from being generated by the timer interrupt request from being generated by the timer _B interrupt request flag. a fears] = [=] FTA |_9__| timer A interrupt request disabled |_1 _| Timer A interrupt request enabled [ia | -2{ Timer ilu request eccopted |_1__| Timer A interrupt request masked = [ = ] = [ura] soe [re |] Timer B interrupt request disabled Timer B interrupt request enabled ia [0 | Timer B interrupt request accepted [1 [Timer B interrupt request masked _| —: Other interrupt control bit Figure 14 Timer Interrupt Control Bits Me 4496204 0048455 786

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———SSSSSSSSSSSSSeSSe HD404304 Series A/D Converter The HD404302R, HD404304, and HD4074308 A/D Mode Register (AMR: $00C): The A/D incorporate a sequential comparison system A/D mode register (figure 16) is a 4-bit write-only converter consisting of a resistor ladder. It can register which selects the A/D conversion speed measure four analog inputs with 8-bit resolution. (bit 0, bit 1) and analog input channel (bit 2, bit 3). Figure 15 shows the A/D converter block diagram. | The A/D converter consists of the following A/D Start Flag (ADSF: $020, Bit 0): A/D conver- registers: sion is started when a | is written to the A/D start flag (figure 16). After a conversion is completed, + A/D mode register (4 bits) the conversion data is set in the A/D data register + A/D start flag (1 bit) and the A/D start flag is cleared simultaneously, + A/D port select register (4 bits) Note that the bit manipulation instruction SEM or + A/D data register (4 bits + 4 bits) SEMD should be used to write data to ADSF. During A/D conversion, ADSF must not be written to. - _ internal bus _ | | ADRL: $00D pe ADPR: $00F AMR: $00C- ADSF: $020 | LADRU: $00E AD port select A/D mode ADD start flag A/D data register (ADPR) ragister (AMR) (ADSF) register (ADR) 4 2 | FAI Ray/ANo OS] RAVAN ot |mpx | AJD interrupt RAy/AN, o-— | | request flag | AVoc 0 E AVgg © ae Figure 15 A/D Converter Block Diagram w4496204 OO4S4LO YTS

601 Hitachi

A/D Port Select Register (ADPR: $00F): The register which selects the digital port and analog A/D port select register (figure 16) is a write-only _ port. A/D mode register (AMR: $00C) [srs [one [ors [oro] T | [Bits [Bito | Conversion cycle _ | popes. Be Li [67 | eee ee ee ————eE Lif; ANs | 1] Special flag bit ($020) LJ AD start flag (ADSF} Start bit | Status information (write) | (test) | 0 [Notattect [A/Didie L_1 [Start [A/D converting | WDON (see Timer section) Not used AID port select register (ADPR: $00F) | 1 [AN | ANe TAN: [ ANo | Lo | Rés | Rap | RA, | Ray | Figure 16 A/D Register Configuration 334 myusb204 GONSHED 602 Hitachi

SSC er de’ A/D Data Register (ADRL: $00D, ADRU: Precautions on Using the A/D Converter: SO0E): The A/D data register (figure 17) is a + Ifa digital signal is input to the R4p to R43 or 4-bit/4-bit read-only register in which the 8-bit adjacent pins during A/D conversion, conver- conversion result is set after completing A/D con- sion accuracy may be affected. version. The data is preserved until the next + Data in the A/D data register is not guaranteed conversion begins, Data read is not guaranteed during A/D conversion. during A/D conversion. The A/D data register is + Port output instructions should not be executed initialized to $80 by the MCU reset. during A/D conversion to allow for a stable A/D converter operation. ee ADRU ($00E) ADRL ($00D) Conversion LSB | result Bit7 Bito Figure 17 A/D Data Register Configuration M445b204 OO484b2 270 603 Hitachi Cnc cccnnnnnnncc

‘The MCU has 33 1/O pins, 25 being high-voltage __tiplexed with ANo, AN;, AN>, and AN3, respec pins. The on/off status of the output buffers of the __ tively. The circuit type of the R port is shown in standard pins (figure 19) is controlled by the com- _ table 3. binations of the value of the port register (PDR) and data control register (DCR). Port Mode Register B (PMRB: $005): Port mode register B is a 4-bit write-only register which con- D Port: The D port is an 1/O port which has 13 dis- trols the Dy,/TGg pin and D,2/TG, pin as shown in crete 1/O pins, each of which can be addressed _ figure 18. The port mode register is initialized to $0 independently. It can be set/reset through the by MCU reset. These pins are therefore initially SED/RED and SEDD/REDD instructions, and can _used a ports. be tested through the TD and TDD instructions. Furthermore, the contents of the status flag become Unused VO Pins: If any unused 1/O pins are left invalid when the unused ports are tested. Dj; and _ floating, the LSI may malfunction due to noise. Dj» ports are multiplexed with tone generator pins The I/O pins should be fixed as follows to prevent TGo and TGy, respectively. The circuit type of the malfunction. D port is shown in table 3. . . + If without pull-down MOS (PMOS open drain) R Ports: The R ports are composed of 20 I/O pins is selected for high-voltage pins connect to Voc and one input-only pin. Data is input through the on the printed circuit board. LAR and LBR instructions and output through the A . LRA and LRB instructions. The MCU will no be * Hf Without pull-up MOS is selected for standard | affected by writing into the input-only and non- pins connect to GND on the printed circuit existing ports. The on/off status of the output joard. potters or the R3 and Ré ports ae cone The contents of PDR and DCR of the correspond- | For at on ee ee aR? in pin should be programmed to remain the same “3 Rh, Ru or. " vind RA. 0 an Hi as in the reset state. The corresponding pin should respectively. R4y, R4,, R42, and R43 pins are mul- 10 be used as a peripheral function I/O pin. Port mode register B (PMRB: $005) [ors] onz |e [oro] | Prescaler | Pulse frequency divide ratio | _(@ = 1.9 us) |? He te | UT Ee Settee —| | [ exe [2 fo tone [4 |TGooutputpin | es f° [OetOnn Figure 18 Port Mode Register B Functions | M445b204 0048453 107 604 Hitachi

: if ALT : Pul-up MOS Hi PMOS (A) Lee fel a DCR -——— PDR NMOS (B) — — [>> ru input P7777" indicates Seooecaa an option Input contro! Mask Option With Pull-Up MOS (B) With Pull-Up MOS (C) = DCR (data contro! register) 0 1 0 1 PDR (port data register) o 1 oOo 1 o 41 o 1 CMOS —PMOS (A) —- -—- — On - -—- = On butter NMOS(B) === — — On — — — on = Pull-up MOS (C) On On On On - - - = Eee Notes: 1: On 0: Off —: Off Figure 19 1/O Buffer Configuration (Standard Pins) myysb204 oo4syby O43 mm 605 Hitachi a

Table 3 1/0 Pin Circuit Types Standard Pins Pin Type _With Pull-Up MOS (B) Without Pull-Up MOS (C) Pin Name vo Input Input to R: common control [> Sout control "Tp Spa Pp t0 RSs pins Voe Weg [rer Ve Lxcr_] Oy Org C_[ ocr ] OM C_f{oer | © _ @ “Lea Fe [pit trea] Dp cpu vos ou Fido to Rds Yoo Weg Lar ] cnr inp Oy beg Leer] Vor © ‘al gy ay [ oon | (Aroq [ra] © od ee Ce) Note: Cannot be used as an analog input pin (ANg to ANs). input Veo TNT, INT, Kt] © — = Can i i pny Mi 4496204 OO4S4LS TST mm 606 Hitachi

I Le; Sennen HD404304 Series ee ss—S—SSSSSCS 404304 errs Table 3_1/O Pin Circuit Types (cont) High-Voltage Pins Pin Type __ Without Pull-Down MOS (D) With Pull-Down MOS (E) Pin Name vO Dot o to Dia, common Voc Vox Rg to RO, pins G4 GH Rig to Ris, @® [ror] @) : Leon] Reo to Rag Nee Vewp : cpu spat D> fo aD wa inpot SSS a pins Input Note: In the stop mode, the MCU is reset, Peripheral functions cannot be selected, HLT becomes 1 ,and /O pins are in high impedance. Circuit type Pe c Product type Mask ROM (HD404302R, HD404304) zrat™ MA V1 (HD4074308) VAN VAN bb Slb We 4456204 00484 607 Hitachi | Neen ee

Reset reset and the status of each after the reset has been carried out. Setting the RESET pin high resets the MCU. At power-on or when cancelling stop mode, the reset Note: After reset, the standard pin port data regis- must satisfy tac for the oscillator to stabilize. In all ter (PDR) is not stable. Therefore, write the other cases, at least two instruction cycles are data to the standard pin port data register required for the MCU to be reset. (PDR) and set data control register (DCR) to Table 4 shows the components initialized by MCU output the data. a Table 4 Initial Values after MCU Reset Item Initial Value Contents Program counter (PC) $0000 Execute program from the top of ROM address Status flag (ST) 1 Enable branching with conditional instructions Stackpointer(SP) SSPE StacktovelisQ vo High-voltage pin port data All bits are 0 Enable to output 0 register(POR) Standard pin port data - Enable to output 1 (with pull-up MOS) | register (PDR) Data control register (DCR) Allbits are 0 Output butfer is off (high impedance) Port mode register A (PMRA) 0000 See Port Mode Register A section Port mode register B (PMRB) 0000 See Port Mode Register B section Interrupt Interrupt enable flag (IE) 0 Inhibit all interrupts flagsimask i Interrupt request flag (!F) 0 No interrupt request Interrupt mask (IM) 1 ‘Mask interrupt request Mode Timer mode register A (TMA) 0000 See Timer Mode Register A section registers Timer mode register B (TMB) 0000 See Timer Mode Register B section Timer/ Timer counter $00 = counter Timer counter B (TCB) $00 — Timer load register (TLR) $00 - Prescaler $000 See Prescaler section AD AID port select register (ADPR) 0000 See A/D Port Select Register section AND mode register (AMR) 0000 ‘See A/D Mode Register section AVD data register (ADR) $80 See A/D Data Register section A\\D start flag (ADSF) 0 See A/D Start Flag section Bit register. Watchdog timer on flag(WDON) _0 See Timer A section Note: Registers and flags except above become as follows after MCU reset. Mm 445b204 OO484L7 652 608 Hitachi On

OT — — — and Rant HD404304 Series $A EI ETE Table 4 Initial Vatues after MCU Reset (cont) After MCU Reset to Recover After MCU Reset to Recover Item Abbr. from Stop Mode trom Other Modes Cam flag IGA) pe cae Carry flag (CA) The contents of these items The contents of these items Accumulator. (A) _ following MCU reset are not following MCU reset are not Accumulator __(A) retained: they must be retained; they must be B register (B) reinitialized by software reinitialized by software W register (Ww) X/SPX register (SPX) YISPY register (Y/SPY) eT Ee RAM The contents of RAM just before MCU reset (just before a STOP instruction) are retained —— SSSSSSSSSSSSSSSSSSSSSFsFSSSSSSSSSSS oo4s4bs 795 myusbeou 609 Hitachi ————

Table 5 Example of Oscillator Circuits Circult Configuration Circult Constant External clock operation Extea osc, Open OSC2 Ceramic C Ceramic oscillator: CSA 4.00 MG oscillator (Murata) iy osc, Ry = 1 MQ 420% Ceramic C, = C2 = 30 pF +20% osc, Ce GND Crystal Ry = 1 MQ.420% ' oscillator cy Cy = 10 pF to 22 pF 420% josc, Co = 10 pF to 22 pF +20% Pe Crystal losc, ee Ce Crystal: Equivalent to the circuit GND shown at bottom left AT-cut paraliot Op = 7 pF max. resonance crystal Ag = 100 2 max. osc, -{ L Gr #5 }-oose, f= 1.0 MHz to 4.5 MHz Co Notes: 1. The circuit parameters written above are recommended by the crystal or ceramic oscillator manufacturer. The circuit parameters are affected by the crystal, ceramic oscillator, and the float- ing capacitance when designing the board. When using the resonator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC,, OSC», and other elements should be as short as possible, and avoid crossing other wires. Refer to the recommended layout of the crystal and ceramic oscillator (figure 21). M449b204 OO48470 347 611 Hitachi

a mode transition diagram of these modes. the /O pins. This is an additional current added to the standby mode current dissipation. Figure 22. MCU Operation Mode Transition

11404304 Series |

Stop Mode: Executing the STOP instruction brings _to stabilize. (Refer to AC Characteristics table.) the MCU into stop mode, in which the oscillator After the stop mode is cancelled, RAM retains the circuit and every function of the MCU stop. State it was in just before the MCU went into stop mode, but the accumulator, B register, W register, ‘The stop mode may be cancelled by resetting the —_X/SPX registers, Y/SPY registers, carry flag, and MCU. At this time, as shown in figure 24, reset A/D data register wilt not retain their contents. input must be applied for at least tac for oscillation Stop mode ossitatr TI __, AMM Internal clock RESET p { bt} | STOP instruction tres 2 tac (stabilization time) execution Figure 24 Timing of Stop Mode Cancellation WM 4496204 0048473 OSb mw 614 Hitachi

PROM Mode Pin Description (DP-42, DP-42S, DC-42) MCU Mode PROM Mode MCU Mode PROM Mode PinNo. PinName UO PinName 0 PinNo. PinName 0 PinName UO.

1 Dio vO Mp 1 22 AVoo Voo

3 D,aTG, VO Voce 24 R4/AN; VO Og vo

4 RAWVgisn | 25 RAYAN, UO Og vO

5 ROy vO Ay 1 26 R4/AN3 OO, vO

6 RO, vO Ap 1 27 «AV gg GND

7 RO, vo Ay | 28 RESET 1 Vpp/RESET

8 R03, WO Ay i 29 TEST ! TEST 1

9 Rig vO As jl 30 Osc, t

10 Rt, VO Ag 134 OSC, °

"1 Rip VO Ay 1 322 Veo Voc

12 Rig VO Ag 1 3 Dy VO Mo 1

13 2p VO Ag f 34 D, vo M, 1 14 RQ, VO Ax 1 35 Dp VO Ay !

15 Rep VO Ady 1 36 Pr) zz

16 R23. «UO Ayo 1 37 De COWOOA 1

17 F3p VO Op vo 38 Ds VO Aa 1

18 R3, vo Oy vO 39 De vo Ce 1

19 R3,/INTo WO Op, vo 40 Dy vO OE i

20 R3,/INT; VO Og vo 41 Dg ie}

Notes: /O: Inputoutput pin {: Input pin ©: Output pin M™449b204 0048474 TI2 mo 615 Hitachi a

PROM Mode Pin Description (FP-54) MCU Mode PROM Mode MCU Mode PROM Mode PinNo. PinName VO PinName UO Pino. PinName UO PinName VO 1 Dio VO Me 1 28 AVoo. Voo

2 DTG VO Vo 29 R4/ANo VO Oy vo

3 DTG, VO Veg 30 R4/AN; VO Os vo

4 RAWVosp | 31 R4yAN, VO Og vO

5 RO vo Ay i 32 R4/AN3 O_O, vo

6 NC 33 NC

7 NC 34 ONC

8 NC 35 NG

9 RO, VO Ae I 36 AVss GND

10 RO, VO As 1 37 RESET 1 Vpp/RESET

1 R03 VO Ay i 38 TEST i TEST '

12 Rig VO As I 39 osc, 1

13 Rt, VO As ' 40 OSC, °

14 Rip vO A; 1 41 Voc Voo

| 15 Rig VO As 1 42 Do vO My l

16 R29 VO Ao ' 43 D, vo M, i

17 R2, VO Ato i 44 De VO As I

18 R2p vO Any t 45 Ds vo

19 R23 VO Ar I 46 Ds vO Ais I

20 NC 47 NC

21 NC 48 NC

22 NC 49. NC

23 R3y VO Op vO 50 Ds vO Ais 1

24 R3; vo 0, vo §1 Ds vo CE I

25 R3INT) UO Op vO 52 D, vo OE 1

26 R3,/INT, VO 03 vO 53 Dg vo

27 GND GND 54 Dy vo

Notes: /O: Input/output pin t: Input pin O: Output pin NC: No connection Mi445b204 0048475 129 mt 616 Hitachi

eeeSSSSSSSSSSSSSSSsSsSSSSSSSSSSSSSSSS HD404304 Series ee IRONS Series: Programmable ROM (HD4074308) The MCU on-chip PROM is programmed in — Erasing conditions are: ultraviolet (UV) light with a PROM mode. PROM mode is set by pulling TEST —_ wavelength of 2537 A with a minimum irradiation low, and RESET, Mg, Mj, and M; high, as shown —_of 15 W-sec/cm2. These conditions are satisfied by in figure 25. In PROM mode, the MCU does not —_ exposing the LSI to a 12,000- W/cm? UV source operate. Table 7 shows the PROM mode selection. _ for 15 to 20 minutes at a distance of 1 inch. It can be programmed like a standard 27256 . EPROM using a standard PROM programmer and _— Precautions a 42-t0-28-pin socket adapter. Table 8 lists recom- oo. mended PROM programmers and socket adapters, __'- Addresses $0000 to $3FFF must be specified if the PROM is programmed by a PROM pro- Since an instruction of the HMCS400 series con- grammer, If addresses of $4000 or higher are sists of 10 bits, the HMCS400 series MCU incorpo- accessed, the PROM may not be programmed or rates a conversion circuit to enable the use of a verified. Note that the plastic type packages can- general-purpose PROM programmer. By this cir- not be erased and reprogrammed. (Ceramic win- cuit, an instruction is read or programmed using 2 dow packages can be erased and re-programmed addresses, generated as the lower 5 bits and upper by ultraviolet light.) Data in unused addresses 5 bits. For example, if 8 kwords of on-chip PROM must be set to $FF. are programmed by a general-purpose PROM pro- grammer, 16 kbytes of addresses ($0000-$3FFF) 2 Be sure that the PROM programmer, socket should be specified. adapter, and LSI are inserted correctly (pin 1 Positions match). Using the wrong programmer Programming and Verification or socket adapter may cause an overvoltage and fe damage the LSI (table 8). Make sure that the The MCU can be high-speed programmed without LSI is firmly fixed in the socket adapter, and causing voltage stress or affecting data reliability. that the socket adapter is firmly fixed onto the programmer. Table 7 shows how programming and verification modes are selected. 3. The PROM should be programmed with Vpp = . 12.5 V. Other PROMS use 21 V. If 21 V is ap- Erasing plied to the MCU, the LSI may be permanently . damaged. 12.5 V is Intel’s 27256 Vp. PROMs with ceramic window packages can be erased by ultraviolet light. All erased bits are set tol. Table 7 PROM Modes Selection Pin Mode CE OE Vpp Ooto0, Programming Low High Vpp Data input Verification High Low Vpp Data output Programming High High Vpp High inhibited impedance M449b204 OO4847b 66S Ml 617 Hitachi a

Table 8 PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer ‘Type Name Manutacturer Package Type Name . DATA VO. 228 Hitachi DP-42 HS430ESD0O1H

298 DP-42S HS430ESS01H

AVAL Comp. PKW-1100 Hitachi DP-42 HS430ESD01H PKW-1000 DP-42S HS430ESS01H FP-54 HS430ESFO1H Note: An automatic programming mode of the PROM programmer is not available, therefore if a silicon signature check is performed, the AS port will be permanently damaged. The A9 port is a high-vottage VO port of the MCU. It will be damaged if an overvoltage (12.5 V) exceeding the voltage resistance of the MCU butfer is applied, When a connection check is made using a protection diode between the MCU and its socket, an open error occurs on an address port. Since the direction of the protection diode of the MCU high-voltage pin is reversed, the address port is regarded as open. = ‘g a Veo OE O cE CE s Data Opto Or Oo to O7 Address to Ay Ag to Arak ‘Ag to Aye Veo My vs TEST| oVpp Vpp/RESET AVoc © Voc AVsg GND | Figure 25 Connections for PROM Mode WM 4456204 0048477 7TL 618 Hitachi

RAM Addressing Modes When the BR instruction is on a page boundary | (256n + 255) (figure 28), executing it transfers the As shown in figure 26, the MCU has three RAM _PC contents to the next page according to the hard- addressing modes: register indirect addressing, ware architecture. Consequently, the program direct addressing, and memory register addressing. _ branches to the next page when the BR instruction . | . is used on a page boundary. The HMCS400-series Register Indirect Addressing Mode: The W cross macroassembler has an automatic paging register, X register, and Y register contents facility for ROM pages. (10 bits) are used as the RAM address. . . Zero-Page Addressing Mode: By executing the Direct Addressing Mode: A direct addressing Ct, instruction, the program can branch to the instruction consists of two words, with the word — zero-page subroutine area, which is located at (10 bits) following the opcode used as the RAM $0000-$003F. When the CAL instruction is exe- address. cuted, 6 bits of immediate data are placed in the . . low-order six bits of the program counter (PCs to Memory Register Addressing Mode: The memo- PCa) and 0s are placed Sarthe hi eh-order eight ‘bits Ty Tegisters (16 digits from $040 to $04F) are (PCy to PC) accessed by executing the LAMR and XMRA 13 ‘6 instructions. Table Data Addressing Mode: By executing the 7 . TBR instruction, the program can branch to the ROM Addressing Modes and the PInstruction isa determined by the contents of the 4-bit The MCU has four ROM addressing modes as immediate data, accumulator, and B register. , shown in figure 27. P Instruction: ROM data addressed by table data . A . addressing can be referenced by the P instruction : The Direct ter esine Mont memory space by (figure 29). When bit 8 in the referred ROM data is executing the JMPL, BRL, or CALL instruction, _!+ 8 bits of ROM data are written into the accumnu- ‘These instructions replace the 14 program counter lator and B register. When bit 9 is 1, 8 bits of ROM bits (PC}3 t0 PCo) with 14-bit immediate data. baal writen into the en oN Current Page Addressing Mode: The MCU has 8 _ ae written into the accumulator and B Tegister, and pages of ROM with 256 words per page. By exe- also to the R1 and R2 port output registers at the cuting the BR instruction, the program can branch same time. to an address in the current page. This instruction a ctect on the replaces the low-order 8 bits of the program e P instruction has no effect on the program counter (PC to PCp) with 8-bit immediate data. counter. wu me 4ysb204 0048476 B38 619 Hitachi Nene

[JMPL] [BRL] (CALL) instruction 1st word Instruction 2nd word Program counter |PC,3PC;2 PC, ;PC;9 PCy PC, PC, PC, PCs PC, PCy PC» PC, PCy Direct Addressing Instruction oe Program counter |PC,3 PC,z PC,,PC49 PCy PC, PC, PC, PC; PC, PC, PCz PC, PCy Current Page Addressing Inston = xy Program counter |PC,3 PC, PC, ;PC;9 PCy PCg PC, PC, PC, PC, PCy PC2 PC, PCy Zero Page Addressing Instruction ee rreRy Ps P21 Pe B register Accumulator ———> Bs B28: 0] As Aa Ar Ao] id pt UT TTT Program counter |PC,3PC;2PC;;PC4g PCy PC, PC, PC, PC; PC, PC, PC, PC, PC, Table Data Addressing Figure 27 ROM Addressing Modes Mi 4456204 0048480 256 me 621 Hitachi Cnn nn cnc cnnccncnc

—eerr 7 256(n - 1) + 255 (] BRAAA | 256n AAA NOP | BR AAA 256n + 254 BRBEB | 256n +255 | 256(n + 1) BBB NOP | Figure 28 BR Instruction Branch Destination on a Page Boundary Instruction ——— ii pA TT TTT | Referred ROM address |RA;3RAyp RA, RA;o Ag RAg RA? RAg RAs RA4 RA3 RAZ RA, RAg Address Designation ROM data |RO, RO, RO, ROs RO; RO, RO3 RO, RO, ROz| ROM data {RO RO RO, RO, RO; RO, RO, RO, RO, ROg Output registers R1, R2 (R23 R2, R2, R2o/Rig Alp At, Rio} If RO =1 Pattern Figure 29 P Instruction Mm 4456204 0048481 lee mt 622 Hitachi

ttem ‘Symbol Value Unit Notes Supply voltage Veco 0.3 to +7.0 Vv 1,12 Program voltage Vep 0.310 +14.0 v 2 Pin voltage Vr 0.3 to Voc + 0.3 Vv 3 Voo-45toVeg + 0.3 V 4 Total permissible input current Zl 50 mA 5 Maximum input current Ig 15 mA 7,8 Maximum output current oo 4 mA 8,9 6 mA 9,10 30 mA 9,11 Total permissible output current Llp 150 mA 6 Operation temperature Toor -20 to +75 °C Storage temperature Tig 55 to +125 °C Notes: 1. Normal operation should be performed under the conditions specified by the electrical characteristics. Exceeding these conditions can result in malfunction, degraded performance, and permanent damage to the LSI. 2. Applies to the RESET pin (Vpp). (HD4074308) 3. Applies to pins other than high-voltage pins. ; 4. Applies to high-vottage pins. 5. Total permissible input current is the sum of input currents which flow in from all /O pins to GND simultaneously. 6. Total permissible output current is the sum of output currants which flow from Vog to all /O pins ‘simultaneously. 7. Maximum input current is the amount of input current allowed from each I/O pin to GND. 8. Applies to R3 and R4. 9. Maximum output current is the amount of output current allowed from Vc to each I/O pin. 10. Applies to RO to R2. 11. Applies to Dg to Dia. 12. Voltage is based on GND.

4496204 O0484se OLD me 623 Hitachi

a |

— SSS

Electrical Characteristics

DC Characteristics (Voc = 5 V 10%, GND = 0 V, Viisp = Voc - 40 V to Voc, Ty = ~20°C to +75°C unless otherwise specified) tem Symbo! Pin Min Typ Max Unit Test Condition Notes ————$ OE est boncitton Notes Input high Vin RESET, 0.8Vog — Veo +03 V voltage INT, INT, osc, Vec-0.5 — Voc +03 V $$$ SN OS Input low Vie RESET, -0.3 — 0.2Ve¢ v voltage INTo, INT, osc, 0.3 = 0.5 Vv $s N Inpuvoutput =| |_| RESET, — - 1 HA Vin=OVtOVog 1 leakage INTo, current INT, Osc, te Current lec Voe = = 3.0 MA Veg =5V; 2,5 dissipation in fosc = 4 MHz active mode SSS | Current Isay Voc = _ 1.5 MA Veg =5V; 3,5 dissipation in fosc = 4 MHz standby mode Current Istop Voce - = 10 HA VitEST)= Voc 4 dissipation in Vin(RESET) = stop mode GND ee Stop mode Vstop Vee 2 _ - Vv retaining voltage — ee Notes: 1. Excluding pull-up MOS current and output buffer current. 2. The MCU is in the reset state. Input/output current does not flow. + MCU in reset state, operation mode + RESET, TEST: Voc + R3, R4: Vog + Do to Diz, RO to R2, RA}: Vgign | 3. The timer/counter operates with the fastest clock. Input/output current does not flow. + MCU in standby mode + Inpuvoutput in reset state + RESET: GND + TEST: Voc * R3, Rd: Voc | + Do to Dyp, RO to R2, RA4: Voign | 4, Excluding pulkdown MOS current. 5. When fogc = x MHz estimate the current dissipation as follows: Max. value foge = x MHz = x/4 x (max. value fog¢ = 4 MHz) T @ wr yyab2o4 oo484as T 624 Hitachi

Input/Output Characteristics for Standard Pins (Vcc = 5 V +10%, GND =0 V, Vaisp = Vcc ~ 40 V to Voc, Ta = -20°C to +75°C unless otherwise specified) item Symbol Pin Min Typ Max Unit Test Condition Note Input high Vw R3,R4 —0.7Veg ad Veg +03 V voltage Input low Vie R3,R4 0.3 - 0.2Vee v voltage Output high Vou R3,R4 Voc-1.0 — Vo on=1.0mA 1 voltage Voo-08 — V tow=0.5mA 1 Output low Vou R3,R4 — _ 0.4 v lot = 1.6 mA voltage Inpuvoutput =| In| R3,R4 — - 1 HA Vin= OVtOVeg 2 leakage current PulupMOS = —Ipy R3,R6 30 70 150 WA Voo=5V. 3 eurent ig OV Notes: 1. Applied to /O pins selected as CMOS output by mask option. 2. Pull-up MOS current and output buffer current are excluded. 3. Applied to /O pins selected as with pull-up MOS by mask option. Mm 4496204 0048484 931 625 Hitachi a

ny . HD404304 Series ooo Input/Output Characteristics for High Voltage Pins (Voc = 5 V +10%, GND = 0 V, Vaisp = Veo - 40 V to Voc, T, = -20°C to +75°C unless otherwise specified) fem Symbol Pin Min Typ = Max Unit TestCondition Note Input high Vin DotoDiz, 0.7Vec — Voc+03 V voltage Rt, R2, RA,, RO Input low Vit DotoDyz, Vec-40 — 0.2Ve¢ v voltage R1, R2, RA, RO Output high Voy, Dg toyz, Vec-30 — Vo lo = 15 mA Son TMA voltage TG 7G: \\.-20 — — V_ toy = 10 mA NH TOMA Veo-1.00 — Vi lon = 4 mA EN lo MA ROtoR2 Vec-30 — — v lo = 3 mA EN oH SMA Voo-2.0 — = — v wloy = 2 mA Se MA Veo-10 — v wloy = 0.8 mA Outputlow Voy Do to Dj, — — Vee-37. -V Veep = 1 voltage RO to R2 Voc - 40 V Ne HOV Doto Diz, — — Voc-37 V 150 kQ at 2 RO to R2 Vee - 40 V Mee FOV | Inpuvoutput = fly] gto Dy, — — 2 BA Vine Vog-40V 3 leakage RO to R2, to Voc current RA, =r nar Pulldown MOS: Ipp DotoDy2, 200 400 800 HA HD404302R, 1 current RO to R2 HD404304: Veigp = | Veco ~ 35 V, Vin = Voc Notes: 1. Applied to VO pins selected as with pull-up MOS by mask option. 2. Applied to /O pins selected as without pull-up MOS (PMOS open drain) by mask option. . 3. Pull-up MOS current and output buffer current are excluded. Mm 4456204 OO4848S5 876 626 Hitachi

AC Characteristics (Voc = 5 V 410%, GND = 0 V, Vuisp = Voc - 40 V to Voc, Ty = -20°C to +75°C unless otherwise specified) ttem Symbol Pin Min Typ Max Unit TestCondition Note Oscillation tose OSC;,,0SC,. 04 4 45 MHz frequency (divide-by-8) Instruction toye 178 2 20 us cycle time Oscillation tac OSC;,,08SC, — — 2 ms (Ceramic 1 stabilization oscillator) time 40 ms (Crystal) External clock top Osc, 04 — 45 MHz frequency External clock toprs, OSC, 2 —- — ns Divide-by-8 2 high and tor. low widths $$ External clock — tp, osc, _ - 20 ns 2 rising and topr falling times a INTy high and ty, INTo 2 - = teye 3 tow widths te i INT; high and tis, INT, 2 - = toye 3 lowwidths te _ a RESET high tasty RESET 20-5 tye 4 width Input HD404302R/ All pins — — »% pC capacitance HD404304 (except RESET) Cin RESET — — 0 p — HD4074308 All pins - -— 2 pF f=1MHz, Cin (except RESET) Vip = OV RESET — — 20 pF f=1MHz, Vin = 0V RESET tasti RESET — — 2 ms 4 falling time Notes: 1. The oscillation stabilization time is the period from when Vg reaches 4.5 V at power-on until when the oscillator stabilizes, or after RESET goes to high to quit the stop mode. At power-on or when cancelling the stop mode, RESET must remain high for at least tac. Since tac depends on the crystal or ceramic oscillator's circuit constant and stray capacitance, it is recommended that the user follow the crystal or ceramic oscillator manufacturer's recommendations when designing the reset circuit. Applies to the HD404302R, HD4074308, and HD404304. co c 8% Crystal: H-491u ct OS: Ceramic oscillator: CSA 4.00 MG crystaie ry (4.19304 MHz: Kinski) Goramic& SR (Murata) | Ry=1 MO 220% Fy=1 MQ. 420% iz JOscp Cy = Cp = 20 pF 20% Josc, Cy = Cp= 30 pF 220% Se & GND GND 2. See figure 30. 3. See figure 31. 4. See figure 32. M44sb204 OO484ab 704 me 627 Hitachi a

———— OO SsSsSSSSSSSSSsSSSSSSSSSSSSSSSSS A/D Converter Characteristics (Vcc = 5.0 V +10%, Vsg = AVgg = GND, Ty = 0°C to +70°C) tem ‘Symbol Pin Min Typ Max Unit Test Condition Notes $$ esol Notes Analog power AVgg AV Veo-0.3 Vog Voc +0.3 V supply voltage Analog input = AVin Noto ANs AVgg = — ~— AV Vv voltage ee Current between lap - 0.08 — mA AV oc and AVgg pl hace Analog input = CA, ANgtoANy — 5 pF capacity a Resolution _ - _ 8 - Bit Conversion - - 61 — 536 us 1 time Number of _ - 0 - 4 Channel inputs meee Absolute - _ - - $2 LsB Ta = 25°C, 1,2 accuracy Veco = 5.0 V, fosc = 1 MHz to

4.5 MHz

Input - ‘ANo to AN3 1M - - Q impedance a SSSSSSSSSSSSSSSSssSssSsssS Notes: 1. The operating frequency fog¢ of the A/D conversion is from 1 MHz to 4.5 MHz. 2. When using the R4/AN port as an analog input, the /O option of the R4 port must be set as without pull-up MOS. Mzy4sbe04 0048487 bYO 628 Hitachi

Please pay attention to the following items regard- ‘The 4 k-word data size is required to change ROM ing ROM out. data to mask manufacturing data since the program used is for a 4 k-word version. On ROM out, fill the ROM area indicated below . with 1s to create the same data size for the This limitation applies when using an EPROM or a HD404302R as an 4 k-word version (HD404304), data base. SSeS ROM 2 k-word version: HD404302R $0000 Vector address $000F $0010 Zero-page subroutine = cen $003F $0040 Pattern & program (2,048 words) $O7FF — | $0800 [2 See ee Pee ees [poe SOFFF iboats oes] Fill this area with 1s Mm 4496204 0048489 413 mm 630 Hitachi

HD404302R and HD404304 Option List a Please check off the appropriate applications and enter [Companyname | the necessary information. Deparment 1. ROM size Name HOES frowns D HD404304 LSItype: 2. VOoption Note: V/O options masked by [i] are not available | 03 | fo heey [Ri3| 2 | v0 Pee gO Toei Td [R23 | [vo Tee | oo | ¢ pop [pst] , [vo oy | o2 | (OE Tl [Rao | 8 [vO [ey aa B: CMOS output with pull-up MOS ¢: CMOS D: Without pull-down MOS (PMOS open drain) E: With pull-down MOS Note: * If pin R4/AN is used for analog input, select it with CMOS output (V/0 option C). 3. RA1Ndisp CI RAT: Without pull-down MOS (D) O Vaisp Note: If even one high-voltage pin is selected with /O option E, pin RA1/Vdisp must be selected to function as Vdisp. 4. ROM code media Please specity the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). TI EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 5. System oscillator for OSC1 and OSC2 6. Stop mode 7. Package Tceranicoscntor [T= We Doe myuse204 O048450 135 mm 691 Hitachi a

Selected Specification

Hitachi Semiconductor HD404304P overview.

Summary

CMOS 4-BIT SINGLE-CHIP MICROCOMPUTER

Description

CMOS 4-BIT SINGLE-CHIP MICROCOMPUTER

Source title HD404304P Datasheet(PDF) - Hitachi Semiconductor

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