HD404201FP

Hitachi Semiconductor

CMOS 4-bit Single-Chip Microcomputers with the same architecture as the HMCS400 Series

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HD404202 HITACHI

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These MCU’s are CMOS 4-bit single-chip micro- + HMCS400 CPU (software-compatible with the computers with the same architecture as the HMCS400 Series) HMCS400 Series. Each microcomputers incorpo- + 1024-word x 10-bit mask ROM (HD404201, rate ROM, RAM, J/O, and peripheral functions HD40L4201) such as one or two timer/counters. Also, + 2048-word x 10-bit mask ROM (HD404202, HD404222 Series has two-channel comparators, HD40L4202, HD404222, HD40L4222) and a serial interface. * 4096-word x 10-bit PROM (HD4074224) + 64-digit x 4-bit RAM (HD404201, HD40L4201, The HD404202 Series includes four chips: the HD404202, and HD40L4202) HD404201 with 1-kword ROM and 5-V operation; 128-digit x 4-bit RAM (HD404222, HD40L4222, ; HD40L4201 with 1-kword ROM and low-voltage and HD4074224) operation; HD404202 with 2-kword ROM and 5-V =. 22:1/0 pins including 10 high-current pins operation; HD40L4202 with 2-kword ROM and. Two timer/counters low-voltage operation. The HD404222 Series — 8-bit free-running or watchdog timer (watch- includes three chips: HD404222 with 2-kword dog timer is selectable by mask option) ROM and 5-V operation; HD40L4222 with (HD404222 Series) 2-kword and low-voltage operation; HD4074224 — 8-bit auto-reloading timer/event counter with 4-kword PROM. * Clock-synchronous 8-bit serial interface The HD4074224, incorporating PROM, isaZTAT™ =, iaiainate Sr alors microcomputer which can dramatically shorten (HD404222 Series) system development period and smooth the process. — Two analog input pins from debugging to mass production. (The PROM — Reference voltage pin program specifications are the same as for the. One external interrupt 27256.) + Low-power dissipation modes — Standby mode — Stop mode Features * Built-in oscillator — Resistor or ceramic oscillator (an external + The differences between HD404202 Series and clock is also possible) HD404222 Series. * Minimum instruction cycle time — 0.89 ps (fosc = 4.5 MHz, Voc = 3.5 V- 1404202 Series _HD404222 Series 6.0 V) RAM (digits) 64 128 — 3.55 us (fosc = 1.125 MHz, Voc = 2.5 V- Timers B-bit x 1 8-bit x2 6.0 V) “Seraiinetace = neaynchronous «= — 2.088 (fosc = 2.0 MHz, Voc = 2.5 V-6.0 V) B-bit x1 for HD40L4222 Comparators — 2 channels + Package — um — — 28 pin shrink-type plastic DIP (DP-28S) — 28-pin SOP (FP-28DA) — 30-pin SSOP (FP-30D) me 4496204 0047390 3 4e1 Hitachi ee

HD404202 Series/HD404222 Series Type of Product ROM Device Size Options Package aes pons Package Mask ROM HD404201S 1024 Selected by mask option DP-28S HD40L4201S HD404201FP FP-28DA HD40L4201FP HD404201FT FP-30D HD40L4201FT HD404202S 2048 DP-28S HD40L4202S. = HD404202FP FP-28DA HD40L4202FP HD404202FT FP-30D | HD40L4202FT HD404222S DP-28S HD40L4222S HD404222FP FP-28DA HD40L4222FP HD404222FT FP30D HD40L4222FT ZTAT™ HD4074224S01 4096 ‘Timer A: Free-running timer DP-28S Oscillator: Resistor HD4074224S02 Timer A: Free-running timer Oscillator: Ceramic oscillator HD4074224S03 Timer A: Watchdog timer Oscillator: Resistor HD4074224S04 Timer A: Watchdog timer Oscillator: Ceramic oscillator HD4074224FP01 ‘Timer A: Free-running timer FP-28DA Oscillator: Resistor HD4074224FP02 Timer A: Free-running timer Oscillator: Ceramic oscillator HD4074224FP03 Timer A: Watchdog timer Oscillator: Resistor HD4074224FP04 Timer A: Watchdog timer Oscillator: Ceramic oscillator HD4074224FT01 Timer A: Free-running timer FP-30D Oscillator: Resistor HD4074224FT02 Timer A: Free-running timer Oscillator: Ceramic oscillator HD4074224FT03 Timer A: Watchdog timer Oscillator: Resistor 1HD4074224FT04 Timer A: Watchdog timer Oscillator: Ceramic oscillator _—— J eee trai sce MB 4496204 0047391 273 a 462 Hitachi

ee eSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSFFFsese HD404202 Series/HD404222 Series i SSSSSSSSSFFSFSSSSSOFS OE orrr—r—ce_ePeeveve’s Differences between Mask ROM and ZTAT™ Microcomputers Mask ROM zar™ tem HD404201 HD40L4201 0404202 HO40L4202 =HD404222 -HD40L4222 ~HD4074224 = Hoan? _HowoLé2e2 0404222 HD40L4222_ HOMOTE224 Power supply voltage 351060V 25106.0V 35060V 25060V 3506.0V 251060V 35055V, (Wee) 2.7035V Se 2S time (ty) 2.0 10 10.0 4s TOM 2.910 10.08 ROM 1024 x 10-bit 1024 x 10-bit 2048 x 10-bit 2048 x 10-bit 2048 x 10-bit 2048 x 10-bit 4096 x 10-bit TE TURAN TOBE _2OMB 1O-DK_2OKB HC 1O-bR _2048x 10-bH 200 x 10-bit 40082 10-00 RAM Bax abit GAx adit — G4 x4bit Ax Abit ZB x Abt -12Bx4DI 128 4-dIt SAAT ABH AMC CA mab ZB Kab 12 Kab 128 x4 Watchdog timer/ - =- - - 1 1 1 free running timer Serial interface = = = = a ‘Comparator =- - = - 2ch 2ch 2h vO pin Without Available Available Available Available Available Available - , drouit pull-up (standard MOS pins) (NMOS ‘pen drain) (option A) With pull-up Available Available Available Available Available Available Available Mos {option B) ‘CMOS Available Available Available Available Available Available - {option C) Clock Ceramic Available Available Available Available Available Available Available Se -Resistor Available with — Available with — ‘Available with — Available only tye = 1.33 t0 tye = 1.3310 ye = 1.33 10 under Voc = 40s 40ps 4.0 ps 35055V With toye = 1.33 to40ps Extemal Available Available Availabe Available Available Available Available Package ‘OP-28S DP-28S DP-28S DP-28S DP.28S DP-28S DP-28S FP-28DA FP-28DA FP-28DA FP-28DA FP-28DA FP-28DA FP-28DA FP-30D FP.30D_ FP.30D FP-30D FP-30D FP-30D FP-30D WM 4496204 0047352 137 463 Hitachi ma

HD404201, HD40L.4201, HD404202, HD40L.4202 Gnd C1 28 (] Rg ne (1 30 [Ne Rip C2 27 [T) Rap eno (2 29 [7] R2g a1, C3 26 [7] R2, Rip (13 28 [7] R2, Rip 4 25 [7] Rao Ri, C4 27 Ra, Rig C15 24 1 Dig Rip O15 26 |] R2y Do Cle 23 1D, Rig Cle 25 [1 Dg pv, C7 op-28s_- 22 1) Test 007 egg 24 FDe | D2 (J8_ FP-28DA 21 [] RESET ov, Cs 23 [1] TEST D3 C9 20 [7 osc, Dd, C9 22 [[] RESET D, C10 19 [J ose, bd, C10 21 [J osc, pg/iNT (11 18 [1] Veco po, C1 20 [7] osc, Ds C12 171700, D,/INT [12 19 7) Veg pb, C13 16 [7] Dig bd, 13 18 11D,, dD, O14 15 [1 Dy bo, (14 17 Dy ob, C15 16 (Dy 1D404222, HD40L4222, HD4074224 eno (1 28 [7] Rag ne (1 30 |] Nc Rip C2 27 7) Rap eno C2 29 [7] Rag ri, C13 26 |] Ra, Ri, 13 28 [7] Rep Rig C4 25 [[] Ra Ri, C4 27 Ra, Rig Cs 24 1 Djs Ri, Cs 26 [7] Ray Do Cle6 23 FD» Ri, C16 25 1 Dg o, C7 p-2es_ 22 Test Do 17 pogop 24 Pe 0, (8 FP-28DA 21 [1] RESET o, Cs 23 [7] Test bd, Ce 20 (F] osc, D. C19 22 [[] RESET Dd, C10 19 [J osc, D3 C10 21 [F) osc, DsNT (J 11 18 [1] Veo o, O11 20 [J] ose, D./SCK (12 17 11 D,,/ComP, Dg /INT [1 12 19 [7] Veg post 113 16 [1] Dy/COMP, D,/SCK (13 18 [1] D,,/COMP, Dg/so [14 15 [1] DyMeet b,st (14 17 [71 D,/COMP, Dg/so (15 16 [7] Dy rer mm 4496204 0047393 O7b 464 Hitachi

HD404202 Series/HD404222 Series eee NE Sere 22 Serle Block Diagram HD404201, HD40L.4201, HD404202, HD40L.4202 a t RESET TEST OSC; OSC2 ia r it 1024 x 10-58 [ inorpe corerot | 2048 x 10-be fee = _ _ | z [TT cea j mts ee = [ x ] = [8 lao] e0] TRB R22 R2y Reo; IRYg Aig RYGAYo} (Drs Ogi Ory Dio Dg Og Dy Dg Qs Os Oy Oe 01 Op High-eurent pins 404222, HD40L4222, HD4074224 Bil, | 84 28 9 ie BY ear rere op eo Ease tes 4096 x 10-b4 Int ROM 5 | ——— oF a =o FTI ew fi [ x | 3 CET 5g See Senos Rts Ble Ba Oa Drei Oa Coke OY, oS Dr! Dg Det Oy Da Oz Dy Op Me 4456204 0047394 Toe me 465 Hitachi a

HD404202 Series/HD404222 Series Pin Description Pin Number DP-28S ftem Symbol FP-28DA FP-30D W/O Function Power supply Voc. 18 19 Power supply pin GND 1 2 Ground connection pin Test TEST 22 23 | Pin used for test purposes only. Connect it to ground. Reset RESET 21 22 1 MCU reset pins Oscillator OsC,, 19 20 1 Pins for the internal oscillator circuit. Connect them to a resistor or a ceramic oscillator, or connect osc, 20 2 O OSC, to an external oscillator circuit, The internal | oscillator is selected by mask option. Port Do-Dis 6-17, 7-18, VO Inputoutput ports addressable by individual bits. 23, 24 24, 25 Pins D,2 and Dg can output 15 mA maximum. Rlp-R2, 2-5, 3-6, VO Input/output ports addressable in 4-bit units. These 25-28 26-29 pins can output 15 mA maximum. Interrupt int 1 12 1 Input pin for external interrupt. It is also used as an external event input for timer B. It is multiplexed with pin Ds. Serial SCK 12 13 VO Serial interface clock input/output pin, ttis interface* multiplexed with pinDg. plexed with pin D>. so 14 15 O Serial interface transmit data output pin. It is multi- plexed with pin Dg. Comparator* Vie 15 16 1 Reference voltage pin to input the threshold voltage of the analog input pins COMPy, 16,17 17,18 | Analog input pins for the voltage comparator COMP, * Only applicable for the HD404222 Series. M@™ 4496204 0047395 949 me 466 Hitachi

.). SS SSS HD404202 Series/HD404222 Series $$ EE |S S ss aes Memory Map ROM Memory Map flag cannot be set by software. The RSP bit is used only to reset the stack pointer. The areas in ROM are described below with its memory map shown in figure 1. Note that if unusable bits are manipulated, the MCU may malfunction (HD404202 Series: bits 0, 1 of Vector Address Area: Locations $0000 through S001, and $002; HD404222 Series: bits 2, 3 of $0009 can be used for JMPL instructions to branch $002). to the starting address of an initialization program for interrupt programs, After MCU reset or an Special Function Registers Area ($003 to $00C): interrupt is performed, the program is executed The special function registers are the mode or data from a vector address. registers for external interrupt, the serial interface, the timer/counters, comparator and are also used as Zero-Page Subroutine Area: Locations $0000 data control registers for 1/0 Ports. These registers through $003F can be used for subroutines. The are classified into three types: write-only, read- | CAL instruction branches to subroutines within only, and read/write, as shown in figure 2. These this area. registers cannot be accessed by RAM bit manipula- tion instructions (except for CMR register). Pattern Area ($0000 to $03FF: HD404201, HD40L4201; $0000 to $07FF: HD404202, Note that if the unusable locations are set, the MCU HD40L4202, HD404222, HD40L4222; $0000 to may mulfunction (only applicable for HD404202 $OFFF: HD4074224): The P instruction allows Series $003, $005 to $008 and $00C). reference to ROM data in this area as a pattern, Data Area ($020 to $03F: HD404202 Series; Program Area ($0000 to $03FF: HD404201, — $020 to $07F: HD404222 Series): The 16 digits of HD40L4201; $0000 to $07FF: HD404202, $020 through $02F are called memory registers HD40L4202, HD404222, HD40L4222; $0000 to (MR) and are also accessible by the LAMR and SOFFF: HD4074224) XMRA instructions (figure 4). RAM Memory Map Stack Area ($0E0 to $0FF): Locations SOEO through SOFF are reserved for LIFO stacks to save In addition to data and stack areas, interrupt control__the contents of the program counter (PC), status bits and special function registers are also mapped _ flag (ST), and carry flag (CA) when a subroutine in RAM memory. The RAM memory map shown call (CAL or CALL instruction) or interrupt is per- in figure 2 is described below. formed. This area can be used as an 8-level nest- ing stack in which one level requires 4 digits. Interrupt Control Bits Area ($0000 to $0002): Figure 4 shows the stack area levels. The program The interrupt control bits area (figure 3) is used for _ counter is restored by the RTN and RTNI instruc- interrupt control. This area and CMR (location tions. The status and carry flags are restored only $03) register is accessible only by RAM bit manip- _ by the RTNI instruction. When this area is not ulation instructions. However, the interrupt request _used asa stack, it becomes available as a data area. M™ 4496204 0047396 865 ml 467 Hitachi Nee eeneeee

HD404202 Series/HD 404222 Series HD404201, HD40L4201, HD404202, HD40L.4202 te) $0000 0 JMPL instruction $0000 Vector address 14{__(Wump to reset routine) _|$0001 9 $0009 2 JMPL instruction $0002 10 $000A 3|__(Jump to INT routine) —|$0003 (64 words) - - 63 $003F 6|_— JMPLinstruction _|$0006

64 Hb404201, HbéoL4201 | $0040 7|_(Jump to timer B routine) |$0007

1023 (1024 words) SO3FF 9 $0009 10241] 404202, HD40L4202 | $0400 program/pattern 2047 (2048 words) $O7FF HD404222, HD40L4222, HD4074224 Vector address 1|_(Jump to RESET routine) |$0001

2 UMPL instruction _|$0002

Pe bead 3[_Wump to INT routine) ~}so003 ; 4[- JPL instruction __|$0004 Zoro-page subroutine er eg 63 s00aF 6|_ — JMPLinstruction —_}$0006 e4 $0040 7[_(Wump to timer B routine) |$0007 0404222, HD40L4222 8 JMPL instruction _|$0008 program/pattern 9[__ (Jump to serial routine) _|$o009 (2048 words) 2047 $O7FF 2048 $0800 HD4074224 program/pattern (4096 words)

4095 SOFFF

468 Hitachi

SsSsSsSsSSssssSsssSsSSSSSSSSSSSSSSSSSSSsS HD404202 Series/HD404222 Series ee een ee SETS HD404201, HD40L4201, HD404202, HD40L4202 0 $000 0 $000 RAM mapped registers Interrupt control bits (82 digits) 2 $002 31 $01F 3 $003 32|” Memory registers (MR) [$020 4| Port mode register (PMA) Lw_|soos 47 (16 digits) $02F 5 $005 a 03 “ Data (16 digits) soar Not used 64 $040 8 $008 9 [Timer mode register B (TMB | w_|soo9 Not used 101 Finer ge TCBLIATLRL) $00A (160 digits) aa [Timer 8 TCBU)(TLRU) $00B Pe 12 $00c 223 $oDF 224 $0E0 Not used Stack (32 digits) 255 (2 dats) SOFF 31 SO1F HD404222, HD40L4222, HD4074224 ° $000 0 $000 RAM mapped registers Interrupt control bits, (82 digits) 2 $002 31 $01F 3[ Comparator mode register (CMR) TR/W| $003 32] Memory registers (MR) $020 4 [Pont mode register (PMR) W $004 a7 (16 digit) $o2F 5 | Serial mode register (SMAY | w }so0s 48 $030 6 | Serial data register lower (SRL) RAW] $006 Data (80 digits) 7 [Serial data register upper (SRU [RW] $007 8 [ Timer mode register A (TMA) [_w_|soo8 127 betta 9 | Timer mode register B (TMB) [Ww _|so09 128 10 Timor ge TOBLIATLAL), [RAW] $00A Not used af "mer 8 TCBU)TLRU) [RAW] $008 (96 digits) 12 | Reference voltage select register (RSA)|R/W|$00C 223 $oDF itacl ligits)

255 SOFF 31 jSO1F

Note: The status flag becomes invalid when CMR bits are tested by the TM or TMD instructions (only applicable for HD404222 Series). Timerevent counter Blower!» | Timer load register B | fea ony to (TCBL) iR lower (TLRL) _} W| $00A ite on : - F ‘ Timerfevent counter B upper: | Timer load register B_ FW: Read/Write " (TCBU) iR upper (TLRU) _} W | $008 * Two registers are mapped on the same address. Figure 2 RAM Memory Map M@™ 4456204 0047398 658 ml 469 Hitachi a

HD404202 Series/HD404222 Series SESE @€ res Functional Description Registers and Flags X and Y registers, respectively. The MCU has eight registers and two flags for © Carry Flag (CA): The carry flag stores the over- CPU operations (figure 5). flow from the ALU generated by an arithmetic operation. It is also affected by the SEC, REC, Accumulator (A), B Register (B): The 4-bit accu. © ROTL, and ROTR instructions. mulator and B register hold the results of the arith- metic logic unit (ALU), and transfer data to/from During an interrupt, the carry flag is pushed onto memory, I/O, and other registers. the stack and is pulled from the stack only by the RTNI instruction. X Register (X), Y Register (Y): The X and Y reg- isters are 4-bit registers used for indirect address- | Status Flag (ST): The status flag holds the ALU ing of RAM. The Y register is also used for D port overflow, ALU non-zero, and the results of a bit addressing. test instruction for arithmetic or compare instruc- Pe tions. The status flag is also used as a branch con- SPX Register (SPX), SPY Register (SPY): The dition for the BR, BRL, CAL, and CALL 4-bit registers SPX and SPY are used to assist the instructions. The value of the status flag remains ee 3 t) [a] Accumulator 3 0° 3 0 3 ° Veit 3 0 SPX rg 3 0 SPY register cary tag Status flag 44 0 Zz 4 o ae Figure 5 Registers and Flags WM 4456204 0047400 O36 me 471 Hitachi Neen nnnnnn

HD404202 Series/HD404222 Series unchanged until the next arithmetic, compare, or Stack Pointer (SP): The stack pointer (SP) is used bit test instruction is executed. The status flag to point to the address of the next stack area (up to becomes a 1 after the BR, BRL, CAL, or CALL 8 levels). instruction was either executed or not. During an interrupt, the status flag is pushed onto the stack The stack pointer is initialized to RAM address and can be pulled from the stack only by the RTNI _SFF. It is decremented by 4 when data is pushed instruction. onto the stack, and incremented by 4 when data is pulled from it. The stack can only be used up to 8 Program Counter (PC): The program counter isa _levels deep because the upper 3 bits of the stack 12-bit binary counter which controls the sequence _ pointer are fixed at 111. in which the instructions stored in ROM are exe- cuted. Table 1 Initial Values After MCU Reset | Initial Vatue by MCU Reset Item (RESET =0) Contents Program counter ‘$0000 Execute program from the top of ROM (Pc) address Status flag (ST) 1 Enable branching with conditional branch instructions Stack pointer (SP) $OFF Stack level is 0 VOpins, Without pull-up MOS 1 Enable input output registers “Win pull-up MOS 1 Enable input CMOS 1 _- Interrupt flags Interrupt enable flag (IE) ° Inhibit all interrupts and mask Interrupt request flag (IF) 0 No interrupt request Interrupt mask (IM) 1 Mask interrupt request Mode registers Port mode register (PMR) 000 ‘See Port Mode Register section Serial mode register (SMR)* 0000 ‘See Serial Mode Register section Timer mode register A (TMA)* 0000 See Timer Mode Register A section Timer mode register B (TMB) 0000 See Timer Mode Register B section Comparator mode register (CMR)* 00. See Comparator Mode Register section Comparator Reference voltage select 0000 See Reference Voltage Select register (RSR)* Register section Timer/counters, _Prescaler $000 = serial interface Timer counter A (TCA)® $00 = Timer counter B (TCB) $00 =_= Timer load register B (TLR) $00 - Octal counter* 000 = * Only applicable for the HD404222 Series. Me 4496204 0047401 T?e 472 Hitachi

a SSSSSSSSSSSsSSSSsSsSsssssssSSSSSsse HD404202 Series/HD404222 Series SS 0 0eE ee The stack pointer is initialized to SFF by either Table 1 shows the components initialized by the MCU reset or RSP bit reset by the REM/REMD — MCU rescl, and the status of cach component. instruction. Table 2 shows how registers recover from the stop Reset mode, The MCU is reset by pulling the RESET pin low. Take note that the reset signal is not acknowledged At power-on or when cancelling the stop mode, the immediately at power-on by the MCU but at the reset period must satisfy tac for the oscillator to —_time the oscillator has stabilized, so during this stabilize. In other cases, at least two instruction period the statuses within the MCU and at the I/O cycles are required for the MCU to be reset. pins are not defined. eee Table 2 Initial Values After MCU Reset After MCU Reset to After MCU Reset to ; item Recover from Stop Mode Recover from Other Modes ee erreeran~ OOOO rere eee Carry flag (CA) The contents of the items The contents of the items ‘Accumulator. (A)”~O«~t«~C:«é Woe MCU reset are not before MCU reset are not Accumulator __(A) retained and must be intial retained and must be initial- B register (B) ized by software. ized by software. X/SPX registers (X/SPX) Y/SPY registers (YISPY) Serial data register (SR)* a RAM The contents of RAM before The contents of RAM before MCU reset (just before the MCU reset are not retained STOP instruction) are and must be initialized by retained. software. EE * Only applicable for the HD404222 Series, Mm 4usb204 GO47402 905 mm 478 Hitachi Cnc n ncn c nnn n nn

HD404202 Series/HD404222 Series Interrupts conditions corresponding to each interrupt source. ‘Two interrupt sources are available on the MCU of _ An interrupt request is generated when the IF is set HD404202 Series. They are an external request to 1 and IM is 0. If the IE is 1 during this period, (INT) and timer/counter (timer B). HD404222 the interrupt will be activated and vector addresses Series has four interrupt sources: the two sources will be gencrated from the priority PLA corre- ‘stated above, timer A and serial interface. Foreach sponding to the interrupt sources. source, an interrupt request flag (IF), interrupt mask (IM), and interrupt vector addresses are pro- _—_ Figure 7 shows the interrupt processing sequence, vided to control and maintain the interrupt request. and figure 8 shows the interrupt processing An interrupt enable flag (IE) is also used to control _ flowchart. If an interrupt is requested, the instruc- interrupt operations. tion being executed finishes in the first cycle. The IE is reset in the second cycle. Also in the second Interrupt Control Bits and Interrupt cycle and third cycle, the carry flag, status flag, Operation: The interrupt control bits are mapped and program counter are pushed onto the stack. | on $000 through $002 of the RAM. These bits are —_ Included in the third cycle is the generation of the accessible by RAM bit manipulation instructions. _ vector address. The interrupt request flag (IF) cannot be set by software. At MCU reset initialization, the IE and —_At each vector address, program the JMPL instruc- IF are cleared to 0, and IM is set to 1. tion to branch to the starting address of the inter- rupt program. The IF which caused the interrupt Figure 6 is a block diagram of the interrupt control _ must be reset by software in the interrupt program. circuit. Table 3 shows the interrupt priority and vector addresses, and table 4 shows the interrupt Table 3 Vector Addresses and Interrupt Priority HD404202 Series HD404222 Series Reset/interrupts Priority Vector Addresses Reset/Interrupts Priority Vector Addresses RESET - $000 RESE - $000 WT 1 $002 WT 1 $002 Timer B 2 $006 Timer A 2 $004 Timer B 3 $006 Serial 4 $008 Table 4 Interrupt Conditions HD404202 Series HD404222 Series Interrupt Control Bits INT Timer B Interrupt __ eT ~*«CR tro Bits__INT __ Timer A_TimerB_ Serial IFEX - IMEX 10 a a te -iMTst=<“C~Ssti‘i< tStSC*«*é«SRX = IMEX 1 0 ° 0) * indicates don't care ETACIMIA ot dt lg IFTB : IMTB * * 1 o IFS - IMS * bd * 1 * indicates don't care

474 Hitachi

mm 4496204 CO47403 845 mm meen

a HD 404202 Series/HD404222 Series eee ; = No ! Yes Yes an, Yes Stack <{PC) Stack (CA) Stack «(ST) Yes Timer-B Cc indicates only applicable! (cerial interrupt) H for the HD404222 Series. ; H Figure 8 Interrupt Processing Flowchart ME 4496204 0047405 615 me 476 Hitachi #4444

HD404202 Series/HD404222 Series Interrupt Enable Flag (IE: $000, Bit 0): The External Interrupt Request Flag (IFEX: $000, interrupt enable flag (table 5) enables or disables Bit 2): The external interrupt request flag is set the interrupt requests. It is reset by an interrupt and set falling edge of the INT input. by the RTNI instruction. __ External Interrupt Mask (IMEX: $000, Bit 3): External Interrupt (INT): The external interrupt The external interrupt mask {table 7) masks the request input (INT) can be selected by the Port —_ external interrupt request. mode register (PMR: $004). Setting bit 2 of PMR causes the Ds/INT pin to be used as INT. Timer A Interrupt Request Flag (IFTA: $001, Bit 0): The timer A interrupt request flag (table 8) The external interrupt request flag IFEX (table 6) is set by the timer A overflow output. It can be is set at the falling edge of INT input. only used by the HD404222 Series. The INT input can be used as a clock signal input Timer A Interrupt Mask (IMTA: $001, Bit 1): to timer B, which counts up at each falling edge of The timer A interrupt mask (table 9) prevents an the INT input. When using INT as the timer B interrupt request from being generated by the | external event input, the external interrupt mask timer A interrupt request flag. It can be only used IMEX (table 7) has to be set so that the INT inter- by the HD404222 Series, Tupt request will not be accepted. ee Table 5 Interrupt Enable Flag Table 8 Timer A Interrupt Request Flag U3 Interrupt Enabled/Disabied \\FTA Interrupt Request ee ate iD isabled $e aves

9 Disabled Ly) No

1 Enabled 1 Yes

cG“2r ee Table 6 External Interrupt Request Flag Table 9 Timer A Interrupt Mask IFEX Interrupt Request IMTA interrupt Request ee ert ——_mermpt Request tt) No t) Enabled = ~ ee.

1 Yes 1 Disabled (masked)

Ss... $$$ aod (masked) Table 7 External Interrupt Mask IMEX Interrupt Request _ reer

0 Enabled

1 Disabled (masked)

een irae) WH 4456204 OO4740b S54 477 Hitachi ee

a HD404202 Series/HD404222 Series Timer B Interrupt Request Flag (IFTB: $001, Serial Interrupt Mask (IMS: $002, Bit 1): The Bit 2): The timer B interrupt request flag (table 10) _ serial interrupt mask (table 13) masks the interrupt : is set by the overflow output of timer B. request. It can be only used by the HD404222 Series. Timer B Interrupt Mask (IMTB: $001, Bit 3): The timer B interrupt mask (table 11) prevents an Port Mode Register (PMR: $004): The 3-bit interrupt request from being generated by the timer _write-only port mode register controls the Ds/INT, B interrupt request flag. D,/SI, and Dy/SO pins as shown in table 14. The port mode register is initialized to $0 by MCU Serial Interrupt Request Flag (IFS: $002, Bit 0): reset. Therefore these pins are initially used as The serial interrupt request flag (table 12) will be ports. Note that if unusable bit 3 is set, the MCU set when the octal counter counts eight transmit — may malfunction. clock signals, or when data transfer is discontinued by resetting the octal counter. It can be only used | by the HD404222 Series. a Table 10 Timer B Interrupt Request Flag Table 14 Port Mode Register IFTB Interrupt Request FO PMR: $004 oo No = Oh VAN ‘Dg/SO pin mode selection + D,/Sl pin mode selection Table 11 Timer B Interrupt Mask Di/INT pin mode selection IMTB Interrupt Request ° Enabled

1 Disabled (masked) PMR2 D,/INT Pin

0 Used as Ds port input/output pin

1 Used as INT input pin

Table 12 Serial Interrupt Request Flag IFS Interrupt Request PMR1* DySI Pin Oo NO 0 Used as D7 port input/output pin

1 Nes 1 Used as SI input pin

‘Table 13 Serial Interrupt Mask Puro” Dy/SOPin

0 Used as Dg port input/output pin

IMS__Interrupt Request _ 1 Used as SO output pin Oo Enabled * PMRO and PMRI can be only used by the 1 Disabled (masked) HD404222 Series. ME 4456204 0047407 450 a 478 Hitachi

____ HD404202 Series/HD404222 Series EES Seles Operating Modes The MCU has two low-power dissipation modes, mode, the oscillator circuit, interrupts, timer/ standby mode and stop mode (table 15). Figure 9 counters, and serial interface remain active. On the shows a mode transition diagram of these modes. other hand, the CPU stops since the clock related to the instruction execution stops. Registers, Standby Mode: Executing the SBY instruction | RAM, and 1/0 Pins retain the states they were in Places the MCU into standby mode. In standby just before the MCU went into standby mode. ——._— Se Table 15 Low-Power Dissipation Mode Function Low-Power Dissipation Oscillator Instruction Registers, Interrupt Mode Instruction Circuit Execution Flags Function pe Standby mode SBY Active Stop Retained Active instruction Te SSS Stop mode STOP Stop Stop Reset*! Stop instruction i Table 15 Low-Power Dissipation Mode Function (cont) Timer/ Low-Power Input/ Counters, Dissipation Output Serial Cancellation Mode RAM Pins Interface’? Comparator*? Method Standby mode Retained Retained*2 Active Stop RESET input, interrupt request ‘Stopmode—-*Relaned—SCHegn Sg OS S—— Stop mode Retained High Stop Stop RESET impedance ‘input Notes: *1. The MCU recovers from stop mode by RESET input. Refer to table 1 for the contents of the flags and registers. *2. lf an VO circuit is active, an VO current may flow, depending on the state of the /O pinin standby mode. This current is in addition to the current dissipation in standby mode, *3. Serial interface and comparator can be only used by the HD404222 Series. @™@ 4496204 0047408 327 479 Hitachi ee

HD404202 Series/HD404222 Series —_-_ em bere 1D 404222 Series Oscillator: Active Peripheral clocks: Active All other clocks: Stop <>" Yes No ypvvvvvnrrornesooes i ; i No ponrrnt storm nnn nn de No; ; i H Yes i : ; No |! H No} : H No! f Yes} H i No } Restart Restart Processor clocks} processor clocks| Execute next instruction “E> = re Yes {C11 indicates only applicable for xecute cept the HD404222 Series. Figure 10 MCU Operating Flowchart in Standby Mode Me 4496204 OO47410 T45 481 Hitachi Neen ncnnnn nee

a HD 404202 Series/HD404222 Series latte ‘Stop mode Oscillator — (TTT Pec UUUUNNNUUGLUNOUTAGINUUTGQOUUOUAGAUONUUAAY Internal clock ITY | RESET 8 tres STOP instruction tres 2 te (stabilization time) execution | Figure 11 Timing of Stop Mode Cancellation we 4496204 0047411 91) 482 Hitachi

Ta — 40 od oat Sort HD404202 Series/HD404222 Series Or ree SETHE Internal Oscillator Circuit Figure 12 shows a block diagram of the internal OSC. See figure 13 for the layout of the ceramic oscillator circuit. Through mask options, either a _gscillator. For other cases, an extemal clock opera- ceramic oscillator or resistor can be selected as the _ tion is available, oscillator type and connected to OSC, and eee osc, GH oscittator

14 Timing

(selectable divider generator System with mask circuit circuit clock osc, Q ions) | Figure 12 Internal Oscillator Circuit MB 4496204 OO4741e 653 Me 483 Hitachi ee

HD404202 Series/HD404222 Series Table 16 Examples of Oscillator Circuits Circult Configuration Circuit Constants External operation Open OSCz Ceramic a Ceramic oscillator: CSA4,00MG (MURATA) oscillator osc, Cy = Cp: 30 pF 220% L Ry: 1 MQ420% R3 Ceramic oscillator: CSB1000J (MURATA) OSC, Cy = Cp: 220 pF 220% | c, Rr Ry 1 MQ 420% Resistor Ry: 20 kK H1% osc, Ry OSC, Notes: The circuit parameters listed above are dependent on the ceramic oscillator and the floating capaci- tance when designing the board, In employing the resonator, consult with the ceramic oscillator manufacturer to determine the circuit parameters. The wiring between OSC;, OSC2, and the elements should be as short as possible without crossing over other wires. Refer to the layout of the ceramic oscillator in figure 13. Test 5 \\WWN reset 1 N8S N OSC. |-7/ es N osc, EW Dy fo \\N WY Figure 13 Layout of the Ceramic Oscillator MH 4496204 0047413 794 a 484 Hitachi

HD404202 Series/HD404222 Series AS EE SEIS Input/Output The MCU has 22 standard I/O pins. As for the D Port: The D Port has 14 discrete I/O pins, each mask ROM version of HD404201, HD40L4201, —_ of which can be addressed independeniy. The D HD404202, HD40L4202, HD404222. and __port can be set/reset through the SED/RED and HD40L4222, one of three circuit types can be | SEDD/REDD instructions, and can be tested selected by the mask option for each standard pin: through the TD and TDD instructions. with pull-up MOS or without pull-up MOS (NMOS open drain) or CMOS. For the HD404222 Series pins Ds to Dy; are multi- plexed with pins INT, SCK, SI, SO, Vyer, COMPo, The I/O pins for the HD4074224 are fixed as with and COMP), respectively. Setting, resetting, or pull-up MOS. testing non-existing ports results in invalid data, As for the HD404202 Series only pin Ds/INT applies. ‘When every input/output pin is used as an input pin, the mask option and output data must be _ R Ports: The R ports are I/O pins that are accessed selected as specified in table 17. in 4-bit units. Data is input through the LAR and Zz LBR instructions and output through the LRA and Output Circuit Operation of with Pull-Up MOS _LRB instructions. Writing into non-existing ports Standard Pins: In the standard pin option with will not affect the MCU, however, the values read pull-up MOS, the circuit shown in figure 14 is used from the non-existing ports cannot be guaranteed. to shorten the rise time of output. Unused 1/O Pins: If unused 1/O pins are left float- When the MCU executes an output instruction, it ing, the LST may malfunction due to noise. The generates a write pulse to the R port addressed by —_1/O pins should be fixed as follows to prevent mal- this instruction. This pulse will switch the PMOS —_ function. (B) on (in figure 14) and shorten the rise time. The write pulse keeps PMOS on for two-eighths of the + Select the option of without pull-up MOS for instruction cycle time. While the write pulse is 0, a unused I/O pins and connect them to GND of high output level is maintained by the pull-up the printed circuit board. MOS (C). * For the HD404222 Series sets Ds/INT, De/SCK, When the HLT signal becomes 0 in stop mode, Dy/SI, Dg/SO, Do/Vief, Dyo/COMPo, and MOSs (A), (B), and (C) turn off. When the HLT Dy\\/COMP, as Ds to Dj}, respectively, by soft- signal is 1, the pins’ states are maintained. ware. As for the HD404202 Series only pin Ds/INT applies. Me 4496204 0047414 b20 485 Hitachi ssi

HD 404202 Series/HD404222 Series Table 17 Data Input from Common Input/Output Pins VO Pin Circult Type Input Possible Input Pin State Standard pins CMOS: No - Without pull-up MOS Yes 1 (NMOS open drain) With pull-up MOS Yes 1 Vee Write pulse Pull-up Vee -- PMOS (B) — J LE. eroutput | MOS (C) M2 instruction) "EUG ALT NMOS (A) [A Data 1 instruction cycle a Figure 14 Output Circuit Operation of Standard Pins with Pull-Up MOS Option Mm 4496204 OO4741S5 Sb? me 486 Hitachi eee

HD404202 Series/HD404222 Series $A ete 104222 Series: Table 18 1/0 Pin Circuit Types ‘Standard Pins VO common pins (Dg-D;3, Rt oil, R2g-R2,) HLT [_>— Input data ALT [_>— Input data Voc | Veco Write pulse _ Cap ALT coe | |e [7 Output data [A Output data Without pull-up MOS (NMOS open drain) (A) With pull-up MOS (B) ; HOT [_}>— Input data Voc Da ALT (A Output data CMOS (Cc) VO common pins (SCK (output mode))* J De—sck J >»—sck ¢° (ALT + mode seleat) Voc | Vee ae le Sele gl 4 rar, LP SK G (internal SCK) (internal SCR) Without pull-up MOS (NMOS open drain) or CMOS (A or C) With pull-up MOS (B) Notes: 1. HD404202 Series: when selecting pin Ds as INT by software, the pull-up MOS will be disabled even if selecting mask option B (with pull-up MOS). 2. HD404222 and HD40L4222: when selecting pins Ds, Dg, and D, as INT, SCR, and SI input, respectively, by software, the pull-up MOS of each terminal will be disabled even if selecting mask option B (with pull-up MOS). HD4074224: pins Ds, Dg; and Dy are fixed as with pull-up MOS (B). But when selecting these pins as INT, SCK, and SI input, respectively, by software, the pull-up MOS of each terminal will be disabled * Only applicable for the HD404222 Series. ME 4456204 0047416 4T3 am 487 Hitachi Ne

1D404202 Series/HD404222 Series ye ee eee Table 18 1/0 Pin Circuit Types (cont) Standard Pins Output pins (SO)* Vec Vee | Vee ne a ALT so A so Without pull-up MOS (NMOS open drain) or | CMOS (A or C) With pull-up MOS (B) Input pins (INT, SI*, SCK* (input mode)) > Input O— Dk o<] ALT Input data o<} ALT Without pull-up MOS (NMOS open drain) or CMOS (A or C) With pull-up MOS (B) Input pins (COMP,*, COMP,*) Input pins (COMP *, COMP,*) Reference voltage Reference voltage CPU input CPU input oS ‘Analog comparator oS Analog comparator Without pull-up MOS (NMOS open drain) or With pull-up MOS (B) CMOS (A or C) Notes: 1. HD404202 Series: when selecting pin Ds as INT by software, the pull-up MOS will be disabled even if selecting mask option B (with pull-up MOS). 2. HD404222 and HD40L4222: when selecting pins Ds, Dg, and D7 as INT, SCK, and SI input, respectively, by software, the pull-up MOS of each terminal will be disabled even if selecting mask option B (with pull-up MOS). HD4074224: pins Ds, Dg, and D are fixed as with pull-up MOS (B). But when selecting these pins a8 INT, SCK, and él input, respectively, by software, the pull-up MOS of each terminal will be disabled * Only applicable for the HD404222 Series. Mm 4496204 0047417? 337 488 Hitachi eee

a HD404202 Series/HD404222 Series eee Timer A Operation (Only Applicable for the the beginning. The program must set bit 3 of timer HD404222 Series): Timer A’s function is selected mode register A to reset timer counter A. via the mask option. Timer B Operation: Timer mode register B . When timer A is used as a free-running timer, it (TMB: $009) selects the auto-reload function, counts up every input clock signal after timer A input clock source, and the prescaler divide ratio has been initialized to $00 by MCU reset. When for timer B. When the external event input is used ; the next clock signal is input after timer A counts _as an input clock signal to timer B, select Ds/INT up to $FF, timer A is set to $00 again, and gener- _as INT and set the external interrupt mask (IMEX) ates an overflow output. This sets the timer A to prevent an external interrupt request from occur- interrupt request flag (IFTA: $001, bit 0) to 1. ring. Therefore, this timer can function as an interval timer periodically generating overflow output at Timer B is initialized by software according to the every 256th clock signal. The clock signals input data written in timer load register B. Timer B to timer A are selected by timer mode register A counts up at every input clock signal, When the | (TMA: $008). next clock signal is input after timer B is set to SFF, timer B will generate an overflow output. Note that when timer A is used as a free-running _Then, if the auto-reload function is selected, timer timer, if setting bit 3 of timer mode resister Amay _B is initialized to the value of timer load register B. cause the MCU to malfunction. If it is not selected, timer B goes back to $00. The timer B interrupt request flag (IFTB: $001, bit 2) When timer A is used as a watchdog timer, the __ will hold the overflow output. input clock is specified as 1/2048 output divided by the prescaler. The watchdog timer is initialized Timer Mode Register A (TMA: $008): Four-bit to $00 at MCU reset, then counts up every input —_write-only timer mode register A selects the timer clock signal. If a clock signal is applied after the function for timer A and the prescaler divide ratio timer becomes $FF, an overflow is generated and of timer A’s clock input as shown in table 19. the MCU is reset. Timer mode register A is initialized to $0 by MCU After reset, the MCU re-executes the program from —_reset. Table 19 Timer Mode Register A Table 20 Timer Mode Register B TMA2 TMA1 TMAO Prescaler Divide Ratio TMB3 Auto-Reload Function 0 o 9 + 2048 0 No ty) t) 1 +1024 1 Yes oo 4 0 812 Prescaler Divide Ratio, ° 1 1 +128 TMB2 TMB1 TMBO Clock Input Source 1 0) 0 +32 0 ° i) +2048 1 0) 1 +8 0 ° 1 +512 1 1 t) +4 t) 1 0 +128 1 1 1 +2 0 1 1 +32 1 0 0 +8 1 0 1 +4 1 1 0 +2 1 1 1 INT (external event input) MB 4496204 0047419 102 490 Hitachi

the source of the clock input signal as shown in (figure 2). table 20. Timer mode register B is initialized to $0 ing data into timer load register B after the contents load register is initialized to $00 by MCU reset. sists of an 8-bit write-only timer load register and time when the high-order digit is read.

TMA only applicable for the HD404222 Series.

HD 404202 Series/HD404222 Series | eee ee Serial Interface Only applicable for the HD404222 Series. signals, or when a transmit/receive operation is dis- | continued by resetting the octal counter, the serial } ‘The serial interface is used to transmit/receive 8-bit interrupt request flag will be set. data serially. It consists of the serial data register, serial mode register, octal counter, and multiplexer, Serial Mode Register (SMR: $005): The 4-bit : as illustrated in figure 17. Pin De/SCK and the —write-only serial mode register controls the transmit clock signal are controlled by the serial De/SCK, prescaler divide ratio, and transmit clock mode register. The contents of the serial data reg- Source as shown in table 21. ister can be written into or read out by software. ‘The data in the serial data register can be shifted A write signal sent to the serial mode register con- synchronously with the transmit clock signal. trols the operating state of the serial interface. | ‘The STS instruction initiates serial interface opera- The write signal to the serial mode register stops tions and resets the octal counter to 000. The the serial data register and octal counter from using counter starts to count at the falling edge of the the transmit clock, and it also resets the octal transmit clock (SCK) signal and increments by one counter to 000 simultaneously. Therefore, when at the rising edge of the SCK, When the octal the serial interface is in the wansfer state, the write counter is reset 10 000 after eight transmit clock signal causes the serial mode register to cease the NN i i SROF oe Interrupt © request flag gf 8sis of serial Oy Dede bel ba interface Serial MPX [2] we [___Internal bus line (S1)_| serial +2 [4 Px i m1 SCK faa SR (8 bits) Serial data register SMR (4 bits) PMR (4 bits) hom mode register] Port mode register Internal bus line (S2) Internal bus line (S2) ae |_| D7/SI | Dg/SO port port port Figure 17 Serial Interface Block Diagram ME 4496204 004742) 660 492 Hitachi

SS HD404202 Series/HD404222 Series eee Te ene’ data transfer and to set the serial interrupt request chronously with the rising edge of the transmit flag. clock. Figure 18 shows the I/O timing chart for the transmit clock signal and the data. The contents of the serial mode register will be changed on the second instruction cycle after writ- The read/write operations of the serial data register ing into the serial mode register. Therefore, it is should be performed after the completion of data necessary to execute the STS instruction after the — transmission/reception. Otherwise, the data may data in the serial mode register has been changed _not be guaranteed. completely. The serial mode register will be reset to $0 by MCU reset. Selecting and Changing the Operation Mode: Table 22 shows the serial interface operation Serial Data Register (SRL: $006, SRU: $007): modes which are determined by a combination of The 8-bit read/write serial data register consists of the values in the Port mode register and in the seri- a low-order digit (SRL: $006) and a high-order —_al mode register, Initialize the serial interface by digit (SRU: $007), the write signal to the serial mode register when the operation mode is changed. , The data in the serial data register is output from the SO pin, from LSB to MSB, synchronously with Operating State of the Serial Interface: The seri- the falling edge of the transmit clock signal. Atthe al interface has three operating states: the STS same time, external data will be input from the SI__ waiting state, ransmit clock wait state, and transfer pin to the serial data register, to LSB first, syn- _ state, as shown in figure 19. eee Table 21 Serial Mode Register SMROD/SCK SMR: $005 ° Used as Dg port input/output pin

1 Used as SCK inputoutput pin SMAI

t_ Transmit clock selection Dg/SCK pin mode selection Transmit Clock OO Prescaler System Clock SMR2 SMAI SMRO D,/SCK Port Clock Source Divide Ratio Divide Ratio eer Ni Ratlo __Divide Ratio ) 0 0 SCK output Prescaler + 2048 + 4096 ees cin ON AG ty) ° 1 SCK output —_—Prescaler +512 +1024 $$ rrr cio te RH 0 1 0 SCK output Prescaler +128 +256 scion NBG 0 1 1 ‘SCK output Prescaler +32 +64 1 0 0 SCK output —_—Prescaler +8 +16 a 1 0 1 SCK output Prescaler +2 +4 1 1 0 SCK output System clock - +1 em 1 1 1 SCK input External clock = — = a Mi 4456204 OO474e2 777 493 Hitachi NN CCC nnn

TS — 404209 Senenngnayo) een HD404202 Series/HD404222 Series Ore rrr’ DETIES The STS waiting state is the initialization of the request flag is set simultaneously. serial interface. In this state, the serial interface © When the internal transmit clock is selected, the does not operate even if the transmit clock is transmit clock output is triggered by the execution applied. of the STS instruction, and stops after 8 clocks. If the STS instruction is executed, the serial inter- Transmit Clock Error Detection: The serial face shifts to the transmit clock wait state. In this interface functions abnormally when the transmit state the falling edge of the first wansmit clock clock is disturbed by external noise. In this case, causes the serial interface to shift to the wansfer —_ uransmit clock errors can be detected by the proce- state, in which the octal counter counts up and the —_ dure shown in figure 20. serial data register shifts simultaneously. If clock continuous output mode is selected, however, the If more than 8 transmit clocks are applied in the serial interface stays in the transmit clock wait transmit clock wait State, the state of the serial state while the transmit clock outputs continuously. interface shifts in the following sequence; transfer state, transmit clock wait state, and transfer state The octal counter becomes 000 again after 8 trans- again. The serial interrupt flag should be reset ; mit clocks or after the execution of the STS before entering into the STS state by writing data instruction, so that the serial interface is returned to to SMR. This Procedure causes the serial interface the transmit clock wait state and the serial interrupt request flag to be set again. Se Transmit/receive (IFS <1) Interrupt disable Write to SMR Yes Transmit clock error processing No Figure 20 Transmit Clock Error Detection M@@ 44596204 0047424 S?7T 495 Hitech! cen nnnnncnnec

HD404202 Series/HD404222 Series see’ The comparison result is obtained by executing the _ initialized to $0 by MCU reset. Therefore, it TD or TDD instruction. When the analog input — becomes input/output mode after MCU reset. voltage is higher than the reference voltage, a 1 is read as input data from the comparator. The com- _ Reference Voltage Select Register (RSR: $00C): Parator automatically stops operating in standby This 4-bit read/write register selects the COMP) and stop modes. reference voltage for the analog comparator from the eight-level internal voltage or the external volt- Comparator Mode Register (CMR: $003): This _age. It is initialized to $0 by MCU reset. 2-bit register selects the Dyo/COMPy and | D,:/COMP, functions. Notes for Use: When using the analog comparator, carefully program the data output instruction and CMR is only affected by the bit manipulation data input into the Port next to COMPo and instructions (set by the SEM or SEMD instruction | COMP to assure precise and stabilized compara- and reset by the REM or REMD instruction). It is tor operation. T_T ——— li CMR: $003 D<Dx fan Djo/COMPy mode selection D,,/COMP, mode selection CMR Mode Selection Bitt BitO0 —DgCOMP, ~—_D,/COMP, oo oes 0) 0 Dio Dn ° 1 COMP, Di 1 0 Dio COMP, 1 1 COMP COMP, Ft Figure 22 Comparator Mode Register W@™ 4496204 GCO474eb 342 497 Hitachi ee

HD 404202 Series/HD404222 Series RSR: $00C oe Internal reference voltage selection External/internal reference voltage selection RSR Bits Bit2 Biti _BitO _ Reference Voltage = 0 0 0 0 1/11 Voo ° 0 0 1 2/11 Vo 0 ° 1 0 3/11 Veo ° 0 1 1 4/11 Voc ° 1 0 0 5/11 Vo 0 1 0 1 6/11 Voc 0 1 1 0 7/1 Voc ° 1 1 1 8/11 Vo. 1 = External Vier (Do/Vret) indicates O or 1 Figure 23 Reference Voltage Select Register me uysb204 00u7427 289 = 498 Hitachi

EEE LI'E=SSN- ~~~ $C ND Series/H1D.404222 Series Pins for PROM Mode OE (Output Enable): OE is the data output con- tol signal for verification. Vpp (Program Voltage): Vpp is the input program voltage (12.5V +0.3V) for programming the Ag-Aj2 (Address Bus): Ag~A;2 are address input PROM. pins for the internal PROM, CE (Chip Enable): CE input enables program- Qg-O, (PROM Data Bus): Og-Og are the data ming and verification of the internal PROM. bus pins for the internal PROM. ee PROM Mode Pin Description Pin No. Pin No. DP-288, —MCUMode _ PROMMode 5265, MCU Mode _ PROM Mode FP-28DA FP-30D Symbol VO Symbol VO —FP-28DA FP-30D Symbol 0 Symbol VO 1 2 GND GND 1516 Dyer SOO, OO | 2 3 Rip VO As | 16 17 _—DigiCOMP9 WO CEI 3 4 Ri, VO As 117-18 ~——«DyCOMP, WO OE 4 5 Rip vo A, | 1B 18 Nog Veo 5 6 Rig WO As | 1920 ~OsG, 1 Veo 6 7 Do vO A, 1 2 at OS)SCO 7 8 D, vO Ay Lot 22. ~RESET 1 ~GND 8 9 De WO Ay | 2 28SSTEST.—dLSsCpp Q 10 Ds VOA 1 2 2h Dy «WO Veo 10 1 De WO LSC vO GND 1 12 D,ANT VO Oo vO 25 26 Ro VO Ag 1 1213 gSCK WOOO, vO 2 27 ~RA VO Ap 1 13 14 DySI VO 0» vo 27 28 —R2p VO Ay i

1415 DySO WO yO VO Ayn 1

Me 44596204 0047428 115 499 Hitachi a

a HD404202 Series/HD404222 Series Programmable ROM Operation Table 24 shows how programming and verification modes are selected. The HD4074224’s on-chip PROM is programmed in PROM mode. Precautions | In PROM mode, the MCU does not operate. Itcan 1. Addresses $0000 to $1FFF should be specified be programmed like a standard 27256 EPROM if the PROM is programmed by a PROM pro- | using a standard PROM programmer and a 28-t0- grammer. Note that the plastic package type 28-pin socket adapter as shown in figure 24. Table devices cannot be erased and reprogrammed. 23 lists the recommended PROM programmers and socket adapters. 2. Be careful that the wrong PROM programmer or socket adapter may cause an overvoltage and Since an instruction of the HMCS400 series con- damage the LSI. Make sure that the LSI is firmly sists of 10 bits, the HMCS400 series microcomput- fixed onto the socket adapter, and that the socket er incorporates a conversion circuit to enable the adapter is firmly fixed in the programmer. | use of a general purpose PROM programmer. By this circuit, an instruction is read or programmed 3. The PROM should be programmed with Vp = using 2 addresses, lower 5 bits and upper 5 bits. 12.5 V. Other PROMs use 21 V. If 21V is For example, if 4 kwords of on-chip PROM are applied to the HD4074224, the LSI may be per- programmed by a general purpose PROM pro- manently damaged. 12.5 V is Intel’s 27256 Vpp. grammer, 8 kbytes of addresses ($0000-$1FFF) should be specified. Programming and Verification The HD4074224 can be high-speed programmed without causing voltage stress or affecting data reliability. muuae2o4 OON7H2T 05h co Hat

404202 Series/#1D404222 Series

Table 23. PROM Programmer and Socket Adapter

9 Data bus

501 Hitachi

HD 404202 Series/HD404222 Series eee eee eee Addressing Modes RAM Addressing Modes ‘When the BR instruction falls on a page boundary (256n + 255), executing the BR instruction As shown in figure 25, the MCU has three RAM transfers the PC contents to the next page addressing modes: register indirect addressing, (figure 27) according to the hardware architecture. direct addressing, and memory register addressing. Consequently, the program branches to the next page when the BR instruction is used on a page Register Indirect Addressing: The contents boundary. The HMCS400 series cross macroassem- (8 bits) of the X and Y registers are used as the bler has an automatic paging facility for ROM. RAM address. pages. Direct Addressing: A direct addressing instruction __Zero-Page Addressing Mode: By executing the consists of two words, the first word contains the CAL instruction, the program can branch to the | opcode, the second word (10 bits) is used as the zeto-page subroutine area, which is located at RAM address. $0000-$003F. When the CAL instruction is exe- cuted, 6-bits of immediate data are placed in the Memory Register Addressing: The memory regis- low-order six bits of the program counter (PCs to ters 6 digits from $020 to $02F) are accessed by PCp) and Os are placed in the high-order six bits executing the LAMR and XMRA instructions, PCj1 10 PCe). . . Table Data Addressing Mode: By executing the ROM Addressing Modes and the PInstruction TBR instruction, the program can branch to the . address determined by the contents of the 4-bit ‘The MCU has four ROM addressing modes 2S immediate data, accumulator, and B register. shown in figure 26. Direct Addressing Mode: The program can P Instruction: ROM data addressed by table data branch to any address in ROM memory by execut- addressing can be referenced by the P instruction ing the JMPL, BRL, or CALL instruction. These (figure 28). When bit 8 of the ROM data is 1 (ROg instructions replace the 12 program counter bits = !), 8 bits of ROM data are written into the accu- (PC}; to PCo) with 12-bit immediate data, mulator and B register. When bit 9 is 1 (ROg = 1), 8 bits of ROM data are written into the R1 and R2 Current Page Addressing Mode: The MCU has 8 Port output registers. When both bits 8 and 9 are 1 pages of ROM with 256 words per page. The pro- (ROs = 1, ROg = 1), ROM data are written into the gram can branch to an address on the current page accumulator, B register, and R1 and R2 port output by executing the BR instruction. This instruction _Tegisters at the same time, replaces the lower eight bits of the program . . counter (PC7 to PCo) with 8-bit immediate data. The P instruction has no effect on the program counter. MB 4496204 0047431 70T 502 Hitachi ;

HD404202 Series/HD404222 Series —_- error’ SIS X register Y register naw aioe [ar [arose [ar esl ar Register Indirect Addressing First word instruction Second word instruction ale are = ra asin [arses dg and dg should be 0. Direct Addressing Instruction [creed [ram os [no 0 0140 aaa ran asen fr Jato rer Memory Register Addressing Figure 25 RAM Addressing Modes MM 4496204 0047432 b4b mm 503 Hitachi | 0 Oe

HD404202 Series/HD404222 Series corre TO [UMPL] [BRL] (CALL) First word instruction Second word instruction | Program counter |PC, ,PC, PC, PC, PC, PC, PCs PC, PC, PC, PC, PCy Pg and Pp should be 0.

7 Direct Addressing

[BR} by by bs by by by b, bo Program counter |PC,,PC,gPC, PC, PC, PC, PC; PC, PC, PC, PC, PCy Current Page Addressing Instruction pitti Tit | Program counter |PC,,PC,9 PCy PC, PC, PC, PCs PC, PCy PC PC, PCy Zero Page Addressing Instruction B register Accumulator Program counter |PC,,PC,9PC, PC, PC, PC, PC; PC, PC; PC, PC, PCy Table Data Addressing Figure 26 ROM Addressing Modes WM 4456204 0047433 582 mm

504 Hitachi

i t#

HD404202 Series/HD404222 Series Absolute Maximum Ratings hem Symbol Value Unit Notes ‘Supply voltage Veo 0.3 to +7.0 v Programming voltage Vep 0.3 to +14 v 1 Pin vottage Vr 0.3 to Vog + 0.3 v ‘Total permissible input current Llp 100 mA 2 Total permissible output current = —Zlp 30 mA 3 Maximum input current , 30 mA 4,6 4 mA 5,6 Maximum output current Ao 4 mA 7 Operating temperature Topr 20 to +75 °C | Storage temperature Tstg 55 to +125 °C Notes: 1. Applies to HD4074224, 2. The total permissible input current is the total of input currents simultaneously flowing in from all /O pins to GND. 3. The total permissible output current is the total of output currents simultaneously flowing out from Veg to all /O pins. 4, Applies to D2, Dyg, Rig to Rig, and R2p to R23. 5. Applies to Do to Djs. 6. The maximum input current is the maximum current flowing from any V/O pins to GND. 7. The maximum output current is the maximum current flowing from Veg to any /O pins. Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LS! may matfunction or its reliability may be affected. All voltages are with respect to GND. MH 4496204 0047435 455 506 Hitachl

HD404202 Series/HD404222 Series OO rrEernrrv—ever’s DC Characteristics (Vcc = 3.5 V to 6.0 V, GND = 0 V, T, = ~20°C to +75°C) Item Symbol Pin Min Typ Max Unit Test Condition — Notes —.$ mn st fonction Notes Input high voltage Vy RESET, 0.9Voc — Voc+03 V INT, SCK* SSeS sit 0.9Vec — Veco + 0.3 V ee _ce osc, Voo-9.5 — Voc +0.3 V er Ne OS Input low voltage Vy. RESET, -0.3 — 02V¢¢ Vv INT, SCK* a eeeseeFSeSFSsSFSsSSSsSSSSSSSSSSSSSSSSSSSSSSSSSS sk 0.3 — 02Vve¢ Vv ah ‘OSC, 03 — 05 Vv tN Output high voltage* Voy, SCK, Veo- 1.0 — — Vo =loy = 1.0 mA | so a Output low voltage* Vo, SCK, = — 04 Vi Iq =0.5mA so eee Input/output Tt RESET, — —- 1 HA Vin=OVI0Veg 1 leakage current INT, SCK*, Sit, SO*, osc, td Current dissipation leg Vee - — 35 MA Voc =5V, 2,5 in active mode fogc = 4 MHz ose loup* — Voc = — $5 mA Voc =5V, 3,5 fosc = 4 MHz Comparator active $e OMparatoractive Current dissipation Iggy Veo - - WwW mA Voc =5V, 4,5 in standby mode fosc = 4 MHz Sos MZ Current dissipation Igtop Veo - - 10 HA VinESET) = in stop mode Voc ~ 0.3 V to Veg, Vintesty = 0 V to 0.3 V Nineties OV 00.3 Stop mode Vstop Veo 2 - - v tetaining voltage oo SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSse Notes on next page. * Applies to HD404222. 2436 29] Mm 4496204 O04 507 Hhach! Nene ee

HD404202 Series/HD404222 Series DC Characteristics (Vcc = 3.5 V to 6.0 V, GND = 0 V, T, = -20°C to +75°C) (cont) item Symbol Pin Min Typ Max Unit Test Condition Notes Input high voltage* Vyiq COMP , VC +0.1 — — Vv COMP, Input low vottage* Vyaq COMP , 0 = VCg-0.1 V COMP, Comparator input VCrer Vret 0 - Veo-1.2 V reference voltage i Deviation of internal Vors_ — 01 — 04 Vo Vec=45Vto 6 seterencevotage® Notes: 1, Excluding output buffer current and pull-up MOS current. 2. Igc is the source current when no /O current is flowing while the MCU is in reset state. | Test conditions: MCU: Reset Pins: RESET at GND, TEST at GND Do to Dyg, Rt, R2 at Veo 3. loup is the source current when no VO current is flowing while the MCU comparator is in operation. Test conditions: MCU: Comparator active Pins: RESET at Voc, TEST at GND Do to Dg, Dy, Dyg, Rt, R2 at Voc Dg to Dy; at GND 4. Iggy is the source current when no I/O current is flowing while the MCU timer is in operation. Test conditions: MCU: V/O same as at reset ‘Standby mode Pins: RESET at Voc TEST at GND Do to Dy, R1, R2 at Veo. 5. Power dissipation is in proportion to fog¢ while the MCU is operating or is in standby mode. The value of the dissipation current when fosc = x MHz is given by the following equation: Maximum value (fogg = x MHz) = x/4 x maximum value (fog¢ = 4 MHz) 6. The reference voltage Is the expected internal VC;9j voltage selected by the reference voltage select register (RSA). Example: when RSR = $1 reference voltage is 2/11 x Voc. * Applies to HD404222. MH 4496204 0047437 128 508 Hitachi

HD404202 Series/HD404222 Series apa Ie ti’ Series Input/Output Characteristics (Voc = 3.5 V to 6.0 V, GND = 0 V, T, = -20°C to +75°C ) Item Symbol Pin Min Typ Max Unit Test Condition Note Yt est Condition Note Input high voltage Vjy Do-Dig, 0.7Vcg = — Veg +03 V Ri, R2 Sa epee eee Input low voltage Va Do-Dig, 0.3 — 03V¢¢ Vv Ri, R2 are prarrser reper rua Output high voltage Voy Do-Dyz, Voc- 1.0 — — Vio Alo = 1.0mMA Ri, R2 SN area Output low voltage = Voy. Do-Dy3, — — 04 Vi lg, = 0.5 mA R1, R2 eS Dy2,Di3, — — 2 Vig = 15 mA, Ri, R2 Voc = 4.5 Vito 6.0V OY Inpuvioutput leakage [I Do-Dy3, - 1 BA Vine OVtOVeg 2 = current R1,R2 _ _ Pull-up MOS current -Ipy —Do-Dy3, 40 80 160 HA Veo = 5V, 3 Rt, R2 Vin = OV Notes: 1. For VO pins selected as CMOS output by mask option. 2. Excluding output butter current and pull-up MOS current. 3. Applies to /O pins selected as with pull-up MOS by mask option. M™ 44596204 0047436 Ob Me 509 Hitachi Cenc nnnnnnnn ee

a HD404202 Series/HD404222 Series AC Characteristics (Vcc = 3.5 V to 6.0 V, GND = 0 V, T, = -20°C to +75°C) ttem Symbol Pin Min Typ Max Unit Test Condition Note . Oscillation fose Osc, 1 4 4.5 MHz _ Ceramic oscillator frequency OSC, “> 3~—sOMHz._-RResistor oscillator Ry = 20k241% | Instruction cycle teye - 089 1 4 us Ceramic oscillator time divided by 4 133. — 4 ps Resistoroscillator divided by 4 ee Oscillator tac osc, — - 20 ms Ceramic oscillator 1 stabilization time OSC, “05 ms _ Resistor oscillator Capacitance Car osc, — — 1 pF | between pins OSC External clock high top, osc, 92 — — os 2 and low widths top. External clock topr osc; — — 2 ns 2 rise time External clock topr osc; — - 2000 ons 2 fall time INT high width ta INT — 3 INT low width te INT 2 — — bye 3 RESET low width trast. RESET 2 — = __bee 4 RESET rise time tastr RESET — — 20° ms 4 Input capacitance Cp, Alpins — — 15 pF {=1MHz,Vi,=0V, Ta = 25°C Comparator testa. COMP) — — 2 ge stabilization time* Notes: 1. The oscillator stabilization time is the period from when Vcc reaches its minimum allowable voltage (3.5 V) at power-on until when the oscillator stabilizes, or after RESET goes low. At power-on or stop mode recovery, RESET must be kept low for at least tac. Sinca tag depends ‘on the ceramic oscillator’s circuit constant and stray capacitance, consul with the ceramic oscil- lator manufacturer when designing the reset circuit. 2. Reterto figure 29. 3. Refer to figure 30, 4. Reterto figure 31. * Applies to HD404222. MH 4496204 0047439 TTO 510 Hitachi

HD404202 Series/HD404222 Series NEES SENNES, Serial Interface Timing Characteristics (HD404222: Voc = 3.5 V to 6.0 V, GND = 0 V, T, = -20°C to +75°C) During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Condition Note Ta Condition Note Transmit clock tgeye SCK 1 — = tye — Load shown in 1 cycle time figure 33 Transmit clock high tscx, = SCK 0.4 — = —_—tggye_ Load shown in 1 and low widths tscKe figure 33 Transmit clock rise tgcKr. SCK — — 100 ns Load shown in 1 and fall times tgcxs figure 33 Solem or Serial output data toso so — — 250 ns — Load shown in 1 dolay time figure 33 ‘“Sorialinputdata” aa Sa Serial input data tsgy, Ss! 300 — — ns 1 fe setup time “Serial input data Serial input data ts sl 150 — — ns 1 hold time SSS During Transmit Clock Input Item Symbol Pin Min Typ Max Unit Test Condition Note —— _ Test Condition Noto Transmit clock tseye SCK 1 —- — toe 1 cycle time Sr ree Transmit clock high — tscKH, SCK 04 -— = Itggye 1 and low widths tscxL Sr rn Transmit clock rise tscKr. StK — — 100 ns 1 and fall times tscxt unum ez x rr Serial output data tpso so — = 250 ns — Load shown in 1 delay time figure 33 ‘Serialinputdala. tea, SSS an SC Serial input data ——tggy st 300 — — ns 1 setup time Sorialinputdala” a SP eS Serial input data tysy sl 1590 — — ns 1 hold time Fr ap se Note: 1. Refer to figure 32. Me 4496204 OO4744O 712 511 Hitachi | ee

—SSSSsssssssseseseses HD404202 Series/HD404222 Series | eee DC Characteristics (Vcc = 2.5 V to 6.0 V, GND = 0 V, T, = -20°C to +75°C) Hem Symbol Pin Min Typ Max Unit Test Condition —_Notes Input high voltage Vy = RESET, 0.9Vcc — Voc+0.3 V , INT, SCK* si* 09Vco Voc +03 -V OSC, —_Vec-0.3 — Voct03 V Input low voltage Vy «RESET, + -0.3 — 0.2Vg¢ V ISR si 03 — 0M V osc, 0.3 — 03 v | Output high voltage* Voy ~~ SCK, Veo-05 —- = Vi lo = 0.5 mA so eS Output low voltage* Vo, SCK, - — 04 Vo Iq =0.5mA so Input/output thu RESET, — - 1 HA Vine OVtoVeg 1 leakage current INT, SCK*, SI*, SO*, SE Current dissipation lec Voc. = —- 1 mA Vcc =3V, 2,5 in active mode tose = 1 MHz leup* Voc - — 16 mA Vcc =3V, 3,5 tose = 1 MHz a omparatonactive Current dissipation Igpy Voc = — 05 mA Voc =3V, 4,5 instandbymede fog TM Current dissipation Istop Voc - — 10 WA Vin(ReSeT) = in stop mode Voc - 0.3 V to Voc, Nites VIO .SV Stop mode Vstop Voc 2 ee v fetaining voltage Notes on next page. Wm 4456204 0047441 659 mf 512 Hitachi ;

HD404202 Series/HD404222 Series SSS erTrEereperies: DC Characteristics (Vcc = 2.5 V to 6.0 V, GND = 0 V, T, = -20°C to +75°C) (cont) item Symbol Pin Min Typ Max Unit Test Condition Notes Input high voltage* Vin COMPo, VGgy+0.1 — Vv COMP, Input low voltage* Vy, COMPy, 0 = VGqp-0.1 V COMP, Comparator input — VCyey Veet ° — Vec-12 V reference voltage scope* Deviation of internal Vopg = — 0.1 — of Vi Veg =45Vto 6 reference voltage* 6.0V Notes: 1. Excluding output butfer current and pull-up MOS current. 2. lec is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset , Pins: RESET at GND, TEST at GND Do to Dig, R1, R2 at Veg 3. Icup is the source current when no VO current is flowing while the MCU comparator is in operation. Test conditions: MCU: Comparator active Pins: RESET at Voc, TEST at GND Do to Dg, Dy2, Dig, A1, R2 at Veg Dg to D,, at GND 4. Igpy is the source current when no V/O current is flowing while the MCU timer is in operation. Test conditions: MCU: VO same as at reset Standby mode Pins: RESET at Veg TEST at GND Do to Dyg, R1, R2 at Veg 5. Power dissipation is in proportion to fogc while the MCU is operating or is in standby mode. The value of the dissipation current when fogc = x MHz is given by the following equation: Maximum value (fog¢ = x MHz) = x/4 x maximum value (log¢ = 1 MHz) 6. The reference voltage is the expected internal VC, voltage selected by the reference voltage select register (RSR). Example: when RSR = $1 reference voltage is 2/11 x Voc. * Applies to HD40L4222. mm yusb2eo4 co474ue 595 ml 513 Hitachi —— LL CCC C CCC

HD404202 Series/HD404222 Series Input/Output Characteristics (Vcc = 2.5 V to 6.0 V, GND = 0 V, T, =-20°C to +75°C ) tem Symbol Pin Min Typ Max Unit Test Condition Note Input high voltage Vy DoDis O7Voo — Voo+03 V Ri, R2 Input low voltage Vie DoDisz 0.3 — 03V¢¢-V Ri, R2 Output high voltage Voy Do-Dizs Voc-05 — — Vi =I =0.5mA 1 Ri, R2 Output low voltage VQ Oy Dye — — 04 Vly =0.4mA Ri, R2 Dia Dig — —- 2 Vly =15mA, Ri, R2 Voc = 4.5 Vto a Inpuvoutput leakage [Ii DoD — — 1 BA Vin= OVt0 Veg 2 current Ri, R2 Pull-up MOS current = =Ipy Do-Di3, 10 25 60 BA Voc=3V, 3 Rt, R2 Vine OV Notes: 1. For I/O pins selected as CMOS output by mask option. 2. Excluding output buffer current and pull-up MOS current. 3. Applies to VO pins selected as with pull-up MOS by mask option. MB 4496204 0047443 421 514 Hitachi

— — —_ 4902 Serie HD404)9) Soniac HD404202 Series/HD404222 Series —_w Er Eee AC Characteristics (Vcc = 2.5 V to 6.0 V, GND = 0 V, T, = -20°C to +75°C) ttem Symbol Pin Min’ Typ Max Unit Test Condition Note Oscillation fosc OSC, 04 1 1.125 MHz Ceramic oscillator frequency OSC, Instruction cycle teye - 355 4 10 us Ceramic oscillator time divided by 4 Oscillator tac osc, — — 20 ms Ceramic oscillator 1 stabilization time OSC, SS rr External clock high — topyy, osc, 425 — — ns 2 and low widths tope ee External clock top, osc; — — 2. os 2 rise time ee External clock topr osc; — ~— 20 ns 2 ; fall time INT high width th iNT 2 = = tye 3 FEF ow INT low width te INT 2 —__ — _ te 3 ee tv RESET low width tasty RESET 2 — — tye 4 ae RESET rise time tastr RESET — — 20 ms 4 TB Input capacitance Cp, Allpins — — 15 pF {=1MHz,V,-0V, Ta = 25°C Sn nS Comparator testa COMP] — — 2 toe stabilization time* Notes: 1. The oscillator stabilization time is the period from when Veg reaches its minimum allowable voltage (2.5 V) at power-on until when the oscillator stabilizes, or after RESET goes low. At Power-on or stop mode recovery, RESET must be kept low for at least tac. Since tag depends ‘on the ceramic oscillator’s circuit constant and stray capacitance, consult with the ceramic oscil- lator manufacturer when designing the reset circuit. 2. Refer to figure 29. 3. Refer to figure 30. 4. Refer to figure 31. * Applies to HD40L4222. mB 4496204 0047444 3bo Me 515 Hitachi LL

HD404202 Series/HD404222 Series Serial Interface Timing Characteristics (Vcc = 2.5 V to 6.0 V, GND = 0 V, T, = -20°C to +75°C ) During Transmit Clock Output tem Symbol Pin Min Typ Max Unit Test Condition Note Transmit clock tscye SCK 1 — — — tye Load shownin 1 cycle time figure 33 Transmit clock high tscx, « SCK. = «0.4. — ~— —_tggqe_ Load shownin 1 and low widths tsckL figure 33 Transmit clock rise tc, =» SCK = =— — 300 ns Loadshownin 1 and fall times tecxt figure 33 Serial output data tpso so — = 600 ns — Load shown in 1 delay time figure 33 Serial input data —_tsgy SI 1000 — — ns 1 | setup time Serial input data_—tasy st 500 — — ns 1 hold time During Transmit Clock Input Item Symbol = Pin Min Typ Max Unit Test Condition Note Transmit clock tseye SCK 1 —- — —§ tye 1 cycle time Transmit clock high tscx, = SCK 4 tye 1 and low widths tscKe Transmit clock rise tscxKr SCK - - 300 ns 1 and fall times Iscxt Serial output data tpso so — — 600 ns Load shown in 1 delay time figure 33 Serial input data. tggy SI 1000 — — ns 1 setup time Serial input data tus) sl 500 — — ns 1 hold time Note: 1. Refer to figure 32, Me 4496204 OO4?4HS OTH 516 Hitachi

HD404202 Series/HD404222 Series Ones DC Characteristics (Vcc = 2.7 V to 5.5 V, GND = 0 V, T, =-20°C to +75°C) ltem Symbol Pin Min Typ Max Unit Test Condition _ Notes SSS oo Input high Vin RESET, 0.9Vec. _ Veo +03 V voltage SCK, INT ae SSSSSSSSSSSSSSSSSSSSFsseeF sl Occ — Voo+03 V oe Osc, Veo-0.3 — Voc+03 V 2.7V< Veo <3.5V Veo-0.5 — Vec+03 Vi 35V< Veg s55V ee Nec $08 VSS E Voc SSS Input low Vi RESET, -03 — 022M Vv voltage SCK, INT ae sl -03 = 03g Sc osc, 03 — 03 Vi 27VS Veg <3.5V i 0.3 _— 0.5 v 3.5V<S Voce <5.5V $A NE Vcc S55 V Output high Voy SCK,SO Vog-05 — — Vi 2.7 Ve Veg <3.5V voltage = on = 0.5 mA Veo-1.0 — = Vi BS VS Veco s5.5V = log = 1.0 mA eee OMA Output low Voy SCK,SO — — 04 v log = 0.5 mA voltage - Inputoutput — |h| RESET, — —- 1 WA Vin=OVtOVeg 1 leakage ‘SCK, INT, current SI, SO, osc, a Current lec Voc - — 42 mA Vec=5V, 2,5 dissipation tosc = 4 MHz in active TD —, mode - - 1 mA Veo =3¥, 2,5 fosc = 1 MHz $$ ees lomp Veo - — 65 mA Voc =5V, 3,5 fose = 4 MHz, comparator active ~ — 16 mA Voc =3V, 3,5 fosc = 1 MHz comparator active ee mparator active Current Ispy Veo = - 2 MA Voc =5V, 4,5 dissipation fosc = 4 MHz ¢ se es in slandy = — 05 mA Vog=3V, 45 mode fos¢ = 1 MHz ets TM Current Istop Voc = — 10 BA VingESET) = dissipation Veg = 0.3 V to Veg in stop mode Vin(TEST) = OVt00.3V oO Stopmode Vstop ~— Veo 2 - = v retaining voltage SSS Notes on next page. MH 44596204 OO4744L 130 517 Hitachi

HD404202 Series/HD404222 Series DC Characteristics (Vcc = 2.7 V to 5.5 V, GND = 0 V, T, = -20°C to +75°C) (cont) tem Symbol Pin Min Typ Max Unit = Test Condition Notes Input high Vian COMPy, VGeit01 — — Vv voltage COMP, Input low Via COMPy, 0 - VC 0.1 V ' voltage COMP, Comparator VCyer Veet 0 — Voeo-1.2 V input reference voltage scope Deviation of Vors — 1 — 04 VV Voc=45Vto. 6 internal 5.5V reference | voltage Notes: 1. Excluding output buffer current and pull-up MOS current. 2. lec is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at GND, TEST at GND Do to Dig, R1, R2 at Veg 3. Ioyp is the source current when no VO current is flowing while the MCU comparator is in operation. ! Test conditions: MCU: Comparator active Pins: RESET at Voc, TEST at GND Dp to Dg, Dy2, Dyg, Rt, R2 at Vog Dg to Dy; at GND 4. Igpy is the source current when no I/O current is flowing while the MCU timer is in operation. Test conditions: MCU: VO same as at reset Standby mode Pins: RESET a Voc, TEST at GND Do to Dy3, Ri, R2 at Veo 5. Power dissipation is in proportion to fg¢ while the MCU is operating or is in standby mode. | The value of the dissipation current when fog¢ = x MHz is given by the following equation: | Maximum value (fosc = x MHz) = x/4 x maximum value (fog¢ = 4 MHz) 6. The reference voltage is the expected internal VC;¢; voltage selected by the reference voltage select register (RSR). Example: When RSR = $1, the reference voltage is 2/11 x Voc. Mm 4496204 OO4?44? O°? 518 Hitachi

HD404202 Series/HD404222 Series AG? Series /H1D404222 Series Inpu/Output Characteristics (Vcc = 2.7 V to 5.5 V, GND = 0 V, T, = -20°C to +75°C) item Symbol Pin Min. Typ Max Unit Test Condition Note ——___ Ite Max _Unit__Test Condition Note Input high Vay Do-Dis, 0.7Vog — Veo+03-V voltage Ri, R2 ee Inputlow Vy, DoD 03 — O3V¢g V voltage Ri, R2 i Outputiow Vo. DoD — — 04 Vk =05mA voltage Ri, R2 ee Dida — = 3 Ve tS mA, AY R2 Veo = 4.5 V 105.5 V ec IOV Inputoutput [I DoD, — = 1 WA Viq= OV 10 Veg 1 leakage Rt, R2 current Pul-up MOS —Ipy Do-Dj3,_ 40 80160 HA Voc=5V,Vin=0V | BBO 0A Voc= SW Vin= OV current RIR2 59 25-60 HA Voc=3V,Vq=0V A Ve 3 OV Note: 1. Excluding output buffer current and pull-up MOS current. M™ 4496204 0047448 TOS 519 Hitachi a

HD404202 Series/HD404222 Series AC Characteristics (Voc = 2.7 V to 5.5 V, GND = 0 V, T, = -20°C to +75°C) ttem Symbol Pin Min Typ Max Unit Test Condition Note Oscillation fosc Osc, 1 4 45 MHz Vog=3.5Vt05.5V frequency (ceramic OSC2 4 11.125 MHZ Veg =2.7V1035V oscillator) Instruction cycle toye - 0.89 1 4 ys Voc = 3.5 V to 5.5 V time (ceramic divided by 4 oscillator) 355. 4 10 ps Voc#27Vt035V divided by 4 Oscillator tac osc,, — - 20 ms 1 stabilization time OSC, (coramic oscillator) frequency (resistor Osc, Ry = 20kQ+1% oscillator) Instruction cycle tye = 133 4 us Voc = 3.5 Vt05.5V time (resistor divided by 4 oscillator) Oscillator tre Ost, — — O05 ms Veg=35VI055V stabilization time OSC, (resistor oscillator) Capacitance Car ost, — — 1 PF Veg 3.5 V1055V between pins OSC, External clock topHy osc, 92 - - ns Vec=3.5Vto5.5V 2 high and low widths top, 25. — — ms Vogw27Vt035V 2 External clock rise top, osc; — — 2 ns 2 time External clock fall top osc; — — 2. ns 2 time INT high width ty TNT 2 - - tee 3 ‘INT low width te ‘INT 2 - = toye 3 RESET low width —tasri. RESET 2 - - teye 4 RESET tise time tastr RESET — —- 2 ms 4 Input capacitance Cn, TEST. — —— —(*'180—pF f= 1 MHz, Vipm OV, Others — — 15 pr la725c Comparator testa «= COMP) — = — 2 tye stabilization time Notes: 1. The oscillator stabilization time is the period from when Voc reaches its minimum allowable voltage (3.5 V) at power-on to when the oscillator stabilizes, or after RESET goes low. At power-on or stop mode release, RESET must be kept low for at least tao. Since tac depends on the ceramic oscillator’s circuit constant and stray capacitance, consult with the ceramic oscillator manufacturer when designing the reset circuit. | 2. Refer to figure 29. | 3. Refer to figure 30. } 4, Refer to figure 31. Me 4y9e204 0047449 TNT i 520 Hitachi

HD404202 Series/HD404222 Series EE een 4222 Seris: Serial Interface Timing Characteristics (Voc = 2.7 V to §.5 V, GND = 0 V, T, = -20°C to +75°C) During Transmit Clock Output Item Symbol Pin Min Typ = Max —_Unit'_‘Test Condition Note Or ero Transmit clock tecye ScK 1 = = tye Load shown in 1 cycle time figure 33 aye figure Transmit clock tscxu, =< SCK.—«OO4=S—~—SO—«tgaye Load shownin 1 high andlow scx. figure 33 widths ee Transmit clock scx, += SOK — Ss —S—S«dO.sns—SsC« gg 3.5 VEOSSV, 1 tise and fall times tscxy load shown in figure 33 ead shown in figure 33 — = 300 ms Vege 2.7VI035V, 1 load shown in figure 33 od shown in figure 33 Serial output tpso SO -— — 250 ns Voc=3SVt055V, 1 Hi data delay time load shown in figure 33 ad Strownr in figure 33 — = 600 ms Vege 27Vt035V, 1 load shown in figure 33 toad shown in figure 33 Serial input tss1 Sl 300 — rs ee 3.5 Vt055V. 1 data setup time 1000 — — os Voo=2.7Vto35V 1 0s Ve 2 7Vt035V Serial input tusi sl 150 — sons Vege 35 VI055V 1 data hold time 500 — — ns Veo =2.7V1035V 1 $A ts Nec 27 VIO SV During Transmit Clock Input tem Symbol Pin = Min Typ Max Unit_—_‘Test Condition Note = OOO errr Transmit clock tgcye SOK 1 = — bye 1 cycle time he Transmit clock tgcxn, = SOK. O04 Ne 1 high and low scx. widths ST Transmitclock tgcy, = SOK SS —SC«dOSts SSS VtOSSV 1 rise and fall times tscxt — — 300 as Veo =2.7Vt035V. 1 PS Voc 27 VIO SV Serial ouput toso SO — — 250 ns Vocu35VI055V, 1 data delay time load shown in figure 33 = = 600 Sqm 2.7 Vt035V, 1 - load shown in figure 33 Serial input tsi Si 300 — ons Voge 3.5 V1055V 1 data setup time 1000 — — ns Voo=2.7Vt035V 1 OS ec 27 VIO SS Serial input tus sl 10 — — ms VogudSV055V. 1 data hold time 500 — — ns Voc =27Vt035V 4 oc 27 IO SEV Note: 1. Refer to figure 2. M™ 4496204 0047450 bbl 621 Hitachi a

HD404202 Series/HD404222 Series Electrical Characteristics (Reference data) Tt ‘ T i Voc = §0V senha a a tnenfenninefennnie, VOOM . a es ee § a a, a ee : a Corre ty rt 7 i i 00 ° — 30 40 50 60 70 ° 0 2 9% «0 60 Voc My Ry (ka) Resistor oscillator characteristics (1) Resistor oscillator characteristics (2) ‘ + ‘4 ; t | Ta= 2010 75° 4 r Ta=~2010 75° ee ee a ee ee ne ee a e a es ee ae e t 4. | +. i Es ee A ee eee eee ee Re on oe ae ne

3 I i H 5 H I I i

oO 10 20 30 0 50 o 10 20 30 40 50 Ry (kQ) Ry (kQ) Resistor oscillator characteristics (3) Resistor oscillator characteristics (4) mm 4496204 0047453 370 524 Hitachi

HD404202 Series/HD404222 Series 0 eee Notes On ROM Out Please pay attention to the following items regard- _data size is required to change ROM data to mask ing ROM out. manufacturing data since the program used is for a 2-kword version, On ROM out, fill the ROM area indicated below with Is to create the same data size as 2-kword _ This limitation apply to the case of using EPROM versions (HD404202, HD40L4202). A 2-kword and the case of using data base. eS ROM 2 kwords version: HD404201, HD40L.4201 Address $0800 to $OFFF soo = Vector address $0009 $000A Zero-page subroutine (64 words) $003F $0040 Pattern and program (2048 words) $03FF $0400 [Eee as | Pe ee ae | ME 4456204 0047454 207 me 525 Hitachi Cenc nnnnnnnnee

HD 404202 Series/HD404222 Series HD404201/HD40L4201/HD404202/HD40L4202 Option List | Please check off the appropriate applications and [Gyseraaie [Sd enter the necessary information. [Custonernane [Cid a 1. ROM Size [ROMcodename [| 1 5-V operation: HD404201 Teword] [tSitypename [| O Low-voltage operation: HD40L4201 1 5-V operation: HD404202 OD Low-voltage operation: HD40L4202 | 2. I/O Options A: Without pull-up MOS (open-drain NMOS); B: With pull-up MOS; C: CMOS (cannot be used as input) Porame| VO aT 3 [e_] |Pinnane [ays [co] por | vo ft) [re 0 | o2 [vw ff [oso | os | vo ft [Rio| vo} | ps | vw ff pRu ft vw [yy [ ps | vo [Ri2[ vo | oe | vo [Ris [vo | | o7 | vw fy [Reo | vo [ oe | vo [Ra | to [po | vo fT 0 Loi | vo Tt [ras] vo TT 3. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). O EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits C EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 4, System Oscillator (OSC1 and OSC2) HD404201/HD404202 HD40L.4201/HD40L4202 External clock [t= MHz [() Externalclock f= MHz | [Co Ceramic oscilator [f= MHz |) Ceramicoscilator [t= MHz | 5. Stop Mode 6. Package [Qused O bP-28s Mm 4496204 0047455 143 me 526 Hitachi

SSeeeSSSSSSSSSSSSSSSSSsSSSSSSSSSS HHD404202 Series/HD404222 Series ee SSSSS—OFeFeFeFeFSFSSS OOO eee eriels HD404222/HD40L4222 Option List Please check ff the appropiate aplicaionsand [Oviedo emer the necessary information. | Gustomername | [Dopanmen [Sd 1. ROM Size [ROMcodename | Or §-V operation: HD404222 [tsitypename [| O Low-voltage operation: HD40L4222 2. /O Options A: Without pull-up MOS (open-drain NMOS); B: With pull-up MOS; C: CMOS (cannot be used as input) [rename] vo [er Pin name | A [ 8 Tc | | do | woof) ono port wo oreo [oz [| vo fot) [oro [os [ow [ty | [Rio[ wo [fy [ os | wo [ai [oP a a [Ris { vo fT | o7 [wo Ty [Raf vo { | bs | vw [yy [Rai { wo} | bo | wo [Raa] vo ff [pio | wo Ty [raa{ vo TT 3. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits 1 EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to differnt EPROMS. 4. System Oscillator (OSC1 and OSC2) 7 2 |

0 External clock [f= MHz | O) External clock [f= MHz |

[cones t= ve PERE TSE O Ceramic oscillator t= MHz | C Ceramic oscillator 5. Timer A 6. Stop Mode 7. Package O Free-running timer operation CO pp-2as Watchdog timer operation O FP-280A OG FP-30D ME 4496204 O04745b O8T 527 Hitachi Ne

Selected Specification

Hitachi Semiconductor HD404201FP overview.

Summary

CMOS 4-bit Single-Chip Microcomputers with the same architecture as the HMCS400 Series

Description

CMOS 4-bit Single-Chip Microcomputers with the same architecture as the HMCS400 Series

Source title HD404201FP Datasheet(PDF) - Hitachi Semiconductor

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