HD404052S

HD404054 HITACHI

Document overview

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Technical content

Features

• The differences between HD404054 Series and HD404094 Series HD404054 Series HD404094 Series I/O pins 10 large-current output pins: Six 15-mA sinks and four 10-mA sources 6 largecurrent output pins: Two 15-mA sinks and four 10-mA sources 4 intermediate voltage output pins
• 27 I/O pins and 8 dedicated input pins
• Three timer/counters
• Eight-bit input capture circuit
• Two timer outputs (including two PWM outputs)
• One event counter inputs (including one double-edge function)
• One clock-synchronous 8-bit serial interface
• Comparator (2 channels)
• Built-in oscillators  Main clock: Ceramic or crystal oscillator (an external clock is also possible)

HD404054 Series/HD404094 Series

• Six interrupt sources  Two by external sources  Four by internal sources
• Subroutine stack up to 16 levels, including interrupts
• Two low-power dissipation modes  Standby mode  Stop mode
• One external input for transition from stop mode to active mode
• Instruction cycle time: 1 µs (fOSC = 4 MHz at 1/4 division ratio)  1/4, or 1/32 division ratio can be selected by hardware
• Two operating modes  MCU mode  MCU/PROM mode (HD4074054, HD4074094)

Ordering Information

ROM (words) RAM (digit) Package Mask ROM HD404052H HD404092H 2,048 512 FP-44A HD404052S HD404092S DP-42S HD40A4052H FP-44A HD40A4052S DP-42S HD404054H HD404094H 4,096 FP-44A HD404054S HD404094S DP-42S HD40A4054H FP-44A HD40A4054S DP-42S ZTAT HD4074054H HD4074094H 4,096 FP-44A HD4074054S HD4074094S DP-42S ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi, Ltd.

HD404054 Series/HD404094 Series Pin Arrangement RD /COMP RD /COMP RD RD RC RE /VCref TEST OSC OSC RESET GND D D D D D D D D D D 0 0 1 1 DP-42S CC 3 1 2 1 1 1 0 1 13 0 FP-44A RE0/VCref TEST OSC1 OSC2 RESET GND D D D D D R4 /EVND R3 /TOD R3 /TOC 13 0 NC RC0 1 1 0 0 CC Top view 3 1 2 1 1 1 V SEL R4 /SO R4 /SI R4 /SCK R4 /EVND R3 /TOD R3 /TOC R0 /INT D /INT D /STOPC RD RD RD /COMP RD /COMP V SEL R4 /SO R4 /SI R4 /SCK D D D D D D /STOPC D /INT R0 /INT NC

HD404054 Series/HD404094 Series Pin Description Pin Number Item Symbol DP-42S FP-44A I/O Function Power supply VCC Applies power voltage GND Connected to ground Test TEST I Used for factory testing only: Connect this pin to VCC Reset RESET I Resets the MCU Oscillator OSC1 I OSC2 O Port D0–D9 12–21 7–16 I/O* Input/output pins addressed by individual bits; pins D0–D3 are high-current source pins that can each supply up to 10 mA. The HD404054 Series: pins D4–D9are high-current sink pins that can each supply up to 15mA. The HD404094 Series: D4–D7 are intermediate voltage (12 V) NMOS open-drain pins, and D8, D9 are high-current sink pins that can each supply up to 15 mA. D12,D13 22, 23 17, 18 I Input pins addressable by individual bits R00–R43 24–40 19–36 I/O Input/output pins addressable in 4-bit units RD0–RD3, RC0, RE0 1–6 39–43,1 I Input pins addressable in 4-bit units Interrupt INT0, INT1 23, 24 18, 19 I Input pins for external interrupts Stop clear STOPC I Input pin for transition from stop mode to active mode Serial SCK1 I/O Serial clock input/output pin SI1 I Serial receive data input pin SO1 O Serial transmit data output pin Timer TOC, TOD 34, 35 30, 31 O Timer output pins EVND I Event count input pins Comparator COMP0, COMP1 1, 2 39, 40 I Analog input pins for voltage comparator VCref Reference voltage pin for inputting the threshold voltage of the analog input pin. Division rate SEL I Input pin for selecting system clock division rate after RESET input or after stop mode cancellation. 1/4 division rate: Connect it to VCC 1/32 division rate: Connect it to GND Note: * D4–D7 of the HD404094 Series are output pins.

HD404054 Series/HD404094 Series Block Diagram RESET TEST STOPC OSC OSC SEL V GND System control RAM (512 4bit) W (2bit) X (4bit) SPX (4bit) Y (4bit) SPY (4bit) ST (1bit) CA (1bit) A (4bit) B (4bit) SP (10bit) Instruction decoder PC (14bit) ROM (4,096 10bit) (2,048 10bit) Internal address bus Internal data bus External interrupt Timer A Timer C Timer D Serial Compa- rator D port R0 port R1 port R2 port R3 port R4 port RD port RC port : Data bus : Signal line ALU High current source pins High current sink pins Intermediate voltage NMOS open-drain output pins* CPU D D D D D D D D D D D D R00 RD RD RD RD RC0 TOC EVND TOD INT INT SI SO SCK VCref COMP COMP CC Internal data bus RE port RE0 Note: Only HD404094 Series

HD404054 Series/HD404094 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000–$07FF (HD404052, HD40A4052, HD404092), $0000–$0FFF (HD404054, HD40A4054, HD4074054, HD404094, HD4074094)): Used for program coding. 2047 $000F $07FF $003F $0040 Vector address Zero-page subroutine (64 words) Program & Pattern 2048 words (HD404052, HD40A4052, HD404092) $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F JMPL instruction (Jump to RESET, STOPC routine) JMPL instruction (Jump to INT routine) JMPL instruction (Jump to timer A routine) JMPL instruction (Jump to timer D, routine) JMPL instruction (Jump to INT routine) JMPL instruction (Jump to serial 1 routine) JMPL instruction (Jump to timer C, routine) Not used $0010 4096 words (HD404054, HD40A4054, HD4074054,HD404094, HD4074094) 4095 $0FFF Figure 1 ROM Memory Map RAM Memory Map The MCU contains a 512-digit × 4-bit RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM memory map is shown in figure 2 and described as follows.

HD404054 Series/HD404094 Series $000 $000 576 960 1023 $040 $050 $003 $004 $005 $006 $007 $008 $009 $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $020 $023 $032 $033 $034 $035 $03F $00E $00F W W R/W W W W W W W W W W W W R R W R/W R/W R/W $3C0 $240 RAM-mapped registers Memory registers (MR) Data (432 digits) Stack (64 digits) Interrupt control bits area Port mode register A Serial mode register 1A Serial data register 1 lower Serial data register 1 upper Timer mode register A Miscellaneous register Timer mode register C1 Timer C Timer mode register D2 Register flag area Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port D to D DCR Port D to D DCR Port D and D DCR Timer read register C lower Timer read register C upper Timer write register C lower Timer write register C upper $090 R/W: Read only Write only Read/Write $011 $012 W W R R Timer read register D lower Timer read register D upper Timer write register D lower Timer write register D upper 144 W Timer mode register D1 R/W R/W Timer D Timer mode register C2 $015 $016 R Compare data register $017 $024 $025 $026 $027 $028 $029 $02A $02B $018 $019 $01F $3FF Compare enable register W W W Port mode register B Port mode register C Detection edge select register 2 Serial mode register 1B Port R4 DCR W W W $02C $02D $02E $02F $031 $030 Two registers are mapped on the same area. R/W R/W (PMRA) (SM1A) (SR1L) (SR1U) (TMA) (MIS) (TMC1) (TRCL/TWCL) (TRCU/TWCU) (TMD1) (TRDL/TWDL) (TRDU/TWDU) (TMC2) (TMD2) (CDR) (CER) (PMRB) (PMRC) (SM1B) (ESR2) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (TRCL) (TRCU) (TRDL) (TRDU) (TWCL) (TWCU) (TWDL) (TWDU) Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Figure 2 RAM Memory Map

HD404054 Series/HD404094 Series RAM-Mapped Register Area ($000–$03F):

• Interrupt Control Bits Area ($000–$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$018, $024–$034) This area is used as mode registers and data registers for external interrupts, serial interface 1, timer/counters, voltage comparator, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023) This area is used for the WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Data Area ($090–$23F): 432 digits from $090 to $23F. Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

HD404054 Series/HD404094 Series $000 $003 PMRA $004 SM1A $005 SR1L $006 SR1U $007 TMA $008 MIS $00C TMC1 $00D TRCL/TWCL $00E TRCU/TWCU $00F TMD1 $010 TRDL/TWDL $011 TRDU/TWDU $012 $013 TMC2 $014 TMD2 $015 $016 CDR $017 CER $018 $020 $023 PMRB $024 PMRC $025 $026 ESR2 $027 SM1B $028 DCD0 $02C DCD1 $02D DCD2 $02E DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 DCR4 $034 $03F Bit 3 Bit 2 Bit 1 Interrupt control bits area : Not used R42/SI1 R43/SO1 Serial transmit clock speed selection 1 Serial data register 1 (lower digit) Serial data register 1 (upper digit) Clock source selection (timer A) SO1 PMOS control Clock source selection (timer C) Timer C register (lower digit) Timer C register (upper digit) Clock source selection (timer D) Timer D register (lower digit) Timer D register (upper digit) Timer-C output mode selection Timer-D output mode selection Result of each analog input comparison Register flag area R40/EVND EVND detection edge selection Port D3 DCR Port D7 DCR Port D2 DCR Port D6 DCR Port D1 DCR Port D5 DCR Port D9 DCR Port D0 DCR Port D4 DCR Port D8 DCR Port R13 DCR Port R23 DCR Port R33 DCR Port R43 DCR Port R12 DCR Port R22 DCR Port R32 DCR Port R42 DCR Port R11 DCR Port R21 DCR Port R31 DCR Port R41 DCR Port R00 DCR Port R10 DCR Port R20 DCR Port R30 DCR Port R40 DCR D12/STOPC D13/INT0 R00/INT1 R41/SCK1 Bit 0 1. Auto-reload on/off 2. Pull-up MOS control 3. Input capture selection 4. Comparator switch 5. Port/comparator selection 6. SO1 output level control in idle states 7. Serial clock source selection 1 Notes: Figure 5 Special Function Register Area

HD404054 Series/HD404094 Series Memory registers $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F 960 $3C0 1023 $3FF MR(0) MR(1) MR(2) MR(3) MR(4) MR(5) MR(6) MR(7) MR(8) MR(9) Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 MR(10) MR(11) MR(12) MR(13) MR(14) MR(15) PC PC PC PC PC PC PC PC PC PC PC PC ST PC CA PC Bit 3 Bit 2 Bit 1 Bit 0 $3FC $3FD $3FE $3FF 1020 1021 1022 1023 PC –PC : ST: CA: Program counter Status flag Carry flag Stack area Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

HD404054 Series/HD404094 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described below. (B) (A) (W) (X) (Y) (SPX) (SPY) (CA) (ST) (PC) (SP) Accumulator B register W register X register Y register SPX register SPY register Carry Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: 1, no R/W Figure 7 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing.

HD404054 Series/HD404094 Series SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction-but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1.

HD404054 Series/HD404094 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value

Contents

(PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt Interrupt enable flag (IE) Inhibits all interrupts flags/mask Interrupt request flag (IF) Indicates there is no interrupt request Interrupt mask (IM) Prevents (masks) interrupt requests I/O Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0 – DCD2) All bits 0 Turns output buffer off (to high impedance) (DCR0– DCR4) All bits 0 Port mode register A (PMRA) - - 00 Refer to description of port mode register A Port mode register B (PMRB) - - - 0 Refer to description of port mode register B Port mode register C bits 3, 2, 1 (PMRC3, PMRC2, PMRC1) 000 - Refer to description of port mode register C Detection edge select register 2 (ESR2) 00 - - Disables edge detection Timer/ Timer mode register A (TMA) - 000 Refer to description of timer mode register A counters, Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1 serial Timer mode register C2 (TMC2) - 000 Refer to description of timer mode register C2 interface Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1 Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2 Serial mode register 1A (SM1A) 0000 Refer to description of serial mode register 1A Serial mode register 1B (SM1B) - - X0 Refer to description of serial mode register 1B Prescaler S (PSS) $000 Timer counter A (TCA) $00 Timer counter C (TCC) $00 Timer counter D (TCD) $00 Timer write register C (TWCU, TWCL) $X0 Timer write register D (TWDU, $X0 Octal counter TWDL) 000 Comparator Compare enable register (CER) 0 - 00 Refer to description of voltage comparator

HD404054 Series/HD404094 Series Item Abbr. Initial Value (WDON) Refer to description of timer C Input capture status flag (ICSF) Refer to description of timer D Input capture error flag (ICEF) Refer to description of timer D Others Miscellaneous register (MIS) 00 - - Refer to description of operating modes, and oscillator circuit Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. – indicates that the bit does not exist Item Abbr. Status After Cancellation of Stop Mode by STOPC Input Status After Cancellation of Stop Mode by MCU Reset Status After all Other Types of Reset Carry flag (CA) Pre-stop-mode values are not guaranteed; values must be initialized by program Pre-MCU-reset values are not guaranteed; values must be initialized by program Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SRL, SRU) RAM Pre-stop-mode values are retained RAM enable flag (RAME) Port mode register 1 bit 2 (PMRC12) Pre-stop-mode values are retained Interrupts The MCU has 6 interrupt sources: Two external signals (INT0, INT1), Three timer/counters (timers A, C, and D), and one serial interface (serial 1). An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $020 to $021 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1.

figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The interrupt program, and reset the IF by a software instruction within the interrupt program.

• The STOPC interrupt request is valid only in stop mode.

HD404054 Series/HD404094 Series IE IFO IMO IF1 IM1 IFTA IMTA IFTC IMTC IFTD IMTD $ 000,0 $ 000,2 $ 000,3 $ 001,0 $ 001,1 $ 001,2 $ 001,3 $ 002,2 $ 002,3 $ 003,0 $ 003,1 Sequence control

• Push PC/CA/ST
• Reset IE
• Jump to vector address Priority control logic Vector address Note: $m,n is RAM address $m, bit number n. $ 003,2 $ 003,3 INT0 interrupt INT1 interrupt Timer A interrupt Timer C interrupt Timer D interrupt Serial 1 interrupt IFS1 IMS1 Not used Figure 8 Interrupt Control Circuit

HD404054 Series/HD404094 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit INT0 INT1 Timer A Timer C Timer D Serial 1 IE IF0 · IM0 IF1 · IM1 IFTA · IMTA IFTC · IMTC IFTD · IMTD IFS1 · IMS1 Note: * Can be either 0 or 1. Their values have no effect on operation. Instruction cycles Instruction execution IE reset Interrupt acceptance Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Vector address generation Note: The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Stacking Figure 9 Interrupt Processing Sequence

HD404054 Series/HD404094 Series Power on RESET = 0? Reset MCU Interrupt request? Execute instruction PC (PC) + 1 PC $0002 PC $0004 PC $0006 PC $000A IE = 1? Accept interrupt IE 0 Stack (PC) Stack (CA) Stack (ST) INT0 interrupt? INT1 interrupt? Timer-A interrupt? No Yes No Yes No Yes Yes Yes Yes Yes No No No (serial 1 interrupt) PC $000C Timer-D interrupt? Yes No No Timer-C interrupt? PC $000E Figure 10 Interrupt Processing Flowchart

HD404054 Series/HD404094 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled Disabled Enabled External Interrupts (INT0, INT1): Two external interrupt signals. External Interrupt Request Flags (IF0, IF1: $000, $001): IF0 and IF1 are set the falling of signals input to INT0 and INT1 as listed in table 5. Table 5 External Interrupt Request Flags (IF0, IF1: $000, $001) IF0, IF1 Interrupt Request No Yes External Interrupt Masks (IM0, IM1: $000, $001): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 ExternalInterrupt Masks (IM0, 1M1: $000, $001) IM0, IM1 Interrupt Request Enabled Disabled (masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2) IFTA Interrupt Request No Yes

HD404054 Series/HD404094 Series Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3) IMTA Interrupt Request Enabled Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 9. Table 9 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request No Yes Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 10. Table 10 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request Enabled Disabled (masked) Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used, as listed in table 11. Table 11 Timer D Interrupt Request Flag (IFTD: $003, Bit 0) IFTD Interrupt Request No Yes

HD404054 Series/HD404094 Series Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 12. Table 12 Timer D Interrupt Mask (IMTD: $003, Bit 1) IMTD Interrupt Request Enabled Disabled (masked) Serial Interrupt Request Flags (IFS1: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 13. Table 13 Serial Interrupt Request Flag (IFS1: $003, Bit 2) IFS1 Interrupt Request No Yes Serial Interrupt Masks (IMS1: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 14. Table 14 Serial Interrupt Mask (IMS1: $003, Bit 3) IMS1 Interrupt Request Enabled Disabled (masked)

HD404054 Series/HD404094 Series Operating Modes The MCU has Three operating modes as shown in table 15. The operations in each mode are listed in tables 16 and 17. Transitions between operating modes are shown in figure 11. Table 15 Operating Modes and Clock Status Mode Name Active Standby Stop Activation method RESET cancellation, interrupt request, STOPC cancellation in stop mode SBY instruction STOP instruction Status System oscillator OP OP Stopped Cancellation method RESET input, STOP/SBY instruction RESET input, interrupt request RESET input, STOPC input in stop mode Note: OP implies in operation Table 16 Operations in Low-Power Dissipation Modes Function Stop Mode Standby Mode CPU Reset Retained RAM Retained Retained Timer A Reset OP Timer C Reset OP Timer D Reset OP Serial interface 1 Reset OP Comparator Reset Stopped I/O Reset* Retained Note: OP implies in operation * Output pins are at high impedance. Table 17 I/O Status in Low-Power Dissipation Modes Output Input Standby Mode Stop Mode Active Mode D0–D9 Retained High impedance Input enabled D12, D13, RC0, RD0–RD3, RE0 Input enabled R0–R4 Retained or output of peripheral functions High impedance Input enabled

HD404054 Series/HD404094 Series Reset by RESET input or by watchdog timer fOSC: ø CPU: ø PER: Oscillate Stop fcyc fOSC: ø CPU: ø PER: Oscillate fcyc fcyc fOSC: ø CPU: ø PER: Standby mode (TMA3 = 0) SBY Interrupt fOSC: fcyc: Main oscillation frequency f /4 or or f /32 (hardware selectable) OSC System clock Clock for other peripheral functions Active mode ø CPU: ø PER RESET1 RESET2 RAME = 0 RAME = 1 STOPC STOP OSC Stop Stop Stop Stop mode Figure 11 MCU Status Transitions Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1 and OSC2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 12.

HD404054 Series/HD404094 Series Standby Oscillator: Active Peripheral clocks: Active All other clocks: Stop No Yes No Yes No Yes No Yes No Yes Yes Restart processor clocks Reset MCU Execute next instruction Accept interrupt Restart processor clocks No Yes IF = 1, IM = 0, and IE = 1? RESET = 0? IF0 • IM0 = 1? IF1 • IM1 = 1? IFTA • IMTA = 1? IFTC • IMTC = 1? IFTD • IMTD = 1? No Yes IFS1 • IMS1 = 1? No Stop Oscillator: Stop Peripheral clocks: Stop All other clocks: Stop RESET = 0? STOPC = 0? RAME = 1 RAME = 0 Yes Yes No No Execute next instruction Figure 12 MCU Operation Flowchart Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. The MCU enters stop mode if the STOP instruction is executed in active mode. Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.

HD404054 Series/HD404094 Series Stop mode Oscillator Internal clock STOP instruction execution tres ≥tRC (stabilization period) tres STOP or RESET Figure 13 Timing of Stop Mode Cancellation Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequences shown in figures 14 to 16. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.

HD404054 Series/HD404094 Series Power on RESET = 0? RAME = 0 Reset MCU MCU operation cycle No Yes Figure 14 MCU Operating Sequence (Power On)

HD404054 Series/HD404094 Series MCU operation cycle IF = 1? Instruction execution SBY/STOP instruction? PC Next location PC Vector address Low-power mode operation cycle IE 0 Stack (PC), (CA), (ST) IM = 0 and IE = 1? Yes No No Yes Yes No IF: IM: IE: PC: CA: ST: Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 15 MCU Operating Sequence (MCU Operation Cycle)

HD404054 Series/HD404094 Series Low-power mode operation cycle IF = 1 and IM = 0? Hardware NOP execution PC Next Iocation MCU operation cycle Standby mode IF = 1 and IM = 0? Hardware NOP execution PC Next Iocation Instruction execution Stop mode No Yes No Yes For IF and IM operation, refer to figure 12. STOPC = 0? RAME = 1 Reset MCU No Yes Figure 16 MCU Operating Sequence (Low-Power Mode Operation)

HD404054 Series/HD404094 Series Table 18 Oscillator Circuit Examples Circuit Configuration Circuit Constants External clock operation External oscillator OSC Open OSC2 Ceramic oscillator (OSC1, OSC2) OSC C OSC Rf Ceramic oscillator GND Ceramic oscillator: CSB400P22 (Murata), CSB400P (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 220 pF ± 5% Ceramic oscillator: CSB800J122 (Murata), CSB800J (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 220 pF ± 5% Ceramic oscillator: CSA2.00MG (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% Ceramic oscillator: CSA3.58MG (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% Notes: 1. Since the circuit constants change depending on the ceramic oscillator and stray capacitance of the board, the user should consult with the ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross other wiring (see figure 18).

HD404054 Series/HD404094 Series Input/Output The MCU has 27 input/output pins (D0–D9, R0 0–R43) and 8 input pins (D12, D13, RC0, RD0– RD3, RE0). The features are described below. Some input/output pins have different features between the HD404054 Series and HD404094 Series. The differences between the HD404054 Series and HD404094 Series are listed in table 19.

• A maximum current of 15 mA is allowed for each of the pins D4 to D9 with a total maximum current of less than 105 mA. In addition, D0–D3 can each act as a 10-mA maximum current source.
• Some input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting.
• Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software.
• Peripheral function output pins are CMOS output pins. Only the R43/SO1 pin can be set to NMOS open- drain output by software.
• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state.
• Pins D0–D3 have built-in pull-down MOSs, and other input/output pins have built-in pull-up MOSs, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 19 programmable I/O circuits are listed in table 20, and I/O pin circuit types are shown in table 21. Table 19 The differences between HD404054 Series and HD404094 Series HD404054 Series HD404094 Series Large-current source pins (15 mA) D0–D3 D0–D3 Large-current sink pins (10 mA) D4–D9 D8, D9 Intermediate voltage NMOS open-drain pins (12 V) D4–D7 (output only) Pull-down MOS current pins D0–D3 D0–D3 Pull-up MOS current pins D4–D9, R0–R4 D8, D9, R0–R4

HD404054 Series/HD404094 Series Table 20-1 Programmable I/O Circuits (with pull-up MOS) MIS3 (Bit 3 of MIS) DCD, DCR PDR CMOS buffer PMOS On On NMOS On On Pull-up MOS On On Note: — indicates off status. Table 20-2 Programmable I/O Circuits (with pull-down MOS) MIS3 (Bit 3 of MIS) DCD, DCR PDR CMOS buffer PMOS On On NMOS On On Pull-down MOS On On Note: — indicates off status. D4–D9, R port (HD404054 Series) D8, D9, R port (HD404094 Series) MIS3 Input control signal VCC Pull-up MOS DCD, DCR PDR Input data VCC HLT Pull-up control signal Buffer control signal Output data Figure 19-1 I/O Buffer Configuration (with pull-up MOS)

HD404054 Series/HD404094 Series D0–D3 port VCC DCD, DCR PDR Pull-down control signal Buffer control signal Output data MIS3 HLT Input control signal Input data Figure 19-2 I/O Buffer Configuration (with pull-down MOS)

HD404054 Series/HD404094 Series Table 21 Circuit Configurations of I/O Pins Pins I/O Pin Type Circuit HD404054 Series HD404094 Series Input/output pins VCC VCC Pull-up control signal Buffer control signal Output data Input data HLT MIS3 DCD, DCR PDR Input control signal D4–D9, R0–R4 D8, D9, R0–R4 VCC DCD, DCR PDR Pull-down control signal Buffer control signal Output data MIS3 HLT Input data Input control signal D0–D3 D0–D3 VCC VCC Pull-up control signal Buffer control signal Output data Input data HLT MIS3 DCR PDR Input control signal MIS2 R43 R43 Output pins Output data HLT PDR DCD D4–D7

HD404054 Series/HD404094 Series Pins I/O Pin Type Circuit HD404054 Series HD404094 Series Input pins Input data Input control signal D12, D13, RC0 RD0–RD3, RE0 D12, D13, RC0 RD0–RD3, RE0 Periphera l function pins Input/ output pins VCC VCC Pull-up control signal Output data Input data HLT MIS3 SCK1 SCK1 SCK1 SCK1 Output pins VCC VCC Pull-up control signal PMOS control signal Output data HLT MIS3 SO1 MIS2 SO1 SO1 VCC VCC Pull-up control signal Output data HLT MIS3 TOC, TOD TOC, TOD TOC, TOD Input pins VCC Input data HLT MIS3 SI1, INT1, EVND PDR SI1, INT1, EVND SI1, INT1, EVND Input data INT0, STOPC INT0, STOPC INT0, STOPC Note: The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. D Port (D0–D13): Consist of 10 input/output pins and 2 input pins addressed by one bit. D0–D3 are high- current sources, and D12 and D13 are input-only pins. D4–D9 of the HD404054 Series are high-current sinks. D4–D7 of the HD404094 Series are middle voltage output-only pins, and D8 and D9 are high-current sink pins. Pins D0–D9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0–D13 are tested by the TD and TDD instructions.

HD404054 Series/HD404094 Series The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2: $02C–$02E) that are mapped to memory addresses (figure 20). Pins D12 and D13 are multiplexed with peripheral function pins S T OP C and I NT0, respectively. The peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode register C (PMRC: $025) (figure 22). R Ports (R00–RE0): 17 input/output pins and 6 input pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. *Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0–DCR4: $030–$034) that are mapped to memory addresses (figure 20). Pin R00 is are multiplexed with peripheral pin INT1 respectively. The peripheral function modes of these pins are selected by bit 0 (PMRB0) of port mode register B (PMRB: $024) (figure 21). Pins R31–R32 are multiplexed with peripheral pins TOC and TOD respectively. The peripheral function modes of these pins are selected by bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014), and bits 0–3 (TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 23, and 24). Pin R40 is multiplexed with peripheral pin EVND respectively. The peripheral function modes of these pins are selected by bit 1 (PMRC1) of port mode register C (PMRC: $025) (figure 22). Pins R41–R43 are multiplexed with peripheral pins SCK1, SI1, and SO1, respectively. The peripheral function modes of these pins are selected by bit 3 (SM1A3) of serial mode register 1A (SM1A: $005), and bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 25 and 26. Ports RD0 and RD1 are multiplexed with peripheral function pins COMP0 and COMP1, respectively. The function modes of these pins are selected by bit 3 (CER3) of the compare enable register (CER: $018) (figure 27). Port RE0 is multiplexed with peripheral function pin VCref. While functioning as VCref, do not use this pin as an R port at the same time, otherwise, the MCU may malfunction. Pull-Up or Pull-Down MOS Transistor Control: A program-controlled pull-up or pull-down MOS transistor is provided for each input/output pin other than input-only pins D12 and D13. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin—enabling on/off control of that pin alone (table 20 and figure 28). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to VCC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 kΩ or pulled down to GND by their pull-down MOS transistors. Note: *If nonexisted bits of R ports is read, undifined data will be latched to accumulator (A) or the B register.

HD404054 Series/HD404094 Series Bit Initial value Read/Write Bit name W DCD03– W DCD02– W DCD00– W DCD01– DCD0, DCD1 Data control register DCD13 DCD12 DCD10 DCD11 Bit Initial value Read/Write Bit name Not used Not used W DCD20 W DCD21 DCD2 Bit Initial value Read/Write Bit name Not used Not used W DCR00 Not used (DCD0 to 2: $02C to $02E) (DCR0 to 4: $030 to $034) DCR0 Bit Initial value Read/Write Bit name Correspondence between ports and DCD/DCR bits DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 Off (high-impedance) On W DCR13– W DCR12– W DCR10– W DCR11– DCR43 DCR42 DCR40 DCR41 DCR1 to DCR4 All Bits CMOS Buffer On/Off Selection Register Name R13 R23 R33 R43 Bit 3 R12 R22 R32 R42 Bit 2 R11 R21 R31 R41 Bit 1 R00 R10 R20 R30 R40 Bit 0 Figure 20 Data Control Registers (DCD, DCR)

HD404054 Series/HD404094 Series Bit Initial value Read/Write Bit name Not used R/W TMC22 R/W TMC20 R/W TMC21 Timer mode register C2 (TMC2: $014) TMC22 TMC20 TMC21 R31/TOC mode selection R31 TOC TOC TOC TOC R31 port Toggle output 0 output 1 output Inhibited PWM output Figure 23 Timer Mode Register C2 (TMC2)

HD404054 Series/HD404094 Series Bit Initial value Read/Write Bit name W MIS3 W MIS2 MIS2 CMOS buffer on/off selection for pin R43/SO1 Miscellaneous register (MIS: $00C) On Off MIS3 Pull-up MOS on/off selection Off On Not used Not used Figure 28 Miscellaneous Register (MIS)

HD404054 Series/HD404094 Series Prescalers The MCU has the following prescaler S. The prescaler operating conditions are listed in table 22, and the prescaler output supply is shown in figure 29. The timers A, C, D input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except at MCU reset. Table 22 Prescaler Operating Conditions Prescaler Input Clock Reset Condition Stop Conditions Prescaler S System clock MCU reset MCU reset, stop mode System clock Prescaler S Timer A Timer C Timer D Serial 1 Figure 29 Prescaler Output Supply

HD404054 Series/HD404094 Series Timers The MCU has three timer/counters (A, C, and D).

• Timer A: Free-running timer
• Timer C: Multifunction timer
• Timer D: Multifunction timer Timer A is an 8-bit free-running timer. Timers C and D are 8-bit multifunction timers, whose functions are listed in table 23. The operating modes are selected by software. Timer A Timer A Functions: Timer A has the following functions.
• Free-running timer The block diagram of timer A is shown in figure 30. Timer A Operations:
• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. Registers for Timer A Operation: Timer A operating modes are set by the following registers.
• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode and input clock source as shown in figure 31.

HD404054 Series/HD404094 Series Table 23 Timer Functions Functions Timer A Timer C Timer D Clock source Prescaler S Available Available Available External event Available Timer functions Free-running Available Available Available Event counter Available Reload Available Available Watchdog Available Input capture Available Timer outputs Toggle Available Available 0 output Available Available 1 output Available Available PWM Available Available Note: — means not available. System clock Selector Prescaler S (PSS) Internal data bus Timer A interrupt request flag (IFTA) Clock Overflow Timer counter A (TCA) Timer mode register A (TMA) øPER 128 512 1024 2048 Figure 30 Block Diagram of Timer A

HD404054 Series/HD404094 Series Bit Initial value Read/Write Bit name W TMA2 W TMA0 W TMA1 Timer mode register A (TMA: $008) PSS PSS PSS PSS PSS PSS PSS PSS Operating mode Timer A mode TMA1 TMA2 TMA0 Source prescaler 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc Input clock frequency Not used Note: Timer counter overflow output period (seconds) = input clock period (seconds) 256. Figure 31 Timer Mode Register A (TMA)

HD404054 Series/HD404094 Series Timer C Timer C Functions: Timer C has the following functions.

• Free-running/reload timer
• Watchdog timer
• Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 32. Watchdog on flag (WDON) System reset signal Timer C interrupt flag (IFTC) Timer output control logic Timer read register CU (TRCU) Timer output control Timer read register CL (TRCL) Clock Timer counter C (TCC) Selector System clock Prescaler S (PSS) Overflow Internal data bus Timer write register CU (TWCU) Timer write register CL (TWCL) Timer mode register C1 (TMC1) Timer mode register C2 (TMC2) Free-running /reload control Watchdog timer control logic TOC øPER ÷32 ÷128 ÷512 ÷1024 ÷2048 Figure 32 Block Diagram of Timer C

HD404054 Series/HD404094 Series Timer C Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details.
• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF.
• Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by MCU reset.  Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer C has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. The output waveform is shown in figure 33.  PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 33.  0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer C has reached $FF. Note that this function must be used only when the output level is high.  1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer C has reached $FF. Note that this function must be used only when the output level is low.

HD404054 Series/HD404094 Series T (N + 1) T 256 T T (256 – N) TMC13 = 0 The waveform is always fixed low when N = $FF. TMC13 = 1 Input clock period to counter (figures 34 and 41) The value of the timer write register Notes: TMD13 = 0 TMD13 = 1 256 clock cycles 256 clock cycles Free-running timer Toggle output waveform (timers C, and D) PWM output waveform (timers C and D) (256 – N) clock cycles (256 – N) clock cycles Reload timer Figure 33 Timer Output Waveform

HD404054 Series/HD404094 Series Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F)

• Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free- running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 34. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C’s initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Bit Initial value Read/Write Bit name W TMC13 W TMC12 W TMC10 W TMC11 Timer mode register C1 (TMC1: $00D) 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc TMC12 TMC10 TMC11 TMC13 Free-running/reload timer selection Free-running timer Reload timer Input clock period Figure 34 Timer Mode Register C1 (TMC1)

HD404054 Series/HD404094 Series Timer D Timer D Functions: Timer D has the following functions.

• Free-running/reload timer
• External event counter
• Timer output operation (toggle, 0, 1, and PWM outputs)
• Input capture timer The block diagram for each operation mode of timer D is shown in figures 40-1 and 40-2. Timer D Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or MCU reset. Refer to figure 3 and table 1 for details.
• External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2tcyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation.
• Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by MCU reset.  Toggle output: The operation is basically the same as that of timer-C’s toggle output.  0 output: The operation is basically the same as that of timer-C’s 0 output.  1 output: The operation is basically the same as that of timer-C’s 1 output.

HD404054 Series/HD404094 Series  PWM output: The operation is basically the same as that of timer-C’s PWM output.

• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing By selecting the input capture operation, pin R32/TOD is set to R32 and timer D is reset to $00.

HD404054 Series/HD404094 Series Timer D interrupt request flag (IFTD) Timer output control logic Timer read register DU (TRDU) Timer output control Timer read register DL (TRDL) Clock Timer counter D (TCD) Selector System clock Prescaler S (PSS) Overflow Internal data bus Timer write register DU (TWDU) Timer write register DL (TWDL) Timer mode register D1 (TMD1) Timer mode register D2 (TMD2) Free-running/ reload control TOD Edge detection logic Edge detection selection register 2 (ESR2) Edge detection control øPER ÷32 ÷128 ÷512 ÷2048 EVND Figure 40-1 Block Diagram of Timer D (Free-Running/Reload Timer)

HD404054 Series/HD404094 Series Selector ÷32 ÷128 ÷512 ÷2048 PER ø Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD) Error control logic Edge detection logic Timer read register DU (TRDU) Timer read register DL (TRDL) Read signal Clock Timer counter D (TCD) Overflow System clock Edge detection control Prescaler S (PSS) Input capture timer control Timer mode register D1 (TMD1) Timer mode register D2 (TMD2) Edge detection selection register 2 (ESR2) EVND Internal data bus Figure 40-2 Block Diagram of Timer D (in Input Capture Timer Mode)

HD404054 Series/HD404094 Series Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027)

• Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free- running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 41. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. Bit Initial value Read/Write Bit name W TMD13 W TMD12 W TMD10 W TMD11 Timer mode register D1 (TMD1: $010) 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc TMD12 TMD10 TMD11 Input clock period and input clock source R40/EVND (external event input) TMD13 Free-running/reload timer selection Free-running timer Reload timer Figure 41 Timer Mode Register D1 (TMD1)

HD404054 Series/HD404094 Series Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 24. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 24 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer Write Register is Updated during Low PWM Output Free running Timer write register updated to value N Interrupt request Timer write register updated to value N Interrupt request T × (N' + 1) T × (255 – N) T × (N + 1) Reload Timer write register updated to value N Interrupt request T T × (255 – N) T Timer write register updated to value N Interrupt request T T × (255 – N) T

HD404054 Series/HD404094 Series Serial Interface 1 The MCU has one channel of serial interface. The serial interface serially transfers or receives 8-bit data, and includes the following features.

• Multiple transmit clock sources  External clock  Internal prescaler output clock  System clock
• Output level control in idle states Serial interface 1
• Serial data register 1 (SR1L: $006, SR1U: $007)
• Serial mode register 1A (SM1A: $005)
• Serial mode register 1B (SM1B: $028)
• Port mode register A (PMRA: $004)
• Miscellaneous register (MIS: $00C)
• Octal counter (OC)
• Selector The block diagram of serial interface 1 is shown in figure 49.

HD404054 Series/HD404094 Series Selector Prescaler S (PSS) ÷32 ÷128 ÷512 ÷2048 Selector I/O control logic Idle control logic Octal counter (OC) Serial interrupt request flag (IFS1) Clock Serial data register (SR1L/U) Serial mode register 1A (SM1A) Serial mode register 1B (SM1B) Transfer control SO1 SCK1 SI1 System clock Internal data bus øPER Figure 49 Block Diagram of Serial Interface 1

HD404054 Series/HD404094 Series Serial Interface Operation Selecting and Changing the Operating Mode: Table 25 lists the serial interface’s operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004), and serial mode register 1A (SM1A: $005) settings; to change the operating mode of serial interface 1, always initialize the serial interface internally by writing data to serial mode register 1A. Note that serial interface 1 is initialized by writing data to serial mode register 1A. Refer to the following section Registers for Serial Interface for details. Pin Setting: The R41/SCK1 pin is controlled by writing data to serial mode register 1A (SM1A: $005). Pins R42/SI1 and R43/SO1 are controlled by writing data to port mode register A (PMRA: $004). Refer to the following section Registers for Serial Interface for details. Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following section Registers for Serial Interface for details. Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L: $006, SR1U: $007). Receive data of serial interface 1 is obtained by reading the contents of serial data register 1. The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO1 pin is invalid until the first data is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: Serial interface 1 is activated by the STS instruction. The octal counter is reset to 000 by the STS instruction, and it increments at the rising edge of the transmit clock for serial interface. When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) for serial interface 1 is set, and the transfer stops. When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 0 to 2 (SM1A0–SM1A2) of serial mode register 1A (SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 26. Table 25 Serial Interface 1 Operating Modes SM1A PMRA Bit 3 Bit 1 Bit 0 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode

HD404054 Series/HD404094 Series Table 26 Serial Transmit Clock (prescaler output) SM1B SM1A Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Tranamit Clock Frequency ÷ 2048 4096tcyc ÷ 512 1024tcyc ÷ 128 256tcyc ÷ 32 64tcyc ÷ 8 16tcyc ÷ 2 4tcyc ÷ 4096 8192tcyc ÷ 1024 2048tcyc ÷ 256 512tcyc ÷ 64 128tcyc ÷ 16 32tcyc ÷ 4 8tcyc Operating States: Serial interface 1 has the following operating states; transitions between them are shown in figure 50.  STS wait state  Transmit clock wait state  Transfer state  Continuous transmit clock output state (only in internal clock mode)

• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 50). In STS wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), serial interface 1 enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04, 14) in transmit clock wait state.
• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks.

HD404054 Series/HD404094 Series In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes serial interface 1, and STS wait state is entered. If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set by the octal counter that is reset to 000.

• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK1 pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait state is entered. STS wait state (Octal counter = 000, transmit clock disabled) Transmit clock wait state (Octal counter = 000) MCU reset SM1A write STS instruction Transmit clock 8 transmit clocks STS instruction (IFS1 1) SM1A write (IFS1 1) External clock mode STS wait state (Octal counter = 000, transmit clock disabled) Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter 000) SM1A write STS instruction Transmit clock STS instruction (IFS1 1) 8 transmit clocks Internal clock mode Continuous transmit clock output state (PMRA 0, 1 = 0, 0) SM1A write Transmit clock Note: Refer to the Operating States section for the corresponding encircled numbers. MCU reset SM1A write (IFS1 1) Transfer state (Octal counter 000) Figure 50 Serial Interface State Transitions Output Level Control in Idle States: When serial interface 1 is in STS instruction wait state, the output of serial output pin, SO1 can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1. The output level control example of serial interface 1 is shown in Figure 51. Note that the output level cannot be controlled in transfer state.

HD404054 Series/HD404094 Series State MCU reset PMRA write SM1A write SM1B write SR1L, SR1U write STS instruction SCK1 pin (input) SO1 pin IFS1 STS wait state Transmit clock wait state Transfer state Transmit clock wait state STS wait state Port selection External clock selection Output level control in idle states Dummy write for state transition Output level control in idle states Data write for transmission Undefined LSB MSB Flag reset at transfer completion External clock mode State MCU reset PMRA write SM1A write SM1B write SR1L, SR1U write STS instruction SCK1 pin (output) SO1 pin IFS1 STS wait state Transfer state Transmit clock wait state STS wait state Port selection Internal clock selection Output level control in idle states Data write for transmission Output level control in idle states Undefined LSB MSB Flag reset at transfer completion Internal clock mode Figure 51 Example of Serial Interface 1 Operation Sequence

HD404054 Series/HD404094 Series Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 52. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer is completed and IFS is reset, writing to serial mode register 1A (SM1A: $005) changes the state from transfer to STS wait. At this time serial interface 1 is in the transfer state, and the serial 1 interrupt request flag is set again, and therefore the error can be detected. Notes on Use:

• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1A (SM1A: $005) again.
• Serial 1 interrupt request flag (IFS1: $003, bit 2) set: For serial interface 1, if the state is changed from transfer state to another by writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial 1 interrupt request flag is not set. To set the serial 1 interrupt request flag, a serial mode register 1A write or STS instruction execution must be programmed to be executed after confirming that the SCK1 pin is at 1, that is, after executing the input instruction to port R4.

HD404054 Series/HD404094 Series Transfer completion (IFS1 1) Interrupts inhibited IFS1 0 SM1A write IFS1 = 1 Transmit clock error processing Normal termination Yes No Transmit clock error detection flowchart Transmit clock error detection procedures State Transmit clock wait state Transfer state Transfer state Transmit clock wait state Noise Transfer state has been entered by the transmit clock error. When SM1A is written, IFS1 is set. Flag set because octal counter reaches 000. Flag reset at transfer completion. SM1A write SCK pin (input) IFS1 Figure 52 Transmit Clock Error Detection

HD404054 Series/HD404094 Series Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers.

• Serial mode register 1A (SM1A: $005)
• Serial mode register 1B (SM1B: $028)
• Serial data register 1 (SR1L: $006, SR1U: $007)
• Port mode register A (PMRA: $004)
• Miscellaneous register (MIS: $00C) Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 53).
• R41/SCK1 pin function selection
• Serial interface 1 transmit clock selection
• Serial interface 1 prescaler division ratio selection
• Serial interface 1 initialization Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock to serial data register 1 (SR1L: $006, SR1U: $007) and the octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that.

HD404054 Series/HD404094 Series Bit Initial value Read/Write Bit name W SM1A3 W SM1A2 W SM1A0 W SM1A1 Serial mode register 1A (SM1A: $005) SM1A2 SM1A0 SM1A1 SM1A3 R41/SCK1 mode selection R41 SCK1 SCK1 Output Output Input Clock source Prescaler System clock External clock Prescaler division ratio Refer to table 26 Figure 53 Serial Mode Register 1A (SM1A) Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 54).

• Serial interface 1 prescaler division ratio selection
• Serial interface 1 output level control in idle states Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SM1B0) of this register, the serial interface 1 prescaler division ratio is selected. Only bit 0 (SM1B0) can be reset to 0 by MCU reset. By setting bit 1 (SM1B1), the output level of the SO1 pin is controlled in idle states of serial interface 1. The output level changes at the same time that SM1B1 is written to.

HD404054 Series/HD404094 Series Miscellaneous Register (MIS: $00C): This register has the following functions (figure 59).

• R43/SO1 pin PMOS control Miscellaneous register (MIS: $00C) is a 2-bit write-only register and is reset to $0 by MCU reset. MIS2 R43/SO1 PMOS on/off selection On Off Bit Initial value Read/Write Bit name W MIS3 W MIS2 Miscellaneous register (MIS: $00C) MIS3 Pull-up MOS on/off selection Off On Not used Not used Figure 59 Miscellaneous Register (MIS)

HD404054 Series/HD404094 Series Comparator The block diagram of the comparator is shown in figure 60. The comparator compares input voltage with the reference voltage. Setting 1 to bit 3 (CER3) of the compare enable register (CER: $018) executes a voltage comparison. When an input voltage at COMP0, COMP1 is higher than the reference voltage, the TM or TMD command sets the status flag (ST) high for the corresponding bits of the compare data register (CDR: $017) to COMP0 and COMP1. On the other hand, when an input voltage at COMP0, COMP1 is lower, the TM or TMD command clears the ST to 0. Selector Com- parator Comparator data register (CDR) Comparator enable register (CER) Internal data bus COMP0 VCref COMP COMP1 Figure 60 Block Diagram of Comparator

HD404054 Series/HD404094 Series Programmable ROM (HD4074054, HD4074094) The HD4074054 and HD4074094 are ZTAT microcomputers with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description Pin No. MCU Mode PROM Mode DP-42S FP-44A Pin Name I/O Pin Name I/O RD0/COMP0 I CE I RD1/COMP1 I OE I RD2 I RD3 I RC0 I RE0/VCref I I TEST I TEST I OSC1 I VCC OSC2 O RESET I RESET I GND I GND I/O O I/O O I/O VCC I/O VCC I/O* I/O I/O* I/O I/O* I/O I/O* I/O I/O A13 I I/O A14 I D12 /STOPC I I D13 /INT0 I VPP R00 /INT1 I/O I R10 I/O I R11 I/O I R12 I/O I Note: I/O: Input/output pin, I: Input pin, O: Output pin * HD404054 Series: I/O, HD404094 Series: O

HD404054 Series/HD404094 Series Pin No. MCU Mode PROM Mode DP-42S FP-44A Pin Name I/O Pin Name I/O R13 I/O I R20 I/O I R21 I/O A10 I R22 I/O A11 I R23 I/O A12 I R30 I/O I R31/TOC I/O I R32/TOD I/O I R33 I/O I R40/EVND I/O I/O R41/SCK1 I/O I/O R42/SI1 I/O I/O R43/SO1 I/O I/O SEL I VCC I VCC NC NC Note: I/O: Input/output pin, I: Input pin, O: Output pin

HD404054 Series/HD404094 Series Programming the Built-In PROM The MCU’s built-in PROM is programmed in PROM mode. PROM mode is set by pulling TEST, M0, and M1 low, and RESET low as shown in figure 63. In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and an 42-to-28-pin socket adapter. Recommended PROM programmers and socket adapters of the HD4074054 and HD4074094 are listed in table 27. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 4-kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 8-kbyte address space ($0000–$7FFF) must be specified. Address A0 to A14 Data O0 to O7 OE CE VPP GND VCC VCC O0 to O7 A0 to A14 OE CE VPP RESET TEST VCC OSC1 HD4074054 HD4074094 Figure 63 PROM Mode Connections Table 27 Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacturer Model Name Package Model Name Manufacturer DATA I/O Corp. 121B DP-42S HS4654ESS01H Hitachi AVAL Corp. PKW-1000 FP-44A HS4654ESH01H Hitachi

HD404054 Series/HD404094 Series Warnings 1. Always specify addresses $0000 to $1FFF when programming with a PROM programmer. If address $2000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased or reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP): 12.5 V and 21 V. Remember that ZTAT devices require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. Programming and verification modes are selected as listed in table 28. Table 28 PROM Mode Selection Pin Mode CE OE VPP O0–O7 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance

HD404054 Series/HD404094 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 64 and described below. AP9 AP0 W register X register Y register RAM address AP9 AP0 RAM address d 9 2nd word of Instruction Opcode 1st word of Instruction AP9 AP0 RAM address Opcode Instruction AP8 AP7 AP AP5 AP4 AP3 AP2 AP1 AP AP AP AP AP AP AP AP d 8 d 5 d 4 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 Direct addressing Memory register addressing Register direct addressing Figure 64 RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.

HD404054 Series/HD404094 Series ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 65 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC13–PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 67. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000– $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight high- order bits (PC13–PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four- bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 66. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter.

HD404054 Series/HD404094 Series d 8 d 5 d 4 2nd word of instruction Opcode 1st word of instruction [JMPL] [BRL] [CALL] PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC PC PC PC Program counter Direct addressing Zero page addressing d 4 d 1 d 0 Instruction [CAL] Opcode PC9

8 PC7

6 PC5

4 PC3

PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC PC PC B 2 B 3 B register [TBR] Instruction Opcode PC Opcode b 5 b 4 Instruction PC9 PC PC PC Program counter Current page addressing [BR] PC10

7 PC6 PC5 PC4 PC3 PC2 PC1 PC

Figure 65 ROM Addressing Modes

HD404054 Series/HD404094 Series B 1 B 0 A 3 A 2 A 1 A 0 Accumulator Referenced ROM address Address designation RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA RA RA B 2 B 3 B register [P] Instruction Opcode RA RO9 RO0 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 B B B B A A A A If RO = 1 Accumulator, B register ROM data Pattern output RO9 ROM data If RO = 1 Output registers R1, R2 R23 R22 R21 R20 R13 R12 R11 R10 RO0 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 Figure 66 P Instruction

HD404054 Series/HD404094 Series BR AAA AAA NOP 256 (n – 1) + 255 256n BR AAA BR BBB 256n + 254 256n + 255 256 (n + 1) BBB NOP Figure 67 Branching when the Branch Destination is on a Page Boundary

HD404054 Series/HD404094 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V Pin voltage VT –0.3 to VCC + 0.3 V –0.3 to +15.0 V Total permissible input current ∑Io mA Total permissible output current –∑Io mA Maximum input current Io mA 5, 6 mA 5, 7 Maximum output current –Io mA 8, 9 mA 8, 10 Operating temperature Topr –20 to +75 Storage temperature Tstg –55 to +125 Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D13 (VPP) of HD4074054 and HD4074094. 2. Applies to D4 to D7 of HD404092, HD404094, and HD4074094. 3. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 4. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 5. The maximum input current is the maximum current flowing from each I/O pin to GND. 6. Applies to D0–D3, and R0–R4. 7. Applies to D4–D9 . 8. The maximum output current is the maximum current flowing out from VCC to each I/O pin. 9. Applies to D4–D9 and R0–R4. 10. Applies to D0–D3.

HD404054 Series/HD404094 Series

Electrical Characteristics

DC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Input high voltage VIH RESET, STOPC, INT0, INT1, SCK1, SI1, EVND

0.9 VCC

VCC + 0.3 V OSC1 VCC – 0.3 VCC + 0.3 V External clock Input low voltage VIL RESET, STOPC, INT0, INT1, SCK1, SI1, EVND –0.3

0.10 VCC

V OSC1 –0.3 0.3 V External clock Output high voltage VOH SCK1, SO1, TOC,TOD VCC – 1.0 V –IOH = 0.5 mA Output low voltage VOL SCK1, SO1, TOC,TOD 0.4 V IOL = 0.4 mA I/O leakage current | IIL | RESET, STOPC, INT0, INT1, SCK1, SI1, SO1, EVND, OSC1, TOC, TOD µA Vin = 0 V to VCC Current dissipation in active mode ICC1 VCC mA VCC = 5 V, fOSC = 4 MHz Digital input mode 2, 4, mA VCC = 5 V, fOSC = 8 MHz Digital input mode 3, 4, ICC2 VCC 0.6 1.8 mA VCC = 3 V, fOSC = 800 kHz Digital input mode 2, 4, ICMP1 VCC mA VCC = 5 V, fOSC = 4 MHz Analog comp. mode 2, 4, mA VCC = 5 V, fOSC = 8 MHz Analog comp. mode 3, 4, ICMP2 VCC 3.1 4.3 mA VCC = 3 V, fOSC = 800 kHz Analog comp. mode 2, 4,

HD404054 Series/HD404094 Series Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Current dissipation in standby mode ISBY1 VCC 1.2 mA VCC = 5 V, fOSC = 4 MHz 2, 6, mA VCC = 5 V, fOSC = 8 MHz 3, 6, ISBY2 VCC 0.2 0.7 mA VCC = 3 V, fOSC = 800 kHz 2, 6, Current dissipation in stop mode ISTOP VCC µA VCC = 3 V 2, 7 µA VCC = 5 V 3, 7 Stop mode retaining voltage VSTOP VCC 1.3 V Comparator input reference voltage scope VCref VCref VCC – 1.2 V Notes: 1. Output buffer current is excluded. 2. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094 and HD4074094. 3. Applies to HD40A4052 and HD40A4054. 4. ICC1 and ICC2 are the source currents when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at GND (0 V to 0.3V) TEST at VCC (VCC – 0.3 to VCC) 5. RD0 and RD1 pins are analog input mode when no I/O current is flowing. Test conditions: MCU: Analog input mode Pins: RD0/COMP0 at GND (0 V to 0.3 V) RD1/COMP1 at GND (0 V to 0.3 V) RE0/VCref at GND (0 V to 0.3 V) 6. ISBY1 and ISBY2 are the source currents when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at VCC (VCC – 0.3 to VCC) TEST at VCC (VCC – 0.3 to VCC) 7. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at VCC (VCC – 0.3 to VCC) TEST at VCC (VCC – 0.3 to VCC) D13* at VCC (VCC – 0.3 to VCC) Note: * Applies to HD4074054 and HD4074094 8. RAM data retention.

HD404054 Series/HD404094 Series I/O Characteristics for Standard Pins (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD40A4052, HD40A4054: V CC = 4.0 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Input high voltage VIH D12–D13, R0–RD, RE0

0.7 VCC

VCC + 0.3 V Input low voltage VIL D12–D13, R0–RD, RE0 –0.3

0.3 VCC

V Output high voltage VOH R0–R4 VCC – 1.0 — V –IOH = 0.5 mA Output low voltage VOL R0–R4 0.4 V IOL = 0.4 mA I/O leakage current | IIL | D12, R0–RD, RE0 µA Vin = 0 V to VCC D13 µA Vin = 0 V to VCC 1, 2, µA Vin = VCC – 0.3 V to VCC 1, 3 µA Vin = 0 V to 0.3 V 1, 3 Pull-up MOS current –IPU R0–R4 µA VCC = 3 V, Vin = 0 V 2, 3 100 500 µA VCC = 5 V, Vin = 0 V Input high voltage VIHA COMP0, COMP1 VCref+0.0 V Analog compare mode Input low voltage VILA COMP0, COMP1 VCref–0.05 — V Analog compare mode Notes: 1. Output buffer current is excluded. 2. Applies to HD404052, HD404054, HD404092, HD404094. 3. Applies to HD4074054, HD4074094. 4. Applies to HD40A4052, HD40A4054. 5. The analog input reference voltage should be in the range 0 ≤ VCref ≤ VCC–1.2.

HD404054 Series/HD404094 Series I/O Characteristics for High-Current Pins and Intermediate-Voltage Pins (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Pin(s) Item Symbol HD404054 Series HD404094 Series Min Typ Max Unit Test Condition Notes Input high voltage VIH D0–D9 D0–D3, D8, D9 VCC + 0.3 V Input low voltage VIL D0–D9 D0–D3, D8, D9 –0.3 V Output high voltage VOH D0–D9 D0–D3, D8, D9 VCC – 1.0 V –IOH = 0.5 mA D0–D3 D0–D3 2.0 V –IOH = 10 mA, VCC = 4.5 V to 6.0 V D4–D7 11.5 V 500 kΩ at 12 V Output low voltage VOL D0–D9 D0–D9 0.4 V IOL = 0.4 mA D4–D9 D4–D9 2.0 V IOL = 15 mA, VCC = 4.5 V to 6.0 V I/O leakage current | IIL | D0–D9 D0–D3, D8, D9 µA Vin = 0 V to VCC 1 D4–D7 µA Vin = 0 V to 12 V Pull-down MOS current IPD D0–D3 D0–D3 µA VCC = 3 V, Vin = 3 V 100 500 µA VCC = 5 V, Vin = 5 V Pull-up MOS current –IPU D4–D9 D8, D9 µA VCC = 3 V, Vin = 0 V 100 500 µA VCC = 5 V, Vin = 0 V Notes: 1. Output buffer current is excluded. 2. When using HD4074054, HD4074094, VCC = 4.5 V to 5.5 V. 3. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094. 4. Applies to HD40A4052, HD40A4054.

HD404054 Series/HD404094 Series AC Characteristics (HD404052, HD404054, HD404092, HD404094: VCC = 1.8 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD40A4052, HD40A4054: VCC = 4.0 V to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074054, HD4074094: VCC = 2.7 V to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Clock oscillation frequency fOSC OSC1, OSC2 0.4 MHz 0.4 8.5 MHz Instruction cycle time tcyc µs fOSC = 4 MHz, ÷32 1, 4 3.76 µs fOSC = 8.5 MHz, ÷32 2, 4 µs fOSC = 4 MHz, ÷4 1, 3 0.47 µs fOSC = 8.5 MHz, ÷4 2, 3 Oscillation stabilization time (ceramic) tRC OSC1, OSC2 7.5 ms VCC = 2.7 V to 5.5 V: HD4074054, HD4074094 3, 4 VCC = 2.7 V to 6.0 V: HD404052, HD404054, HD404092, HD404094 ms VCC = 1.8 V to 2.7 V: HD404052, HD404054, HD404092, HD404094 7.5 ms VCC = 4.0 V to 6.0 V: HD40A4052,HD40A4054 5, 6 External clock high width tCPH OSC1 105 ns 1, 7 ns 2, 7 External clock low width tCPL OSC1 105 ns 1, 7 ns 2, 7 External clock rise time tCPr OSC1 ns 1, 7 ns 2, 7 External clock fall time tCPf OSC1 ns 1, 7 ns 2, 7 INT0, INT1, EVND high width tIH INT0, INT1, EVND tcyc INT0, INT1, EVND low width tIL INT0, INT1, EVND tcyc RESET low width tRSTL RESET tcyc STOPC low width tSTPL STOPC tRC RESET rise time tRSTr RESET ms STOPC rise time tSTPr STOPC ms

HD404054 Series/HD404094 Series Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Input capacitance Cin All pins except D13 D4–D7 pF f = 1 MHz, Vin = 0 V D4–D7 pF f = 1 MHz, Vin = 0 V D13 pF f = 1 MHz, Vin = 0 V: HD404052, HD404054, HD404092, HD404094, HD40A4052,HD40A4054 180 pF f = 1 MHz, Vin = 0 V: HD4074054, HD4074094 Analog comparator stabilization time tCSTB COMP0, COMP1 tcyc VCC = 2.7 V to 5.5 V: HD4074054, HD4074094 VCC = 2.7 V to 6.0 V: HD404052, HD404054, HD404092, HD404094 tcyc VCC = 4.0 V to 6.0 V: HD40A4052,HD40A4054 tcyc VCC = 1.8 V to 2.7 V: HD404052, HD404054, HD404092, HD404094 Notes: 1. Applies to HD404052, HD404054, HD4074054, HD404092, HD404094, HD4074094. 2. Applies to HD40A4052, HD40A4054. 3. SEL = 1 4. SEL = 0 5. The oscillation stabilization time is the period required for the oscillator to stabilize after VCC reaches 2.7 (HD4074054, HD4074094)/1.8 (HD404052, HD404054, HD404092, HD404094) /4.0 (HD40A4052, HD40A4054)V at power-on, or after RESET input goes low or STOPC input goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 6. Applies to ceramic oscillator only. 7. Refer to figure 68. 8. Refer to figure 69. 9. Refer to figure 70. 10. Refer to figure 71. 11. Analog comparator stabilization time is the period for the analog comparator to stabilize and for correct data to be read after entering RD0/COMP0, RD1/COMP1 into analog input mode.

HD404054 Series/HD404094 Series During Transmit Clock Input Item Symbol Pin(s) Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK1 tcyc Transmit clock high width tSCKH SCK1 0.5 tScyc Transmit clock low width tSCKL SCK1 0.5 tScyc Transmit clock rise time tSCKr SCK1 100 ns 1, 2 ns 1, 3 Transmit clock fall time tSCKf SCK1 100 ns 1, 2 ns 1, 3 Serial output data delay time tDSO SO1 500 ns Load shown in figure 73 1, 2 200 ns 1, 3 Serial input data setup time tSSI SI1 300 ns 1, 2 150 ns 1, 3 Serial input data hold time tHSI SI1 300 ns 1, 2 150 ns 1, 3 Note: 1. Refer to figure72. 2. Applies to HD404052, HD404054, HD404092, HD404094, HD4074054, HD4074094. 3. Applies to HD40A4052, HD40A4054.

HD404054 Series/HD404094 Series tCPr tCPf VCC – 0.3 V 0.3 V tCPH tCPL 1/fCP OSC 1 Figure 68 External Clock Timing tRSTr tRSTL

0.1 VCC

Figure 69 Interrupt Timing INT0 , INT1, EVND tIH tIL Figure 70 Reset Timing tSTPr tSTPL

HD404054 Series/HD404094 Series Notes On ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as 4-kword versions (HD404054, HD404094 and HD40A4054). A 4-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 4-kword version. This limitation apply to the case of using EPROM and the case of using data base. Fill this area with all 1s Vector address Zero-page subroutine (64 words) Pattern and program (2048 words) Not used ROM 2 kwords version: HD404052, HD404092, HD40A4052 Address $0800 to $0FFF $0000 $000F $0010 $003F $0040 $07FF $0800 $0FFF

HD404054 Series/HD404094 Series HD40(A)4052/HD40(A)4054 Option List Please check off the appropriate applications and enter the necessary information. 2. ROM code media Date of order Customer Department Name ROM code name LSI number EPROM: Ceramic oscillator Crystal oscillator External clock f = MHz f = MHz f = MHz 3. Oscillator for OSC1 and OSC2 The upper bits and lower bits are mixed together. The upper five bits and lower five bits EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. HD404052: 2-kword HD404054: 4-kword HD40A4052: 2-kword HD40A4054: 4-kword 1. ROM size DP-42S FP-44A 5. Package Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). Used Not used 4. Stop mode

HD404054 Series/HD404094 Series 100 HD404092/HD404094 Option List Please check off the appropriate applications and enter the necessary information. 2. ROM code media Date of order Customer Department Name ROM code name LSI number EPROM: Ceramic oscillator Crystal oscillator External clock f = MHz f = MHz f = MHz 3. Oscillator for OSC1 and OSC2 The upper bits and lower bits are mixed together. The upper five bits and lower five bits EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. HD404092: 2-kword HD404094: 4-kword 1. ROM size DP-42S FP-44A 5. Package Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). Used Not used 4. Stop mode

HD404054 Series/HD404094 Series 101 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. Hitachi Asia Pte. Ltd.

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