HD404019

Hitachi Semiconductor

CMOS 4-BIT SINGLE-CHIP MICROCOMPUTERS

Manufacturer variants: 1

Selected specification: Hitachi Semiconductor

Documents: 1

Request Quote Download Datasheet Read online HTML view

Compare manufacturer specifications More from Hitachi Semiconductor Browse H parts

Manufacturer Specifications

Compare HD404019 variants.

Select a manufacturer to view its specifications, local PDF, and searchable HTML text.

1 manufacturers / 1 documents

Manufacturer	Series	Package	Documents	Available	Select specification
Hitachi Semiconductor	-	-	1	PDF HTML	Viewing

Online Datasheet

Read the Hitachi Semiconductor document online.

HD404019 HITACHI

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 69

Technical content

HD404019/HD4074019 49 44-04 Description —Preliminary— ‘The HD404019, HD4074019 are CMOS 4-bit © Packages single-chip microcomputers in the HMCS400 —64-pin shrink type plastic DIP series, Each device incorporates ROM, RAM, ~-64-pin flat plastic package 1/O, serial interface, and 2 timer/counters and —64-pin shrink type ceramic DIP with contains high-voltage 1/O pins, including window high-current output pins to drive fluorescent @ Instruction set compatible with displays directly. HMCS408: 101 instructions — —_ # High programming officioncy with 10-bit/ word ROM: 79 single-word instructions Features @ Direct branch to all RAM areas © Direct or indirect addressing of all RAM © 4-bit architecture areas © 16384 words of 10-bit ROM © Subroutine nesting up to 16 levels includ- —Mask ROM: HD404019 ing interrupts —PROM: HD4074019 © Binary and BCD arithmetic operations © 992 digits of 4-bit RAM © Powerful logical arithmetic operations @ 68 1/O pins, including 26 high-voltage I/O @ Pattern generation-table lookup capabil- pins (40 V max) ity © 2 timer/counters © Bit manipulation for both RAM and 1/0 —11-bit prescaler —8-bit free running timer/counter Program Development Support Tools —8-bit auto-reload timer/event counter P ml Clock synchronous 8-bit serial interface ® Cross assembler and simulator software for @ Five interrupt sources use with IBM PCs and compatibles —Extemal: 2 , —imer/counter: 2 © In circuit emulator for use with IBM PC Serial interface: 1 © Programming socket adapter for program- © Subroutine stack ee the BEBO chee —Up to 16 levels including interrupts ming the Fon-chip 8 e “ou instruction execution time Ordering Information —Standby: Stops instruction execution Mask ROM HD404019S. OP-64S while allowing clock oscillation and = ‘YP? HD404019F ——_*FP-64B, interrupt functions to operate HOsoao1st FPGA Stop: Stops instruction execution and ==—____TDAAOIGH_FRS#A_ clock oscillation while retaining RAM — TAT type HD4074019S_DP-64S data HO4074010F _FP-648 © On-chip oscillator Hoso7401I96_ OAS TGryetal or coramie filter HD4O74010H__FD-G4A geiiz 3 sesse booAAnAAgnAAAAA vo (S2eseea5e2a0e588 | Bie Gh2 oBo, map Boe mae pas] mes corer me ae mofo 25 chs xB mee 35 ee TTT ET gagaseeaaa [ CRETE CICILY € Ei BBEY FP-64A @uHITACHI 24 Hitachi America Ltd, « Hitachi Piaza * 2000 Sierra Pint Phy. « Brisbane, CA 94005-1819 « (415) 569-8300

Pin Arrangement T-49-19-04 o. ro The. $essssssasaad once Be AOARIENONOOOnA pa “Bs po pesesse ane aTaGL st ‘Be roe: Ep mH “Be mols ojo mee Bo. autie «hose, eae a rs }i0 af]ars wes “Bae mo, sasaseeeg = Sl tone “Base OOUOW ONO bs Pine badedd Ree Zee Vie z z {DP-648,DC-648) {Top View) (FP-64B) SSS‘ Block Diagram acvor ——} CAP ere) Case] bs oo a ee me am | ff ff ™ ST UT UF Fa 5 raleaiea [=\\ APIO] = if ia | _ oa LE Eee LES RARLDEAS LRASEEERR ERLE] @HITACHI Hitachi America Ltd. « Hitachi Plaza # 2000 Sierra Point Pkwy. © Brisbana, CA 94005-1819 (415) 589-8300 285

Pin Description 7-49-19-04 GND, Voc, Vaisp (Power) high-voltage pins. The circuit type for each pin can be selected using a mask option. For GND, Vcc, and Vaisp are the power supply pins details, see Input/Output section. for the MCU. Connect GND to the ground (0 V) and apply ROo—R0s, Rlo—Ris, R2—R2s, R3o—R3s, the Vcc power supply voltage to the Vcc pin. R4o—R4s, R5o—RSs, R6o—R6sz, R7o—R7s, The Vasp pin (multiplexed with RAi) is a R80—R8s, R9o—R9z, RAo, RA: (R Ports) power supply for high-voltage I/O pins with maximum voltage of 40 V (Voc - 40 V). For RO to R9 ere 4-bit I/O ports. RA is a Z-bit port, details, see Input/Output section. R9 and RA are input ports, and RO to R8 1/0 ports, RO, Ri, R2, and RA are high-voltage TEST (Test) ports, and R3 to R9 are standard ports. Each pin has a mask option which selects its circuit TEST is for test purposes only. Connect it to _ type. The pins R3z, Rs, R4o, Ray, and R42 are Veo. multiplexed with INTo, INT;, SCK, SI, and SO respectively. For details, see Input/Output RESET (Reset) section. RESET resets the MCU, For details, see Reset INT), INT: (Interrupts) section, INT and INT; are oxtomal interrupts for the OSC, OSC2 (Oscillator Connections) MCU. INT; can be used as an external event input pin for timer B, INT and INT; are OSC; and OSC; are input pins for the internal _—multipiexed with R3z and R3s respectively. oscillator circuit. They can be connected toa For details, see Interrupt section, crystal resonator, ceramic filter resonator, or external oscillator circuits. For details, see SCK, SI, SO Internal Oscillator Circuit section, __ The transfer clock 1/O pin (SCR), serial data Do—Dis (D Port) input pin (SI), and serial data output pin (SO) are used for sorial interface. SCK, SI, and SO The D port is an input/output port addressed are_ multiplexed with R4o, R4;, and R42 by the bit, These 16 pins are all input/output —_respectively. For details, see Serial Interface pins, Do to Dy are standard and Dy to Dis are Section. @uitacHi Hitachi America Lid. « Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300 27

ROM (mask ROM or PROM). It is described in branch to subroutines. Locations $0000 through $000F are reserved —as.a pattern. or interrupt routine is serviced, the program program code. is exeouted from the vector address.

4 MPL Instruction $0004

4095 SOFFF tof 5 0008

Figure 1. ROM Memory Map

RAM Memory Map However, the interrupt request flag cannot be set by software. The RSP bit is used only to The MCU includes 992 digits of 4-bit RAMas _reset the stack pointer, T-49-19-04 the data and stack area. In addition to these whan aa=' areas, interrupt control bits and special func- Special Function Registers Area (S004 to tion registers are also mapped on the RAM —_$00B): The special function registers are the memory space. The RAM memory mep (figure mode or data registers for the external inter- 2) is described in the following paragraphs. Tupt, the serial interface, and the timer/ counter. Theso registers are classified into Interrupt Control Bit Area ($000 to $003): _three types: write-only, read-only, and read/ The interrupt control bit area (figure 3) is write as shown in figure 2, These registers used for interrupt controls. It is accessable cannot be accessed by RAM bit manipulation only by a RAM bit manipulation instruction. _ instructions. -)——— 9 [$000 0 1s 000 RAM-mapped Ragisters 1 $001 a1 gore 2 Interrupt Control Bits 1$ 002 32) '$ 021 3 1s 003 M ax}__Mamory Resistors (MP oor 4| Por Made Reg (PMAY_| w | 008 “a i$ 030 5|_Serial Mode Reg. (SMA) | W ]$.005 peta 6] Serial Data Reg. Lower (SRL) $006 (028 Digits} 7[_ Serial Date Rea. Upper (SAU) IRAN] $ 007 8] __Timer Mode Reg. A (TMA) | W [$008 9f Timer Mode Reg.8 (TMB) | W |$ 009 rol (TCBL/TLAL) [RW] $ 0OA aap tmer8 ITCBU/TLAU)|RAW| $ 008 12] '$ 00¢ 959] '$ 3BF

980 I$ 3cO

1029 (64 Digits) sre Note: Two registers are mapped on same address. \\Timer/Event Counter B Lower! Timer Load Reg. Lower : R: Read Only 10 trent} A OLR iw | gooa We Witte Only r/Event Ce BU 4 Ti Load Re U; ; Timer ‘ountar B Upper! mer ea. Upper RAY: Read/Write " TreBU} fa maa LW | soos Figure 2, RAM Memory Map @uitacui Hitachi America Ltd, « Hitachi Plaza 2000 Sierra Point Phy. « Brisbane, CA 94005-1819 « (46) 689.8900 289

(PC), status (ST), and carry (CA) when su- _used for a stack, is available as a data area.

1 IMTA ITA m4 al $001

8 Not Used (IM of SERIAL) ur of sertar) | $08

‘affected by the SEM/SEMD instruction. ‘The contents of status bacomes Invalid when a “Not Used! bit is tested. Figure 3. Interrupt Control Bit Area Configuration

4 S028

Figure 4. Configuration of Memory Register, Stack Area, and Stack Position

W Register (W), X Register (X), Y Regis- instruction, but not by a RTN instruction. SPX Register (SPX), SPY Register (SPY): stored in ROM are executed. Carry (CA): The carry (CA) stores the over- _—_(up to 16 levels). During interrupt servicing, carry is pushed cremented by 4 when data is restored from it. Figure 6. Registers and Flags

counter (timer A, timer B), and serial port 1 at initialization by MCU reset. Figure 6. Interrupt Control Circuit Block Diagram

priority PLA corresponding to the interrupt address. Table 1. Vector Addresses and Inter- Table 2. Conditions of Interrupt Service

can be solected by the port mode register —_ respectively. masks mask the external interrupt requests. is used as timer B extemal event input, initially used as ports. Table 3. Interrupt Enable Flag Table 6. Port Mode Register Table 4. External Interrupt Request pmn2 _Raa/IfiTo Pin

1 Yes

Table 6. External Interrupt Mask ° Used 2s R41 port input/output pin

1 Disable (mask) PMRO —R42/SO Pin

1 Used as SO output pin

Figure 7. Interrupt Servicing Sequence

Figure 8. Interrupt Servicing Flowchart

T-49-19-04 HD404019/HD4074019 Serial Interface Therefore, the STS instruction must be executed after the data in the serial mode The serial interface is used to transmit/ register has been changed completely. The receive B-bit data serially. It consists of the serial mode register will be reset to $0 by serial data register, the serial mode register, MCU reset. the octal counter, and the multiplexer as illustrated in figure 9. Pin R4o/SCK and the Serial Data Register (SRL: $006, SRU: transfer clock signal are controlled by the $007): The 8-bit read/write serial data regis- serial mode register. The contents of the ter consists of a low-order digit (SRL: $006) serial data register can be written into or _ and a high-order digit (SRU: $007). read out by software, The data in the serial data register can be shifted synchronously The data in the serial data register is output with the transfer clock signal. from the SO pin, from LSB to MSB, synchronously with the falling edge of the STS instruction initiates sorial interfaco transfer clock signal. At the same time, operations and resets the octal counter to $0. external data is input from the SI pin to the The counter starts to count at the fallingedge _serial data register, MSB first, synchronously of the transfer clock (SCX) signal_and incre- _ with the rising edge of the transfor clock. ments by one at the rising edge of SCK. When _Figure 10 shows the I/O timing chart for the the octal counter is reset to $0 after eight _transfer clock signal and the data. transfer clock signals, or when a transmit/ receive operation is discontinued when the ‘The read/write operations of the serial data octal counter is reset, the serial interrupt _ register should be performed after the com- request flag will be set. pletion of data transmit/receive. Otherwise the data can not be guaranteed. Serlal Mode Register (SMR: $005): The 4- bit write-only serial mode register controls Serial Interrupt Request Flag (IFS: $003 the R4o/SCK, prescaler divide ratio, and Bit 0): The serial interrupt request flag will transfer clock source as shown in table 7. be set when tho octal counter counts eight transfer clock signals, or when data transfer is The write signal to the serial mode register _ discontinued by resetting the octal counter. controls the operating state of the serial Refer to table 8. interface. Serial Interrupt Mask (IMS: $003 Bit 1): The write signal to the serial mode register The serial interrupt masks the interrupt stops the serial data register and octal —_ request. Refer to table 9. counter from accepting transfer clock, and it also resets the octal counter to $0 simultane- = Selection and Change of the Operation ously. Therefore, when the serial interface is © Mode: Table 10 shows the serial interface in the transfer state, the write signal causes operation modes which are determined by a the serial mode register to cease the data combination of the value in the port mode transfer and to set the serial interrupt request —_register and that in the serial mode register. flag. Initialize the serial interface by a write signal Contents of the serial mode register will be _to the serial mode register when the opera- changed on the second instruction cycle after _tion mode is changed. the serial mode register has been written to. @HITACHI Hitachi America Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 © (415) 589-8300 27

1 Used as SCK input/output pin

Figure 9. Serial Interface Block Diagram

serial interface does not operate even if the request flag is set simultaneously. In this state the falling edge of the first trans- after 8 clocks.

1 Yes 1 ° 1 Transmit mode

1 Disable (mask)

Figure 10. Serial Interface 1/O Timing Chart

counters (timer A, timer B). See figure 13.The clock signal input. prescaler is an 11-bit binary counter, timer A. nals to timer A, timer B, and the serial inter- _ interrupt request from occurring. signal is applied after timer A becomes $FF, it ized according to the value of the timer load .

3 Request Flag

Figure 13. Timer/Counter Block Diagram

HD404010/HD4074019 T-49-19-04 $002 bit 0) will be set at this overflow output, Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: SOB): Timer B consists of an 8- Timer Mode Register A (TMA: $008); __ bit writo-only timer load register, and an 8-bit Timer mode register A is a 3-bit write-only _read-only timer/event counter. Each of them register, The TMA controls the prescaler has a low-order digit (TCBL: $00A, TLRL: divide ratio of timer A clock input, as shown‘ $00A) and a high-order digit (TCBU: $00B, in table 11. The timer mode register A is TLRU: $008). (Refer to figure 2.) initialized to $0 by MCU reset. The timer/event counter can be initialized by Timer Mode Register B (TMB: $009): writing data into the timer load register. Timer mode register B (TMB) is a 4-bit write- Write the low-order digit first, and then the only register which selects the auto-reload high-order digit. The timer/event counter is function, the prescaler divide ratio, and the _initialized when the high-order digit is writ- source of the clock input signal, as shown in. ten. The timer load register is initialized to table 12, The timer mode register B is initial. $00 by the MCU reset. ized to $0 by MCU roset. The counter value of timer B can be obtained The operation mode of timer Bchangesat the by reading the timer/event counter. In this sacond instruction cycle after the timer mode —_—_case, read the high-order digit first, and then register B is written to, Timer B should be _—the low-order digit. The count value of the initialized by writing data into the timer load low-order digit is latched at the time when register after the contents of TMB are chan- _—_tha high-order digit is read. ged. Configuration and function of timer mode register B is shown in figure 14. PMR:$ 004 SMR:$ 005 ——— LL transfer clock selection R40/SCK pin mode selection R42/SO pin mode selection R4,/SI pin mode selection R32/INTo pin mode selection R3,/INT; pin mode selection TMA:$ 008 TMB:$ 009 NJ] TMA2| TMA 1]TMAO ITMB3}TMB2|TMB 1/TMBO} VAN Le ‘Timer B Input clock selection Auto-reload function selection Timer A input clock selection Figure 14, Mode Register Configuration and Function @HITACHI 302 Hitachi America Lid, © Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1619 » (616) 589-6300

the timer A interrupt request flag (table 14), _timer B Interrupt request flag (table 16). Table 11. Timer Mode Register A Table 13, Timor A Interrupt Request Table 15. ‘Timer B Interrupt Request

1 Yes: 1 Yes:

pull-up MOS (NMOS open drain); and one of circuit types. only and/or non-existing ports are read. table 18. Pins respectively. See tables 17 and 18 for the Pins With Pull-Up MOS: In the standard pins. When the MCU executes an output instruc- _to prevent the malfunction. time. The write pulse keeps the PMOS in the —_ connect to Voc on the printed circuit board. MOS (C). connect to GND on the printed circuit board.

Table 17. I/O Pin Circuit Types T-49-19-04 Table 17. 1/0 Pin Circuit Types (cont)

TT T-49-19.04 Tablo 17. 1/O Pin Circuit Types (cont) [Without Pull-Up MOS (NMOS Open Drain} Applicable lor CMOS (A or C) Pins SCK ‘SCK (Te vo we “OF ode select Mee a uv = SGK (Note 2) Common (Output mode! Pina ‘pat ‘internal SCR | intemal SCK é Vez ve [We Output ar CF Pins ‘SO ‘SO INT input | NT Input Input oD Inout oD Inout | ine HLT HLT SK (Input mode}} Notes: 1. In the stop mode, HLT signal is 0, HLT signal is 1 and I/O pins are in high impedance state. 2. If the MCU is interrupted by serial interface in the external clock input mode, the SCK terminal becomes input only. @HITACHI 06 Hitachi America Ltd, « Hitachi Plaza + 2000 Siarra Point Pray, + Brisbano, CA 94005-1819 « (416) 689-8900

Table 18. Date Input from Input/Output Common Pins T-49-19-04

1 Instruction cycle

Bringing the RESET pin high resets the MCU. the reset must satisfy trc for the oscillator to _—reset, and the status of each. Table 19. Initial Value After MCU Reset Vo Pin ‘Standard Pin (a) Without Pup 1 Enable to input .

Table 19. Initial Value After MCU Reset (cont) T-49-19-04 “Accumulator rm) MCU reset are not retained. MCU reset are not retained. 8 Regster @) software. software.

Table 20. Examples of Oscillator Circuits 7-49-19-04

Wiring between OSC1, OSC2, and elements should be as short as possible, and never cross

Low Power Dissipation Mode tion puts the MCU into standby mode, In standby mode, the oscillator circuit is active The MCU has two low power dissipation and interrupts, timer/counter and serial modes, standby mode and stop mode (tabla _— interface working. On the other hand, the 21), Figure 18 is a mode transition diagram for © CPU stops since the clock related to the these modes, instruction execution stops. Registers, RAM, and 1/O pins retain the states they were in Standby Mode: Executing an SBY instruc- _ just before the MCU went into standby mode. Table 21, Low Power Dissipation Mode Condition Standby Mode Stop Mode Instruction SBY instruction STOP instruction Oscillator circuit Active Stopped Instruction execution Stoppad Stopped Register, flag Retained Reset (note 1) Interrupt function Active Stopped RAM Retained Retained input/output pins Retained (note 2) High impedance Timer/counter,serial Active ‘Stopped interface Recovery method RESET input, interrupt request RESET input Notes: 1. The MCU recovers from stop mode by RESET input. Refer to table 19 for the contents of flags and registers. 2. As I/O circuits are active, an I/O current may flow in standby mode, depending on the state of the 1/0 pins. This is an additional current added to the standby mode current dissipation. @HITACHI 312 Hitachi America Lid, © Hitachl Plaza * 2000 Sierra Point Phy. « Brisbane, CA 94005-1819 + (415) 689-8300

Table 22. PROM Mode Signals

348 RS O:C<ié‘«“ SSCS SOO

3226 Vee Nec S468 Dio VO Noo

the program voltage (12.5 V + 0.3 V) for _ input pins for intemal PROM. GE (Chip Enable): CH input programs and —_data bus for intemal PROM. — _ Mo, Mi: (Mode): Mo and Mi set PROM mode. control signal for verify input. pins are low level and RESET pin is high level. Figure 21. PROM Mode Pin Arrangement

T-49-19-04 HD404019/HD4074019 Programmable ROM Operation with wavelength 2537A with a minimum irradiation of 15W-s/cm*. These conditions The HD4074019's on-chip PROM is pro- are satisfied by exposing the LSI to a 12,000 grammed in PROM mode (figures 22—24). W/cm’ UV source for 16-20 minutes, at a PROM mode is set by bringing TEST, Mo, and _—_ distance of 1 inch. MM; low, and RESET high as shown in figure 22, In PROM mode, the MCU does not oper- Precautions ato. It can be programmed like a standard 27266 EPROM using a standard PROM pro- 1. Addresses $0000 to $7FFF should be speci- grammer and a 64-to-28-pin socket adapter. fied if the PROM is programmable by a Table 24 lists recommended PROM pro- PROM programmer. Note that the plastic gtammers and socket adapters. package type cannot be erased and repro- grammed. (Ceramic window packages can Since an instruction of the HMCS400 series be erased and reprogrammed by ultraviolet consists of 10 bits, the HMCS400 series light.) Data in address space beyond $8000 microcomputer incorporate conversion circuit must be set to $FF. to use @ general perpose PROM programmer. By this circuit, an instruction is read or pro- 2. Be careful that the PROM programmer, grammed using 2 addresses, lower 5 bits and socket adapter and LSI match. Using the upper 5 bits as shown in figure 23. For wrong programmer of socket adapter may example, if 8 kwords of on-chip PROM aro cause an overvoltage and damage the LSI. programmed by a general purpose PROM Make sure that the LSI is firmly fixed in programmer, 16 kbytes of addresses ($0000- the socket adapter, and that the socket $3FFF) should be specified. adapter is firmly fixed in the programmer. Programming And Verification 3. The PROM should be programmed with Vep=12.5 V. Other PROMS use 21 V. If 21 V The HD4074019 can be high-speed pro- is applied to the HD4074019, the LSI may grammed without causing voltage stress or be permanently damaged. 12.6 V is Intel's affecting data reliability. 27286 Vpp. Table 23 shows how programming and veri- On-Chip EPROM Rellability after Pro- fication modas are selected. gramming Figuro 24 is a programming flowchart, and _ Generally, semiconductors are reliable oxcept figure 42 is a timing chart, For precautions on _for initial failures. Parts can be screened to PROM programming, refer to Precautions and _avoid failures, Exposure to high temperature On-Chip EPROM reliability after programing. _is a kind of screening which removes PROM memory cells with data hold failures in a Erasing short time. This is done to the ZTATs in the wafer stage, so ZTAT data hold charcteristics PROMs in ceramic window packages can be _are high. Exposing the LSI to 160°C after user erased by ultraviolet light. All erased bits programming can effectively upgrade these become Is. characteristics. Figure 25 shows the recom- meded screening flow. Erasing conditions are: ultraviolet (UV) light @HITACHI Hitachi America Ltd. # Hitachi Plaza * 2000 Slerra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 37

Table 23. PROM Mode Selection Table 24. PROM Programmers and Figure 24. PROM Programming

tures, please inform a Hitachi engineer. Figure 26. Recommended Screening Flow

Addressing Mode T-49-19-04 RAM Addressing Mode When BR is on a page boundary (256n + 256) (figure 28), executing a BR instruction trans- As shown in figure 26, the MCU has three _fers the PC contents to the next page, due to RAM addressing modes: register indirect ad- the hardware architecture. Consequently, dressing, direct addressing, and memory reg- _ the program branches to the next page when. ister addressing. the BR is used on a page boundary. The HMCS400 series cross macro assembler has Register Indirect Addressing: The W reg- _an automatic paging facility for ROM pages. ister, X register, and Y register contents (10 bits) are used as the RAM address. Zero Page Addressing Mode: By executing a CAL instruction, the program can branch to Direct Addressing: A direct addressing the zero page subroutine area, which is instruction consists of two words, with the located at $0000-$003F. When a CAL ‘word (10 bits) following the opcode used as _— instruction is executed, 6-bits of immediate the RAM address. data are placed in the low- order six bits of the program counter (PCs to PCy) and Os are Memory Register Addressing: The mem- placedin the high-order eight bits (PCs to PCs). ory register (16 digits from $020 to $02F) is accessed by executing the LAMR and XMRA = Table Data Addressing: By executing a instructions, TBR instruction, the program can branch to the address determined by the contents of ROM Addressing Mode and P Instructions the 4-bit immediate data, accumulator, and B registor. The MCU has four kinds of ROM addressing modes, as shown in figure 27, P Instruction: ROM data addressed by table data addressing can be referred to by a P Direct Addressing Mode: The program can instruction (figure 29). When bit 8 in the branch to any address in the ROM memory _referenced ROM data is 1, 8 bits of ROM data space by executing a JMPL, BRL, or CALL are written into the accumulator and B regis- instruction, These instructions replace the 14_ter. Wher bit 9 is 1, 8 bits of ROM data are program counter bits (PC13 to PC) with the written into the R1 and R2 port output regis- 14-bit immediate data. ter. When both bits 8 and 9 are 1, ROM data are written into the accumulator and B regis- Current Page Addressing Mode: The ROM ter and also to the R1 and R2 port output memory space is divided into pages, with 266 register at the same time. words in each page. Page zero begins at ad- dress $0000. By executing a BRinstruction,the ‘The P instruction has no effect on the pro- program can branch to an address in the current gram counter. page. This instruction replaces the low-order eight bits of the program counter (PC, to PC,) with the 8-bit immediate data. @HITACHI Hitachi America Ltd. + Hitachi Plaza « 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 + (415) 689-8900 22

Figure 26. RAM Addressing Modes 7

Figure 27. ROM Addressing Modea

858 NOP

Figure 28. BR Instruction Branch Destination on Pages Boundary Figure 29. P Instruction

324 Hitachi Amerlca Lt, « Hitech Plaza» 2000 Sera Point Phwy,« Brisbane, CA 94005-1819 « (416) §80-8800

RAM register instructions is an opcode map.

Table 25. Immediate Instructions Table 26. Register-to-Register Instructions

Table 27. RAM Address Instructions

ON * HD404019/HD4074019

7 FIO

T~49-19-04 Table 28, RAM Register Instructions Words/ Operation Mnemonic Operation Code Function Status Cycles SS o—e— SEO’ __C*Fumection Status: Cycles Load A from Memory LAMIXY)} 00100100y x M-A, (X~SPX, Ww YoSPY) ee Load A from Memory LAMD a 0110010000 M-A 2/2 da de d7 do dg dy dg dz d} do A ia Load B from Memory LBMIXY) 00010000y x MB, (X-SPxX, Ww Y=sPyh se Load Memory from A UMAIXY) 00100101 y x A=M, (X=SPX, TA ~ Y=SPY) es Load Memory from A LMAD d 0110010100 A=M 2/2 dg dg d7 dg ds d4 dg de dy do re deh i Lead Memory from A, LMAIY(X) 000101000x A=-M,Y¥+i-Y NZ TA) Increment Y (X-SPX) Load Memory from A, UMADY(x)_ 001101000x A-M, Y-1-¥ NB Wt Decrement Y (X+SPX) es Exchange Memory and A XMAIXY) 00100000y x MHA, (X-SPX, vA) Y=SPY) Exchange Memory and A XMAD d 0110000000 M-aA 2/2 9 de dy ds ds de dg de dt do ee Exchange Memory and B XMBIXY) O011T0000y x MHB, K+SPX, WV YesPY) ee Note: (XY) and (X) have the following meaning: 1. The instructions with (XY) have 4 mnemonics and 4 object codes for each (example of LAM [XY) is given below). The op-code X or Y is assembled as follows. Mnemonic y x Function Patalianiatin eho LAM oo LAMX ° 1 X + SPX LAMY 1 0 Yo SPY LAMXY 1 1 X=—SPX, YoSPY SV 2. The instructions with (X) have 2 mnemonics and 2 object codes for each (example of LMAIY(X) is given below). The op-code X is assembled as follows. Mnemonic x Function umaly oO LMAIYX 1 X— SPX @HITACHI Hitachi America Ltd, * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 327

Table 29. Arithmetic Instructions

Table 30. Compare Instructions 7-49-19-04

Table 33. Input/Output Instructions Table 34. Control Instructions

Table 36. Opcode Map T-49-19-04

item ‘Symbol Value Unit Note tt Sven ‘Supply Voltage Vec -0.3t0+7.0 v _Sveey Voltage eee Programming Voltage Ver -0.3to+ 14 v 13 _Programming Voltage Me ee Terminal Voltage Vr = 0.3 to Voc + 0.3 v 3 Veo — 42 to Nec + 0.3 Vv 4 Total Allowance of Input Current = lo 50 mA 6 Maximum Input Current lo 15 mA 7,8 _Moximum Input Curreng Maximum Output Current =o 4 mA 9,10 6 mA 9,11 30 mA 9,12 Total Allowance of Output Current — Z lo 150 mA 6 Operating Temperature Tose = 2010 + 75 c . _ Operating Temperature tor Storage Temperature Tag = 55 to + 126 “c _Storage Temperature te SSE Notes: 1. Permanent damage may occur if Absolute Maximum Ratings are exceeded. Normal operation should be under the conditions of Electrical Characteristics. If these conditions are exceeded, it may cause a malfunction or affect the reliability of LSI. 2. All voltages are with respect to GND. 3. Standard pins. 4. High-voltage pins. 6. Total allowance of input current is the total sum of input current which flows in from all / O pins to GND simultaneously. 6. Total allowance of output current is the total sum of the output current which flows out from Vec to all 1/O pins simultaneously. 7. Maximum input current is the maximum amount of input current from each 1/0 pin to GND. 8. Do-Da and R3-R8. 9. Maximum output current is the maximum amount of output current from Vec to each 1/0 pin. 10.D9~Ds and R3-R8. 11.RO-R2. 12.D4—-Dis. 13.Applied to HD4074019. @HITACHI 332 Hitachl America Ltd. © Hitachi Plaza « 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (415) 589-8300

(Voc = 6 V + 10%, GND = 0 V, Vaup = Veo — 40 V to Voc, Ta = —20°C to + 75°C, unless otherwise noted.) Item Symbol Pin Min Max Unit —‘ Test Condition Note ea Input High Vy RESET, SCK, 0.8 Voc Veco +0.3 Voltage INTo, INT; osc; Veo-0.5 Vcc + 0.3 vy 8! 0.7Vee Vee + 0.3 Vv Voltage INTo, INTs osc; -0.3 0.8 Vv SI -0.3 0.3Vec v — : Output High = Voy, 5CK, Veo - 1.0 v =loH=1.0 mA. i Voltage so Vec — 0.5 v —lon=0.5 mA Output Low Vo, SCK, O48 v fo.=1.6 mA Voltage so Input/Output — J. | RESET, SCK, ' uh Nig = OV to Vee. 1 Leekage INTo, INTs, Currant OSC}, SI, SO Current lee Veo TBO mA Veco = BV 2.6 Dissipation in Active Mode Current Isay Vec TBD mA Maximum logic 3.5 Dissipation in operation ‘Standby Mode Veo = SV Current Istop Veo Tap uA VplFET =Vec-03Vt0 4 Dissipation in Voc. Vin‘RESET) = OV ‘Stop Mode 00.3V ‘Stop Mode Veron Vee 2 v Retain Voltage SSS Notes: 1, Excluding pull-up MOS current and output buffer current. 2. The MCU is in the reset state. Input/output current does not flow. + MCU in reset state, operation mode + RESET, TEST: Voc + Do-Da, R3—R9: Vee + D4-Dis, RO-R2, RAo, RAs: Vise 3. The timer/counter operates with the fastest clock. Input/output current does not flow. + MCU in standby mode + Input/output in reset state + Serial interface: Stop + RESET: GND + TEST: Veo + Do-Ds, R3—R9: Veco + D4-Dis, RO-R2, RAo, RAr? Vaso @HITACHI Hitachi America Ltd. « Hitachi Ptzza © 2000 Siora Point Prwy. « Brisbane, CA 94005-1819 « (416) 689-8300 333

Excluding pull-down MOS current. 5. When fore = x MHz, estimate the current dissipation as follows: Max value @ x MHz = x/4 x (max value @ 4 MHz) Input/Output Characteristics for Standard Pin (Vcc = 5 V + 10%, GND = 0 V, Vaup = Vec — 40 V to Vcc, Ta = —20°C to + 75°C, unless otherwise noted.) Item Symbol Pin Min Max Unit Test Conditions Note Input High Vin Oo-Da, 0.7Vec Mec +0.3 VV Voltage A3-R6 Ro Input Low Vi Og-Da, -0.3 0.9Vec 8 -V Voltage ROR Rg Output Low Vor 90-Da, 0.4 v lou = 1.6 mA Voltage R3-RB Input/Output Ut Do-Ds, 1 ad Vin = OY to Voc 1 Leakage Current RQ-RB, RO}-RO3 RQ 20 aA Note: 1. Puil-up MOS current and output buffer current are excluded. Input/Output Characteristics for High Voltage Pin (Veo = & V + 10%, GND = 0 V, Vairp = Vee — 40 V to Veco, Ta = —20'C to + 78°C, unless otherwise noted.) Item Symbol Pin Min Max Unit Test Conditions Note Input High Vin De-Dis, 0.7Vcc =e $0.3 V Voltage RO, RY, 2, Rio, RAy Input Low Vu ais, = Mec 40.3 Vee CV Voltage RO, RI, R2, Rio, RAy Output High Vou 04-015. Mee = 8.0 v ~ lon = 18 mA, Voc = 8 V Voltage Vec ~ 2.0 v ~ lon = 10.mA, Voc = 8 ¥ Veo - 1.0 v = lon = 4 mA, Voc = 6V RO-R2 Vee ~ 3.0 v ~ lon = 3mA, Voc = 5 VV Vec ~ 2.0 v lon = 2mA, Veo = 5 V Vee - 1.0 v = low = 0.8mA, Voc = 5V Output Low Vor 4-15, Veo - 34 -V 150 kn to ec ~ 40 Voltage RO-R2 Input/Output Ul Da-Dis, 20 UA A= Neg ~ 40V, Vee 1 Leakage RO-R2, Current Rag, RAy Note: 1. Pull-down MOS current and output buffer current are excluded. @HITACHI au Hitachi America Ltd. « Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1619 « (415) 589-8900

AC Characteristics T-49-19-04 (Voo = 65 V + 10%, GND = 0 V, Vain = Vec — 40 V to Voc, Ts = —20°C to + 75°C, unless otherwise noted.) Tost teem Symbol Pin Min Typ = Max Unit Conditions Note TS ——OO—r—erren OO Concitiong Noto Oseilation Frequency fogs OSC, 0820.2 4.6 MHz — divide by 4 —$—$ OEE Instruction Cycle tye 0.89 1 200 ys divide by 4 : Time SSS Oscillator Stabiliza- tpg OSCy, OSCz 20° ms 1 tion Time External Clock tcp, OSC 92 ns divide by 4 2 High, Low tept Level Width External Clock Riso tcp, OSC} 20 ns 2 Timo a SSSSSSSSSSSSSSSSSSSSSSSSMhFeFeFesFFFFFFSF External Clock Fall tcp, OSC 20° ons 2 Time SSS INTo High Level tion INTo 2 teye 3 Width INT Low Level vo. INTo 2 ‘oe 3 Width INT) High Lovet tin iNT: 2 teye 3 Width INT) Low Lovel ti. INT, 2 leye 3 Width RESET High Lovel tagry RESET 2 tye 4 Width Input Capacitance Ci, pins exept R99 3000 pF f= Mz, Via = OV R89 180 pF RESET Fell Time tasrv 200 oms 4 a SSS Notes: 1. Oscillator stabilization time is the time until the oscillator stabilizes after Vec reaches its minimum allowable voltage after power-on, or after RESET goes high. At power-on or STOP mode release, RESET must be kept high for at least tac. Since tac depends on the crystal or ceramic filter's circuit constant and stray capacitance, please get tho manufacturer's advice when designing the RESET circuit. (See figure 30) 2. See figure 31. 3: See figure 32 4, See figure 33. @uHiTaAcHt titachi America Ltd, Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (415) 589-8300 335

. T-49-19-04 Serial Interface Timing Characteristics (Vco = 6 V + 10%, GND = 0 V, Vamp = Voc — 40 V to Voc, Ta = —20°C to + 75°C, unless otherwise noted.) item Symbol Pin Min Max Unit Test Condition Note Transfer Clock tseve SCK 1 teye 1.2 Cycle Time (Output) Transfer Clock tscKH SCR 0.4 tee 72 High, Low tscKe (Output) . Level Width Transfer Clock tscke SCK 40 ns 12 Rise, Fall Time sexe (Output) Transfer Clock TSeye ‘SCkK 1 teye 1 Cycle Time (input) ‘Transfer Clock ‘sexe SCK 0.4 toe 7 High, Low tscKi (input) Level Width ‘Transfer Clock tscKHo SCK 1 toe 1 END Detect (Input) High Level Width — Transfer Clock tscxe SCK 40 ns 1 Rise, Fall Time text (input) Serial Output Data toso Se) 300 ns 2 Delay Time Serial Input Data tes) st 100 ns 1 Set-up Time Serial Input Data tust sl ‘200 ns. 1 Hold Time Note: 1. See figure 34 2, See figure 35 @ HITACHI 336 Hitachi America Ltd. * Hitachi Plaza « 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 580-8300

DC Characteristics ~ (Vcc = 3.6 V to 6 V, GND = 0 V, Vatep = Vee — 40 V to Veo, Ta = —20°C to + 76°C) ttem Symbol Pin Min Max Unit Test Condition Note Or Input High Vin RESET. SCK 0.8Ve¢ Mec +03 y Voltage INTo, INT si 0.7Vee Vec $0.3 v Osc; Vee - 0.6 Vec + 0.3 Vv Input Low i RESET, SCK -0.3 0.2Vec v Voltage INTo, INT) st -0.3 0.3Vcec v Osc; -0.3 0.5 v Output High Voy SCK. Veg - 1.0 v low = 1.0 mA Voltage so Vee - 0.6 v — lon = 0.5 mA Outputlow Vo, «SCR, or Vtg 1.6mA Voltage so Input/Output 141 RESET, SCK 1 ry Vin = OV to Voc. 1 Leakage INTo, INT, ‘Current Si, SO, Osc, Current lec Veo Teo mA Veo = 5 V: 26 Dissipation in for: = 4 MHz, + 4 Active Mode @HITACHI Hitachi America Ltd. © Hitachi Plaza © 2000 Siar Point Pkwy. # Brisbane, CA 94005-1819 « (416) 589-8300 39

HD404019/HD4074019 T-49-19-04 ftom Symbol Pin Min Max Unit Test Condition Note Current ‘sav Vee TBO mA Vec = BV; 3.6 Dissipation in foac = 4 MHz, + 4 ‘Standby Mode Current stop Veco TBD uA VpITEST) = Vee - 0.3V10 4 Dissipation in Vec: ViniRESET} = OV to ‘Stop Mode O3V Stop Mode Vitop Vee. 2 v Retain Voltage Notes: 1. Excluding pull-up MOS current and output buffer current. 2. The MCU is in the reset state. input/output current does not flow. + MCU in reset state, operation mode + RESET, TEST: Vec + Do-Ds, R3-R9: Veco + Dé-Dis, RO-R2, RAo, RAr: Veiep 3. The timer/counter operates with the fastest clock. Input/output current does not flow. + MCU in standby mode + Input/output in reset state + Serial interface: Stop + RESET: GND + TEST: Veco + Do-Da, R3-A9: Veo + Ds-D15, RO-R2, RAo, RAI: Vetp 4. Excluding pull-down MOS current. 5. Whon foe = x MHz, estimate the current dissipation as follows: Max value @ x MHz = x/4 x (max value @ 4 MHz) @ HITACHI 340 Hitachi America Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 » (416) 589-8300

T-49-19-04 HD404019/HD4074019 Input/Output Characteristics for Standard Pins (Vee = 3.6 V to 6 V, GND = 0 V, Vite) =Vec — 40 V to Voc, Tes = —20°C to + 75°C) Item ‘Symbol Pia Min Typ Mex Unit Test Conditions Note Input High Vin D9-D3, 0.7Vee Veo + 0.3 V Voltage RG-R5, Ro input Low Vie Oo-D3, -0.3 . 0.3Vec v Voltage R3-R5, Ro ‘Output High Von Do-D3, Vee - 1.0 v lon = 1.0 mA 1 Voltage R3-R8 Do-D3, Vee - 0.5 v lon = 0.5 mA 1 = RB-RB Output Low Vou Do-D3. 04 v to. = 1.6 mA Voltage RS-RB Input/Output Whol Do-D3, 1 ph Vin = 0 V to Veo 2 Leakage Current R3-RO Pull-Up MOS lp Do-Dg, = TBD Tep Teo nA Mec = BV, Vin = OV 3 Current R3-R9 Notes: 1. Applied to 1/0 pins with CMOS output selected by mask option. 2. Pull-up MOS current and output buffer current are excluded. 3. Applied to 1/0 pins with pull-up MOS selected by mask option. @uitach Fitachl America Ltd, « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1619 « (415) 689-8900 oat

HD404019/HD4074019 7919-04 Input/Output Characteristics for High Voltage Pins (Veo = 3.6 V to 6 V, GND = 0 V, Vasp =Voc — 40 V to Voc, Ta = —20°C to + 75°C) item ‘Symbol Pin Min Typ Max Unit Test Conditions Note Input High Vin Dy-Dis, 0.7 Vee Veo $0.3 V Voltage RO, RI, R2, Rag, Ray Input Low Vie Ds-Dis, Veo - 40 0.3Vec V Voltage RO, R1, R2, RA, RAY Output High Von D-Dig_ Ye - 3.0 Vo = lon =18 mA Nec = 5 V + 20% Voltage Vec - 2.0 v = Ion=10 mA.Nec = 5 V + 20% Vec - 1.0 v —low= 4mA RO-R2 Vec - 3.0 v ~ lon = 9 mA, Voc = SV + 20% Vee ~ 2.0 Vo =o = 2 mA. Veo = 8 V # 20% Veo - 1.0 v — lon = 0.8 mA Output Low Vow Ds-Dis, Veco - 37 v Veep = Veo - 40 V 1 Voltage RO-R2 Ds-O15. Vec - 37 -y 150 kO to Voc — 40 V 2 RO-R2 Input/Output thu Ds-Di5, 20 uA Vin= Veo 40VtoVec 3 Leakage RO-R2, ‘Current RAo, RA: Pull-Down MOS ig D4-Dig, TBD TBD TBD yA Vem =Veo-35V, 4 Current RO-R2, Va = Vee Rao, RAt Notes: 1. Applied to I/O pins with pull-down MOS selected by mask option. 2. Applied to I/O pins without pull-down MOS (PMOS open drain) selected by mask option. 3. Pull-down MOS current and output buffer current are excluded. 4. Applied to 1/0 pins with pull-down MOS selected by mask option. @HITACHI we Hitachi America Ltd, « Hitachi Plaza » 2000 Sierra Point Pkay.« Brisbane, CA 94005-1619 » (415) $89-8900

———— rrr 49-19-04 AC Characteristics T-49 (Voc = 3.6 V to 6 V, GND = 0 V, Vas =Vec ~ 40 V to Voc, Ta = —20°C to + 75°C) Tet {tem ‘Symbol Pia Min Typ = Max = Unit Conditions Mots Oscillation fc O8C1,08Cz O24 4.8 MHz — divide by 4 Frequency Instruction Cycle toye 080 1 200 us Time Oscillator Stabiliza- te OSCy, OSC 20° ome 1 tion Time External Clock top, © OSC 92 ns divide by 4 2 High, Low tere Level Width “Extome! Clock Rise top, OSC,—=—=Ss—=“‘t*‘ CUT Time ee ea rr Time INTo High Level ton INTo 2 tore 3 Width INTo Low Level tin —iNTo 2 teye 3 Width INT: High Level tun INTs 2 toys 3 Wiath INT: Low Level tie iNT 2 tere 3 Wisth RESET High Level tpsry RESET 2 toye 4 Width Input Capacitance Gq Alpin 3000 pF 1 Mi, Va = OV RESET Fall Time test 2002—oms 4 Notes: 1. Oscillator stabllization time is the time until the oscillator stabilizes after Vec reaches its minimum allowable voltage (3.6 V) after power-on, or after RESET goes high. At power- ‘on or stop mode release, RESET must be kept high for at least trc. Since tac depends on ‘the crystal or ceramic filter's circuit constant and stray capacitance, please get the manufacturer's advice when designing the RESET circuit. (See figure 36) 2. See figure 37. 3. See figure 38. 4. See figure 39. @urracui Hitachi America Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 » (415) 589-8300 43

HD404019/HD4074019 49-19-04 Serial Interface Timing Characteristics (Voc = 3.6 V to 6 V, GND = 0 V, Vay = Vee — 40 V to Vec, Ta = —20°C to + 75°C) tem Symbot Pin Min Max Unit Test Condition Note Transfer Clock Cycle Time tsove 5cK 1 teye 1.2 (Output) Transfer Clock High, tscKH ‘SCK 04 teye 1.2 Low Level Width tscKL (Output) Transfer Clock Riso, Fall Time tgcxe Fad 40 Py 1.2 tsoxe (Output) Transfer Clock Cycle Time teoye BCK 1 teve 1 (input) Transfer Clock High, tsckH ‘Sck 0.4 teye 1 Low Level Width tsext {Input} Transfer Cock END Detect —tgcxrp «= SCK 1 teye 1 High Level Width (input) Transfer Clock Rise, Fall Time tecxr SCK 40 ns 1 tscxt input) Serial Output Data Delay Time toso, so 300 ns 1.2 Serial Input Data Set-up Time tgs; st 100 ns 1 Serial Input Data Hold Time tus, st 200 ns 1 Notes: 1. See figure 40. 2. See figure 41. @HITacui 4 Hitachi America Ltd, Hitachi Piaza » 2000 Sierra Point Pkwy, « Brisbane, CA 94005-1649 + (416) 689-8900

- _ - ee HD404019/HD4074019 Programming Electrical Characteristics for HD4074019 T-49-19-04 Write and Verify Mode DC Characteristics (Voo = 6 V + 0.26 V, Ver = 12.5 V + 0.3 V, Vas = 0 V, T. = 26°C + 65°C, unless otherwise noted) item Symbol Min Typ Max Unit Test Condition Input high voltage __Oo—O7, Ao—Ais, OF, CE Vin 2.2 Vect0.3 V Input tow voltage Oo—O7, Ao—Ara, OE, CE Vit -0.3 0.8 v Output high voltage _Oo—O7 Von 2.4 V__lon==200 yA Output low voltage Oo—O7 Vou 0.4 V___lo=1.6 mA Input leakage current Oo—O7, Ao—Ara, OE, CE |tul 2 BA Ne =8.25 V/0.5 V Veg current lec 30 mA Vee current lee 40 mA AC Characteristics (Voc = 6 V = 0.25 V, Ver = 12.5 V + 0.3 V, Ta = 25°C + 5°C, unless otherwise noted) Item Symbol Min Typ Max Unit — Test Condition ‘Address set-up time tas 2 us Fig. 42 > ,_-H lip Pat tev: OE set-up time toes 2 us 0.8-2.2V input risa Data set-up time tos 2 us time 5 20 ns Address hold time ta ° as level _ rt 10,209 Data hold time ton 2 Hs ouput: 08V, 2.00 Output disable delay time tor 130 ns Ver sat-up time tyes 2 us Program pulse width tew 0.95 1.0 1.05 ms TE pulse width when overprogramming toew 2.86 78.75 ms Vee set-up time tves 2 2S Data output delay time toe ° 500 ns @uHITACHI Hitachi Ameria Lid. « Hitachi Plaza + 2000 Sierra Point Pay. + Brisbane. CA 94005-1819 « (445) 589-8300 ar

a eeeSSSSSSSSSSSSSSSeeeeseseseeeEeeee HD404019/HD4074019 7249-19-04 Program Mectty eS, Sas Ses a Sse TT Ver etef Topp SS c ry ee = Le] Figure 42, PROM Programming/Verify Timing @HITACHI ue Hitachi America Lid, « Hitach! Plaza « 2000 Sierra Point Pkwy. # Brisbane, CA $4005-1819 + (415) 589-8300

(Voc = 5 V + 10%, Ver = Veo + 0.6 V, Ts = 25'C + 5'C, unless otherwise noted) ftom Symbol Min Typ Max __Unit__ Test Condition input Leakage Current tu 7 uA Veo = 6.8 V, Vis = GND to Veo Output Leakage Current ho i uA Veo = 5.5V, Vou = GND to Veo Program Current lee 7 100 uA Vor = Vec + 0.6V Current Dissipation Tee 30 mA Active Mode input Voltage Vie =0.3 0.8 Vv Vin 2.2 Vec+0.3 V Output Voltage Vou 0.40 Vl =1,.6mA Vou 2.4 Vow = =200 vA AC Characteristics (Veo = 5 V + 10%, Ver = Veo + 0.6 V, T, = 28°C + 5'C, unless otherwise noted) ftom Symbol Min Max Unit Test Condition —Note ‘Access Time tace 600 ons CE=0E= CE Output Delay Time tee 600 ons OE = Vi OE Output Delay Time toe 10 150 ns CE=VM Output Disable Delay Time tor ° 105 ons CEM 1 Data Output Hold Time ton ° ns CE = OF = Wu Note: 1. tor is defined when output becomes open because output level cannot be defined. @ HITACHI Hitachi America Ltd. © Hitachi Plaza # 2000 Sierra Pont Phy. « Brisbane, CA 94005-1819 « (41) 589-8900 349

Input Pulse Level 0.8 to 2.2V Output Load 1TTL Gate + 100 pF Input Rise/Fall Time S 20.ns Input/Output Timing Reference Level Output: 1V, 2 V_ Input: 0.8V,2V. “ oe “ ar tos: tor: —tace: ton Deta Out Kea Data Out Valid SS Xs LV Figure 44, PROM Read Timing @ HITACHI 360 Hitachl America Ltd. # Hitachi Plaza + 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 * (416) 589-8300

Mat neeee NurrY soc DO MM 447bcU4 UULbtbd ¢ me eSSSFSFSFSFSFSSsSSSSSSSSSSSSSSSSSSSsseFs 7-49-19.04 __1D404019/HD4074019 task oro ust a ee Please enter check marks in [tne id Lm [ mm Freer [mom Freres [oy ewan Cee a want 7 (i lo. ] [renin YT” | loa] [rowonom [| | lo] [renenen 777 | Ina] rwwoum [| | ix Poco Mic coo Zico Sooo ca eco Mi ec a —s_ On HH [mo] 2 [rwwoare Jy [] oe | | - [ns Pfmewomen 77 [| tem) foe Sic 7 Sec a — res fom | | [| =e pesos SNS © Re WisoutPaheup MOS RIGS On eae ee a putayp MOS C; CMOS (not bs used as Input) (0; Without Pull-down MOS (PMOS Open Drain) €; With Pull-down MOS: @HITACHI Hitachi America Lid. © Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 351

HD404019/HD4074019 T-49-19-04 2) PANww (0) Package [ rectage Ps > Fieae enter check mans (1, X. VI * fitpictte ene VI In eppiabie tem. Note) RA1/Vaw has to be selected a5 Vaw pin even if one high voltage pin is specified as “E". (4) Divider (DIV) (6) ROM Coda Media, [Geek vide to] , {2 EPROM: Euler Type EPROM: EPRON On-Package Mcocom” puter Type (AY Osctor (CPG opin) cro Geran rte se * loose enter check marks (Ml, X, v) in epotcabie item: @HITACHI 382 ‘Hitachi America Lid, # Hitachl Plaza * 2000 Sierra Point Pkwy. Brisbane, GA 94005-1619 © (415) 589-8300

Selected Specification

Hitachi Semiconductor HD404019 overview.

Summary

CMOS 4-BIT SINGLE-CHIP MICROCOMPUTERS

Description

CMOS 4-BIT SINGLE-CHIP MICROCOMPUTERS

Source title HD404019 Datasheet(PDF) - Hitachi Semiconductor

Related Parts

More parts from the same family.

Browse manufacturer