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HD38750 HITACHI

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HMCS43(HD38750,HD38755) The HMCS43 is the PMOS 4-bit single chip microcomputer HMCS43 which contains ROM, RAM, I/O and Timer/Event Counter on single chip, The HMCS43 is designed to perform efficient can- troller function as well as arithmetic function for both binary and BCD data, The PMOS technology of the HMCS43 provides high voltage 1/O capability for direct driving vacuum-fluorescent dis- play, @ FEATURES @ 4-bit Architecture @ 1,024 Words of Program ROM (10 bits/Word)

64 Words of Pattern ROM {10 bits/Word)

© 80 Digits of Data RAM (4 bits/Digit) © 32 VO Lines and 2 External interrupt Lines © Timer/Event Counter @ 10 usec instruction Cycle Time (DP-42) © All instructions except One Instruction; Single Word and Single Cycte HMCS43 ® BCD Arithmetic instructions © Pattern Generation Instruction — Table Look Up Capability — © Powerful Interrupt Function

3 Interrupt Sources

bz External Interrupt Lines Timer/Event Counter i Multiple interrupt Capabélity © Bit Manipulation Instructions for Both RAM and I/O uth © High Voltage I/O Capability, —49V max. ‘ ® Option of VO Configuration Selectable on Each Pin; Pull Up MOS or Open Drain © Built-in RC Oscillator; Standard Type (HO38750) © Built-in Ceramic Fitter Oscillator; Ceramic Filter Oscillator Type(HD38755) ({DP.42S) © Built-in Power-on Reset Circuit © Stand-by Mode (RAM Data Hold); 4mW max, @ PIN ARRANGEMENT ® PMOS Technology ® Single, ~ 10V Power Supply oo bs) bs oo. fay) Ds oO DB) [45] De oo & (99) Fag o> FF [38 Paz oa & [37] Rav oo | 134] Foo Ow] [33] Ras o. [34] Raa oO (5) Ray on OQ (3 Rio o.. 7 aint, Ow fh) SO}INTo Veisp [Ta] OUR Reser BR. 2 Ves (i) PRs Voo [17] $28] Ro Osc*/osc,** 23] Ros Ves (24 123) Roo * Standard Type(HO38760} ** Ceramic Filter Oscillator Type (MD38755) (Top View) @ HITACHI 54 Hitachi America Ltd. * 2210 O'Toole Ave. * San Jose, CA 95131 © (408) 435-8300

=" St i 7 1 =sssi i rage i ls T ~ oe vs SLR

= ABSOLUTE MAXIMUM RATINGS: item [Symbot_[ Vawe | unt] Remarks Pin Votage (1) [=v [osteo tie |v [except tor pins specified by —Vra Pin Vottage (2) Toswsso Bpping (nah break-down vaiage fins Maximum Total Output Current [=a [45 | ma _|INote al Operating Temperature =2010 +75 Storage Temperature =55 10 +125 INOTE 1] Permanent LS! damage may occur if maximum ratings are exceeded. Normal operation should be under the conditions of “ELECTRICAL CHARACTERISTICS-1.-2 If those Conditions ere exceeded, could affect relobilty of LSI INOTE 2] Allwoltages ere with respect 10 Vee, INOTE 3] High bresk-down voltage pins cer be specified by user among the following pins. They ere specified at ROM ordering using the “Mask Option List’. {Unspecified pine re low break-down voltage pins) Dy t0 Dy Rog tO Roy Ryo 10 Ry, Reo 10 Ry Rap t0 Ray INTs INT,, RESET, Vises. Other pita estmot 8s spcined ge high brosk-down vokage pin INOTE 4) Maximum Total Output Current is the total sum of output currents which can flow out simultaneously from output pins and /O common pins. @ ELECTRICAL CHARACTERISTICS-1 (~Vpp=— Vag 10V+ 10%, ~ Vaisp=49V max., Ta=— 20 to +75°C) item Test Conditions Note —Vpo= — Vaa=9V Input “Low” Voltage (1) Var Lo. [so | v 3 | =Voo==Vee= tiv | 47 | Input “Low” Voltage (2) Vez 20 2 [40 | v 4 Woo = Van= HV [ar] Input “High” Voltage (1) [Me [oT Pees Tv fs Input “High” Voltage (2) [Vie [Oo vs Output “Low” Voltage (7) = Vang= 49 fas [- [-[v ts ‘Output “Low” Voltage (2 56k to —49V [as | - [= |v y's Output “High” Voltage (1) [Vou [=tow=ama = = te Tv Output “High” Voltage (2) [Vows | =toy=toma = = Pe Tv Te Interrupt Input Hold Time a | Interrupt input Fall Time [tr [= 0s Interrupt input Rise Time [tw f= 80 Ts Input Leakage Current | =n | =Va=0 to 49V P= | = [so [ua [9 Pull up MOS Current [te | Weap=asv 00 T= [400 Tua | 2 (to be continued! @ HITACHI 56 Hitachi America Ltd. © 2210 O'Toole Ave. * San Jose, CA 95131 * (408) 435-8300

a HMcs43 Item Symbot Test Conditior [—_—vawe___ Note acer: [min [ve [max | ° External Clock Operation [Standard Type] External Clock Frequency fep “"" 1" 260 meen Ce — External Clock Duty [ow [od as so fs External Clock Rise Time a External Clock Fall Time [te | | OT = fo? fs | External Clock “Low” Level —Veet fo [40 | 7 v External Clock “High” Level [over [CUT CT = Po TV Instruction Gycle Time [Tn [Tmo tT = 20 Ts Internal Clock Operation (R, C, Oscillation) [Standard Type] __ R= 30k +2%, Clock Oscillation Frequency fosc Ci= 100pF = 5% 320 - 480 | kHz Instruction Cycle Time [Tou [Tre aose 8 [= P28 | ws | Internal Clock Operation (Ceramic Filter Oscillation) a __ [Ceramic Filter Oscillator Type) — oe Clock Oscillation Frequency fose Ceramic Filter 392 = 408 | kHz Instruction Cycle Time [Ton [Tr fosc 8 T= 02 Ts Specifications of low break-down voltage pins specified by user are as follows, (-Vpp=— Vas= 10V+ 10% —Vgisp=17V max. Ta=—20 to + 75°C) ne [ seme | torcontone | FP ue | Neve i" : [rin [mex | . —Vop= — Vas=9V [ 40 | Input “Low’’ Voltage (1) Var se 38 wv v 3 | =Voo=—Vee=ttv 47 | [ =Voo=—Vee=8V_— | 40 Input “Low” Voltage (2) —Vez 0088 7 v 4 =Voo=—Ven=11V [a7 | Output "Low" Voltage (1) [Vor | —Vos=tov Tes | = Tv Ts Output “Low” Voltage (2) [ =Vor | seentvo—vov Tes T - Tv Input Leakage Current Dou [-veowm TT 8 Ta | 8 Pull up MOS Current [ [—Vvae=tov | 80 | 960 [ua | 2 [NOTE 1) All voltages are with respect to Vs INOTE 2] Pull up MOS current (the current which flows in Vga, through pull up MOS when the pin is connected to Vc) varies with the value of Vix ftis shown a Figure 1 to - 200 | fi | |" ° a a a Figure 1 Ip vs. Vdisp @HITACHI 57 Hitachi America Ltd. * 2210 O'Toole Ave. * San Jose, CA 95131 * (408) 435-8300

HMCS43 —o ——— KKK {NOTE 3) This is applied 10 Dy to Dy, Ryo t0 Ros. Ryo to Ry [NOTE 4] This is applied to INT,, INT, and RESET. The system isin the reset state when RESET is at “1” (High) level, and in the operating state at “0” (Low) level. When Built-in Reset is used, RESET should be connected 10 Vg, NOTE 51 This is applied to With Pull up MOS pins NOTE 6} This is applied to No Pull up MOS pins. [NOTE 7] This is applied to D, to Dy, Ryo to Ry. Ryo tO Rey, Ryo to Ryy INOTE €] This is applied to D, t0 Dye [NOTE 9] Pull up MOS current is excluded. = ELECTRICAL CHARACTERISTICS-2 (Ta=~20 to + 75°C) © Reset " Symvo! ent ‘em ‘est Conditions ni | min Tmax | External Reset =Vpp=~ Vee=9 to 11V [Standard Type) (External Clock Operation, R, C, Oscillation) RESET Pulse Width (1) tasrs —— ms External Reset =Voo= — Ves=9 to 11V {Ceramic Filter Oscillator Type) (Ceramic Filter Oscillation) External Reset RESET Rise Time [twsr | AET=Vec 20s RESET Fall Time [tinsr [ HETSVec T= 20s [NOTE] All volteges are with respect to Vs © Data Hold f | sym | Test Condi Unit Item ‘est Conditions ni [min [mex | Data Hold Voltage RESET=—0.2V [| 20 | - | v Data Hold Current | =ton | RESET=~0.2V, —Von=2 [ - | 2 | m (Standard Type] (External Clock Operation, operation Re time ‘ R, C, Oscillation) ration Recover ms eration Recovery "e [Ceramic Filter Oscillator Typel (Ceramic Filter Oscillation) INOTE] Alt voltages are with respect to Ves, 58 @ HITACHI Hitachi America Ltd. * 2210 O'Toole Ave. ¢ San Jose, CA 95131 © (408) 435-8300

= SIGNAL DESCRIPTION © R,toR,, ‘The input and output signals for the HMCS43, shown in PIN These 4 lines are one 4-bit Input/Output Common Channel. ARRANGEMENT, are described in the following paragraphs. 4-bit register (Data I/O Register) is attached to this channel. This channel is directly addressed by the operand of an instruction. © Vop. Vee and Ves, 1/O configuration of each pin can be specified among Open Power is supplied to the HMCS43 using these pins. Vpp is Drain and With Pull up MOS using a mask option. power of logic parts except RAM, Vpg is power of RAM and Vss Refer to INPUT/OUTPUT for additional information. is ground connection. ® Rao to Ros, Ryo to R55 © Vaiep These 8 lines are two 4-bit output channels, 4-bit registers are ‘Vaisp is used as power supply of Pull up MOS and has no rela~ attached to these channels. Each channel is directly addressed by tion to internal logic operation. the operand of an instruction. 1/O configuration of each pin can be specified among Open © RESET Drain and With Pull up MOS using a mask option. This pin resets the HMCS43 independently of the automatic Refer to INPUT/OUTPUT for additional information. resetting capability (ACL; Built-in Reset Circuit) already in the HMCS43. The HMCS43 can be reset by pulling RESET high. © D,toD, Refer to RESET FUNCTION for additional information. ‘These lines are four 1-bit Discrete Input/Output Common Pins. The 1-bit latches are attached to these pins. Each pin is ad- * OSC (OSC, and OSC.) dressed by the Y register. These pins are also addressed directly ‘These pins provide control input for the built-in oscillator cir- by the operand of input/output instruction. cuit. Resistor and capacitor, ceramic filter circuit, or an external Refer to INPUT/OUTPUT for additional information. oscillator can be connected to these pins to provide a system clock with various degrees of stability/cost tradeoffs. Lead length * D,toD,, and stray capacitance on these two pins should be minimized. ‘These lines are twelve 1-bit Discrete Output Pins. The 1-bit Refer to OSCILLATOR for recommendations about these latches are attached to these pins. Each pin is addressed by the Y pins. register Refer to INPUT/OUTPUT for additional information. TEST This pin is not for user application and must be connected to = ROM Vss- © ROM Address Space ROM is used as a memory for the instructions and the pat- © INT, and INT, terns (constants). The instruction used in the HMCS43 consists These pins generate interrupt request to the HMCS43. of 10 bits. These 10 bits are called “‘a word’, which is a unit for Refer to INTERRUPTS for additional information. writing into ROM. The ROM address is composed of the program area (page 0 © Ryo to Rog to 15) and the pattern area (page 30). (64 words/page). These 4 lines are one 4-bit input channel. The ROM capacity is 1,088 words (1 word = 10 bits) in all. Refer to INPUT/OUTPUT for additional information. Only the program area can contain both the instructions and the patterns (constants). The ROM address space is shown in Figure 2. J 84 worse} 1F0F 07 <—30 36 3F-—Hoxadecimad [ne 0 rimercounter inwrupt Address (Page © Adéress 3F) [rr input rtrupt Adress (Page 1 Aderess 3° —— | [Prev 14 eR Sa words Reset Address (Page 15 Address 3F) 1F OF 07 «——~30 3E 3F (Hexadecima’) Page 90 Figure 2 ROM Address Space @HITACHI Hitachi America Ltd. © 2210 O'Toole Ave. * San Jose, CA 95131 * (408) 435-8300 59

tor and the Carry F/F respectively. The Carry F/F can be set, re- put Channels (R2, R3). can be right or left rotated. The accumulator is the main register and R3 channels. flow generated by ALU operation when the calculation of two or output instruction. The result of ALU operation (4 bits) is loaded into this regis- _the pattern instruction. © SPX Register (SPX) shown in Figure 14. ‘The SPX register is exchangeable with the X register. with the X register. It is composed of 3-bit (0 to 7) register. twelve 1-bit Discrete Output Pins. ter. The Y register is exchangeable with the SPY register. The Y _struction. The SPY register is exchangeable with the Y register. The input/output instruction and can be set or reset. ‘SPY register is used to stack the contents of the Y register and The block diagram is shown in Figure 15 and the 1/O timing. expand the addressing system of RAM and 1-bit Discrete 1/0 in is in Figure 16. combination with the Y register. The HMCS43 has one 4-bit Data I/O Common Channel (R1) ‘shown in Figure 17.

2 E [>< O Paz

The register is cleared (0) by the reset function. Figure 13. 4-bit Data 1/0 Block Diagram

(a) Configuration of Input Pin Ves.

0 Dra Véisp

4 Voo

Figure 17. 1/0 Conhguration as shown in Figure 18. scaler operates and cannot be stopped. Mode it counts INT, input pulse (counts leading edge), and in- overflow output pulse is input to the counter (Timer Mode). The prescaler is a 6-bit frequency divider. It generates 100/64 can be used as timer/counter interrupt mask. LTI instructions. The frequency division is 0 when the prescaler Figure 19. Interrupt Request of Timer/Counter ‘TF. Set has priority over the reset.

Table 3. Timer Range The INT, and INT, pins have interrupt request functions. terrupt request. At the same time, the IFO F/F or IF1 F/F is set. of the present program counter is pushed onto the stack STI and Enable State. ble F/F (I/E) is set and the address jumps to a fixed destination _INT, can be used as additional input pins with latches. The input interrupt has priority over the timer/counter inter- The interrupt circuit block diagram is shown in Figure 20.

IMOS43 A$$ @ INSTRUCTION LIST The instructions of the HMCS43 are listed according to their functions, as shown in Table 4. Table 4 Instruction List Group [Mnemonic [Function Status LAB BoA LBA An~B Register» Register Lay YA Instruction LASPX SPX—A LASPY sPY—-A XAMR m A= MR (m) A A=x LA Any uxt i-x wii i-y RAM Address Register v Yriey Ne Instruction ov yosy NB AYY Y+A>Y c sYY Y-A>Y NB XSPX X= SPX xSPY Y= spy XSPXY X= SPX, Y= SPY LAM (xy) M— A (XY = SPXY) LBM (xy) M— B IXY = SPXY) RAM - Register XMA (XY) M=— A (XY = SPXY) Instruction XMB (XY) M-—B (XY = SPXY) LMAIY (X) AM, Y+1— ¥ (X= SPX) NZ LMADY (x) AM, Y~-1— ¥ (X= SPX) NB Immediate Transfer umay i iT M yet oy Ne Lali ina Instruction ton ine Ali Ati“ A c

3 B+1-B NZ

AMC Mt+A+C (F/F) A c ‘SMC M-A-CIF/F) =A NB AM MtA—A Cc DAA Decimal Adjustment (Addition) ‘Arithmetic Instruction DAS Decimal Adjustment (Subtraction) NEGA A+1 =A COMB B-6 SEC “ym C (FFD REC “O" — CUFF) Te Test C (F/F) C (F/F) ROTL Rotation Left ROTR Rotation Right OR AUB-A {to be continued) @ HITACHI 70 Hitachi America Ltd. * 2210 O'Toole Ave. * San Jose, CA 95131 © (408) 435-8300

ee DhqhlwwWWW— HMESAB_ Group [Wnemonc [Function Status (MNEI i. MFi NZ YNEL i Yi NZ ANEM AM NZ Compare Instruction BNEM BHM NZ ALELi ASi NB ‘ALEM ASM NB BLEM B=sM NB SEM n “yt — M in) RAM Bit Manipulation REM n “0% = M In) instruction Mt) eRe Branch on Status 7 7 CALa ‘Subroutine Jump on Status 1 1 ROM Address Instruction LeU Load Program Counter Upper on Status 1 TBR p Table Branch RIN Return from Subroutine ‘SEIE yt VE ‘SEIFO “1 = FO ‘SEIFT ay IFT SET oy TF SECF “yt — CF REIE “O" = VE REIFO. “0% — IFO ReIF1 "0" = IF RETF “0” = TF Interupt Instruction Recr “0” CF To Test INT, INT mH Test INT, INT,

110 Test FO Fo

um i= Timer/Counter ua A — Timer/Counter Lar Timer/Counter = A RTNI Return Interrupt SED “1 —= Dy) RED “o" = Dy) TO Test OY) oly) SEDD n “1 = Din) Input/Output REDD n "0" = Din) Instruction LAR p Rip) — A LBR pp Rip) — B LRA Dp A— Rip) LRB p B— Rip) Pp Pattern Generation [wor | ne onenion Cd @HITACHI Pi Hitachi America Ltd. * 2210 O'Toole Ave. ¢ San Jose, CA 95131 * (408) 435-8300

M43 $$$ $a INOTE] 1. (XY) afters mnemonic code has four masnings 2s follows ‘Mnemonic only Instruction execution only Mnemonic with X Afr instruction execution, X SPX Mnemonic with ¥ After mstruction execution, ¥ — SPY Mnemonic with XY After instruction execution, X — SPX, ¥ — SPY [Example] = LAM MmA asx MAX — $x tay Mo AY— SPY Lay M—AX= SPX, ¥— SPY 2. Status column shows the factor which brings the Status F/F 1" under judgement istuction of inattuction accompanying the judgement NZ ALU Not Zero c AALU Overtow in Addition, hati, Cary Ne {ALU Ovarflow in Subtraction, that, No Borrow Except above Contents of the status column affects the Status F/F directly 3. The Carry FF ICIF/A ie not always atfected by executing the instruction which affects the Status FF Instructions which affect the Corey F/F are eight as follows. ame Sec smc ec DAA ROTL Das RoTR 4. Atinstrutions except the pattern instruction (Pare executed in 1 cycle. The pattern instruction (Ps executed in 2 yctes. 2 @HITACHI Hitachi America Ltd. © 2210 O'Toole Ave. * San Jose, CA 95131 * (408) 435-8300

Selected Specification

Hitachi Semiconductor HD38750 overview.

Summary

PMOS 4-bit single chip

Description

PMOS 4-bit single chip

Source title HD38750 Datasheet(PDF) - Hitachi Semiconductor

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