HD3-6409-9Z

HD-6409_V02 RENESAS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

Features

• Converter or Repeater Mode
• Independent Manchester encoder and decoder operation
• Static to 1Mbps data rate ensured
• Low bit error rate
• Digital PLL clock recovery
• On-chip oscillator
• Low operating power: 50mW Typical at +5V
• Pb-Free (RoHS Compliant) Related Literature For a full list of related documents, visit our website:
• HD-6409 device page

Figure 1. Block Diagram

HD-6409 1. Overview FN2951 Rev.5.00 Page 2 of 18 Jul.8.19 1. Overview

1.1 Logic Symbol

1.2 Ordering Information

1.3 Pin Configuration

(1Mbps) (Notes 2, 3)P a r t M a r k i n g Temp. Range (°C) Tape and Reel (Units) (Note 1) Package (RoHS Compliant) Pkg. Dwg. # HD3-6409-9Z (No longer available or supported) HD3-6409-9Z -40 to +85 - 20 Ld PDIP E20.3 HD9P6409-9Z HD9P6409-9Z -40 to +85 - 20 Ld SOIC M20.3 HD9P6409-9Z96 HD9P6409-9Z -40 to +85 1k 20 Ld SOIC M20.3 Notes: 1. See TB347 for details on reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. For Moisture Sensitivity Level (MSL), see the HD-6409 device page. For more information about MSL, see TB363.

20 Ld PDIP, SOIC

HD-6409 1. Overview FN2951 Rev.5.00 Page 3 of 18 Jul.8.19

1.4 Pin Descriptions

Number Type Symbol Name Description 1 I BZl Bipolar Zero Input Used in conjunction with Pin 2, Bipolar One Input (BOl), to input Manchester II encoded data to the decoder, BZI and BOl are logical complements. When using Pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high. 2 I BOl Bipolar One Input Used in c onjunction with Pin 1, Bipolar Zero Input (BZI), to input Manchester II encoded data to the decoder, BOI and BZI are logical complements. When using Pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low. 3 I UDI Unipolar Data Input An alternate to bipolar input (BZl, BOl ), Unipolar Data Input (UDl) inputs Manchester II encoded data to the decoder. When using Pin 1 (BZl) and Pin 2 (BOl) for data input, UDI must be held low.

4 I/O SD/CDS Serial

In the converter mode, SD/CDS is an input that receives serial NRZ data. NRZ data is accepted synchronously on the falling edge of encoder clock output (ECLK). In the repeater mode, SD/CDS is an output indicating the status of last valid sync pattern received. A high indicates a command sync and a low indicates a data sync pattern. 5 O SDO Serial Data Out The decoded serial NRZ data is transmitted out synchronously with the decoder clock (DCLK). SDO is forced low when RST is low. 6O S R S T Serial Reset In the converter mode, SRST follows RST. In the repeater mode, when RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero, and a valid synchronization sequence is received. 7O N V M Nonvalid Manchester A low on NVM indicates that the decoder has received invalid Manchester data and present data on Serial Data Out (SDO) is invalid. A high indicates that the sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST, and remains low after RST goes high until valid sync pulse followed by two valid Manchester bits is received. 8 O DCLK Decoder Clock The decoder clo ck is a 1X clock recovered from BZl and BOl, or UDI to synchronously output received NRZ data (SDO). 9I R S T Reset In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low. A high on RST enables SDO and DCLK, and forces SRST high. NVM remains low after RST goes high until a valid sync pulse followed by two Manchester bits is received, after which it goes high. In the repeater mode, RST has the same effect on SDO, DCLK, and NVM as in the converter mode. When RST goes low, SRST goes low and remains low after RST goes high. SRST goes high only when RST is high, the reset bit is zero and a valid synchronization sequence is received.

10 I GND Ground Ground

11 O C O Clock Output Buffered output of clock input I X. Can be used as a clock signal for other peripherals. 12 I I X Clock Input I X is the input for an external clock or, if the internal oscillator is used, IX and OX are used for the connection of the crystal. 13 O O X Clock Drive If the inter nal oscillator is used, OX and IX are used for the connection of the crystal. 14 I MS Mode Select MS must be held low for operation in the conver ter mode, and high for operation in the repeater mode. 15 I CTS Clear to Send In the converter mode, a high disables the encoder , forcing outputs BOO, BZO high and ECLK low. A high to low transition of CTS initiates transmission of a Command sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode, the function of CTS is identical to that of the converter mode with the exception that a transition of CTS does not initiate a synchronization sequence. 16 O ECLK Encoder Clock In the converter mode, ECLK is a 1X clock o utput that receives serial NRZ data to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from BZl and BOl data by the digital phase locked loop. 17 I SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock frequency while a low sets the data rate at 1/16 times the clock frequency.

HD-6409 1. Overview FN2951 Rev.5.00 Page 4 of 18 Jul.8.19 18 O BZO Bipolar Zero Output BZO and its logical complement BOO are the Manchester data outputs of the encoder. The inactive state for these outputs is in the high state.19 O BOO Bipolar One Out 20 I V CC VCC VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (Pin 20) to GND (Pin 10) is recommended. Note: (I) Input(O) Output Pin Number Type Symbol Name Description

HD-6409 2. Specifications FN2951 Rev.5.00 Page 5 of 18 Jul.8.19 2. Specifications

2.1 Absolute Maximum Ratings

2.2 Thermal Information

2.3 Operating Conditions

2.4 Die Characteristics

Parameter Minimum Maximum Unit Supply Voltage +7.0 V Input, Output or I/O Voltage GND - 0.5 VCC + 0.5 V ESD Classification Class 1 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. Thermal Resistance (Typical, Note 4 )θ JA (°C/W) θ JC (°C/W) Notes: 4. θ JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379. Parameter Minimum Maximum Unit Storage Temperature Range -65 +150 °C Maximum Junction Temperature Ceramic Package +175 °C Plastic Package +150 °C Pb-Free Reflow Profile (Note 5)s e e TB493 Note: 5. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Parameter Minimum Maximum Unit Operating Temperature Range -40 +85 °C Operating Voltage Range +4.5 +5.5 V Input Rise and Fall Times 50 ns Sync. Transition Span (t 2) 1.5 Typical, ( Notes 6, 7)D B P Short Data Transition Span (t4) 0.5 Typical, ( Notes 6, 7)D B P Long Data Transition Span (t5) 1.0 Typical, ( Notes 6, 7)D B P Zero Crossing Tolerance (tCD5) ( Note 8) Notes: 6. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. 7. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by ±2 IX clock cycles (16X mode) or ±6 IX clock cycles (32X mode). 8. The maximum zero crossing tolerance is ±2 IX clock cycles (16X mode) or ±6 IX clock cycles (32 mode) from the nominal. Parameter Value Gate Counts 250

HD-6409 2. Specifications FN2951 Rev.5.00 Page 6 of 18 Jul.8.19

2.5 DC Electrical Specifications

2.6 Capacitance

2.7 AC Electrical Specifications

VCC = 5.0V ± 10%, TA = -40°C to +85°C Parameter Symbol Test Conditions ( Note 9) Min (Note 11) Max (Note 11)U n i t Logical “1” Input Voltage V IH VCC = 4.5V 70% V CC -V Logical “0” Input Voltage V IL VCC = 4.5V - 20% V CC V Logic “1” Input Voltage (Reset)V IHR VCC = 5.5V V CC -0.5 - V Logic “0” Input Voltage (Reset)V ILR VCC = 4.5V - GND +0.5 V Logical “1” Input Voltage (Clock) V IHC VCC = 5.5V V CC -0.5 - V Logical “0” Input Voltage (Clock) V ILC VCC = 4.5V - GND +0.5 V Input Leakage Current (Except IX)I I VIN = VCC or GND, VCC = 5.5V -1.0 +1.0 µA Input Leakage Current (IX)I I VIN = VCC or GND, VCC = 5.5V -20 +20 µA I/O Leakage Current I O VOUT = VCC or GND, VCC = 5.5V -10 +10 µA Output HIGH Voltage (All Except OX)V OH IOH = -2.0mA, VCC = 4.5V (Note 10)V CC -0.4 - V Output LOW Voltage (All Except OX)V OL IOL = +2.0mA, VCC = 4.5V (Note 10)- 0 . 4 V Standby Power Supply Current I CCSB VIN = VCC or GND, VCC = 5.5V, Outputs Open - 100 µA Operating Power Supply Current I CCOP f = 16.0MHz, VIN = VCC or GND VCC = 5.5V, CL = 50pF - 18.0 mA Functional Test F T (Note 9)- - - Notes: 9. Tested as follows: f = 16MHz, VIH = 70% VCC, VIL = 20% VCC, VOH ≥ VCC/2, and VOL≤ VCC/2, VCC = 4.5V and 5.5V. 10. Interchanging of force and sense conditions is permitted. 11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TA = +25°C, Frequency = 1MHz. Parameter Symbol Test Conditions Typ Unit Input Capacitance C IN All measurements are referenced to device GND 10 pF Output Capacitance C OUT 12 pF VCC = 5.0V ±10%, TA = -40°C to +85°C Parameter Symbol Test Conditions (Note 12) Min (Note 11) Max (Note 11)U n i t Clock Frequency f C -1 6 M H z Clock Period t C 1/fC -s e c Bipolar Pulse Width t 1 tC+10 - ns One-Zero Overlap t 3 -t C-10 ns Clock High Time t CH f = 16.0MHz 20 - ns Clock Low Time t CL f = 16.0MHz 20 - ns Serial Data Setup Time t CE1 120 - ns Serial Data Hold Time t CE2 0- n s DCLK to SDO, NVM tCD2 -4 0 n s ECLK to BZO tR2 -4 0 n s

HD-6409 2. Specifications FN2951 Rev.5.00 Page 7 of 18 Jul.8.19 Output Rise Time (All except Clock) t r From 1.0V to 3.5V, CL = 50pF, Note 13 -5 0 n s Output Fall Time (All except Clock) t f From 3.5V to 1.0V, CL = 50pF, Note 13 -5 0 n s Clock Output Rise Time t r From 1.0V to 3.5V, CL = 20pF, Note 13 -1 1 n s Clock Output Fall Time t f From 3.5V to 1.0V, CL = 20pF, Note 13 -1 1 n s ECLK to BZO, BOO tCE3 Notes 13, 14 0.5 1.0 DBP CTS Low to BZO, BOO Enabled t CE4 Notes 13, 14 0.5 1.5 DBP CTS Low to ECLK Enabled t CE5 Notes 13, 14 10.5 11.5 DBP CTS High to ECLK Disabled t CE6 Notes 13, 14 -1 . 0 D B P CTS High to BZO, BOO Disabled t CE7 Notes 13, 14 1.5 2.5 DBP UDI to SDO, NVM tCD1 Notes 13, 14 2.5 3.0 DBP RST Low to CDLK, SDO, NVM Low t CD3 Notes 13, 14 0.5 1.5 DBP RST High to DCLK, Enabled t CD4 Notes 13, 14 0.5 1.5 DBP UDI to BZO, BOO tR1 Notes 13, 14 0.5 1.0 DBP UDI to SDO, NVM tR3 Notes 13, 14 2.5 3.0 DBP Notes: Input rise and fall times driven at 1ns/V, Output load = 50pF. 13. Limits established by characterization and are not production tested. 14. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles. VCC = 5.0V ±10%, TA = -40°C to +85°C (Continued) Parameter Symbol Test Conditions (Note 12) Min (Note 11) Max (Note 11)U n i t

2.8 Timing Waveforms

Figure 3. Clock Timing Figure 4. Output Waveform

2.9 Test Load Circuit

Figure 11. Repeater Timing Figure 12. Test Load Circuit

3.1 Encoder Operation

the encoder to drive the external circuits which supply the NRZ data to the MED at pin SD/CDS. data is clocked into the encoder at SD/CDS on the high to low transition of ECLK during the command sync pulse. continuously without parity check or word framing. The length of the data block encoded is defined by CTS. Manchester data out is inverted.

3.2 Decoder Operation

clock synchronized with incoming data for its clocking. Bipolar Zero inputs accept data from differential inputs such as a comparator sensed transformer coupled bus. recognize either a command or data sync pattern. A data sync is a logically inverted command sync. There is a 3-bit delay between UDI, BOl, or BZI input and the decoded NRZ data transmitted out of SDO. remains low after a low-to-high transition on RST until a valid sync pattern is received. Figure 13. Encoder Operation

decoder does not re-establish proper data decoding until another sync pattern is recognized.

3.3 Repeater Operation

Speed Select high. For long data links the 32X mode should be used as this permits a wider timing jitter margin. 2X ECLK is transmitted out of the repeater synchronously with BOO and BZO. received, with high indicating a command sync and low indicating a data sync. synchronously with the 1X DCLK. Figure 14. Decoder Operation Figure 15. Repeater Operation

3.4 Manchester Code

data cell. Manchester has bandwidth, error detection, and synchronization advantages over NRZ code. of 5 to 10 octaves. It is much easier to design a narrow band than a wideband amp. synchronization must be re-established. This places relatively stringent requirements on the incoming data. Manchester is a self clocking code. The clock in serial data communication defines the position of each data cell. Figure 16. Manchester Code

3.5 Crystal Oscillator and LC Oscillator Modes

3.6 Using the 6409 as a M anchester Encoded UART

Figure 17. Crystal Oscillator Mode Figure 18. LC Oscillator Mode Figure 19. Manchester Encoder UART

HD-6409 4. Revision History FN2951 Rev.5.00 Page 15 of 18 Jul.8.19 4. Revision History Rev. Date Description 5.00 Jul.8.19 Applied new formatting throughout. Updated links throughout. Added Related Literature. Updated Ordering Information table by adding tape and reel information, removing HD3-6409-9, and updating Notes 1 and 3. Removed About Intersil section. Updated Disclaimer 4.00 Oct.1.15 Added Rev History beginning with Rev 4. Added About Intersil Verbiage. Updated Ordering Information on page 1 Updated POD M20.3 to most current version. Revision changes are as follows: Top View: Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion) Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion) Side View: Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion) Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion) Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994" Updated to new POD format by moving dimensions from table onto drawing and adding land pattern

HD-6409 5. Package Outline Drawings FN2951 Rev.5.00 Page 16 of 18 Jul.8.19 5. Package Outline Drawings M20.3

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)

Rev 3, 2/11 7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm DETAIL "X"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW 13.00 0.75 0.25 x 45° 0.32 0.23 MAX 1.27 0.40 10.65 10.007.60 7.40 12 3 INDEX AREA 2.65 2.35 0.30 MAXBSC 1.27 0.35 0.49 0.25 (0.10) MC S BMA 0.10 (0.004) 0.25 (0.10) MB M 1 2

1.27 BSC

(9.40mm) SEATING PLANE (0.60) (2.00) NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension does not include mold flash, protrusions or gate 3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. 8. Controlling dimension: MILLIMETER. 9. Dimensions in ( ) for reference only. burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. (0.024 inch) 10. JEDEC reference drawing number: MS-013-AC. 12.60 For the most recent package outline drawing, see M20.3.

HD-6409 5. Package Outline Drawings FN2951 Rev.5.00 Page 17 of 18 Jul.8.19 Notes: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendicular to datum . 7. e B and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E20.3 (JEDEC MS-001-AD ISSUE D)

20 Lead Dual-In-Line Plastic Package (PDIP)

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.55 1.77 8 C 0.008 0.014 0.204 0.355 - D 0.980 1.060 24.89 26.9 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N2 0 2 0 9 Rev. 0 12/93 For the most recent package outline drawing, see E20.3.

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