HD26LS32 RENESAS

Document overview

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Technical content

Features

  • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD26LS32P DILP-16 pin (JEITA) DP-16E, -16FV P — HD26LS32FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) Note: Please consults the sales office for the above package availability. Logic Diagram Enable G Enable G

Rev.2.00, Jul.16.2004, page 2 of 14 Pin Arrangement (Top view) GND Enable G

16 VCC

Differential Input Enable Output A – B G GGGG Y VID ≥ V TH HXH XLH VTL < VID < VTH HX? XL? VID ≤ V TL HXL XLL XL H Z H : High level L : Low level X : Immaterial ? : Irrelevant Z : High impedance

Rev.2.00, Jul.16.2004, page 3 of 14 Absolute Maximum Ratings Item Symbol Ratings Unit Supply Voltage V CC*1 7.0 V In Phase Input Voltage V IC ±25 V Differential Input Voltage V ID*2 ±25 V Enable Input Voltage V IN 7V Output Sink Current Iout 50 mA Continuous Total Dissipation P T 1W Operating Temperature Range Topr 0 to +70 °C Storage Temperature Range Tstg –65 to 150 °C Notes: 1. All voltage values except for differential input voltage are with respect to network ground terminal. 2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting onput. 3. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply Voltage V CC 4.75 5.00 5.25 V In Phase Input Voltage V IC ——± 7 . 0 V Output Current I OH — — –440 µA IOL ——8 m A Operating Temperature Topr 0 — 70 °C

Rev.2.00, Jul.16.2004, page 4 of 14 Electrical Characteristics (Ta = 0 to +70°C) Item Symbol Min Typ *1 Max Unit Conditions Differential Input High Threshold Voltage VTH ——0 . 2 V V IC = –7 to +7 V V OH = 2.7 V, IOH = –440 µA Differential Input Low V TL — — –0.2 V OL = 0.4 V, IOL = 4 mA Threshold Voltage — — –0.2 V OL = 0.45 V, IOL = 8 mA Input Hysteresis*2 VTH – VTL —3 0—m V Enable Input Voltage V IH 2 . 0 ——V VIL ——0 . 8 Enable Input Clamp Voltage VIK ——1 . 5 V CC = 4.75 V, IIN = –18 mA Output Voltage V OH 2.7 — — V CC = 4.75 V V ID = 1 V, IOH = –440 µA VOL ——0 . 4 V IL (G) = 0.8 V V ID = –1 V, IOL = 4 mA — — 0.45 V ID = –1 V, IOL = 8 mA Off State (High I OZ ——2 0µ A V CC = 5.25 V V O = 2.4 V Impedance) Output Current Line Input Current I I — 2.3 2.8 mA V I = 15 V, Other Inputs –10 to +15 V VI = –15 V, Other Inputs –15 to +10 V Enable Input Current I I (EN) — — 100 µA V I = 5.5 V IIH ——2 0 V I = 2.7 V IIL — — –0.36 mA V I = 0.4 V Input Resistance ri 6 9.8 — k Ω VIC = –15 to +15 V (Other Inputs AC GND) Short Circuit Output Current IOS*3 –15 — –85 mA V CC = 5.25 V Supply Current I CC —5 27 0 V CC = 5.25 V, VI = 0 V (All Outputs Disable) Notes: 1. All typical values are at V CC = 5 V, Ta = 25°C,VIC = 0. 2. Hysteresis is the differential between the positive going input threshold voltage and the negative going input threshold voltage. 3. Not more than one output should be shorted at a time. Switching Characteristics (VCC = 5 V, Ta = 25°C) TItem Symbol Min typ Max Unit Conditions Propagation Delay Time t PLH, tPHL —1 72 5n sC L = 15 pF Output Enable Time t ZH, tZL —1 52 2 Output Disable Time t HZ —1 52 2 C L = 5 pF tLZ —2 03 0

Rev.2.00, Jul.16.2004, page 5 of 14 1. tPLH, tPHL Test circuit Pulse Generator Input CL Output Ω2 k VCC Ω5 k 2 V Waveforms Input A 0 V 0 V

0 V 0 V

V 1.3 V 2.5 V –2.5 V 2.5 V –2.5 V tPHL 1.3 V Input B Output

Rev.2.00, Jul.16.2004, page 6 of 14 2. tHZ, tZH Test circuit Input Pulse Generator 2.5 V 2 V C L Output Ω2 k VCC Ω5 k Waveforms Enable G 1.3 V 1.3 V 1.3 V 1.3 V tZH OHV 1.3 V 3 V 0 V 3 V 0 V tHZ

0.5 VOutput

S1 : Open 0 V 1.4 V S1 : Closed

Rev.2.00, Jul.16.2004, page 7 of 14 3. tLZ, tZL Test circuit Input Pulse Generator –2.5 V 2 V CL Output Ω2 k VCC Ω5 k Waveforms Enable 1.3 V 1.3 V 1.3 V 1.3 V tZL OH VOL V 1.3 V 3 V 0 V 3 V 0 V tLZ 0.5 V Output Enable G S2 : Open S2 : Closed 1.4 V Notes: 1. The pulse generator has the following characteristics : PRR = 1 MHz, 50 % duty cycle, tr ≤ 15 ns, t f ≤ 6 ns, Zout = 50 Ω . 2. C L includes probe and jig capacitance. 3. All diodes are 1S2074 (H) 4. To test G input,ground G input and apply an inverted input waveform.

Rev.2.00, Jul.16.2004, page 8 of 14 HD26LS32 Line Receiver Applications The HD26LS32 is a line receiver that meets the EIA RS-422A and RS-423A conditions. It has a high in-phase input voltage range, both positive and negative, enabling highly reliable transmission to be performed even in noisy environments. Its main features are listed below.

  • Operates on a single 5 V power supply.
  • Three-state output
  • On-chip fail-safe circuit
  • ±7 V in-phase input voltage range
  • ±200 mV input sensitivity
  • Minimum 6 kΩ input resistance A block diagram is shown in figure 1. The enable function is common to all four drivers, and either active-high or active-low input can be selected. When exchange is carried out using a party line system, it is better to keep the receiver input bias current constituting the driver load small, as this allows more receivers to be connected. Consequently, whereas an input resistance of 4 kΩ or above is stipulated in RS-422A and RS-423A, the HD26LS32 has been designed to allow a greater margin, with a minimum resistance of 6 kΩ . Figure 2 shows the input current characteristics of the HD26LS32. The shaded areas in the graph indicate the input current allowable range stipulated in RS-422A and RS-423A. HD26LS32 output is LS-TTL compatible and has a three-state function, enabling the output to be placed in the high- impedance state, and so making the device suitable for bus line type applications. With an in-phase input voltage range of ±7 V and a ±200 mV input sensitivity, the HD26LS32 can withstand use in noisy environments. Also, since signals sent over a long-distance transmission line require a long transition time, it also takes a long time to cross the receiver’s input threshold level. Therefore, the input is provided with hysteresis of around 30 mV to prevent receiver output misoperation due to noise. An example of input hysteresis is shown in figure 3. The fail-safe function consists of resistances R connecting input A to V CC and input B to GND, as shown in figure 4. This circuit provides for the receiver input section to be pulled up or down by a high resistance that prevents it from becoming a driver load so that the output goes high in the event of a transmission line breakage or connector detachment. When the input pin is placed in the open state by the pull-up/pull-down resistance, the differential input voltage V ID is as follows: VID: (VIA – VIB) ≥ 0.2 V and the output is fixed high. However, if the receiver-side termination resistance remains connected despite a line breakage or connector detachment, the output will be undetermined (figure 5).

Rev.2.00, Jul.16.2004, page 13 of 14 Package Dimensions 19.2

20.32 Max

6.3 7.4 Max5.06 Max2.54 Min

0.51 Min

(reference value) DP-16E Conforms Conforms 1.05 g 0.89 1.3 7.62 0.25 + 0.1 – 0.05 0˚ – 15˚ As of January, 2003 Unit: mm 19.2 6.3 7.4 Max5.06 Max2.54 Min (reference value) DP-16FV Conforms Conforms 1.05 g 2.54 ± 0.25 *NI/Pd/AU Plating *0.48 ± 0.08 0.89 1.3 7.62 *0.25 ± 0.06 0˚ – 15˚ Unit: mm

Rev.2.00, Jul.16.2004, page 14 of 14 Package Code JEDEC JEITA Mass (reference value) FP-16DAV Conforms 0.24 g *Ni/Pd/Au plating *0.20 ± 0.05 *0.40 ± 0.06 0.12 0.15 M

2.20 Max

5.5 10.06

0.80 Max

10.5 Max

+ 0.20 – 0.307.80 0.70 ± 0.20 0˚ – 8˚ 0.10 ± 0.10 1.15 1.27 As of January, 2003 Unit: mm

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