SL74HCT32 SLS

Document overview

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Technical content

High-Performance Silicon-Gate CMOS The SL74HCT32 may be used as a level converter for interfacing TTL or NMOS outputs to High -Speed CMOS inputs. The SL74HCT32 is identical in pinout to the LS/ALS32.

  • TTL/NMOS-Compatible Input Levels.
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 4.5 to 5.5 V
  • Low Input Current: 1.0 µA

ORDERING INFORMATION

TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN 14 =VCC PIN 7 = GND PIN ASSIGNMENT FUNCTION TABLE Inputs Output A B Y L L L L H H H L H H H H

MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ 750 500 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C tr, tf Input Rise and Fall Time (Figure 1) 0 500 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high -impedance circuit. For proper operation, V IN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C to -55°C ≤85 ≤125 Unit VIH Minimum High-Level Input Voltage VOUT= VCC-0.1 V IOUT≤ 20 µA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 3.98 3.84 3.7 VOL Maximum Low-Level Output Voltage VIN= VIL IOUT ≤ 20 µA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 V VIN= VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 0.26 0.33 0.4 IIN Maximum Input Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 5.5 1.0 10 40 µA ΔICC Additional Quiescent Supply Current VIN=2.4 V, Any One Input ≥-55° C 25°C to 125 °C mA VIN=VCC or GND, Other Input IOUT= 0 µA 5.5 2.9 2.4

AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limits Symbol Parameter 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) 20 25 30 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 15 19 22 ns CIN Maximum Input Capacitance 10 10 10 pF Power Dissipation Capacitance (Per Gate) Typical @25°C,VCC=5.0 V CPD Used to determine the no -load dynamic power consumption: PD=CPDVCC 2f+ICCVCC 15 pF Figure 1 Switching Waveforms. Figure 2. Test Circuit EXPANDED LOGIC DIAGRAM (1/4 of the Device)