HCD66204

HD66204 HITACHI

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

. ~—. . . (Dot Matrix Liquid Crystal Graphic Display Column Driver with 80-Channel Outputs) Description Features The HD66204F/HD66204FL/HD66204TF/HD + Duty cycle: 1/64 to 1/240 66204TFL, the column driver for a large liquid + High voltage crystal graphic display, features as many as 80 — LCD drive: 10-28 V LCD outputs powered by 80 internal LCD drive + High clock speed circuits. This device latches 4-bit parallel data — 8 MHz max under 5-V operation sent from an LCD controller, and generates LCD (HD66204F/HD66204TF) drive signals. In standby mode provided by its — 4 MHz max under 3-V operation internal standby function, only one drive circuit (HD66204FL/HD66204TFL) operates, lowering power dissipation. The + Display off function HD66204 has a complete line-up: the HD66204F, Internal automatic chip enable signal generator a standard device powered by 5 V + 10%; the + Various LCD controller interfaces HD66204FL, a 2.7-5.5 V, low power dissipation — LCTC series: HD63645, HD64645, device suitable for battery-driven portable HD64646 equipment such as “notebook” personal computers — LVIC series: HD66840, HD66841 and palm-top personal computers; and the — CLINE: HD66850 HD66204TF and HD66204TEL, thin package devices powered by 5 V + 10% and 2.7-5.5 V, respectively.

Ordering Information

Type No. Voltage Range Package WDespoae ee HD66204F 5 V+ 10% 100-pin plastic QFP (FP-100) HD66204TF 5V+10% 100-pin thin plastic QFP (TFP-100) HOD66204. TS yan toa HCD66204 5V+10% Chi a_i ee ip HD66204FL 2,7-55V 100-pin plastic FP (FP-100) HD66204TFL 2.7-55V 100-pin thin plastic QFP (TFP-100) Nebessgan SSRs pastiC OFP (TFP-100) _ HCD66204L 27-55V Chip —_soo re HITACHI 691 M@™ 4496204 004648? bbb ——— LL

Pin Arrangement | eo@2@eare 5see2ean aod . BISTLLISLEESSSSSSSSs OO ONO OOOO Nooo SSSF5RBSRISRSSSSRSIIS ysi (1 80[- 30 ys2 C2 79[-J 29 Ys3 Cj3 78{—] Y28 ys4 4 7(2 Ye7 yss (Js 76{_] Y26 ys6 (6 75-1 Yes ys7 C17 74) Yea ! Ys¢ Clg 73[-) Y23 ys9 (}9 7217) Y22 ! Yeo C10 7117) Y21 yet C11 70{-] Y2o Ye2 (12 699) Yi9 Yes (13 HD66204F 6af Y18 Yes (14 HD66204FL 67 17 yes (15 (FP-100) 66[) Y16 ves CJ 16 65f) v5 ye7 (17 64[7J v14 yes C]18 63[J 13 Yeo C119 62-1 Yi2 Y70 J20 if) yi1 y71 (Jat 6o;-} Yio y72 Cj22 s9[_] Y9 y73 CJ23 ss] ys Y74 (24 57) Y7 7s Cas 56] Y6 y7e (26 55[J Ys y77 Cj27 sa 4 y7e (J28 s3[7) Y3

79 C]29 s2[7] Ye

Yao (}30 51 v1 BSBSSRVSERSITIVILITISS OOUDOOUUUODUUUOOOUOUU msoSusae 83222 88s bye io (Top View)

692 HITACHI

M™™ 4456204 0046488 772 i

eeeeeesa(‘ ié‘(‘ CU CHDO6204 SEBISS SES OYE Seenenvenc SESIISLISLESLBSSSSsssosee SSB588S8S58SS5S8SR95SleRe Y53(CJ1 7 75[_] Ya7 Y54(_j2 74[ 7 Yee Y55 (_43 73] Y25 Y56 C_|4 7207) Y24 Ys7 (J5 71) Y23 Y58 [_]6 70[_] Y22 Y59 (_]7 69[-] Y21 Yeo (_js 68[_] Y20 Y61 C_j9 67[_] Y19 Y62 (_]10 66, Y18 Y63 (_J11 65[ Y17 Y64 (_J12 HD66204TF 647) Y16 Y65 (13 63[ 7 15. Yes (]14 HD66204TFL 62 14 Yes (16 (TFP-100) 60f J y12 6s (_]17 Sof Y11 Y70 (_]18 5817] Y10 Y71 C19 57[-] v9 Y72 (_j20 567) Ys Y73 (_j2t 557 Y7 Y74 (_j22 5417] Ye Y75 (_]23 53 Y5 78 ais 52 ¥4 ‘7 (2! 1 ft) ¥3 RA ECEI EER a SVSsUsoQsus oOhOsPAroNOOOET| EgNSssy i iS (Top View) HITACHI Py MB 4496204 0046489 639 me ee

a HD66204 Pin Description Symbot Pin No. (FP-100/TFP-100)__ Pin Name inpuvOutput__Classification | Voc 40/38 Voc = Power supply GND 38736 GND = Power supply | Vee 35/33 Vee = Power supply vi 32/30 Mi Input Power supply v3 391 v3 Input Power supply v4 3432 v4 Input Power supply cui 37/35 Clock 1 Input Control signal cL 49/44 Clock 2 Input Control signal M 36/34 M Input Control signal Do-Ds 48-45/43-40 Data O-data 3 Input Control signal SHL 4139 Shift lett Input Control signal E 31/29 Enable Input Control signal | CAR 50/48 Carry Output Control signal | DISPOFF 39/37 Display off Input Control signal | Y1-Yoo 51-100, 1-30/49-100, 1-28 _Y1-Y80 Output LCD drive output NC 42, 43, 44/45, 46, 47 No connection - = |

694 HITACHI

—_ oss HD66204 SSSSSSSSCS G04 Pin Functions Do-D3: Input display data. High-voltage level of data corresponds to a selected level and turns an Power Supply LCD pixel on, and low-voltage level data . corresponds to a non-selected level and turns an Yee: Vee GND: Voc-GND supplies power to Lp pixel off. the internal logic circuits. Voc-Vgg supplies power to the LCD drive circuits. SHL: Shifts the destinations of display data output. See figure 2. V1, V3, V4: Supply different levels of power to _ _ drive the LCD. V1 and Vpp are selected levels, E: A low Eenables the chip, and a high E disables and V3 and V4 are non-selected levels. See figure the chip. 1 — CAR: Outputs the E signal to the next HD66204 if Control Signal HD66204s are connected in cascade. CLI: Inputs display data latch pulses for the line DISPOFF: A low DISP sets LCD drive outputs data latch circuit. The line data latch circuit Y1-Y 4p to V1 level, latches display data input from the 4-bit latch circuit, and outputs LCD drive signals LCD Drive Output corresponding to the latched data, both at the falling edge of each CL1 pulse. Y1-¥go: Each Y outputs one of the four voltage levels V1, V3, V4, or Vag, depending on a CL2: Inputs display data latch pulses for the 4-bit combination of the M signal and display data latch circuit, The 4-bit latch circuit latches display _levels. See figure 3, data input via at the fallit e of each cL2 pulse. Pods ng edg NC: Must be open. a 'M: Changes LCD drive outputs to AC. panne eee eeeeeee VI popatens-=-= V4 Figure 1 Different Power Supply Voltage Levels for LCD Drive Circuits HITACHI 695 MB 4496204 0046491 29? LL

—_— SSS HD66204 Block Functions Level Shifter LCD Drive Circuit The level shifter changes 5-V signals into high- voltage signals for the LCD drive circuit. Controller: The controller generates the latch signal at the falling edge of each CL2 pulse for the LCD Drive Circuit 4-bit latch circuit, The 80-bit LCD drive circuit generates four 4-Bit Latch Circuit voltage levels V1, V3, V4, and VEE, for driving an LCD panel. One of the four levels is output to The 4-bit latch circuit latches 4-bit parallel data the Corresponding Y pin, depending on a input via the Do to D3 pins at the timing generated combination of the M signal and the data in the by the control circuit. line data latch circuit. Line Data Latch Circuit ‘The 80-bit line data latch circuit latches data input from the 4-bit latch circuit, and outputs the latched data to the level shifter, both at the falling edge of each clock 1 (CLI) pulse. ooo Block Diagram v1 > V4 LCD drive circuit VEE " ee Level shifter DISPOFF Line data latch circuit 4-bit latch circuit A-bit latch circuit meee el SHL cL2 Controller oa CAR HITACHI 697 M™@ 44596204 0046493 ObT mw

Comparison of the HD66204 with the HD61104 tem H066204 HD61104 Clock speed 8.0 MHz max. 3.5 MHz max. Display off function Provided Not provided LCD drive voltage range 10-28 V 10-26 , Relation between SHL and See figure 4 See figure 4 | LCD output destinations Relation between LCD output See figure 5 See figure | levels, M, and data LCD drive V pins V4, V3, V4 V1, V2, V3, V4 (V2 level is the same as VEE level) ze Oe oh oP swesgere EERSERES sypvocce SERSESES EEREEERE BESEEERE BSEEESEE FEREEESE| FeSEESSS) 4 _PBRSEEBEE] BREEBBAA , Do 0 | D2} <= o2t = DS Last and tt ist 2nd Last SHL = low SHL = low | owe erees 0 of we | sugsvere SSERERES soeseere RERRERES BBEEESSE, EBEBEBSE| _RRRBERE| Oy ist and Last Oy Last 2nd ist | SHL = high SHL « high HD66204 HDBt 104 Note the exact reverse relation for the two devices. Figure 4 Relation between SHL and LCD Output Destinations for the HD66204 and HD61104 Ms 12 1 o M 1 2 oe rn re [oe re A Youtput evel ESM apt YS Youtput level UL se S ape 2 aja

066204 HD61104

Figure 5 Relation between LCD Output Levels, M, and Data for the H1D66204 and HD61104 ws HITACHI ME 4496204 OO4b4SH TTL Ml ie

ol — SU | 123 19 20f 24 i i owe 00 — DOC QC | Daas DOOT —— NODE — cu i = jt] (No, 1) 166204 ro. 1 latches data Can | (No. 2) HD66204 no. 2 latches data CAR (No. 3) HD66204 no. 3 _ latches data CAR (No. n) HD66204 no. n latches data Y1-¥e0 CE HITACHI on M™ 4496204 0046455 932

a HD66204 Application Example : i“ yours gi ; Lal aa! | et ei Stiscseres serum em CH Malini SEH “alll = oimcssccesery 2I( 3) ee SESH in ii eve i woo (om foo ibe veal ES " ' = Blais: 1 bitssstae | Pecteeeteed| | [I [iS S3:SSSsam oe

7 AAA

| tebe AJ q ii Notes: 1. The resistances of Rt and R2 depend on the type of the LCD panel used. For example, for an LCD panel with a 1/15 bias, R1 and R2 must be 3 kQ and 33 kQ, respectively. That is, R1/(4 + R1 + R2) should be 1/15. 2. To stabilize the power supply, place two 0.1-uF capacitors near each LCD driver: one between the Voc and GND pins, and the other between the Voc and Vee pins.

700 HITACHI

—_WT-- SCO 66204 Absolute Maximum Ratings Item Symbol __ Rating Unit__ Notes Power supply voltage for logic circuits Voc ~0.310+7.0 v 1 Power supply voltage for LCD drive circuits Vee Voc = 30.0 to Veo +0.3 V Input voltage 1 Vn ~0.3 t0 Voc + 0.3 v 1,2 Input voltage 2 Va2 Vee ~0.310Vog+0.3 V 1,3 Operating temperature Top. -20 to +75 °C Storage temperature Tow 55 to +125 °C Notes: 1. The reference point is GND (0 V). 2. Applies to pins CL1, CL2, M, SHL, E, Do-Ds, DISPOFF. 3. Applies to pins V1, V3, and V4. 4. It the LSI is used beyond its absolute maximum ratings, it may be permanently damaged. It should always be used within its electrical characteristics in order to prevent malfunctioning or degradation of reliability.

Electrical Characteristics

DC Characteristics for the HD66204F/HD66204TF (Voc = 5 V + 10%, GND = 0 ¥, Voc - Vee = 10 to 28 V, and Ta = -20 to +75°C, unless otherwise noted.) Item Symbol Pins Min. Typ. Max. Unit Condition Notes Input high voltage Vw 1 07xVog — Vv v ~ Input low voltage Vie 10 = 03x Veo V Output high voltage Vou 2 Veq-04 — — V bon =-0.4 mA Output low voltage Vo 2 — — 04 Vo =0.4mA Vi-Yjon resistance Row 3 — — 40 kQ_ lon = 100 pA 1 Input leakage current 1 In 1-10 — 10 HA Vin= Voc to GND Input leakage current 2 In» 4-25 -— 2 BA Vin = Voc to Vee Current consumption! Igyp os — Ss — — 30 MA foiz=8.0MHz = 2 fous = 20 kHz Voc - Vee = 28 V Current consumption 2 lee - = 150 500 pA Sameasabove 2 Current consumption 3 Igy - — = 200 HA Sameasabove 2,3 Pins and notes on next page. HITACHI 701 ME 4456204 004b49? 205 mm 0 ee

DC Characteristics for the HD66204FL/HD66204TFL (Vcc = 2.7 to 5.5 V, GND = 0 V, Voc - Vee = 10 to 28 V, and Ta = -20 to +75°C, unless otherwise noted.) | tem Symbol Pins Min. Max. Unit Condition Notes | Input high voltage Vi 1 0.7% Veg _ Voc v Input low voltage Vie 1 0 0.3x Voc V Output high voltage Vou 2 Voc-0.4 — Vy =-0.4mA Output low voltage Vor 2 - 0.4 Vv ly = 0.4 mA Vi-Yj on resistance Ron 3 = 40 kQ lon = 100 pA 1 Input leakage current 1 Ins 1 =1.0 1.0 uA _Vin= Voc to GND Input leakage current 2 nz 4 25 25 WA Vive Vooto Vee | Current consumption? Ignn 1.0 mA foig=4.0MHz 2 four © 16.8 kHz | f= 35 Hz Voc = 3.0 V Voc — Vee = 28 V Checker-board pattern Current consumption 2 lee - = 500 WA _Sameasabove 2 Current consumption 3 _Isr - = 50 WA _Sameasabove 2,3 Pins: 1. CL1, CL2,M, SHL, E, DD, DISPOFF 2. CAR 3. Yi-Yeo, V1, V3, V4 4, V1, V3, V4 Notes: 1. Indicates the resistance between one pin from Y;-Ygo and another pin from V1, V3, V4, and | Vee, when load current is applied to the Y pin; defined under the following conditions. Voc- GND = 28 V V1, V3 = Veg ~ {2/10(Voc - Vee} V4 = Veg + {2/10(Voc - Vee} V1 and V3 should be near Veg level, and V4 should be near Veg level (figure 6). All voltage must be within AV. AV is the range within which Roy, the LCD drive circuits’ output impedance, is stable. Note that AV depends on power supply voltage Voc—Vee (figure 7). 2. Input and output current is excluded. When a CMOS input is floating, excess current flows from the power supply through the input circuit. To avoid this, Vy and Vy_ must be held to Voc and GND levels, respectively. 3. Applies to standby mode.

702 HITACHI

i

a HD66204 AC Characteristics for the HD66204F/HD66204TF (Vcc = 5 V + 10%, GND =0 V, and Ta = -20 to | +75°C, unless otherwise noted.) | tom Symbol Pins Min. Max. Unit Notes | Clock cycle time tere cla 125 = ns | Clock high-level width 1 town Lt, CL2 45 = ns Clock low-level width town oz 45 — ns Clock setup time tsct CLi, CL2 80 — ns Clock hold time tHe CLi, CL2 80 = ns | Clock rise time Ci CLI, CL2 — Note? ns 1 Clock fall time t Lt, CL2 = Notet ns 1 Data setup time tos Do-D3, CL2 20 - ns Data hold time tou Do-Dz.CL2 20 = ns Enable (E) setup time tesu E, CL2 30 =_ ns Carry (CAR) output delay time tcan CAR, CL2 _ 80 ns 2 M phase difference time tom M, CL2 _ 300 ns CL1 cycle time tous cli toy x 50 = ns AC Characteristics for the HD66204FL/HD66204TFL (Vcc = 2.7 to 5.SV, GND = 0 V, and Ta = -20 to +75°C, unless otherwise noted.) tem Symbol Pins Min. Max. Unit Notes Clock cycle time tere cL2 250 - ns Clock high-level width 1 town Lt, CL2 95 — ns Clock low-level width tow. C12 95 = ns Clock setup time tou Lt, CL2 80 = ns Clock hold time thot CLI, CL2 80 = ns Clock rise time t Lt, CL2 — Note1 ns 1 Clock fall time t Lt, CL2 — Notet ons 1 Data setup time tos Do-Dg, CL2 50 - ns Data hold time tox Do-Ds,ClL2 50 = ns Enable (E) setup time tesu E,ci2 65 - ns Carry (CAR) output delay time tcar CAR, CL2 = 155 ns 2 M phase difference time tom M, CL2 = 300 ns CLI cycle time tou cui teyex50 ns Notes: 1. th th < (toye — town ~ tow)/2 and t, ts 50 ns 2. The load circuit shown in figure 8 is connected.

708 HITACHI

ME 44596204 0046500 O2T ml