HCD66108BP

HD66108 HITACHI

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 60

Technical content

Features

• Four types of LCD driving circuit configurations can be selected: Configuration Type No. of Column Outputs No. of Row Outputs Column outputs only 165 0 Row outputs from the left and right sides 100 65 (from left: 32, from right: 33) Row outputs from the right side 1 100 65 Row outputs from the right side 2 132 33

• Seven types of multiplexing duty ratios can be selected: 1/32, 1/34, 1/36, 1/48, 1/50, 1/64, 1/66 Notes: The maximum number of row outputs is 65.
• Built-in bit-mapped display RAM: 10 kbits (165 × 65 bits)
• The word length of display data can be selected according to the character font: 8-bit or 6-bit
• A standby operation is available
• The display can be extended through a multi-chip operation
• A built-in CR oscillator
• An 80-system CPU interface: ø = 4 MHz
• Power supply voltage for operation: 2.7V to 6.0V
• LCD driving voltage: 6.0V to 15.0V
• Low current consumption: 400 µA max (at fOSC = 500 kHz, fOSC is external clock frequency)
• Package: 208-pin TCP (Tape-Carrier-Package)

Ordering Information

Type No. Package HD66108T00 208 pin TCP (Quad) HD66108TA0 (Double side) HD66108TB0 (Double side & folding TCP) HCD66108BP (Chip with bump) Note: The details of TCP pattern are shown in “The Information of TCP.” HD66108 Pad Arrangement Chip size (X × Y) Coordinate Origin Pad size (X × Y) 8.30 × 6.02 mm Pad Center Chip Center 70 × 70 µm (Bump size)TYPE CODE 115 pin 51 pin 116 pin (DMY22) 50 pin (DMY24) 1 pin (DMY23) 165 pin 166 pin 208 pin (DMY21) (DMY5) (DMY20)(DMY12) (DMY13) X Y

HD66108 Pad Location Coordinates Pin Pad Coordinate Pin Pad Coordinate Pin Pad Coordinate Pin Pad Coordinate No. Name X Y No. Name X Y No. Name X Y No. Name X Y (DMY23) 4040 –2550 34 X33 4040 850 67 Y66 1600 2900 101 X100 –1800 2900 1X 0 ↓ –2450 35 X34 ↓ 950 68 X67 1500 ↓ 102 X101 –1900 ↓ 2X 1 ↓ –2350 36 X35 ↓ 1050 69 X68 1400 ↓ 103 X102 –2000 ↓ 3X 2 ↓ –2250 37 X36 ↓ 1150 70 X69 1300 ↓ 104 X103 –2100 ↓ 4X 3 ↓ –2150 38 X37 ↓ 1250 71 X70 1200 ↓ 105 X104 –2200 ↓ 5X 4 ↓ –2050 39 X38 ↓ 1350 72 X71 1100 ↓ 106 X105 –2300 ↓ 6X 5 ↓ –1950 40 X39 ↓ 1450 73 X72 1000 ↓ 107 X106 –2400 ↓ 7X 6 ↓ –1850 41 X40 ↓ 1550 74 X73 900 ↓ 108 X107 –2500 ↓ 8X 7 ↓ –1750 42 X41 ↓ 1650 75 X74 800 ↓ 109 X108 –2600 ↓ 9X 8 ↓ –1650 43 X42 ↓ 1750 76 X75 700 ↓ 110 X109 –2700 ↓

10 X9 ↓ –1550 44 X43 ↓ 1850 77 X76 600 ↓ 111 X110 –3300 ↓

11 X10 ↓ –1450 45 X44 ↓ 1950 78 X77 500 ↓ 112 X111 –3400 ↓

12 X11 ↓ –1350 46 X45 ↓ 2050 79 X78 400 ↓ 113 X112 –3500 ↓

13 X12 ↓ –1250 47 X46 ↓ 2150 80 X79 300 ↓ 114 X113 –3600 ↓

14 X13 ↓ –1150 48 X47 ↓ 2250 81 X80 200 ↓ 115 X114 –3700 2900

15 X14 ↓ –1050 49 X48 ↓ 2350 82 X81 100 ↓ (DMY24) –4040 2550

16 X15 ↓ –950 50 X49 ↓ 2450 83 X82 0 ↓ 116 X115 ↓ 2450

17 X16 ↓ –850 (DMY24) 4040 2550 84 X83 –100 ↓ 117 X116 ↓ 2350

18 X17 ↓ –750 51 X50 3700 2900 85 X84 –200 ↓ 118 X117 ↓ 2250

19 X18 ↓ –650 52 X51 3600 ↓ 86 X85 –300 ↓ 119 X118 ↓ 2150

20 X19 ↓ –550 53 X52 3500 ↓ 87 X86 –400 ↓ 120 X119 ↓ 2050

21 X20 ↓ –450 54 X53 3400 ↓ 88 X87 –500 ↓ 121 X120 ↓ 1950

22 X21 ↓ –350 55 X54 3300 ↓ 89 X88 –600 ↓ 122 X121 ↓ 1850

23 X22 ↓ –250 56 X55 2700 ↓ 90 X89 –700 ↓ 123 X122 ↓ 1750

24 X23 ↓ –150 57 X56 2600 ↓ 91 X90 –800 ↓ 124 X123 ↓ 1650

25 X24 ↓ –50 58 X57 2500 ↓ 92 X91 –900 ↓ 125 X124 ↓ 1550

26 X25 ↓ 50 59 X58 2400 ↓ 93 X92 –1000 ↓ 126 X125 ↓ 1450

27 X26 ↓ 150 60 X59 2300 ↓ 94 X93 –1100 ↓ 127 X126 ↓ 1350

28 X27 ↓ 250 61 X60 2200 ↓ 95 X94 –1200 ↓ 128 X127 ↓ 1250

29 X28 ↓ 350 62 X61 2100 ↓ 96 X95 –1300 ↓ 129 X128 ↓ 1150

30 X29 ↓ 450 63 X62 2000 ↓ 97 X96 –1400 ↓ 130 X129 ↓ 1050

31 X30 ↓ 550 64 X63 1900 ↓ 98 X97 –1500 ↓ 131 X130 ↓ 950

32 X31 ↓ 650 65 X64 1800 ↓ 99 X98 –1600 ↓ 132 X131 ↓ 850

33 X32 4040 750 66 X65 1700 2900 100 X99 –1700 2900 133 X132 ↓ 750

Note: The pin marked by * must be hold VCC .

Pin Pad Coordinate Pin Pad Coordinate Pin Pad Coordinate No. Name X Y No. Name X Y No. Name X Y

134 X133 –4040 650 * (DMY6) –3650 –2900 192 /G35/G28/G36/G28/G37 1030 –2850

135 X134 ↓ 550 * (DMY7) –3550 ↓ 193 TEST2 1160 ↓

136 X135 ↓ 450 * (DMY8) –3450 ↓ 194 TEST1 1290 ↓

137 X136 ↓ 350 * (DMY9) –3350 ↓ 195 BND3 1400 ↓

138 X137 ↓ 250 * (DMY10) –3250 ↓ 196 GND2 1500 ↓

139 X138 ↓ 150 * (DMY11) –3150 ↓ 197 GND1 1600 ↓

140 X139 ↓ 50 * (DMY12) –3050 –2900 (GNDA) 1700 ↓

141 X140 ↓ –50 166 V EE2 –2920 –2872 198 OSC2 1815 ↓

142 X141 ↓ –150 167 VGR –2820 ↓ 199 OSC1 1995 ↓

143 X142 ↓ –250 168 VML3 –2720 ↓ 200 V CC2 2105 –2850

144 X143 ↓ –350 169 VML2 –2620 ↓ 201 V CC1 2205 –2882

145 X144 ↓ –450 170 VMH2 –2520 ↓ 202 VIL 2320 ↓

146 X145 ↓ –550 171 VMH3 –2420 ↓ 203 VMH1 2420 ↓

147 X146 ↓ –650 172 VIR –2320 ↓ 204 V3 2520 ↓

148 X147 ↓ –750 173 V CC4 –2210 –2872 205 V4 2620 ↓

149 X148 ↓ –850 174 V CC3 –2110 –2850 206 VML1 2720 ↓

150 X149 ↓ –950 (V CCA ) –2010 ↓ 207 V6L 2820 ↓

151 X150 ↓ –1050 175 DB0 –1860 ↓ 208 V EE1 2920 –2882

152 X151 ↓ –1150 176 DB1 –1660 ↓ * (DMY13) 3050 –2900

153 X152 ↓ –1250 177 DB2 –1460 ↓ * (DMY14) 3150 ↓

154 X153 ↓ –1350 178 DB3 –1260 ↓ * (DMY15) 3250 ↓

155 X154 ↓ –1450 179 DB4 –1060 ↓ * (DMY16) 3350 ↓

156 X155 ↓ –1550 180 DB5 –860 ↓ * (DMY17) 3450 ↓

157 X156 ↓ –1650 181 DB6 –660 ↓ * (DMY18) 3550 ↓

158 X157 ↓ –1750 182 DB7 –460 ↓ * (DMY19) 3650 ↓

159 X158 ↓ –1850 183 /G35/G27 –285 ↓ * (DMY20) 3750 –2900

160 X159 ↓ –1950 184 /G3A/G35 –155 ↓ (Unit : µm)

161 X160 ↓ –2050 185 RS –25 –

162 X161 ↓ –2150 186 /G26/G36 105 ↓

163 X162 ↓ –2250 187 M 250 ↓

164 X163 ↓ –2350 188 FLM 440 ↓

165 X164 ↓ –2450 189 CL1 580 ↓

(DMY21) –4040 –2550 190 CO 755 ↓ * (DMY5) –3750 –2900 191 MS 900 –2850 Note: The pin marked by * must be hold VCC .

V EE2 V6R VML3 VML2 VMH2 VMH3 V1R V CC4 VCC3 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RD WR RS CS M FLM CL1 CO M/S RESET TEST2 TEST1 GND3 GND2 GND1 OSC2 OSC1 V CC2 VCC1 V1L VMH1 VML1 V6L V EE1 X10 X11 V EE2 V6R VML3 VML2 VMH2 VMH3 V1R V CC4 VCC3 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RD WR RS CS M FLM CL1 CO M/S RESET TEST2 TEST1 GND3 GND2 GND1 OSC2 OSC1 V CC2 VCC1 V1L VMH1 VML1 V6L V EE1 X115

159 X49

(Top View)

44 X164

(Top View) Note : These figures of TCP are not drawn to a scale.

Classification No. of Pins Symbol I/O No.of Pins Function Power 8, 9, 35, 36 V CC1 –VCC4 — 4 Connect these pins to V CC . supply 12 to 14 GND1–GND3 — 3 Ground these pins. 1, 43 V EE1 , VEE2 — 2 These pins supply power to the LCD driving circuits and should usually be set to the V6 level. 2, 7 37, 42 4, 5 6, 39, 38 3, 40, 41 V6L, V1L, V1R, V6R, V4, V3, VMH1–VMH3, VML1–VML3 — 12 Apply an LCD driving voltage V1 to V6 to these pins. CPU interface 23 /G26/G36 I 1 Input a chip select signal via this pin. A CPU can access the HD66108T’s internal registers only while the /G26/G36 signal is low. 25 /G3A/G35 I 1 Input a write enable signal via this pin. 26 /G35/G27 I 1 Input a read enable signal via this pin. 24 RS I 1 Input a register select signal via this pin. 27 to 34 DB7–DB0 I/O 8 Data is transferred between the HD66108T and a CPU via these pins. LCD driving output 44 to 208 X164–X0 O 165 These pins output LCD driving signals. The X0–X31 and X100–X164 pins are column/row common pins and output row driving signals when so programmed. X32–X99 pins are column pins. LCD interface 21 FLM I/O 1 This pin outputs a first line marker when the HD66108T is a master chip and inputs the signal when the chip is a slave chip.

20 CL1 I/O 1 This pin outputs latch clock pulses of

display data when the chip is a master chip and inputs clock CL1 pulses when the chip is a slave chip.

22 M I/O 1 This pin outputs or inputs an M signal,

which converts LCD driving outputs to AC; it outputs the signal when the HD66108T is a master chip and inputs the signal when the chip is a slave chip.

No.of Pins Symbol I/O No.of Pins Function Control 10 OSC1 I 1 Input system clock pulses via this pin. signals 11 OSC2 O 1 This pin outputs clock pulses generated by the internal CR oscillator.

19 CO O 1 This pin outputs the same clock pulses as the

system clock pulses. Connect with the OSC1 pin of a slave chip. 18 /G30 /S I 1 This pin specifies master/slave. Set this pin low when the HD66108T is a master chip and set high when the chip is a slave chip; must not be changed after power-on. 17 /G35/G28/G36/G28/G37 I 1 Input a reset signal via this pin. Setting this pin low initializes the HD66108T. 15, 16 TEST1, TEST2 I 2 These pins input a test signal and must be set low.

165 × 65-bit display memory Y decoder Memory I/O buffer X decoder X address counter Timing generator MPX BUSY MPX I/O controller I/O buffer DB7–DB0RSRDWRCS Clock pulse frequency divider Row counter Y address counter 8- to 6-bit converter MPX VCC2 –VCC3 GND1–GND3 M CL1 FLM M/S RESET CO OSC2 OSC1 TEST1 TEST2 VEE1 V6L V4 V3 VML1 V1L VMH1 VCC1 X0 X31 X32 X99 X100 X164 V CC4 V1R VMH2 VHL2 V EE2 VMH3 VML3 V6R X address register Y address register Control register Mode register C select register Address register

Reg. No. Reg. Register Read/ Data Bit Assignment CS RS 2 1 0 Symbol Name Write 7 6 5 4 3 2 1 0 Busy Time Notes 0 0 — — — AR Address R Busy STBY DISP Register No. None W 0 1 0 0 0 DRAM Display R D7 D6 D5 D4 D3 D2 D1 D0 8 clocks max 2 memory W 3 010 0 1 X A R X R XAD None address W 1.5 clocks max 010 1 0 Y A R Y R YAD None address W 1.5 clocks max 0 1 0 1 1 FCR Control R INC WLS PON ROS DUTY None W 0 1 1 0 0 MDR Mode R FFS DWS None W 0 1 1 0 1 CSR C select R EOR CLN None W 0 1 1 1 0 — Invalid — — 0 1 1 1 1 — Invalid — — Notes: 1. Shaded bits are invalid. Writing 1 or 0 to invalid bits does not affect LSI operation. Reading these bits returns 0. 2. DRAM is not actually a register but can be handled as one. 3. Setting the WLS bit of control register to 1 invalidates D7 and D6 bits of the display memory register. 4. DRAM must not be written to or read from until a time period of t CL1 has elapsed rewriting the DUTY bit of FCR or the FFS bit of MDR. tCL1 can be obtained from the following equation; in general, a time period of 1 ms or greater is sufficient if the frame frequency is 60–90 Hz. tCL1 = D2 D2 (duty correction value): 192 (duty = 1/32, 1/34, or 1/36) 128 (duty = 1/48 or 1/50) 96 (duty = 1/64 or 1/66) Ni (frequency-division ratio specified by the mode register’s FFS bits): Refer to “6. Clock and Frame Frequency.” f CLK : Input clock frequency (kHz)

The HD66108T can assign a maximum of 65 out of 165 channels to row outputs for LCD driving. It also incorporates a timing generator and display memory, which are necessary to drive an LCD. If connected to an MPU and supp lied with LCD driving voltage, one HD66108T chip can be used to configure an LCD system with a 100 × 65 dot panel (Figure 1). In this case, clock pulses should be supplied by the internal CR oscillator or the MPU. Using LCD expansion signals CL1, FLM and M enables the display size to be expanded. In this case, LCD expansion signal pins output corresponding signals when pin /G30 /S is set low for master mode and conversely input corresponding signals when pin /G30 /S is set high for slave mode; LCD expansion signal pins of both master chip and slave chips must be mutually connected. Figure 2 shows a basic system configuration using two HD66108T chips. 100 × 65-dot LCD 100-column output HD66108T LCD driving power supply 65-row output Control bus Data bus MPU Figure 1 Basic System Configuration (1)

265 × 65-dot LCD 100-column output HD66108T (Slave chip) HD66108T (Master chip) 165-column output 65-row output Control bus Data bus MPU LCD expansion signals LCD driving power supply Figure 2 Basic System Configuration (2)

1. Display Size Programming A variety of display sizes can be programmed by changing the system configuration and internal register settings. (1) System Configuration Using One HD66108T Chip When the 65-row-output mode is selected by internal register settings, a maximum of 100 dots in the X direction can be displayed (Figure 3 (a)). Display size in the Y direction can be selected from 32, 34, 36, 48, 50, 64, and 65 dots according to display duty setting. Note that Y direction settings does not affect those in the X direction (100 dots). When the 33-row-output mode is selected by internal register settings, a maximum of 132 dots in the X direction can be displayed (Figure 3 (b)). Table 1 shows the relationship between display sizes and the control register’s (FCR) ROS and DUTY bits. ROS and DUTY bit settings determine the function of X pins. For more details, refer to “4.1 Row Output Pin Selection.” (2) System Configuration Using One HD66108T Chip and One HD61203 Chip as Row Driver A maximum of 64 dots in the Y direction and 165 dots in the X direction can be displayed. 48 or 64 dots in the Y direction can be selected by HD61203 pin settings (Figure 3 (c)). (3) System Configuration Using Two or more HD66108T Chips X direction size can be expanded by 165 dots per chip. Figure 3 (d) shows a 265 × 65-dot display. Y direction size can be expanded up to 130 dots with 2 chips; a 100 × 130-dot display provided by 2 chips is shown in Figure 3 (e). Table 1 Relationship between Display Size and Register Settings (No. of Dots) ROS Bit Setting Duty Bit Setting (Multiplexing Duty Ratio) (X0–X164 Pin Function) 1/32 1/34 1/36 1/48 1/50 1/64 1/66 165-column-output Specified by a row driver 65-row-output from the right side X: 100 Y: 32 X: 100 Y: 34 X:100 Y: 36 X: 100 Y: 48 X: 100 Y: 50 X: 100 Y: 64 X:100 Y: 65 65-row-output from the left and right sides X: 100 Y: 32 X: 100 Y: 34 X:100 Y: 36 X: 100 Y: 48 X: 100 Y: 50 X: 100 Y: 64 X:100 Y: 65 33-row-output from the right side X: 132 Y: 32 X: 132 Y: 33 X: 132 Y: 33 X: 132 Y: 33 X: 132 Y: 33 X: 132 Y: 33 X: 132 Y: 33

X: 100 dots Y: 65 dots X: 132 dots Y: 33 dots Y: 65 dots Y: 130 dots X: 165 dots Y: 64 dots X: 265 dots Area displayed by chip 1 Area displayed by chip 2 Area displayed by chip 1 Area displayed by chip 2 (a) (b) (c) (d) Configuration Using Two HD66108T Chips (1) (e) Configuration Using Two HD66108T Chips (2) X: 100 dots Configuration Using One HD66108T Chip (2) (33-Row Output from the Right Side) Configuration Using One HD66108T Chip (1) (65-Row Output from the Right Side) Configuration Using One HD66108T Chip and One HD61203 as Row Driver (165-Column Output) Figure 3 Relationship between System Configurations and Display Sizes

1. Display Memory Construction and Word Length Setting The HD66108T has a bit-mapped display memory of 165 × 65 bits. As shown in Figure 4, data from the MPU is stored in the display memory, with the MSB (most significant bit) on the left and the LSB (least significant bit) on the right. The sections on the LCD panel corresponding to the display memory bits in which 1’s are written will be displayed as on (black). Display area size of the internal RAM is determined by control register (FCR) settings (refer to Table 1). The start address in the Y direction for the display area is always Y0, independent of the register setting. In contrast, the start address in the X direction is X0 in the modes for 165-column-output, 65-row-output from the right side, and 33-row-output from the right side, and is X32 in the 65-row-output mode from the left and right sides. Each display area contains the number of dots shown in Table 1, beginning from each start address. For more detail, refer to “4.2 Row Output Data Setting,” Figures 15 to 19. In the display memory, one X address is assigned to each word of 8 or 6 bits long in X direction. (Either 8 or 6 bits can be selected as word length of display data.) Similarly, one Y address is assigned to each row in Y direction. Accordingly, X address 20 in the case of 8-bit word and X address 27 in the case of 6-bit word have 5 and 3 bits of display data, respectively. Nevertheless, data is also stored here with the MSB on the left (Figure 5). Display on 165 × 65-dot LCD COM1 COM2 COM65 X0 X1 X2 X3 X4 X5 X6 X7 X164 10100101 DB7 (MSB) DB0 (LSB) Y64 Y direction 156 × 65-bit display memory Figure 4 Relationship between Memory Construction and Display

(H'00) (H'01) (H'02) (H'12) (H'13) (H'14) X address 8 bit 0(H'00) 1(H'01) 63(H'3F) 64(H'40) Y address (H'00) (H'01) (H'03) (H'18) (H'19) (H'1B) X address 6 bit 0(H'00) 1(H'01) 63(H'3F) 64(H'40) Y address (H'02) (H'1A) (a) Address Assignment When 1 Word Is 8 Bits Long (b) Address Assignment When 1 Word Is 6 Bits Long Figure 5 Display Memory Addresses

1. Display Data Write

3.1 Display Memory and Data Register Accesses

(1) Access Figure 6 shows the relationship between the address register (AR) and internal registers and display memory in the HD66108T. Display memory shall be referred to as a data register since it can be handled as other registers. To access a data register, the register address assigned to the desired register must be written into the address register’s Register No. bits. The MPU will access only that register until the register address is updated. Registers accessible with pin RS = 0 Address register B i t76543210 Register No. Registers accessible with pin RS = 1 Data registers Register No. = 0 Display memory X address register Y address register Control register Mode register C select register Figure 6 Relationship between Address Register and Register No.

(2) Busy Check A busy time period appears after display memory read/write or X or Y address register write, since post-access processing is performed synchronously with internal clock pulses. Updating data in registers other than the address register is disabled during this time. Subsequent data must be input after confirming ready mode by reading the address register. The busy time period is a maximum of 8 clock pulses after display memory read/write and a maximum of 1.5 clock pulses after X or Y address register write (Figure 7). HD66108T OSC BUSY FLAG Internal operation WR CPU RD RS DB7 Ready Busy 8 clock pulses max Operates internally Ready Figure 7 Relationship between Clock Pulses and Busy Time (Updating Display Data)

(3) Dummy Read When reading out display data, the data which is read out immediately after setting the X and Y addresses is invalid. Valid data can be read out after one dummy read, which is performed after setting the X and Y addresses desired (Figure 8). CS RS WR RD DB (accessed register) Output data X and Y addresses Sets an X address Xm (address increment direction: X) Sets a Y address Yn Display memory dummy read BUSY CHECK AR WRITE XAR WRITE BUSY CHECK AR WRITE YAR WRITE BUSY CHECK AR WRITE DRAM READ BUSY CHECK DRAM READ BUSY CHECK DRAM READ * (Xm, Yn) (Xm+1, Yn) (Xm+2, Yn) (Xm, *) (Xm, Yn) (Xm+1, Yn) (Xm+2, Yn) Figure 8 Display Memory Reading

(4) Limitations on Access As shown in Figure 9, the display memory must not be rewritten until a time period of tCL1 or longer has elapsed after rewriting the control register’s DUTY bits or the mode register’s FFS bits. However, display memory and registers other than the control register and mode register can be accessed even during this time period. t CL1 can be obtained from the following equation. If using an LSI with a frame frequency of 60 Hz or greater, a time period of 1 ms should be sufficient. tCL1 = D2 D2 (duty correction value): 192 (duty = 1/32, 1/34, or 1/36) 128 (duty = 1/48 or 1/50) 96 (duty = 1/64 or 1/66) Ni (frequency-division ratio specified by the mode register’s FFS bits): f CLK : Input clock frequency (kHz)

3.2 X and Y address Counter Auto-Incrementing Function

As described in “2. Display Memory Construction and Word Length Setting,” the HD66108T display memory has X and Y addresses. Internal X address counter and Y address counter both employ an auto- incrementing function. After display data is read or written, the X or Y address is incremented according to the address increment direction selected by internal register. Although X addresses up to 20 are valid when 8 bits make up one word (up to 27 when 6 bits make up one word), the X address counter can count up to 31 since it is a 5-bit free counter. Similarly, although Y addresses up to 64 are valid, the Y address counter can count up to 127. Consequently, X or Y address must be reset at an appropriate point as shown in Figure 10. Rewriting DUTY or FFS bits Accessing other registers Rewriting display memory tCL1 or longer Figure 9 Rewriting Display Memory after Rewriting Registers

(1) Example of X Address Counter Increment (Word Length: 8 Bits) 127 Reset Y address Set address Write display data Dummy read/write Valid display area Invalid display area Y address counted (2) Example of Y Address Counter Increment (Multiplexing Duty Ratio: 1/32) Figure 10 X/Y Address Counter Increment

1. Selection for LCD Driving Circuit Configuration

4.1 Row Output Pin Selection

The HD66108T can assign a maximum of 65 pins for row outputs among the 165 pins named X0–X164. The X0–X164 pins can be classified into four blocks labelled A, B, C, and D (Figure 11 (a)). Blocks A, C, and D consist of row/column common pins and block B consists of column pins only. The output function of the LCD driving pins and the combination of blocks can be selected by internal registers. Figure 11 shows an example of 165-column-output mode. This configuration is useful when using more than one HD66108T chip or using the HD66108T as a slave chip of the HD61203U. Figure 12 shows an example of 65-row-output mode from the right side. Blocks A and B are used for column output and blocks C and D (X100–X164 pins) for row output. This configuration offers an easy way of connecting row output lines in the case of using one or more HD66108T chips. Figure 13 shows an example of 65-row-output mode from the left and right sides. 32 pins of X0–X31 and 33 pins of X132–X164 are used for row output here. This configuration offers an easy way of connecting row output lines in the case of using only one HD66108T chip. Figure 14 shows an example of 33-row-output mode from the right side. Block D, i.e., X132–X164 pins, is used for row outputs. This configuration provides a means for assigning many pins to column outputs when 1/32 or 1/34 multiplexing duty ratio is desired. In all modes, it is row data and multiplexing duty ratio that determine which pins are actually used among the pins assigned to row output. Y values shown in Table 1 indicate the numbers of pins that are actually used. Pins not used must be left disconnected.

Column driver Column driver Column driver Column driver Block DBlock CBlock BBlock A (a) LCD Driving Circuit Configuration LCD HD66108T 165-column output Row driver (b) System Configuration Figure 11 165-Column-Output Mode

Column driver Column driver Row driver Row driver Block DBlock CBlock BBlock A (a) LCD Driving Circuit Configuration LCD HD66108T 100-column output (b) System Configuration 65-row output Figure 12 65-Row-Output Mode from the Right Side

Row driver Column driver Column driver Row driver Block DBlock CBlock BBlock A (a) LCD Driving Circuit Configuration LCD 100-column output (b) System Configuration HD66108T 33-row output 32-row output Figure 13 65-Row-Output Mode from the Left and Right Sides

Column driver Column driver Column driver Row driver Block DBlock CBlock BBlock A (a) LCD Driving Circuit Configuration LCD HD66108T 132-column output (b) System Configuration 33-row output Figure 14 33-Row-Output-Mode from the Right Side

4.2 Row Output Data Setting

If certain LCD driving output pins are assigned to row output, data must be written to display memory for row output. The specific area to which this data must be written depends on the row-output mode and the procedure of writing row data to the display memory (0 or 1 to which bits?) depends on which X pin drives which line of the LCD. Row data area is determined by the control register’s (FCR) ROS and DUTY bits and is identical to the protected area, which will be described below. (165-column-output mode has no protected area, thus requiring no row data to be written (Figure 15).) Procedure of writing row data to the display memory is as follows. First, 1 must be written to the bit at the intersection between line Yj and line (column) Xi (column). Line Yj is filled with data to be displayed on the first line of the LCD and line Xi is connected to pin Xn, which drives the first line of the LCD. Following this, 0s must be written to the remaining bits on line Yj in the row data area. This rule applies to subsequent lines on the LCD. Table 2 shows the relationship between FCR settings and protected areas. Figure 16 shows the relationship between row data and display. Here the mode is 65-row output from the right side. Display data on Y0 is displayed on the first line of the LCD and data on Y64 is displayed on the 65th line of the LCD. If X164 is connected to the first line of the LCD and X100 is connected to the 65th line of the LCD, 1s must be written to the bits on the diagonal line between coordinates (X164, Y0) and (X100, Y64) and 0s to the remaining bits. Row data protect function must be turned off before writing row data and be turned on after writing row data. Turning on the row data protect function disables read/write of display memory area corresponding to the row output pins, i.e., prevents row data from being destroyed. In Figure 16, display memory area corresponding to pins X100 to X164 is protected. Figures 17 to 19 show examples of row data settings. Some multiplexing duty ratios result in invalid display areas. Although an invalid display area can be read from or written to, it will not be displayed. Table 2 Relationship between FCR Settings and Protected Areas Control Register (FCR) ROS LCD Driving Signal Output Pins Connected to PON 4 3 Mode Protected Area of Display Memory Figures 165-column 65-row (R) 65-row (L/R) 33-row (R) No area protected X100–X164 X0–X31 and X132–X164 X132–X164 16, 19 65-row (R) : 65-row-output mode from the right side 65-row (L/R): 65-row-output mode from the left and right sides 33-row (R): 33-row-output mode from the right side

165 × 64-dot LCD Display data Invalid display data Invalid display area Valid display area Y62 Y63 Y64 X2 X4 X160 X161 X162 X164 X163 Row driver 165-column driver HD66108T X address 8 bits/1 word 6 bits/1 word Control register ROS bit = 00 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V3, VML2 = V4, VMH3 = V3, VML3 = V4 DUTY bit = 101 0123456 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 01234 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 words + 2 bits 4 bits + 10 words + 4 bits 2 bits + 5 words 5 words + 3 bits 4 bits + 3 bytes + 5 bits4 bytes 8 bytes + 4 bits 4 bits + 3 bytes + 4 bits Block A (32 bits) Block B (68 bits) Block C (32 bits) Block D (33 bits) Column driver Column driver Column driver Column driver Figure 15 Relationship between Row Data and Display (165-Column Output, 1/64 Multiplexing Duty Ratio)

Control register ROS bit = 01 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V2, VML2 = V5, VMH3 = V2, VML3 = V5 DUTY bit = 110 0123456 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 01234 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 words + 2 bits 4 bits + 10 words + 4 bits 2 bits + 5 words 5 words + 3 bits 4 bits + 3 bytes + 5 bits4 bytes 8 bytes + 4 bits 4 bits + 3 bytes + 4 bits Block A (32 bits) Block B (68 bits) Block C (32 bits) Block D (33 bits) Column driver Column driver Row data protected blocks Row driver Row driver 65-row driver 100-column driver HD66108T 100 × 65-dot LCD Display data Display memory X95 X96 X97 X98 X99 X100 X101 X102 X160 X161 X162 X163 X164 Area protected with PON = 1Accessible area Y62 Y63 Y64 Row data Figure 16 Relationship between Row Data and Display (65-Row Output from the Right Side, 1/66 Multiplexing Duty Ratio)

Control register ROS bit = 10 LCD driving voltages: VMH1 = V2, VML1 = V5, VMH2 = V3, VML2 = V4, VMH3 = V2, VML3 = V5 DUTY bit = 110 0123456 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 01234 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 words + 2 bits 4 bits + 10 words + 4 bits 2 bits + 5 words 5 words + 3 bits 4 bits + 3 bytes + 5 bits4 bytes 8 bytes + 4 bits 4 bits + 3 bytes + 4 bits Block A (32 bits) Block B (68 bits) Block C (32 bits) Block D (33 bits) Column driver Column driver Row driverRow driver Row data protected block X30 X31 X32 X33 X34 X35 X36 X127 X128 X129 X130 X131 X132 X133 X164 Y30 Y31 Y32 Y33 Y63 Y64 X163 100 × 65-dot LCD Display data Accessible area Area protected with PON = 1 Area protected with PON = 1 Row data Row data Row data protected block 100-column driver 33-row driverHD66108T32-row driver Figure 17 Relationship between Row Data and Display (65-Row Output from the Left and Right Sides, 1/66 Multiplexing Duty Ratio)

Control register ROS bit = 11 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V3, VML2 = V4, VMH3 = V2, VML3 = V5 DUTY bit = 001 0123456 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 01234 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 words + 2 bits 4 bits + 10 words + 4 bits 2 bits + 5 words 5 words + 3 bits 4 bits + 3 bytes + 5 bits4 bytes 8 bytes + 4 bits 4 bits + 3 bytes + 4 bits Block A (32 bits) Block B (68 bits) Block C (32 bits) Block D (33 bits) Column driver Column driver Row driverColumn driver Row data protected block 132-column driver HD66108T 33-row driver X127 X128 X129 X130 X131 X132 X133 X134 X162 X163 X164 132 × 33-dot LCD Display data Invalid display data Accessible area Area protected with PON = 1 Row data Valid display area Invalid display area Y29 Y31 Y32 Y33 Y34 Y63 Y64 Figure 18 Relationship between Row Data and Display (33-Row Output from the Right Side, 1/34 Multiplexing Duty Ratio)

Control register ROS bit = 01 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V2, VML2 = V5, VMH3 = V2, VML3 = V5 DUTY bit = 011 0123456 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 01234 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 words + 2 bits 4 bits + 10 words + 4 bits 2 bits + 5 words 5 words + 3 bits 4 bits + 3 bytes + 5 bits4 bytes 8 bytes + 4 bits 4 bits + 3 bytes + 4 bits Block A (32 bits) Block B (68 bits) Block C (32 bits) Block D (33 bits) Column driver Column driver Row driver Row driver 65-row driver 100-column driver HC66108T 48-row driver used X95 X96 X97 X98 X99 X100 X116 X117 X118 X119 X162 X164 100 × 48-dot LCD Display data Accessible area Area protected with PON = 1 Invalid display area Valid display areaValid row data Row data Y45 Y46 Y47 Y48 Y49 Y63 Y64 Note: Pins X100–X116 are left disconnected here. Row data protected blocks Unused X163 Figure 19 Relationship between Row Data and Display (65-Row Output from the Right Side, 1/48 Multiplexing Duty Ratio)

4.3 LCD Driving Voltage Setting

There are 6 levels of LCD driving voltages ranging from V1 to V6; V1 is the highest and V6 is the lowest. As shown in Figure 20, column output waveform is made up of a combination of V1, V3, V4, and V6 while row output waveform is made up of V1, V2, V5, and V6. This means that V1 and V6 are common to both waveforms while mid-voltages are different. To accommodate this situation, each block of the HD66108T is provided with power supply pins for mid- voltages as shown in Figure 21. Each pair of V1R and V1L and V6R and V6L are internally connected and must be applied the same level of voltage. Block B is fixed for column output and must be applied V3 and V4 as mid-voltages. The other blocks must be applied different levels of voltages according to the function of their LCD driving output pins; if the LCD driving output pins are set for row output, VMHn and VMLn must be applied V2 and V5, respectively, while they must be applied V3 and V4, respectively, if the pins are set for column output (n = 1 to 3). Table 3 Relationship between FCR Settings and LCD Driving Voltages Control Register (FCR) LCD Driving Voltage Pins ROS4 ROS3 Mode VIR/VIL V3 V4 VMH1 VML1 VMH2 VML2 VMH3 VML3 V6R/V6L 165-column 65-row (R) 65-row (L/R) 33-row (R) 65-row (R): 65-row-output mode from the right side 65-row (L/R): 65-row-output mode from the left and right sides 33-row (R): 33-row-output mode from the right side

(non selected waveform) Column- row (selected waveform) 1234 1234 VLCD 7/9VLCD 1/9VLCD -1/9VLCD -7/9VLCD -VLCD VLCD 1/9VLCD -1/9VLCD -VLCD Figure 20 LCD Driving Voltage Waveforms

1. Multiplexing Duty Ratio and LCD Driving Waveform Settings A multiplexing duty ratio and LCD driving waveform can be selected via internal registers. A multiplexing duty ratio of 1/32, 1/34, 1/36, 1/48, 1/50, 1/64, or 1/66 can be selected according to the LCD panel used. However, since there are only 65 row-output pins, only 65 lines will be displayed even if 1/66 multiplexing duty ratio is selected. There are three types of LCD driving waveforms, as shown in Figure 22: A-type waveform, B-type waveform, and C-type waveform. The A-type waveform is called per-half-line inversion. Here, the waveforms of M signal and CL1 signal are the same and alternate every LCD line. The B-type waveform is called per-frame inversion; in this case, the M signal inverts its polarity every frame so as to alternate every two LCD frames. This is the most common type. The C-type waveform is called per-n-line inversion and inverts its polarity every n lines (n can be set as needed within 1 to 31 via the internal registers). The C-type waveform combines the advantages of the A- and B-types of waveforms. However, some lines will not be alternated depending on the multiplexing duty ratio and n. To avoid this, another C-type waveform is available which is generated from the EOR of the C-type waveform M signal mentioned above and the B-type waveform M signal. Since the relationship between n and display quality usually depends on the LCD panel, n must be determined by observing actual display results. The B-type waveform should be used if the LCD panel specifies no particular type of waveform. However, in some cases, the C-type waveform may create a better display. Block A X31X0 VMH1 VML1 Block B X99X32 V3 V4 Block C X131X100 VMH2 VML2 Block D X164X132 VMH3 VML3 LCD driving output pins V6R V1RV6LV1L LCD driving power supply pins Figure 21 Relationship between Blocks and LCD Driving Voltages

M Xn M Xn M Xn M 1 line 1 frame A-type waveform (per-half-line inversion) B-type waveform (per-frame inversion) C-type waveform (per-n-line inversion) EOR function off (n = 5) C-type waveform (per-n-line inversion) EOR function on (n = 5) 1234512345 Figure 22 LCD Driving Waveforms (Row Output with a 1/32 Multiplexing Duty Ratio)

1. Clock and Frame Frequency An input clock with a 200-kHz to 4-MH frequency can be used for the HD66108T. Note that raising clock frequency increases current consumption although it reduces busy time and enables high-speed operations. An optimum system clock frequency should thus be selected within 200 kHz to 4 MHz. The clock frequency driving the LCD panel (= frame frequency) is usually 70 Hz to 90 Hz. Accordingly, the HD66108T is so designed that the frequency-division ratio of the input clock can be selected. The HD66108T generates around 80-Hz LCD frame frequency if the frequency-division ratio is 1. The frequency-division ratio can be obtained from the following equation. Ni =fCLK fF 500

80 D1××

Ni: Frequency-division ratio fF: Frame frequency required for the LCD panel (Hz) fCLK : Input clock frequency (kHz) D1: Duty correction value 1 D1 = 1 when multiplexing duty ratio is 1/32, 1/48 or 1/64 D1 = 32/34 when multiplexing duty ratio is 1/34 D1 = 32/36 when multiplexing duty ratio is 1/36 D1 = 48/50 when multiplexing duty ratio is 1/50 D1 = 64/66 when multiplexing duty ratio is 1/66 The frequency-division ratio nearest the value obtained from the above equation must be selected; selectable frequency-division ratios by internal registers are 2, 1, 1/2, 1/3, 1/4, 1/6, and 1/8. 7. Display Off Function The HD66108T has a display off function which turns off display by rewriting the contents of the internal register. This prevents random display at power-on until display memory is initialized.

1. Standby Function The HD66108T has a standby function providing low-power dissipation. Writing a 1 to bit 6 of the address register starts up the standby function. The LCD driving voltages, ranking from V1 to V6, must be set to VCC to prevent DC voltage from being applied to an LCD panel during standby state. The HD66108T operates as follows in standby mode. (1) Stops oscillation and external clock input (2) Resets all registers to 0’s except the STBY bit Here, note that the display memory will not preserve data if the standby function is turned on; the display memory as well as registers must be set again after the standby function is terminated. V1 to V6 terminals must be connected to V CC to prevent DC voltage being supplied during stand by. Table 4 shows the standby status of pins and Table 5 shows the status of registers after standby function termination. Writing a 0 to bit 6 of the address register terminates the standby function. Writing values into the DISP and Register No. bits at this time is ignored; these bits need to be set after the standby function has been completely terminated. Figure 23 shows the flow for start-up and termination of the standby function and related operations.

Table 4 Standby Status of Pins Pin Status OSC2 High CO Low CL1 Low (master chip) or high-impedance (slave chip) FLM Low (master chip) or high-impedance (slave chip) M Low (master chip) or high-impedance (slave chip) Xn V4 (column output pins) Xn’ V5 (row output pins) Table 5 Register Status after Standby Function Termination Register Name Status after Standby Function Termination Address register Reset to 0’s except for the STBY bit X address register Reset to 0’s Y address register Reset to 0’s Control register Reset to 0’s Mode register Reset to 0’s C select register Reset to 0’s Display memory Data not preserved

Set the LCD driving voltages to VCC level Set the STBY bit to 1 (turn on the standby function) Wait until external clock pulses stabilize Set the STBY bit to 0 (turn off the standby function) Supply the LCD driving voltages Set registers again Wait for a time period of tCL1 or longer Set the display memory Set the DISP bit to 1 (turn on LCD) Start-up Termination Notes: 1. Not necessary in the case of using internal oscillation. Refer to equation 1 (Section 3.1). Figure 23 Start-Up and Termination of Standby Function and Related Operations

1. Multi-Chip Operation Using multiple HD66108T chips (= multi-chip operation) provides the means for extending the number of display dots. Note the following items when using the multi-chip operation. (1) The master chip and the slave chips must be determined; the /G30 /S pin of the master chip must be set low and the /G30 /S pin of the slave chips must be set high. (2) All the HD66108T chips will be slave chips if HD61203 or its equivalent is used as a row driver. (3) The master chip supplies the FLM, CL1, and M signals to the slave chips via the corresponding pins, which synchronizes the slave chips with the master chip. (4) Since a master chip outputs synchronization signals, all data registers must be set. (5) The following bits for slave chips must always be set: INC, WLS, PON, and ROS (control register) FFS (mode register) It is not necessary to set the control register’s DUTY bits, the mode register’s DWS bits, or the C select register. For other registers’ settings, refer to Table 6. (6) All chips must be set to LCD off in order to turn off the display. (7) The standby function of slave chips must be started up first while that of the master chip must be terminated first. Figure 24 to 26 show the connections of the synchronization signals for different system configurations and Table 6 lists the differences between master mode and slave mode. Table 6 Comparison between Master and Slave Mode Item Master Mode Slave Mode Pin: /G30 /S Must be set low Must be set high OSC1, OSC2 Oscillation is possible Oscillation is possible CO = OSC1 = OCS1 FLM, CL1, M Output signals Input signals Register: AR Valid Valid XAR Valid Valid YAR Valid Valid FCR Valid Valid except for the DUTY bits MDR Valid Valid except for the DWS bits CSR Valid (only if the DWS bits are set for the C-type waveform) Invalid Notes: Valid: Needs to be set Invalid: Needs not be set

Note: Clock pulses for the slave chip can be supplied from the master chip's CO pin. Figure 24 Configuration Using Two HD66108T Chips (1)

Note: Clock pulses for the slave chip can be supplied from the master chip CO pin. Figure 25 Configuration Using Two HD66108T Chips (2)

Notes: 1. The slave chip can oscillate CR clock pulses. In this case, the clock pulses must be supplied to the HD61203U from the HD66108T’s CO pin. The HD61203U’s control pins must be set in accordance with the type of RAMs. LCD Figure 26 Configuration Using One HD66108T Chip with Another Row Driver (HD61203U)

All HD66108T’s registers can be read from and written into. However, the BUSY FLAG and inv alid bits cannot be written to and reading invalid bits or registers returns 0’s. 1. Address Register (AR) (Accessed with RS = 0) This register (Figure 27) contains Register No. bits, BUSY FLAG bit, STBY bit, and DISP bit. Register No. bits select one of the data registers according to the register number written. The BUSY FLAG bit indicates the internal operation state if read. The STBY bit activates the standby function. The DISP bit turns the display on or off. This register is selected when RS pin is 0. Bits D4 and D3 are invalid. D7 D6 D5 D4 D3 D2 D1 D0 Register No.—DISPSTBYBUSY FLAG (1) (2) (3) STBY 1: Standby function on 0: Normal (standby function off) Note: When standby function is on, all registers are reset to 0’s. DISP 1: LCD on 0: LCD off Register No. Bit No. Register210 Display memory X address register Y address register Control register Mode register C select register (4) BUSY FLAG (can be read only) 1: Busy state 0: Ready state Figure 27 Address Register

1. Control Register (FCR) (Accessed with RS = 1, Register Number = (B’011) This register (Figure 31), containing eight bits, has a variety of functions such as specifying the method for accessing RAM, determining RAM valid area, and selecting the function of the LCD driving signal output pins. It must be initialized as soon as possible after power-on since it determines the overall operation of the HD66108T. The PON bit may have to be reset afterwards. If the DUTY bits are rewritten after initialization at power-on (if values other than the initial values are desired), the display memory will not preserve data; the display memory must be set again after a time period of t CL1 or longer. For determining tCL1 , refer to equation 1 (Section 3.1). D7 D6 D5 D4 D3 D2 D1 D0 (1) (2) (3) (4) INC (address increment direction select) 1: X address is incremented 0: Y address is incremented WLS (word length (of display data) select) 1: 6-bit word 0: 8-bit word PON (row data protect on) 1: Protect function on 0: Protect function off ROS (row output (function of LCD driving output pins) select) Bit No. Contents43 165 column outputs 65 row outputs from the right side 65 row outputs from the left and right sides 33 row outputs from the right side No. 2 1 Bit Multiplexing Duty Ratio0 Invalid (testing mode) INC WLS PON ROS DUTY (5) DUTY (multiplexing duty ratio) Figure 31 Control Register

1. Mode Register (MDR) (Accessed with RS = 1, Register Number = (B’100) This register (Figure 32), containing 3 invalid bits (D7 to D5) and 5 valid bits (D4 to D0), selects a system clock and type of LCD driving waveform. It must also be initialized after power-on since it determines overall HD66108T operation like the FCR register. If the FFS bits are rewritten after initialization at power-on (if values other than the initial values are desired), the display memory will not preserve data; the display memory must be set again after a time period of t CL1 or longer. For determining tCL1 , refer to equation 1 in section 3.1). D7 D6 D5 D4 D3 D2 D1 D0 (1) FFS (frame frequency select) Bit No. Driving Waveform10 A-type waveform B-type waveform C-type waveform (2) DWS (LCD driving waveform select) — FFS DWS No. 4 3 Bit Frequency- Division Ratio2 Figure 32 Mode Register

1. C Select Register (CSR) (Accessed with RS = 1, Register Number = (B’101) This register (Figure 33) contains 2 invalid bits (D7 and D6) and 5 valid bits (D5 to D0). It controls C- type waveforms and is activated only when MDR register’s DWS bits are set for this type of waveform. D7 D6 D5 D4 D3 D2 D1 D0 (1) (2) EOR (B-type waveform M signal + no. of counting lines on/off) 1: EOR function on 0: EOR function off CLN (No. of counting lines in C-type waveform) 1 to 31 should be set in these bits; 0 must not be set. — EOR CLN Figure 33 C Select Register

The /G35/G28/G36/G28/G37 pin starts the HD66108T after power-on. A /G35/G28/G36/G28/G37 signal must be input via this pin for at least 20 µs to prevent system failure due to excessive current created after power-on. Figure 34 shows the reset definition. (1) The Status of Pins during Reset Table 7 shows the reset status of output pins. The pins return to normal operation after reset. Table 7 The Status of Pins during Reset Pin Status OSC2 Outputs clock pulses or oscillates CO Outputs clock pulses CL1 Low (master chip) or high-impedance (slave chip) FLM Low (master chip) or high-impedance (slave chip) M Low (master chip) or high-impedance (slave chip) Xn V4 (column output pins) Xn’ V5 (row output pins) 0.15 × VCC 0.15 × VCC After resetAt reset During reset (reset status) RESET Figure 34 Reset Definition

(2) The Status of Registers during Reset The /G35/G28/G36/G28/G37 signal has no effect on registers or register bits except for the address register’s STBY bit and the X and Y address registers, which are reset to 0’s by the signal. Table 8 shows the reset status of registers. (3) Status after Reset The display memory does not preserve data which has been written to it before reset; it must be set again after reset. A /G35/G28/G36/G28/G37 signal terminates the standby mode. Table 8 The Status of Registers during Reset Register Status Address register Pre-reset status with the STBY bit reset to 0 X address register Reset to 0’s Y address register Reset to 0’s Control register Pre-reset status Mode register Pre-reset status C select register Pre-reset status Display memory Preserves no pre-reset data

Precautionary Notes When Using the HD66108T (1) Install a 0.1-µF bypass capacitor as close to the LSI as possible to reduce power supply impedance (VCC –GND and V CC –V EE ). (2) Do not leave input pins open since the HD66108T is a CMOS LSI; refer to “Pin Functions” on how to deal with each pin. (3) When using the internal oscillation clock, attach an oscillation resistor as close to the LSI as possible to reduce coupling capacitance. (4) Make sure to input the reset signal at power-on so that internal units operate as specified. (5) Maintain the LCD driving power at V CC during standby state so that DC is not applied to an LCD, in which Xn pins are fixed at V4 or V5 level. Programming Restrictions (1) After busy time is terminated, an X or Y address is not incremented until 0.5-clock time has passed. If an X or Y address is read during this time period, non-updated data will be read. (The addresses are incremented even in this case.) In addition, the address increment direction should not be changed during this time since it will cause malfunctions. (2) Although the maximum output rows is 33 when 33-row-output mode from the right side is specified, any multiplexing duty ratio can be specified. Therefore, row output data sufficient to fill the specified duty must be input in the Y direction. Figure 35 shows how to set row data in the case of 1/34 multiplexing duty ratio. In this case, 0s must be set in Y33 since data for the 34th row (Y33) are not output. (3) Do not set the C select register’s CLN bits to 0 for the M signal of C-type waveform. X132 X133X131 X164 X163 All 0’s Row data areaDisplay data area Y30 Y31 Y32 Y33 Figure 35 How to Set Row Data for 33-Row Output from the Right Side

Power supply voltage (1) V CC1 to VCC3 –0.3 to +7.0 V Power supply voltage (2) V CC –VEE –0.3 to +16.5 V Input voltage Vin –0.3 to V CC + 0.3 V Operating temperature T op –20 to +75 °C Storage temperature T stg –40 to +125 °C Notes: 1. Permanent LSI damage may occur if the maximum ratings are exceeded. Normal operation should be under recommended operating conditions (VCC = 2.7 to 6.0V, GND = 0V, Ta = –20 to +75°C). If these conditions are exceeded, LSI malfunctions could occur. 2. Power supply voltages are referenced to GND = 0V. Power supply voltage (2) indicates the difference between VCC and VEE .

Electrical Characteristics

DC Characteristics (1) (VCC = 5V ±20%, GND = 0V, V CC – VEE = 6.0 to 15V, Ta = –20 to +75°C, unless otherwise noted) Item Symbol Min Typ Max Unit Test Conditions Note s Input high OSC1 V IH1 0.8 × VCC —V CC + 0.3 V voltage /G30 /S, CL1, FLM, M, TEST1, TEST2 VIH2 0.7 × VCC —V CC + 0.3 V /G35/G28/G36/G28/G37 VIH3 0.85 × VCC —V CC +0.3 V The other inputs VIH4 2.0 — V CC + 0.3 V V CC = 5V ±10% 5 Input low OSC1 V IL1 –0.3 — 0.2 × VCC V voltage /G30 /S, CL1, FLM, M, TEST1, TEST2 VIL2 –0.3 — 0.3 × VCC V /G35/G28/G36/G28/G37 VIL3 –0.3 — 0.15 × VCC V The other inputs VIL4 –0.3 — 0.8 V V CC = 5V ±10% 6 Output high voltage CO, CL1, FLM, M VOH1 0.9 × VCC —— V – I OH = 0.1 mA DB7–DB0 V OH2 2.4 — — V –I OH = 0.2 mA VCC = 5V ±10% Output low voltage CO, CL1, FLM, M VOL1 — — 0.1 × VCC VI OL = 0.1 mA DB7–DB0 V OL2 — — 0.4 V I OL = 1.6 mA VCC = 5V ±10% Input leakage current All except DB7–DB0, CL1, FLM, M I IIL –2.5 — 2.5 µA Vin = 0 to V CC Tri-state leakage current DB7–DB0, CL1, FLM, M I TSL –10 — 10 µA Vin = 0 to V CC V pins leakage current V1L, V1R, V3, V4, V6L, V6R, VMHn, VMLn I VL –10 — 10 µA Vin = V EE to VCC Current consumption During display I CC1 — — 400 µA External clock fOSC = 500 kHz ICC2 — — 1.0 mA Internal oscillation R f = 91 kΩ During standby I SB — — 10 µA 1, 2

Item Symbol Min Typ Max Unit Test Conditions Notes ON resistance between Vi and Xj X0–X164 R ON ——1 0k Ω ±ILD = 50 µA VCC –VEE = 10V V pins voltage range ÆV — — 35 % 4 Oscillating frequency f OSC 315 450 585 kHz R f = 91 kΩ Notes: 1. When voltage applied to input pins is fixed to VCC or to GND and output pins have no load capacity. 2. When the LSI is not exposed to light and Ta = 0 to 40°C with the STBY bit = 1. If using external clock pulses, input pins must be fixed high or low. Exposing the LSI to light increases current consumption. 3. I LD indicates the current supplied to one measured pin. 4. ÆV = 0.35 × (VCC –VEE ). For levels V1, V2, and V3, the voltage supplied should be between the VCC and the ÆV and for levels V4, V5, and V6, the voltage supplied should be between the VEE and the ÆV (Figure 36). 5. VIH4 (min) = 0.7 × VCC when used under conditions other than VCC = 5V ±10%. 6. VIL4 (max) = 0.15 × VCC when used under conditions other than VCC = 5V ±10%. 7. VOH2 (min) = 0.9 × VCC (–IOH = 0.1 mA) when used under conditions other than VCC = 5V ±10%. 8. VOL2 (max) = 0.1 × VCC (IOL = 0.1 mA) when used under conditions other than VCC = 5V ±10%.

DC Characteristics (2) (VCC = 2.7 to 4.0V, GND = 0V, VCC –V EE = 6.0 to 15V, Ta = –20 to +75°C, unless otherwise noted) Item Symbol Min Typ Max Unit Test Conditions Notes Input high /G35/G28/G36/G28/G37 VIH1 0.85 × VCC —V CC + 0.3 V voltage The other inputs VIH2 0.7 × VCC —V CC + 0.3 V Input low voltage /G30/G12 S, OSC1, CL1, FLM, TEST1, TEST2, M V IL1 –0.3 — 0.3 × VCC V The other inputs VIL2 –0.3 — 0.15 × VCC V Output high voltage VOH1 0.9 × VCC —— V – I OH = 50 µA Output low voltage VOL1 — — 0.1 × VCC VI OL = 50 µA Input leakage current All except DB7–DB0, CL1, FLM, M I IIL –2.5 — 2.5 µA Vin = 0 to V CC Tri-state leakage current DB7–DB0, CL1, FLM, M I TSL –10 — 10 µA Vin = 0 to V CC V pins leakage current V1L, V1R, V3, V4, V6L, V6R, VMHn, VMLn I VL –10 — 10 µA Vin = V EE to VCC Current consumption During display ICC1 — — 260 µA External clock fOSC = 500 kHz ICC2 — — 700 µA Internal oscillation R f = 75 kΩ During standby state ISB — — 10 µA 1, 2 ON resistance between Vi and Xj X0–X164 R ON —— 1 0 k Ω ±ILD = 50 µA VCC –VEE = 10V V pins voltage range ÆV — — 35 % 4 Oscillating frequency f OSC 315 450 585 kHz R f = 75 kΩ Notes: 1. When voltage applied to input pins is fixed to VCC or to GND and output pins have no load capacity. Exposing the LSI to light increases current consumption. 2. When the LSI is not exposed to light and Ta = 0 to 40°C with the STBY bit = 1. If using external clock pulses, input pins must be fixed high or low. 3. ILD indicates the current supplied to one measured pin. 4. ÆV = 0.35 × (VCC –VEE ). For levels V1, V2, and V3, the voltage supplied should be between the VCC and the ÆV and for levels V4, V5, and V6, the voltage supplied should be between the VEE and the ÆV (Figure 36).

ΔV V1, V2, V3 levels ΔV V4, V5, V6 levels VCC VEE Figure 36 Driver Output Waveform and Voltage Levels

AC Characteristics (1) (VCC = 4.5 to 6.0V, GND = 0V, Ta = –20 to +75°C, unless otherwise noted) 1. CPU Bus Timing (Figure 37) Item Symbol Min Max Unit /G35/G27 high-level pulse width t WRH 190 — ns /G35/G27 low-level pulse width t WRL 190 — ns /G3A/G35 high-level pulse width t WWH 190 — ns /G3A/G35 low-level pulse width t WWL 190 — ns /G3A/G35 –/G35/G27 high-level pulse width t WWRH 190 — ns /G26/G36 , RS setup time t AS 0— n s /G26/G36 , RS hold time t AH 0— n s Write data setup time t DSW 100 — ns Write data hold time t DHW 0— n s Read data output delay time t DDR — 150 ns Note Read data hold time t DHR 20 — ns Note External clock cycle time t CYC 0.25 5.0 µs External clock high-level pulse width tWCH 0.1 — µs External clock low-level pulse width tWCL 0.1 — µs External clock rise and fall time tr, tf —2 0 n s Note: Measured by test circuit 1 (Figure 39). 2. LCD Interface Timing (Figure 38) Item Symbol Min Max Unit Notes /G30 /S = 0 CL1 High-level pulse width tWCH1 35 — µs 1, 4 CL1 Low-level pulse width tWCL1 35 — µs 1, 4 FLM Delay time t DFL1 –2.0 +2.0 µs 4 FLM Hold time t HFL1 –2.0 +2.0 µs 4 M output delay time t DMO1 –2.0 +2.0 µs 4 /G30 /S = 1 CL1 High-level pulse width tWCH2 35 — µs 4 CL1 Low-level pulse width tWCL2 11 × tCYC — µs 2, 4 FLM Delay time t DFL2 –2.0 1.5 × tCYC µs 3, 4 FLM Hold time t HFL2 –2.0 +2.0 µs 4 M delay time t DMI –2.0 +2.0 µs 4 2. When bits FFS are set for 1 or 2. The value is 19 × tCYC in other cases. 3. When bits FFS are set for 1 or 2. The value is 8.5 × tCYC in other cases. 4. Measured by test circuit 2 (Figure 39).

AC Characteristics (2) (VCC = 2.7 to 4.5V, GND = 0V, Ta = –20 to +75°C, unless otherwise noted) 1. CPU Bus Timing (Figure 37) Item Symbol Min Max Unit /G35/G27 high-level pulse width t WRH 1.0 — µs /G35/G27 low-level pulse width t WRL 1.0 — µs /G3A/G35 high-level pulse width t WWH 1.0 — µs /G3A/G35/G03 low-level pulse width t WWL 1.0 — µs /G3A/G35 –/G35/G27 high-level pulse width t WWRH 1.0 — µs /G26/G36/G0F RS setup time t AS 0.5 — µs /G26/G36/G0F RS hold time t AH 0.1 — µs Write data setup time t DSW 1.0 — µs Write data hold time t DHW 0— µ s Read data output delay time t DDR — 0.5 µs Note Read data hold time t DHR 20 — ns Note External clock cycle time t CYC 1.6 5.0 µs External clock high-level pulse width tWCH 0.7 — µs External clock low-level pulse width tWCL 0.7 — µs External clock rise and fall time tr, tf — 0.1 µs Note: Measured by test circuit 2 (Figure 39). 2. LCD Interface Timing (Figure 38) Item Symbol Min Max Unit Notes /G30 /S = 0 CL1 High-level pulse width tWCH1 35 — µs 1, 4 CL1 Low-level pulse width tWCL1 35 — µs 1, 4 FLM Delay time t DFL1 –2.0 +2.0 µs 4 FLM Hold time t HFL1 –2.0 +2.0 µs 4 M output delay time t DMO1 –2.0 +2.0 µs 4 /G30 /S = 1 CL1 High-level pulse width tWCH2 35 — µs 4 CL1 Low-level pulse width tWCL2 11 × tCYC — µs 2, 4 FLM Delay time t DFL2 –2.0 1.5 × tCYC µs 3, 4 FLM Hold time t HFL2 –2.0 +2.0 µs 4 M delay time t DMI –2.0 +2.0 µs 4 2. When bits FFS are set for 1 or 2. The value is 19 × tCYC in other cases. 3. When bits FFS are set for 1 or 2. The value is 8.5 × tCYC in other cases. 4. Measured by test circuit 2 (Figure 39).

5.0V R L All diodes are IS2074 H RC C C = 50 pF RL = 2.4 kΩ R = 11 kΩ C = 130 pF Test Circuit 1 Test Circuit 2 Figure 39 Load Circuits