HCD404669

HD404669 HITACHI

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 142

Technical content

Features

• 1,152-digit · 4-bit RAM
• I/O pins: 47 ¾ High-current I/O pins (source: 10 mA max.): 4 ¾ High-current I/O pins (sink: 15 mA max.): 5
• Timer counters: 3
• Input capture: one 8-bit channel
• Timer outputs: 2 (with PWM output capability)
• Event input: 1 (edge-programmable)
• Clock synchronous 8-bit serial interface: 1
• DTMF generation circuit
• Comparator: 2 channels
• System clock oscillator Ceramic oscillator, crystal oscillator, or external clock operation possible

• Subsystem clock oscillator 32.768 kHz crystal oscillator for realtime clock use
• Interrupts ¾ External: 5 (including 3 edge-programmable) ¾ Internal: 4
• Subroutine stack: max. 16 levels including interrupts
• Low-power modes: 4
• System clock division software switching (1/4, 1/8, 1/16, 1/32)
• Instruction execution time Min. 1 ms (fOSC = 4 MHz, 1/4 clock division) Min. 0.5 ms (fOSC = 8 MHz, 1/4 clock division)
• Operating voltage 1.8 V to 5.5 V 2.2 V to 5.5 V (ZTAT™)

Ordering Information

Type Product Name Model Name ROM (Words) RAM (Digits) Package Mask ROM (standard version) HD404668 HD404668H 8,192 1,152 64-pin plastic QFP (FP-64A) HD4046612 HD4046612H 12,288 HD404669 HD404669H 16,384 HCD404669 HCD404669 16,384 Chip *1 *2 Mask ROM (high-speed version) HD40A4668 HD40A4668H 8,192 64-pin plastic QFP (FP-64A) HD40A46612 HD40A46612H 12,288 HD40A4669 HD40A4669H 16,384 ZTAT™ (high-speed version) HD407A4669 HD407A4669H 16,384 Note: 1. ZTAT™ chip shipment is not supported. 2. The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details. Cautions about Operation The mask ROM and ZTAT™ versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this data sheet. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, internal

wiring patterns, etc. Users are therefore requested to confirm the operation of individual products by conducting evaluation tests under conditions equivalent to those in the actual application system. List of Functions Standard version HD404668 HD4046612 HD404669 HCD404669 Product name High- speed version HD40A4668 HD40A46612 HD40A4669 ——— HD407A4669 ROM (Words) 8,192 12,288 16,384 16,384 16,384PROM RAM (Digits) 1,152 I/O 52 (max) Large-current I/O pins 4 ( Source 10mA max), 5 (Sink 15 mA max) Timer / Counter 3 Input capture 8 bit · 1 Timer output 2 (PWM output possible) Event input 1 (edge selection possible) Serial interface 1 (8-bit clock syncronous) DTMF generation circuit Available Comparator 2 Interrupt External 5 (edge selection possible for 3) Internal 4 Low-Power Dissipation Mode 4 Stop mode Available Watch /mode Available Standby mode Available Subactive mode Available Main Oscillator Ceramic oscillation 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz*, 8 MHz* Crystal oscillation 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 Mhz, 7.16 MHz*, 8 MHz* Sub oscillator Crystal oscillation 32.768 kHz Minimum instruction execution time Standard version 1 ms (fOSC = 4 MHz, 1/4 frequency division) High-speed version 0.5 ms (fOSC = 8 MHz, 1/4 frequency division) Package 64-pin plastic QFP (FP-64A) Chip 64-pin plastic QFP (FP-64A) Guaranteed operation temperature (˚C) –20 to +75 +75 °C –20 to +75 Note: * Applies to high-speed versions (HD40A4668, HD40A46612, HD40A4669, HD407A4669).

D D 9 D 10 D 3 D 4 D 1 D 2 D 0 RD 1/COMP 1 RD 0/COMP 0 VT ref TONER TONEC VCC SEL RA 1 RA 0 R9 3 R9 2 R9 1 R9 0 R8 3 R8 2 R8 1 D 11 R0 1 /INT2 R0 2 /INT3 R0 3 /INT4 R2 1 R2 2 R2 3 R3 0 FP-64A Top view D 12 /STOPC D 13 /INT0 R0 0 R1 3 R2 0 R1 0 R1 1 R1 2 /INT1

TYPE CODE: HD404669

Chip Size (X × Y): 4.34 × 4.01 (mm) Coordinates: Pad Center Home Point position: Chip Center Pad size (X × Y): 90 × 90 (µm) Chip thickness: 400 (µm) Y XChip center (X=0, Y=0) Pad Pad Coordinates Pad Pad Coordinates Pad Pad Coordinates Pad Pad Coordinates No. Name X Y No. Name X Y No. Name X Y No. Name X Y

1 RE0 –1983 1444 17 D11 –1607 –1819 33 R33 1983 –1444 49 R81 1587 1819

2 TESTN –1983 1252 18 D12 –1394 –1819 34 R32 1983 –1252 50 R82 1374 1819

3 OSC1 –1983 1062 19 D13 –1181 –1819 35 R31 1983 –1060 51 R83 1161 1819

4 OSC2 –1983 871 20 R00 –968 –1819 36 R40 1983 –867 52 R90 948 1819

5 RESET –1983 657 21 R01 –755 –1819 37 R41 1983 –675 53 R91 735 1819

6 X1 –1983 466 22 R02 –541 –1819 38 R42 1983 –483 54 R92 522 1819

7 X2 –1983 275 23 R03 –329 –1819 39 R43 1983 –291 55 R93 309 1819

8 GND –1983 84 24 R10 –117 –1819 40 R60 1983 –99 56 RA0 93 1819

9 D0 –1983 –108 25 R11 96 –1819 41 R61 1983 93 57 RA1 –177 1819

10 D1 –1983 –299 26 R12 309 –1819 42 R62 1983 285 58 SEL –329 1819

11 D2 –1983 –490 27 R13 522 –1819 43 R63 1983 478 59 V CC –542 1819

12 D3 –1983 –680 28 R20 735 –1819 44 R70 1983 670 60 TONEC –755 1819

13 D4 –1983 –871 29 R21 948 –1819 45 R71 1983 862 61 TONER –968 1819

14 D5 –1983 –1062 30 R22 1161 –1819 46 R72 1983 1054 62 VTREF –1181 1819

15 D9 –1983 –1253 31 R23 1374 –1819 47 R73 1983 1246 63 RD0 –1394 1819

16 D10 –1983 –1444 32 R30 1587 –1819 48 R80 1983 1444 64 RD1 –1607 1819

Item Symbol FP-64A, chip I/O Function Power V CC 59 – Applies power voltage supply GND 8 – Connected to ground Test TEST 2 I Used for factory testing only: Connect this pin to V CC Reset RESET 5 I Resets the MCU Oscillator OSC 1 3 I Input/output pins for the internal oscillator circuit: Connect them to a ceramic oscillator ,crystal oscillator or connect OSC 1 to an external oscillator circuit OSC 2 4O X1 6 I Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to VCC and leave the X2 pin open. X2 7 O Port D 0–D5, D 9–D11 9-17 I/O Input/output pins addressed by individual bits; D 0 to D3 are source high-current input/output pins. A maximum 10 mA current can be supplied to each pin. D 4, D5, and D9 to D11 are sink high-current input/output pins. A maximum 15 mA current can be supplied to each pin. D 12, D13 18, 19 I Input pins addressable by individual bits R00–R4 3, R60–RA 1 20–57 I/O Input/output pins addressable in 4-bit units RD 0, RD1, RE0 63, 64, 1 I Input pins addressable in 4-bit units Interrupt INT0, INT1, INT2–INT4 19-23 I Input pins for external interrupts Stop clear STOPC 18 I Input pin for transition from stop mode to active mode Serial SCK1 37 I/O Serial interface clock input/output pin interface SI1 38 I Serial interface receive data input pin SO 1 39 O Serial interface transmit data output pin Timer TOC, TOD 35, 34 O Timer output pins EVND 36 I Event input pin DTMF TONER 61 O Output pin for DTMF row signals TONEC 60 O Output pin for DTMF column signals VTref 62 – Reference voltage pin for DTMF signals. Voltage conditions are: VCC ‡ VTref ‡ GND

Item Symbol FP-64A, chip I/O Function Voltage comparator COMP 0, COMP 1 63, 64 I Comparator analog input pins. VC ref 1 – Analog input pin threshold voltage reference level power supply pin. Frequency division ratio selection SEL 58 I Pin that selects the system clock division ratio immediately after a reset and when returning from stop mode to active mode. Connect to Vcc voltage to select division-by-4, or to GND potential to select division-by-32.

: Data bus RESET TEST STOPC OSC OSC 2 V CC GND SEL HMCS400 CPU ROM RAM 8-bit timer A (free-running timer) 8-bit timer C D 0 D 1 D 2 D 3 D 4 D 5 D 9 D 10 D 11 D 12 D 13 R4 0 R4 1 R4 2 R4 3 R0 port R0 0 R0 1 R0 2 R0 3 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 R3 0 R3 1 R3 2 R3 3 R6 0 R6 1 R6 2 R6 3 TOC VC ref COMP 0 COMP 1 Comparator External interrupt control circuit INT0 INT1 INT2 INT3 INT4 R7 0 R7 1 R7 2 R7 3 8-bit timer DEVND TOD Synchronous 8-bit serial interface SCK1 SI1 SO 1 RA 0 RA 1 RD 0 RD 1 RE 0 : Signal line R9 0 R9 1 R9 2 R9 3 R8 0 R8 1 R8 2 R8 3 DTMF generation circuit VT ref TONER TONEC D portR1 portR2 portR3 portR4 portR6 portR7 portR8 portR9 portRA port RD port RE port

The ROM memory map is shown in figure 1 and described below. Vector addresses (16 words) Zero page subroutine area (64 words) Pattern area (4,096 words) HD404668/HD40A4668 program area (8,192 word) $000F $0FFF $1000 $3FFF $0010 $003F $0040 $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F ROM address JMPL instruction (Jump to reset, stop mode clearance routine) JMPL instruction (Jump to INT 0 interrupt handling routine) JMPL instruction (Jump to INT 1 interrupt handling routine) ROM address HD4046612/HD40A46612 program area (12,288 words) HD404669/HD40A4669/ HCD404669/HD407A4669 program area (16,384 words) $1FFF $2000 $2FFF $3000 JMPL instruction (Jump to timer A interrupt handling routine) JMPL instruction (Jump to INT 2 interrupt handling routine) JMPL instruction (Jump to timer C, INT3 interrupt handling routine) JMPL instruction (Jump to timer D, INT4 interrupt handling routine) JMPL instruction (Jump to serial 1 routine) Figure 1 ROM Memory Map Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000–$1FFF: HD404668, HD40A4668; $0000–$2FFF: HD4046612, HD40A46612; $0000–$3FFF: HD404669, HD40A4669, HD407A4669, HCD404669): Used for program coding.

The MCU contains a RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same RAM memory space. The RAM memory map is shown in figure 2 and described below. RAM-Mapped Register Area ($000–$03F):

• Interrupt Control Bits Area ($000–$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$01F, $024–$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timers, DTMF, comparator, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

$000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F Port mode register A Serial mode register 1A Serial data register 1L Serial data register 1U Timer mode register A Miscellaneous register Timer mode register C1 Timer C Timer mode register D1 Timer D Timer mode register C2 Timer mode register D2 Compare data register Compare enable register Tone generator mode register Tone generator control register System clock select register 1 System clock select register 2 Data control register D 0 to D3 Data control register D4 to D5 Data control register D9 to D11 Data control register R0 Data control register R1 Data control register R2 Data control register R3 Data control register R4 Data control register R6 Data control register R7 Data control register R8 Data control register R9 Data control register RA V register Interrupt control bit area Register flag area Not used (PMRA) (SM1A) (SR1L) (SR1U) (TMA) (MIS) (TMC1) (TRCL/TWCL) (TRCU/TWCU) (TMD1) (TRDL/TWDL) (TRDU/TWDU) (TMC2) (TMD2) (CDR) (CER) (TGM) (TGC) (PMRB) (PMRC) (ESR1) (ESR2) (SM1B) (SSR1) (SSR2) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR6) (DCR7) (DCR8) (DCR9) (DCRA) W W R/W R/W W W W R/W R/W W R/W R/W R/W R/W R W W W W W W W W W W W W W W W W W W W W W W W (V) R/W (TWCL) (TWCU) (TWDL) (TWDU) W W W W R R R R $000 $260 $3C0 $3FF RAM-mapped register area Memory registers (16 digits) Data (464 digits x 2) V = 0 (bank = 0) V = 1 (bank = 1) Data (144 digits) Stack area (64 digits) R W R/W : Read only : Write only : Read/Write Not used RAM addressRAM address $040 $050 Not used$2F0 $090 Port mode register B Port mode register C Detection edge select register 1 Detection edge select register 2 Serial mode register 1B $00E $00F $011 $012 Timer read register CL Timer read register CU Timer read register DL Timer read register DU (TRCL) (TRCU) (TRDL) (TRDU) Timer write register CL Timer write register CU Timer write register DL Timer write register DU $090 $25F Note : *1. There are two data areas, V = 0 (bank 0) and V = 1 (bank 1) Data (464 digits) V = 0 (bank = 0) Data (464 digits) V = 1 (bank = 1) *2. Two registers are mapped onto the same address ($00E, $00F, $011, $012) Not used Not used Not used Not used Not used Not used Not used Figure 2 RAM Memory Map

: Interrupt Request Flag : Interrupt Mask : Interrupt Enable Flag : Stack Pointer Interrupt control bits area Register flag area RAM address $000 $001 $002 $003 IM0 (INT 0 interrupt mask) IF0 (INT0 interrupt request flag) RSP (Reset stack pointer) IE (Interrupt enable flag) IMTA (Timer A interrupt mask) IFTA (Timer A interrupt request flag) IM1 (INT1 interrupt mask) IF1 (INT1 interrupt request flag) IMTC (Timer C interrupt mask) IFTC (Timer C interrupt request flag) Not used Not used IMS1 (Serial 1 interrupt mask) IFS1 (Serial 1 interrupt request flag) IMTD (Timer D interrupt mask) IFTD (Timer D interrupt request flag) Bit 3 Bit 2 Bit 1 Bit 0 RAM address $020 $021 $022 $023 Bit 3 Bit 2 Bit 1 Bit 0 DTON (DTON flag) Not used Not used WDON (Watchdog on flag) LSON (Low speed on flag) RAME (RAM enable flag) ICEF (Input capture error flag) ICSF (Input capture status flag) IM3 (INT 3 interrupt mask) IF3 (INT3 interrupt request flag) IM2 (INT2 interrupt mask) IF2 (INT2 interrupt request flag) Not used Not used IM4 (INT4 interrupt mask) IF4 (INT4 interrupt request flag) Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

Not executed in active mode Used in subactive mode Allowed Allowed Not executed Not executed Not executed Allowed Allowed Not executed Allowed Not executed Allowed Inhibited Inhibited Allowed Inhibited REM/REMD TM/TMD Bits in the interrupt control bits area and register flag area can be set and reset by the SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not affected by any other instructions. The following restrictions apply to individual bits. Note:WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

$000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F PMRA SM1A SR1L SR1U TMA MIS TMC1 TRCL/TWCL TRCU/TWCU TMD1 TRDL/TWDL TRDU/TWDU TMC2 TMD2 CDR CER TGM TGC PMRB PMRC ESR1 ESR2 SM1B SSR1 SSR2 DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR6 DCR7 DCR8 DCR9 DCRA V Interrupt control bits area 2/SI1 R4 3/SO 1 R4 1/SCK1 Serial data register 1 (lower) Serial data register 1 (upper) Serial transfer clock speed selection 1 Clock source setting (timer A) MOS pull-up/pull-down controlR4 3/SO1 PMOS control Timer C register (lower) Timer C register (upper) Bit 0 Port R03DCR Port R13DCR Port R23DCR Port R33DCR Port R02DCR Port R12DCR Port R22DCR Port R32DCR Port R01DCR Port R11DCR Port R21DCR Port R31DCR Port R00DCR Port R10DCR Port R20DCR Port R30DCR Clock source setting (timer C) Timer A/time base Interrupt frame period selection Reload on/off Reload on/off Clock source setting (timer D) Timer D register (lower) Timer D register (upper) Input capture selection Timer C output mode setting Timer D output mode setting COMP 0 comparison resultCOMP 1 comparison result Register flag area R0 3/INT4 D 13/INT0 R0 2/INT3 D 12/STOPC R0 1/INT2 R4 0/EVND R0 0/INT1 INT2 detection edge selectionINT3 detection edge selection INT4 detection edge selectionEVND detection edge selection *2*1 SO1 idle High/Low settingSerial clock selection Port D3DCR Port D11DCR Port D2DCR Port D10DCR Port D1DCR Port D5DCR Port D0DCR Port D4DCR Port D9DCR Port R43DCR Port R63DCR Port R73DCR Port R42DCR Port R62DCR Port R72DCR Port R41DCR Port R61DCR Port R71DCR Port R40DCR Port R60DCR Port R70DCR Port R83DCR Port R8 2DCR Port R8 1DCR Port R8 0DCR Port R93DCR Port R9 2DCR Port R9 1DCR Port R9 0DCR Port RA1DCR Port RA 0DCR Bank setting : Not used *1: 32kHz oscillation stop setting *2: 32kHz frequency division ratio switching TONER output frequencyTONEC output frequency TONEC output Comparator operation selection Comparator selection TONER output DTMF enable DTMF speed setting OSC frequency division ratio switchingDTMF speed setting Figure 5 Special Function Register Area

Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. (b) Stack area(a) Memory registers PC 13 to PC0 ST CA : Program counter : Status flag : Carry flag $3C0 $3FF Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 PC PC7 PC4 PC0 PC12 PC8 PC5 PC1 PC13 PC9 PC6 PC2 ST PC10 CA PC3 Bit 3 Bit 2 Bit 1 Bit 0 $3FC $3FD $3FE $3FF RAM address MR MR MR MR MR MR MR MR MR MR MR MR MR MR MR MR (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

Data Area ($090–$2EF): 464 digits from $090 to $25F have two banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $026 to $2EF is accessed without setting the bank register. Bit Initial value Read/Write Bit name Not used Not used R/W Not used Bank area selection Bank 0 is selected Bank 1 is selected Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected. Bank register (V: $03F) Figure 7 Bank Register (V) Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below. (B) (A) (W) (X) (Y) (SPX) (SPY) (CA) (ST) (PC) (SP)11 11 Accumulator B register W register X register Y register SPX register SPY register Carry Status Program counter Initial value: $0000, R/W not possible Stack pointer Initial value: $3FF, R/W not possible Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: 1, R/W not possible Figure 8 Registers and Flags Accumulator (A) and B Register (B): A and B are 4-bit registers, and are used to hold the results of ALU (arithmetic and logical unit) operations and to transfer data between memory, I/O ports, and other registers.

W Register (W), X Register (X), and Y Register (Y): W is a 2-bit register and X and Y are 4-bit registers. These registers are used in RAM register indirect addressing. The Y register is also used in D port addressing. SPX Register (SPX) and SPY Register (SPY): The SPX and SPY registers are 4-bit registers used to supplement the X and Y registers. Carry Flag (CA): CA is a 1-bit flag that stores ALU overflow generated by an arithmetic operation. CA is set to 1 when an overflow is generated, and is cleared to 0 after operations in which no overflow occurred. CA is also affected by the carry set/carry clear instructions (SEC and REC), and by the rotate with carry instructions (ROTL and ROTR). During interrupt handling, CA is saved on the stack, and is restored from the stack by the RTNI instruction. (but is not affected by the RTN instruction) Status Flag (ST): ST is a 1-bit flag that stores the results of arithmetic instructions, compare instructions, and bit test instructions, and is used as the branch condition for the BR, BRL, CAL, and CALL conditional branch instructions. The contents of the ST flag are held until the next arithmetic, compare, bit test, or conditional branch instruction is executed. After the execution of a conditional branch instruction, the value of ST is set to 1 without regard to the condition. During interrupt handling, ST is saved on the stack, and is restored from the stack by the RTNI instruction. (but is not affected by the RTN instruction) Program Counter (PC): The PC is a 14-bit counter that indicates the ROM address of the next instruction the CPU will execute. Stack Pointer (SP): The SP is a 10-bit register that indicates the RAM address of the next stack frame in the stack area. The SP is initialized to $3FF by a reset. The SP is decremented by 4 by a subroutine call or by interrupt handling, and is incremented by 4 when the saved data has been restored by a return instruction. The upper 4 bits of the SP are fixed at 1111; the maximum number of stack levels is thus 16. In addition to the reset method described above, the SP can also be initialized to $3FF by clearing the reset stack pointer (RSP) in the interrupt control bits area with a RAM bit manipulation instruction, i.e., REM or REMD.

The MCU can be reset by setting the RESET pin high or by setting the STOPC pin low*. When power is first applied, or when clearing subactive mode, watch mode, or stop mode, the RESET input must be held for at least t RC to assure that the oscillation stabilization time (tRC ) condition is fulfilled. Similarly, the STOPC pin input must held for at least tRC when clearing stop mode with a STOPC pin input to assure that the oscillator stabilizes. In all other cases, the MCU is reset by a RESET input that is held for at least two instruction execution cycles. Table 1 lists the section of the MCU that are initialized by a reset and the initial values. Note: * The STOPC pin reset is only effective in stop mode.

Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt Interrupt enable flag (IE) 0 Inhibits all interrupts flags/mask Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests I/O Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0) 0000 Turns output buffer off (to high impedance) Data control register (DCD1) --00 Data control register (DCD2) 000- Data control register (DCR0–DCR4, DCR6–DCR9) 0000 Data control register (DCRA) --00 Port mode register A (PMRA) --00 Refer to description of port mode register A Port mode register B (PMRB) 0000 Refer to description of R port Port mode register C bits 3, 1, 0 (PMRC3, PMRC1, PMRC0) 00- Refer to description of port mode register C Detection Edge select registers 1 and 2 (ESR1, 2) 0000 Refer to description of interrupts Timer/ counters, serial interface Timer mode register A (TMA) 0000 Refer to description of timer mode register A section Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1 Timer mode register C2 (TMC2) -000 Refer to description of timer mode register C2 Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1 Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2 Serial mode register 1A (SM1A) 0000 Refer to description of serial mode register Serial mode register 1B (SM1B) --X0 Refer to description of serial mode register Prescaler S (PSS) $000 Refer to description of prescalers Prescaler W (PSW) $00 Refer to description of prescalers Timer counter A (TCA) $00 Refer to description of timer A Timer counter C (TCC) $00 Refer to description of timer C Timer counter D (TCD) $00 Refer to description of timer D

Item Abbr. Initial Value Contents Timer/ counters, serial interface Timer write register C (TWCU, L) $X0 Refer to description of timer write register C Timer write register D (TWDU, L) $X0 Refer to description of timer write register D Serial data register 1 (SR1U, L) $XX Refer to description of serial data register 1 Octal counter (OC1) 000 Refer to description of serial interface DTMF Tone generator mode register (TGM) 0000 Refer to description of tone generator mode register Tone generator control register (TGC) 000 - Refer to description of tone generator control register Comparator Compare data register (CDR) --XX Refer to description of compare data register Compare enable register (CER) 0-00 Refer to description of compare enable register Bit registers Low speed on flag (LSON) 0 Refer to description of operating modes Watchdog timer on flag (WDON) 0 Refer to description of timer C Direct transfer on flag (DTON) 0 Refer to description of operating modes Input capture status flag (ICSF) 0 Refer to description of timer D Input capture error flag (ICEF) 0 Refer to description of timer D Others Miscellaneous register (MIS) 0000 Refer to description of operating modes and pull-up and pull-down MOS transistor control. System clock select register 1 bits 2 to 0 (SSR12 –SSR10)

000 Refer to description of internal oscillator circuit

and system clock select register 1 and 2 System clock select register 2 (SSR2) 0000 Refer to description of internal oscillator circuit and system clock select register 1 and 2 Bank register (V) - - -0 Refer to description of RAM memory map Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. – indicates that the bit does not exist. Item Abbr. Status After Cancel-lation of Stop Mode by STOPC Input Status After all Other Types of Reset Carry flag (CA) Pre-stop-mode values are not guaranteed; values must be initialized by program Pre-MCU-reset values are not guaranteed; values must be initialized by program Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) RAM Pre-stop-mode values are retained RAM enable flag (RAME) 1 0 Port mode register C bit 2 (PMRC2) Pre-stop-mode values are retained System clock select register 1 bit 3 (SSR13)

(timers A, C, and D), serial interface (Serial 1). source, and an interrupt enable flag (IE) controls the entire interrupt process. request that has occurred must be checked at the beginning of interrupt processing. reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. (IE) and the IF to 0 and the interrupt mask (IM) to 1. figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The interrupt program, and reset the IF by a software instruction within the interrupt program. Note: * The STOPC interrupt request is valid only in stop mode.

$000, 2 $000, 3 Priority controller$001, 0 $001, 1 $001, 2 $001, 3 $002, 2 $002, 3 $003, 0 $003, 1 $003, 2 $003, 3 INT0 interrupt INT1 interrupt Timer C interrupt Timer D interrupt Serial 1 interrupt Timer A interrupt Interrupt request IF0 IM0 IF1 IM1 IFTA IMTA IFTC IMTC IFTD IMTD $000, 0 IE $022, 0 $022, 1 $022, 2 $022, 3 $023, 0 $023, 1 INT2 interrupt INT3 interrupt INT4 interrupt IF2 IM2 IF3 IM3 IF4 IM4 Vector address IFS1 IMS1 Figure 9 Interrupt Control Circuit

Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Cuntrol Bit INT0 INT1 Timer A INT 2 Timer C or INT3 Timer D or INT

4 Serial 1

IF0 . IM0 1000 0 0 0 IF1 . IM1 * 100 0 0 0 IFTA . IMTA 10 0 0 0 IF2 . IM2 * 1000 IFTC . IMTC + IF3 . IM3 **** 100 IFTD . IMTD + IF4 . IM4 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1234 56 Instruction execution IE reset Interrupt acceptance Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Vector address generation Note: * Stacking The stack is accessed and the IE reset after the instruction is executed, even if it is a 2-cycle instruction. Figure 10 Interrupt Sequence

RESET = "1"? Interrupt request? MCU reset Execute instruction IE = 1? Accept interrupt Yes INT0 interrupt? Yes INT1 interrupt? Yes Timer A interrupt? Yes INT2 interrupt? Yes Yes No No No No No No IE 0 Stack (PC) Stack (CA) Stack (ST) PC (PC)+1 PC $0002 PC $0004 PC $0006 PC $0008 PC $000A PC $000C PC $000E Timer C or INT3 interrupt? Timer D or INT4 interrupt? (Serial 1 interrupt) Figure 11 Interrupt Processing Flowchart

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled

0 Disabled

1 Enabled

External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling edge of signals input to INT0 and INT1, and IF2–IF4 are set at the rising or falling edge of signals input to INT 2–INT 4, as listed in table 5. The INT2–INT 4 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Bit Initial value Read/Write Bit name W ESR13 W ESR12 W ESR10 W ESR11 Detection edge selection register 1 (ESR1: $026) ESR11 ESR10 INT 2 detection edge No detection Falling-edge detection Rising-edge detection Falling/Rising-edge detection ESR13 ESR12 INT 3 detection edge No detection Falling-edge detection Rising-edge detection Falling/Rising-edge detection Figure 12 Detection Edge Selection Register 1 (ESR1)

W ESR23 W ESR22 W ESR20 W ESR21 Detection edge selection register 2 (ESR2: $027) ESR21 ESR20 INT 4 detection edge No detection Falling-edge detection Rising-edge detection Falling/Rising-edge detection ESR23 ESR22 EVND detection edge No detection Falling-edge detection Rising-edge detection Falling/Rising-edge detection Figure 13 Detection Edge Selection Register 2 (ESR2) Table 5 External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023) IF0–IF4 Interrupt Request 0N o

1 Yes

External Interrupt Masks (IM0–IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0–IM4: $000, $001, $022, $023) IM0–IM4 Interrupt Request

0 Enabled

1 Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A, C, D Interrupt Request Flags (IFTA: $001, Bit 2, IFTC: $002, Bit 2, IFTD: $003, Bit 0) Timer A, C, D Interrupt Request Flags (IFTA, IFTC, IFTD) Interrupt Request 0N o Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A, C, D Interrupt Masks (IMTA: $001, Bit 3, IMTC: $002, Bit 3, IMTD: $003, Bit 1) Timer A, C, D Interrupt Masks (IMTA, IMTC, IMTD) Interrupt Request Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 7. Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 8. Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling of signals input to EVND when the input capture function is used, as listed in table 7. Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 8. Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 9. Table 9 Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2) IFS1 Interrupt Request 0N o

Serial 1 Interrupt Mask (IMS1: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial 1 interrupt request flag, as listed in table 10. Table 10 Serial 1 Interrupt Mask (IMS1: $003, Bit 3) IMS1 Interrupt Request

The MCU has five operating modes as shown in table 11. The operations in each mode are listed in table 12. Transitions between operating modes are shown in figure 14. Table 11 Operating Modes and Clock Status Mode Name Active Standby Stop Watch Subactive *2 Activation method RESET cancellation, interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) SBY instruction STOP instruction when TMA3 = 0 STOP instruction when TMA3 = 1 STOP/SBY instruction in subactive mode (except when direct transition is specified) INT 0 or timer A interrupt request from watch mode when LSON = 1 Status System oscillator Operation Operation Stopped Stopped Stopped Subsystem oscillator Operation Operation *1 Operation Operation Cancellation method RESET input, STOP/SBY instruction RESET input, interrupt request RESET input, STOPC input RESET input, INT 0 or timer A interrupt request RESET input, STOP/SBY instruction Notes: 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029). 2. Subactive mode is an optional function; specify it on the function option list.

Table 12 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode *2 CPU Reset Retained Retained Operation RAM Retained Retained Retained Operation Timer A Reset Operation Operation Operation Timer C Reset Stopped Operation Operation Timer D Reset Stopped Operation Operation Serial interface 1 Reset Stopped *1 Operation Operation DTMF Reset Reset Operation Reset Comparator Reset Stopped Stopped Operation I/O Reset (high- impedance) Retained Retained Operation Notes: 1. When a clock is input in external clock mode, transmit/receive operations are performed, but interrupt operations are halted. 2. Subactive mode is a function option, and should be specified in the function option list.

fOSC : fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate Stop f cyc fcyc fOSC : fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate Stop f W fcyc fOSC : fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate f cyc fcyc fcyc fOSC : fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate f cyc fW fcyc fOSC : fX: ø CPU : ø CLK : ø PER : Stop Oscillate f SUB fW fSUB fOSC : fX: øCPU : øCLK : øPER : Stop Stop Stop Stop Stop f OSC : fX: ø CPU : ø CLK : ø PER : Stop Oscillate Stop f W Stop fOSC : fX: ø CPU : ø CLK : ø PER : Stop Oscillate Stop f W Stop Standby mode Stop mode (TMA3 = 0, SSR13 = 1) Watch mode Subactive mode (TMA3 = 1) (TMA3 = 1, LSON = 0) (TMA3 = 1, LSON = 1) SBY Interrupt SBY Interrupt STOP INT0, timer A STOP 1. STOP/SBY (DTON = 1, LSON = 0) 2. STOP/SBY (DTON = 0, LSON = 0) 3. STOP/SBY (DTON = Don’t care, LSON = 1) f OSC : fX: fcyc: fSUB : fW : LSON: DTON: Main oscillation frequency Suboscillation frequency for time-base f OSC /32 (selected by software) fOSC /4, fOSC /8, fOSC /16 or fX/8 or fX/4 (software selectable) f X/8 System clock Clock for time-base Peripheral functions clock Low speed on flag Direct transfer on flag Active mode Notes: ø CPU : ø CLK : ø PER : fOSC : fX: øCPU : øCLK : øPER : Stop Oscillate Stop Stop Stop (TMA3 = 0, SSR13 = 0) RESET1 RESET2 RAME = 0 RAME = 1 INT0, timer A (TMA3 = 0) STOP STOPC STOPC STOP Figure 14 MCU Status Transitions

Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC1 and OSC 2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. (Interrupts, timers, the serial interface, and other peripheral functions continue to operate. The exception is the comparator, which is halted.) The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. Figure 15 shows a flowchart of MCU operation. Stop mode System clock oscillator started MCU reset System clock oscillator started STOPC=0? RAME=1 RAME=0 Interrupts enabled IF0 · IM0=1? IF1 · IM1=1? IFTA · IMTA=1? IF2·IM2 = 1? IFTC·IMTC + IF3·IM3=1? IFTD·IMTD + IF4·IM4=1? IF =1, IM=0, IE =1? No No Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Yes No Yes Only when clearing from standby mode. Note: * Standby mode Watch mode RESET=1? Next instruction execution Next instruction execution IFS1·IMS1=1 RESET=1? Figure 15 MCU Operation Flowchart

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. For the X1 and X2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register 1 (SSR1: $029; operating: SSR13 = 0, stop: SSR3 = 1) (figure 24). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 40). Stop mode is cleared by a RESET or STOPC* input. The RESET or STOPC input must be held for at least the oscillation stabilization time (t RC ) as shown in figure 16. (refer to the "AC Characteristics" section.) In either of these cases, the MCU will start program execution from the program start address (location 0). However, the value of the RAM enable flag (RAME: $021,3) will be different in these cases. In particular, RAME will be set to 0 for a RESET input and will be set to 1 for a STOPC input. Also note that while a RESET input is effective in all MCU modes, STOPC is only effective in stop mode, and is ignored in all other modes. If a program needs to determine if stop mode was cleared by a STOPC input (for example, if the program intends to use the contents of RAM that were stored before stop mode was entered after returning to active mode) the program should test the RAM enable flag with a TEST instruction at the start of the program. Note: * If stop mode is to be cleared by a S T O P C input, applications should set bit 2 of port mode register C (PMRC) to 1 (PMRC2 = 1) before switching to stop mode. /#04 /#14/#18 /#04 /#02 /#07 /#0C/#0D/#0E Stop mode Oscillator Internal clock STOP instruction execution (at least equal to oscillation stabilization time tRC ) tres RESET STOPC Figure 16 Timing of Stop Mode Cancellation Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator, but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or by executing a STOP/SBY instruction while LSON is set to 1 or DTON is cleared to 0 in subactive mode. Watch mode is terminated by a RESET input or a timer-A/INT 0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated, the time required to enter active mode is t RC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC ) for an INT0 interrupt, as shown in figures 17 and 18.

Operation during mode transition is the same as that at standby mode cancellation (figure 15). tRCTT XT t : Interrupt frame period Oscillation stabilization timeRC (During the transition from watch mode to active mode only) Interrupt strobe INT Interrupt request generation Active mode Watch mode Active mode Oscillation stabilization time Note: If the time from the fall of the INT0 signal until the interrrupt is accepted and active mode is entered is designated Tx, then Tx will be in the following range: T + t RC < Tx < 2T + tRC Figure 17 Interrupt Frame

Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions other than the DTMF generation circuit operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. The CPU instruction execution speed can be selected as 244 ms or 122 ms by setting bit 2 (SSR12) of the system clock select register (SSR1: $029). Note that the SSR12 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, f CLK is applied to timer A and the INT0Icircuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame periods (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, the timer-A/INT 0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. Bit Initial value Read/Write Bit name W MIS3 W MIS2 W MIS0 W MIS1 Miscellaneous register (MIS: $00C) MIS1 MIS0 T * 0 0.24414 ms tRC 0.12207 ms 0.24414 ms 7.8125 ms 31.25 ms Oscillation circuit conditions External clock input Ceramic oscillator Crystal oscillator 15.625 ms 62.5 ms Not used Not used — Notes: 1. Values of T and t RC when a 32.768-kHz crystal oscillator is used to pins x1 and x2. The value is applied only when direct transfer operation is used. Buffer control. See figure 37 in the pull-up and pull-down MOS transistor control section MIS3 MIS2 1 * 1 * 2 Figure 18 Miscellaneous Register (MIS)

Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below:

• Set LSON to 0 and DTON to 1 in subactive mode.
• Execute the STOP or SBY instruction.
• The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19). Notes: 1. The DTON flag can be set only in subactive mode. It is always reset in active mode. 2. The transition time (T D ) from subactive mode to active mode: tRC < TD < T + tRC Subactive mode Interrupt strobe Direct transfer completion timing MCU internal processing time Oscillation stabilization time Active mode T T t RC t : T : RC D D STOP/SBY instruction execution (Set LSON = 0, DTON = 1) Interrupt frame period Oscillation stabilization time Direct transition time Figure 19 Direct Transition Timing MCU Operation Sequence: The MCU operates in the sequence shown in figure 20. It is reset by an asynchronous RESET input, regardless of its status. With the IE flag cleared and an interrupt request flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt request flags are cleared or all interrupts are masked.

IF = 1 and IM = 0? Hardware NOP execution ←PC (PC)+1 ←PC (PC)+1 MCU operation cycle Standby/watch mode IF = 1 and IM = 0? Hardware NOP execution Instruction execution Stop mode No Yes IE = 0 Yes No Yes Note: * Refer to figure 15, Flowchart for Exiting Low Power Modes, for IF and IM operation. STOPC = 0? RAME = 1 Reset MCU No No Yes Interrupt service routine Figure 20 MCU Operating (Low-Power Mode Operation) Notes: When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of I NT 0 is shorter than the interrupt frame, I NT 0 is not detected. Also, if the low level period after the falling edge of I NT 0 is shorter than the interrupt frame, I NT 0 is not detected. Edge detection is shown in figure 21. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected.

Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 23. As shown in table 13, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Set bits 0 and 1 (SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22, SSR23) of system clock select register 2 (SSR2: $02A) according to the frequency of the oscillator connected to OSC 1 and OSC 2 (figures 24 and 25). The system clock division ratio can be set with bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2: $02A). The value set in these bits does not become valid until watch mode is entered. Therefore, the system clock must be halted temporarily when changing the division ratio. The system clock division ratio immediately after a reset or when stop mode is cleared can be selected by means of the SEL pin level, division-by-4 being selected when the SEL pin is at Vcc potential, and division-by-32 when at GND potential. Note: If the system clock select register 1 and 2 (SSR1, SSR2: $029, $02A) setting does not match the oscillator frequency, DTMF generation circuit and subsystems using the 32.768-kHz oscillation will malfunction. OSC 2 OSC 1 System clock oscillator Sub- system clock oscillator 1/4, 1/8, 1/16 or division circuit Timing generation circuit System clock selection circuit CPU with ROM, RAM, registers, flags, and I/O Internal Peripheral module interrupts Time base interrupt Time-base clock selection circuit 1/8 or 1/4 division circuit Timing generation circuit Timing generation circuit division circuit fW fSUB tsubcyc LSON TMA3 bit fcyc tcyc fOSC fX tWcyc øCPU øPER øCLK Figure 23 Clock Generation Circuit

W SSR13 W SSR12 W SSR10 W SSR11 System clock select register 1 (SSR1: $029) SSR12 ratio selection f SUB = fX/8 fSUB = fX/4 SSR13 32-kHz oscillation stop Oscillation operates in stop mode Oscillation stops in stop mode 32-kHz oscillation division SSR23 System clock selection 400 kHz 800 kHz

2 MHz

4 MHz

3.58 MHz

8 MHz

7.16 MHz

Note: SSR13 is cleared only by a RESET input. SSR13 will not be cleared by a STOPC input during stop mode, and will retain its value. SSR13 will also not be cleared upon entering stop mode. Figure 24 System Clock Select Register 1 (SSR1) SSR21 SSR20 System clock division ratio selection* Division by 4 Division by 8 Division by 16 Division by 32 System clock select register 2 (SSR2: $02A) SSR23 SSR22 System clock selection*2 Selected from 400 kHz, 800 kHz, 2 MHz, 4 MHz 3.58MHz 8MHz 7.16MHz Notes :*1 The DTMF generation circuit frequencies are not affected by the system clock division ratio setting. See system clock select register 1 (SSR1). Bit Initial value Read/Write Bit name W SSR23 W SSR22 W SSR20 W SSR21 Figure 25 System Clock Select Register 2 (SSR2)

Table 13 Oscillator Circuit Examples Circuit Configuration Circuit Constants External clock operation External oscillator OSC Open OSC 2 Ceramic oscillator (OSC 1, OSC2) OSC C 1 OSC R f Ceramic oscillator GND Ceramic oscillator: CSB400P22 (Murata) CSB400P (Murata) R f = 1 MW – 20% C 1 = C2 = 220 pF – 5% Ceramic oscillator: CSB800J122 (Murata), CSB800J (Murata) R f = 1 MW – 20% C 1 = C2 = 220 pF – 5% Ceramic oscillator: CSA2.00MG (Murata) R f = 1 MW – 20% C 1 = C2 = 30 pF – 20% Ceramic oscillator: CSA4.00MG (Murata) R f = 1 MW – 20% C 1 = C2 = 30 pF – 20% Ceramic oscillator: CSA3.58MG (Murata) R f = 1 MW – 20% C 1 = C2 = 30 pF – 20% Ceramic oscillator: CSA8.00MT (Murata) R f = 1 MW – 20% C 1 = C2 = 30 pF – 20% Crystal oscillator (OSC 1, OSC2) OSC 1 C 1 OSC 2 Crystal oscillator GND L SC R S R f C 0 OSC 1 OSC 2 R f = 1 MW – 20% C 1 = C2 = 10 to 22pF – 20% Crystal oscillator: Equivalent circuit at left C 0 =7pF max R s = 100W max f = 400kHz, 800kHz, 2MHz, 3.58MHz, 4MHz, 7.16MHz, 8MHz

Circuit Configuration Circuit Constants Crystal oscillator (X1, X2) X1 C 1 Crystal oscillator GND L SC R S C 0 X1 X2 Crystal oscillator: 32.768 kHz: MX38T (Nippon Denpa) C 1 = C2 = 20 pF – 20% R S=14 kW C 0=1.5 pF Notes: 1. Circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC 1, OSC2 (X1 and X2 pins), and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 26. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to VCC and leave the X2 pin open. GND GND RESET OSC OSC 1 TEST Figure 26 Typical Layouts of Crystal and Ceramic Oscillator

The MCU has 47 input/output pins (D0 to D5, D9 to D11, R00 to R43 and R60 to RA1) and 5 input pins (D12, D 13, RD0, RD1 and RE0). The features are described below.

• Four pins D0 to D3 are high source current (10 mA maximum) input/output pins.
• Five pins D4, D5, and D9 to D11 are high sink current (15 mA maximum) input/output pins.
• Certain of these input and output pins have shared functions with timers, the serial interface, and other peripheral functions. The D12, D13, R0, R30, R32, R4, RD0, RD1 and RE0 pins are shared function pins. The use of these pins as peripheral function pins takes precedence over their use as the D and R port pins. Pins that are set to function as peripheral function pins are switched automatically between their various functions and between the input and output directions according to their specifications under the peripheral function setting.
• Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software.
• Peripheral function output pins are all CMOS outputs. However, the SO 1 pin and the R43 port pin can be set to function as NMOS open drain outputs by software.
• Since the MCU goes to the reset state internally after a reset and in stop mode, the peripheral function settings for these pins are cleared. Furthermore, since the data control registers (DCD and DCR) are also reset, the input/output pins go to the high-impedance state.
• The D 0 to D3 pin circuits include pull-down MOS transistors, and all the other pin circuits include pull- up MOS transistors. Note that the on/off states of the pull-up and pull-down MOS transistors can be set independently of the setting for use as peripheral function pins. I/O buffer configurations are shown in figures 27 and 28, and I/O pin circuit structures are listed in tables 14 and 15. VCC VCC Pull-up control signal Buffer control signal Output data Input data HLT MIS3 DCD,DCR PDR Input control signal Pull-up MOS Figure 27 I/O Buffer Configuration (with Pull-Up MOS)

Figure 28 I/O Buffer Configuration (with Pull-Down MOS) Table 14 I/O Pin Control by Register Settings (with Pull-Up MOS) MIS3 (bit 3 of MIS) 0 1 DCD, DCR 0 1 0 1 P D R 01010101 CMOS buffer PMOS — — — On — — — On Note: 1. — indicates off status. 2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions. Table 15 I/O Pin Control by Register Settings (with Pull-Down MOS) MIS3 (bit 3 of MIS) 0 1 DCD 0 1 0 1 P D R 01010101 CMOS buffer PMOS — — — On — — — On Pull-down MOS Note: 1. — indicates off status. 2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions.

Table 16 Input/Output Pin Circuit Configurations I/O Pin Type Circuit Configuration Relevant Pins Input/output pins VCC VCC Pull-up control signal Buffer control signal Output data Input data HLT MIS3 DCD,DCR PDR Input control signal D4 , D5 , D9 – D11 R0 0–R0 3 R1 0–R1 3 R2 0–R2 3 R3 0–R3 3 R4 0–R4 2 R6 0–R6 3 R7 0–R7 3 R8 0–R8 3 R9 0–R9 3 RA 0, RA1 VCC Buffer control signal Output data Input data DCD PDR Input control signal Pull-down control signal HLT MIS3 D 0–D 3 Pull-up control signal Buffer control signal Output data Input data HLT MIS3 DCR PDR Input control signal MIS2 VCC VCC R4 3 Input pins Input data Input control signal D 12, D13 RD 0, RD 1, RE 0

Table 16 Input/Output Pin Circuit Configurations (cont) I/O Pin Type Circuit Configuration Relevant Pins Peripheral function Input/output pins VCC VCC Pull-up control signal Output data Input data HLT MIS3 SCK1 SCK 1 SCK1 Output pins Pull-up control signal PMOS control signal Output data HLT MIS3 SO 1 MIS2 VCC VCC SO 1 Pull-up control signal Output data HLT MIS3 TOC,TOD VCC VCC TOC, TOD Input pins Input data HLT MIS3 PDR SI1,INT1,etc. VCC SI1, INT1, INT2, INT3, INT4, EVND Input data INT0, STOPC, RESET INT0, STOPC RESET Note: In a reset and in stop mode, since the I/O control registers are reset, input/output pins go to the high- impedance state and peripheral function selections are cleared.

The D port consists of 9 input/output pins and 2 input-only pins that can be addressed individually on a per- bit basis. The D0 to D3 pins are high source current input/output pins and the D4, D5, and D9 to D11 pins are high sink current input/output pins. The D12 and D13 pins are input-only pins. The D0 to D5 and D9 to D11 pins can be set or reset by the SED/RED and SEDD/REDD instructions. The output data is stored in the port data register for the pin. All the D port pins can be tested using the TD and TDD instructions. The D port data control registers (DCD0 to DCD2: $02C to $02E) are used to turn the D 0 to D5 and D9 to D 11 pin output buffers on and off. The DCD registers are mapped to addresses in the RAM area. (figure 29.) The D12 and D13 pins have shared functions as internal peripheral function pins and the STOPC and INT0 pins. Port mode register C (PMRC: $025) bits 2 and 3 (PMRC2 and PMRC3) are used to switch the functions of these pins. (figure 32.)

W DCD03, W DCD02, W DCD00– W DCD01– DCD0 to DCD2 Data control register (DCD0 to 2: $02C to $02E) (DCR0 to 4, DCR6 to A: $030 to $034, $036 to $03A) DCD23 DCD22 DCD10DCD21 Bit Initial value Read/Write Bit name Note: Other bits are not used. W DCR03– W DCR02– W DCR00– W DCR01– DCR0 to DCR4 DCR6 to DCRA DCR43 DCR42 DCR40DCR41 DCR61– DCR60–DCR62–DCR63– DCRA1 DCRA0DCR92DCR93 All Bits CMOS Buffer Control

0 CMOS buffer Off (high-impedance)

1 CMOS buffer active

Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D

3 D 2 D 1 D 0

DCD1 — — D 5 D 4 DCD2 D 11 D 10 D 9 — DCR0 R0 3 R0 2 R0 1 R0 0 DCR1 R1 3 R1 2 R1 1 R1 0 DCR2 R2 3 R2 2 R2 1 R2 0 DCR3 R3 3 R3 2 R3 1 R3 0 DCR4 R4 3 R4 2 R4 1 R4 0 DCR6 R6 3 R6 2 R6 1 R6 0 DCR7 R7 3 R7 2 R7 1 R7 0 DCR8 R8 3 R8 2 R8 1 R8 0 DCR9 R9 3 R9 2 R9 1 R9 0 DCRA — — RA 1 RA 0 Figure 29 Data Control Registers (DCD, DCR)

The R port consist of 38 input/output pins and 3 input pins that can be addressed in groups of 4 bits. Data can be input using the LAR and LBR instructions, and data can be output using the LRA and LRB instructions. Output data is stored in the port data register for the corresponding pin. The R port data control registers (DCR0 to DCR4 and DCR6 to DCRA: $030 to $034, and $036 to $03A) are used to turn the R port output buffers on and off. The DCR registers are mapped to addresses in the RAM area. (figure 29.) The R0 0 to R04 port pins have shared functions as the external interrupt input pins INT1 to INT4. Port mode register B (PMRB $024) is used to set these pins to their peripheral function usage. (figure 31.) The R40 port pin has a shared function as the EVND peripheral function pin. Port mode register C (PMRC: $025) bit 1 (PMRC1) is used to switch the function of this pin. (figure 32.) The R3 1 and R32 port pins have shared functions as the TOC and TOD peripheral function pins. Timer mode register C2 (TMC2: $014) bits 0 to 2 (TMC20 to TMC22) and timer mode register D2 (TMD2: $015) are used to set these pins to their peripheral function usage. (figures 33 and 34.) The R4 1 to R43 port pins have shared functions as the SCK1, SI1, and SO1 peripheral function pins. Serial mode register 1A (SM1A: $005) bit 3 (SM1A3) and port mode register A (PMRA: $004) bits 0 and 1 (PMRA0 and PMRA1) are used to set these pins to their peripheral function usage. (figures 30 and 35.) The R4 3/SO1 pin can be set to function as an NMOS open drain output with the output buffer off. Miscellaneous register (MIS: $00C) bit 2 (MIS2) is used for this setting. (figure 37.) The RD 0 and RD1 port pins have shared functions as the COMP0 and COMP 1 peripheral function pins. The compare enable register (CER: $018) is used to set these pins to their comparator pin functions. (figure 36.) Bit Initial value Read/Write Bit name Not used Not used W PMRA0 W PMRA1 PMRA0 3/SO1 mode selection R4 3 SO 1 Port mode register A (PMRA: $004) PMRA1 2/SI1 mode selection R4 2 SI1 Figure 30 Port Mode Register A (PMRA)

Pull-up and Pull-down MOS Transistor Control The D4, D5, D9 to D11, and the R port pins have built-in pull-up MOS transistors that can be controlled by software, and the D0 to D3 pins have built-in pull-down MOS transistors that can be controlled by software. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin—enabling on/off control of that pin alone (tables 14, 15 and figure 37). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. Bit Initial value Read/Write Bit name W MIS3 W MIS2 W MIS0 W MIS1 MIS2 CMOS buffer on/off selection for pin R4 3/SO1 Miscellaneous register (MIS: $00C) Active Off Refer to figure 18 in the operation modes section. tRC selection. MIS3 Pull-up/Pull-down MOS transistor control Off Active MIS1 MIS0 Figure 37 Miscellaneous Register (MIS) How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to VCC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 kW . Pins provided with pull-down MOS should be pulled down to GND potential with the built-in pull-down MOS or connected to GND.

The MCU has three timer/counters (A, C, D).

• Timer A: Free-running timer
• Timer C: Multifunction timer
• Timer D: Multifunction timer Timer A is an 8-bit free-running timer. Timers C, D are 8-bit multifunction timers, whose functions are listed in table 18. The operating modes are selected by software. Table 18 Timer Functions Functions Timer A Timer C Timer D Clock Prescaler S Available Available Available source Prescaler W Available — — External event — — Available Timer Free-running Available Available Available functions Time-base Available — — Event counter — — Available Reload — Available Available Watchdog — Available — Input capture — — Available Timer Toggle — Available Available outputs 0 output — Available Available 1 output — Available Available PWM — Available Available Note: — implies not available. Timer A Timer A Functions: Timer A has the following functions.
• Free-running timer
• Clock time-base The block diagram of timer A is shown in figure 39.

1/4 1/232.768-kHz oscillator System clock Prescaler W (PSW) Selector Selector Prescaler S (PSS) Selector Internal data bus Timer A interrupt request flag (IFTA) Clock Overflow Timer counter A (TCA) Timer mode register A (TMA) 2 f 1/2 twcyc f twcyc øPER 128 512 1024 2048 W W Data bus Clock line Signal line Figure 39 Block Diagram of Timer A Timer A Operations Free-running timer operation: The timer A input clock is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $001, 2). Timer A continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. Realtime clock time base operation: Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1. As the prescaler W output is input to timer counter A (TCA), interrupts are generated with accurate timing using the 32.768 kHz crystal oscillator as the basic clock.When timer A is used as the realtime clock time base, prescaler W and timer counter A (TCA) can be reset to $00 by the program. Registers for Timer A Operation Timer A operating modes are set by the following registers. Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode and input clock source as shown in figure 40.

W TMA3 W TMA2 W TMA0 W TMA1 Timer mode register A (TMA: $008) 0 0 PSS PSS PSS PSS PSS PSS PSS PSS PSW PSW PSW PSW Operating mode Timer A mode TMA3 TMA1TMA2 TMA0 Source prescaler 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc Input clock frequency 32tWcyc 16tWcyc 8tWcyc 2tWcyc 1/2tWcyc Time-base mode × : Don’t care Note: 1. t Wcyc = 244.14 µs (when a 32.768-kHz crystal oscillator is used) Timer counter overflow output period (seconds) = input clock period (seconds) × 256. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Not used Reset PSW and TCA Figure 40 Timer Mode Register A (TMA)

Timer C Functions: Timer C has the following functions.

• Free-running/reload timer
• Watchdog timer
• Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 41.

(IFTC) Timer write register C (TWCL) (TWCU) ÷ 2 ÷ 4 ÷ 8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ø PER 4 4 clock Overflow TOC Watchdog on flag (WDON) Watchdog timer control logic System reset signal ÷ 2048 Timer read register CL (TRCL) Timer counter C (TCCL) (TCCU) Timer mode register C1 (TMC1) Data bus Clock line Signal line Timer mode register C2 (TMC2) Timer read register CU (TRCU) Prescaler S (PSS) Selector Free-running/reload control Internal data bus Figure 41 Block Diagram of Timer C

Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C (TWCL: $00E, TWCU: $00F); if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2 ). The timer C interrupt request flag is reset by the program, an MCU reset or a transition to stop mode. For details, see figure 3, Configuration of Interrupt Control Bits and Register Flag Area, and table 1, Initial Values after MCU Reset. Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). With timer C, the R3 1/TOC pin is designated as the TOC pin, and toggle waveform output, low-level output, high-level output, or PWM waveform output can be selected, by timer mode register C2 (TMC2: $014). TOC pin output is initialized to the low level by an MCU reset.

• Toggle output With toggle output, the output level is changed upon input of the next clock pulse after the timer C value reaches $FF. Use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. The output waveform is shown in figure 42.
• Low-level output With low-level output, the output is changed to the low level when timer C overflows. This function should be used when the output is high.
• High-level output With high-level output, the output is changed to the high level when timer C overflows. This function should be used when the output is low.
• PWM output With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 42, according to the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F).

T (N + 1) T 256T T (256 – N) TMC13 = 0 TMC13 = 1 TMD13 = 0 (free-running timer) TMD13 = 1 (reload timer) 256 clock cycles 256 clock cycles Free-running timer Toggle output waveform (timers C and D) PWM output waveform (timers C and D) (256 – N) clock cycles (256 – N) clock cycles Reload timer Notes: T: Counter input clock period The clock input source and division ratio are controlled by timer mode register C1 and timer mode register D1. Value in timer write register C or timer write register D (When N = 255 (= $FF), PWM output is always fixed low.) Figure 42 Timer Output Waveforms

Registers for Timer C Operation By using the following registers, timer C operation modes are selected and the timer C count is read and written.

• Timer mode register C1 (TMC1: $00D)
• Timer mode register C2 (TMC2: $014)
• Timer write register C (TWCL: $00E, TWCU: $00F)
• Timer read register C (TRCL: $00E, TRCU: $00F) Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload timer function, and the prescaler division ratio as shown in figure 43. It is reset to $0 by MCU reset or in stop mode. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C’s initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Bit Initial value Read/Write Bit name W TMC13 W TMC12 W TMC10 W TMC11 Timer mode register C1 (TMC1: $00D) 2048t cyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc TMC12 TMC10TMC11TMC13 Free-running/reload timer selection Free-running timer Reload timer Input clock period Figure 43 Timer Mode Register C1 (TMC1)

R TRCU3 Undefined R TRCU2 Undefined R TRCU0 Undefined R TRCU1 Timer read register C (upper digit) (TRCU: $00F) Figure 48 Timer Read Register C Upper Digit (TRCU) Timer D Timer D Functions: Timer D has the following functions.

• Free-running/reload timer
• External event counter
• Timer output operation (toggle, low-level, high-level, and PWM outputs)
• Input capture timer The block diagram for each operation mode of timer D is shown in figures 49(1) and 49(2).

(TMD1) Timer write register D (TWDL) (TWDU) ÷ 2 ÷ 4 ÷ 8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 øPER 4 4 EVND Data bus Clock line Signal line Edge detection select register 2 (ESR2) Timer D interrupt request flag (IFTD) Timer read register DU (TRDU) (TCDL) (TCDU) Timer mode register D2 (TMD2) Timer output control logic TOD Timer counter D Timer read register DL (TRDL) Prescaler S (PSS) Free-running/reload control Internal data bus Selector clock Overflow Figure 49(1) Block Diagram of Timer D (Free-Running/Reload Timer/Event Counter Modes)

(TMD1) Timer read register D (TRDL) (TRDU) ÷ 2 ÷ 4 ÷ 8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 Input capture timer control ø PER 4 4 EVND Data bus Clock line Signal line Edge detection select register 2 (ESR2) Timer counter D (TCDL) (TCDU) Timer D interrupt request flag (IFTD) Error control logic Input capture error flag (ICEF) Input capture status flag (ICSF) Timer mode register D2 (TMD2) Read signal Prescaler S (PSS) Selector Internal data bus Overflow clock Figure 49(2) Block Diagram of Timer D (Input Capture Timer)

Timer D Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D (TWDL: $011, TWDU: $012); if the free- running timer function is enabled, the timer is initialized to $00 and then incremented again. The timer D interrupt request flag (IFTD: $003, 0) is reset by the program, and by an MCU reset or a transition to stop mode. For details, see figure 3, Configuration of Interrupt Control Bits and Register Flag Areas, and table 1, Initial Values after MCU Reset.
• External event counter operation: When external event input is designated for the input clock by timer mode register D1 (TMD1), timer D operates as an external event counter.In this case, pin R4 0/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation.
• Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle Low-level output Hige-level output PWM output Pin R3 2/TOD is set to TOD. ¾ Toggle output: The operation is basically the same as that of timer-C’s toggle output. ¾ 0 output: The operation is basically the same as that of timer-C’s 0 output. ¾ 1 output: The operation is basically the same as that of timer-C’s 1 output. ¾ PWM output: The operation is basically the same as that of timer-C’s PWM output.

• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 0) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing By selecting the input capture operation, pin R3 2/TOD is set to R32 and timer D is reset to $00. Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 50. Timer mode register D1 (TMD1: $010) is reset to $0 by an MCU reset or in stop mode.
• Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid.
• When selecting the input capture timer operation, select the internal clock as the input clock source. When designating external event input for the input clock, set bit 1 (PMRC1) of port mode register C (PMRC) to 1.

W TMD13 W TMD12 W TMD10 W TMD11 Timer mode register D1 (TMD1: $010) 2048t cyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc TMD12 TMD10TMD11 Input clock period and input clock source EVND (external event input) TMD13 Free-running/reload timer selection Free-running timer Reload timer Figure 50 Timer Mode Register D1 (TMD1)

Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function as shown in figure 56. It is reset to $0 by MCU reset. Port mode register C (PMRC: $025) bits 3 and 1 (PMRC3, PMRC1) are reset to 00 by an MCU reset or in stop mode. Bit 2 (PMRC2) is reset to 0 by an MCU reset, but retains its previous setting in stop mode. Port mode register C (PMRC: $025) PMRC3 D 13/INT0 pin mode selection D 13 INT0 PMRC2 D 12/STOPC pin mode selection D 12 STOPC PMRC1 R4 0/EVND pin mode selection R4 0 EVND Bit Initial value Read/Write Bit name W PMRC3 W PMRC2 Not Used W PMRC1 Figure 56 Port Mode Register C (PMRC)

Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 57. It is reset to $0 by an MCU reset or in stop mode. Bit Initial value Read/Write Bit name W ESR23 W ESR22 W ESR20 W ESR21 Detection edge select register 2 (ESR2: $027) ESR21 ESR20 INT 4 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection ESR23 ESR22 EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection Note: Both falling and rising edges are detected. Figure 57 Detection Edge Select Register 2 (ESR2)

• 8-bit serial data transmission/reception
• Multiple transmit clock sources ¾ External clock ¾ Internal prescaler output clock ¾ System clock
• High/low control in idle states Configuration
• Serial data register 1 (SR1L: $006, SR1U: $007)
• Serial mode register 1 A (SM1A: $005)
• Serial mode register 1 B (SM1B: $028)
• Port mode register A (PMRA: $004)
• Miscellaneous register (MIS: $00C)
• Octal counter (OC1)
• Selector The block diagram of the serial interface is shown in figure 58.

÷32 ÷128 I/O control logic Idle control logic Octal counter (OC1) Serial 1 interrupt request flag (IFS1) Clock Serial data register 1 (SR1L, SR1U) Serial mode register 1A (SM1A) Serial mode register 1B (SM1B) SO 1 SCK1 SI1 System clock ø PER ÷512 ÷2048 Data bus Clock line Signal line Transfer control Prescaler S (PSS) Internal data bus Selector Selector Figure 58 Block Diagram of Serial Interface

Serial Interface Operation Selecting and Changing the Operating Mode: Table 19 lists the serial interface’s operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial mode register 1A (SM1A: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to serial mode register 1A (SM1A: $005). Note that the serial interface is initialized by writing data to serial mode register 1A(SM1A: $005). Refer to the following Serial Mode Register 1A section for details. Pin Setting: The R4 1/SCK1 pin is controlled by writing data to serial mode register 1A (SM1A: $005). The R42/SI1 and R43/SO1 pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the following Registers for Serial Interface section for details. Transmit Clock Source Setting: The transmit clock source is set by writing data to serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). Refer to the following Registers for Serial Interface section for details. Data Setting: Transmit data is set by writing data to the serial data register 1 (SR1L: $006, SR1U: $007). Receive data is obtained by reading the contents of the serial data register 1 (SR1L: $006, SR1U: $007). The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO 1 pin is invalid until the first data is output after MCU reset, or until the High/Low level control in idle states is performed. Table 19 Serial Interface Operating Modes SM1A PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Serial clock continuous output mode

1 Transmit mode

1 Transmit/receive mode

Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and the transfer stops. When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t cyc to 8192tcyc by setting bits 2 to 0 (SM1A2– SM1A0) of serial mode register 1A (SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 20.

Table 20 Serial Transmit Clock (Prescaler Output) SM1B SM1A Bit 0 Bit 2 Bit 1 Bit 0 Transmit Clock Division Ratio Transmit Clock Frequency 0000( ø PER / 2048) ‚ 2 4096t cyc 1( ø PER / 512) ‚ 2 1024t cyc 10( ø PER / 128) ‚ 2 256t cyc 1( ø PER / 32) ‚ 2 64t cyc 100( ø PER / 8) ‚ 2 16t cyc 1( ø PER / 2) ‚ 24 t cyc 1000( ø PER / 2048) ‚ 4 8192t cyc 1( ø PER / 512) ‚ 4 2048t cyc 10( ø PER / 128) ‚ 4 512t cyc 1( ø PER / 32) ‚ 4 128t cyc 100( ø PER / 8) ‚ 4 32t cyc 1( ø PER / 2) ‚ 48 t cyc Operating States: The serial interface has the operating states shown in figure 59 in external clock mode and internal clock mode. STS wait state Transmit clock wait state Transfer state Serial clock continuous output state (internal clock mode only)

• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), the serial interface enters transmit clock wait state.

(Octal counter 1 = 000, transmit clock disabled) Transmit clock wait state (Octal counter 1 = 000) Transfer state (Octal counter 1 = 000) MCU reset00 SM1A write 04 STS instruction01 Transmit clock02 8 transmit clocks STS instruction (IFS1 1) SM1A write (IFS1 1)06 ← External clock mode STS wait state (Octal counter 1 = 000, transmit clock disabled) Transmit clock wait state (Octal counter 1 = 000) Transfer state (Octal counter 1 = 000) SM1A write 14 STS instruction11 Transmit clock12 STS instruction (IFS1 1) ← 8 transmit clocks13 Internal clock mode Continuous clock output state (PMRA 0, 1 = 00) SM1A write Transmit clock17 Note: Refer to the Operating States section for the corresponding encircled numbers. MCU reset10 ←SM1A write (IFS1 1) Figure 59 Serial Interface State Transitions

• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register 1 (SR1L: $006, SR1U: $007), and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register 1A (SM1A: $005) (04, 14) in transmit clock wait state.
• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register 1A (SM1A: $005) (06, 16) initializes the serial interface, and STS wait state is entered.

If the state changes from transfer to another state, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set by the octal counter that is reset to 000.

• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK 1 pin. When bits 1 and 0 (PMRA1, PMRA0) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register 1A (SM1A: $005) is written to in continuous clock output mode (18), STS wait state is entered. High/Low Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state, the output level of the SO 1 pin can be controlled by setting bit 1 (SM1B1) of serial mode register 1B (SM1B: $028) to 0 or 1. The high/low control example is shown in figure 60. Note that the high/low level cannot be controlled in transfer state.

/,/#01/#05 /#09/#0A/#0E /#14/#15 State MCU reset PMRA write SM1A write SM1B write SR1L, SR1U write STS instruction SCK 1 pin (input) SO 1 pin IFS1 Idle Idle Idle Idle STS wait state Transmit clock wait state Transfer state Transmit clock wait state STS wait state Port selection External clock selection Output level control in idle states Dummy write for state transition Output level control in idle states Data write for transmission Undefined LSB MSB Flag reset at transfer completionExternal clock mode State MCU reset PMRA write SM1A write SM1B write SR1L, SR1U write STS instruction SCK 1 pin (output) SO 1 pin IFS1 STS wait state Transfer state Transmit clock wait state STS wait state Port selection Internal clock selection Output level control in idle states Data write for transmission Output level control in idle states Undefined LSB MSB Flag reset at transfer completionInternal clock mode Figure 60 Example of Serial Interface Operation Sequence

Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 61. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial 1 interrupt request flag is reset, and a dummy write is performed to serial mode register 1A (SM1A: $005). The serial interface then returns to the STS wait state, and the serial 1 interrupt request flag (IFS1: $003, 2) is set again. It is therefore possible to detect a serial clock error by testing the serial 1 interrupt request flag after the dummy write to serial mode register 1A.

(IFS1 1) Interrupts inhibited IFS1 0 SM1A write IFS1 = 1? Transmit clock error processing Normal termination Yes No Transmit clock error detection flowchart /#14/#15 Transmit clock error detection procedure State SCK1 pin (input) Transmit clock wait state Transfer state Transfer state Transmit clock wait state Noise Transfer state has been entered by the transmit clock error. When SM1A is written, IFS1 is set. Flag set because octal counter reaches 000 Flag reset at transfer completion SM1A write IFS1 12 345678 Figure 61 Transmit Clock Error Detection

Notes on Use:

• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register 1A (SM1A: $005) again.
• Serial 1 interrupt request flag (IFS1: $003, bit 2) set: If the state is changed from transfer to another by writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag 1 (IFS1: $003, 2) is not set. To set the serial interrupt request flag, serial mode register 1A (SM1A: $005) write or STS instruction execution must be programmed to be executed after confirming that the SCK 1 pin is at 1, that is, after executing the input instruction to port R4. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial Mode Register 1A (SM1A: $005) Serial Mode Register 1B (SM1B: $028) Serial Data Register 1 (SR1L: $006, SR1U: $007) Port Mode Register A (PMRA: $004) Miscellaneous Register (MIS: $00C) Serial Mode Register 1A (SM1A: $005): This register has the following functions (figure 62).
• R4 1/SCK1 pin function selection
• Transfer clock selection
• Prescaler division ratio selection
• Serial interface initialization Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by an MCU reset or when the MCU switches to stop mode. A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock to the serial data register 1 (SR1L: $006, SR1U: $007) and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that.

W SM1A3 W SM1A2 W SM1A0 W SM1A1 Serial mode register 1A (SM1A: $005) SM1A2 SM1A0SM1A1SM1A3 /SCK mode selection R4 1 1SCK Output Output Input Clock source Prescaler division ratio Refer to table 20 SCK Prescaler System clock External clock Figure 62 Serial Mode Register 1A (SM1A) Serial Mode Register 1B (SM1B: $028): This register has the following functions (figure 63).

• Serial clock division ratio selection
• High/low level control in idle states Serial mode register 1B (SM1B: $028) is a 2-bit write-only register. It cannot be written during data transfer. Setting bit 0 (SM1B0) of the serial mode register 1B (SM1B: $028) selects the divisor applied to the prescaler output used for the transfer clock. Only bit 0 (SM1B0) is cleared to 0 by an MCU reset or when the MCU switches to stop mode. Bit 1 (SM1B1) of the serial mode register (SM1B: $028) controls the high/low state of the SO 1 pin during idle. The SO1 pin changes state as soon as the high/low control bit is written. The value of this bit is undefined after a reset or when the MCU enters stop mode.

Miscellaneous Register (MIS: $00C): This register has the following function (figure 68).

• R4 3/SO1 pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by an MCU reset or in stop mode. Bit Initial value Read/Write Bit name Note: * The value is applied only when direct transfer operation is used. W MIS3 W MIS2 W MIS0 W MIS1 Miscellaneous register (MIS: $00C) MIS1 MIS0 t RC 0.12207 ms 0.24414 ms* 7.8125 ms 31.25 ms Not used MIS2 R431/SO PMOS control On Off MIS3 Pull-up/Pull-down MOS control Off On Figure 68 Miscellaneous Register (MIS)

The MCU provides a dual-tone multifrequency (DTMF) generation circuit. Figure 69 shows a block diagram of the DTMF circuit. A DTMF signal consists of two sine waves corresponding to the numbers and symbols on a telephone keypad. DTMF signals are used to access telephone switching equipment. Figure 70 shows the DTMF frequency matrix. The OSC clock (400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz, or 8 MHz) is changed into seven clock signals through the division circuit (1/2, 1/5, 1/9*, 1/10, 1/18*, and 1/20). The DTMF circuit uses one of the seven clock signals, which is selected by the system clock select register 1, 2 (SSR1: $029, SSR2: $02A) depending on the OSC clock frequency. The DTMF circuit has transformed programmable dividers, sine wave counters, and control registers. The DTMF generation circuit is controlled by the following three registers.

1/9* fOSC Tone generator control register (TGC) System clock select register 1 (SSR1) System clock select register 2 (SSR2) 400 kHz* T one generator mode register (TGM)

2 Data bus

1/18* Note: * 397.8 kHz when an fOSC frequency of 3.58 MHz or 7.16 MHz is used. Signal line Selector Figure 69 Block Diagram of DTMF Circuit

SSR23 System clock selection 0 400kHz 800 kHz System clock select register 1 (SSR1: $029) SSR22 SSR11 SSR10

3.58 MHz1 ××

7.16 MHz1 ×

× : Don't care SSR12 32 kHz division ratio switch f SUB =fX/8 fSUB =fX/4 SSR13 32 kHz oscillation stop setting Oscillation continues in stop mode Oscillation stops in stop modeSSR21 System clock division ratio selection*2 Division by 4 Division by 8 Division by 16 Division by 32 System clock select register 2 (SSR2: $02A) SSR20 Bit Initial value Read/Write Bit name W SSR13 *1 W SSR12 W SSR10 W SSR11 Bit Initial value Read/Write Bit name W SSR23 W SSR22 W SSR20 W SSR21 1. SSR13 is cleared to 0 only by RESET input. In the case of STOPC input in stop mode it retains its current value. SSR13 is not reset in stop mode 2. The DTMF generation circuit frequencies are not affected by the system clock division ratio setting. Notes: Figure 73 System Clock Select Register 1 and 2 (SSR1, SSR2)

DTMF Output: The sine waves of the row-group and column-group are output from the DTMF output pins (TONER and TONEC). These are output by a high-precision resistance-ladder type D/A converter. Figure 74 shows the TONE output pin equivalent circuit, and figure 75 shows the output waveform. One output waveform cycle is composed of 32 slots, giving stable output with a low distortion factor. Table 21 shows the deviation of the output frequencies with respect to the standard DTMF signals. Table 21 Frequency Deviation of the MCU from Standard DTMF OSC =400kHz, 800kHz, 2MHz , 4MHz , 8MHz ) Standard DTMF (Hz) MCU (Hz) Deviation from Standard (%) R1 697 694.44 –0.37 R2 770 769.23 –0.10 R3 852 851.06 –0.11 R4 941 938.97 –0.22 C1 1,209 1,212.12 0.26 C2 1,336 1,333.33 –0.20 C3 1,477 1,481.48 0.30 C4 1,633 1,639.34 0.39 Table 22 Frequency Deviation of the MCU from Standard DTMF (fOSC =3.58kHz, 7.16MHz ) Standard DTMF (Hz) MCU (Hz) Deviation from Standard (%) R1 697 690.58 –0.92 R2 770 764.96 –0.65 R3 852 846.33 –0.67 R4 941 933.75 –0.77 C1 1,209 1,205.39 –0.30 C2 1,336 1,325.92 –0.75 C3 1,477 1,473.25 –0.25 C4 1,633 1,630.23 –0.17 Notes: 1. The DTMF signal frequency deviation must be within –1.5%, totaling the values in tables 21 and 22 and the precision of the oscillator used. When an fOSC frequency of 3.58 MHz or 7.16 MHz is used, in particular, the frequency deviation is greater (max - 0.92%) than with an fOSC frequency of 400 kHz, 800 kHz, 2 MHz, 4 MHz, or 8 MHz, and thorough consultation with the oscillator manufacturer is essential before deciding on the oscillator to be used. 2. This frequency deviation does not include the frequency deviation of the oscillator. Also, the ratio of oscillator waveform high-level width and low-level width in this case is 50% : 50%.

The MCU has a built-in comparator that compare an input voltage with the reference voltage (VCref). The comparator block diagram is shown in figure 76. The comparator can operate in active mode and subactive mode. They are halted in other modes. Compare enable register (CER) Compare data register (CDR) COMP 0 COMP 1 VC ref Comparator Selector Internal data bus Figure 76 Comparator Block Diagram Comparator Operation (1) Analog input pin selection is performed by bits 0 and 1 (CER0, CER1) of the compare enable register (CER). Setting bit 3 (CER3) to 1 places the RD0/COMP 0 and RD1/COMP 1 pins in analog input mode and starts comparator operation. While comparator operation is in progress, none of these pins (including pins not used for comparison) can be used as R port pins. (2) The compare result can be read by means of a bit test instruction (TM or TMD) on the compare data register (CDR) bit corresponding to the selected analog input pin.

Registers Used by Comparator

• Compare enable register (CER: $018)
• Compare data register (CDR: $017) Compare enable register (CER: $018): The compare enable register (CER) is a 3-bit write-only register that selects comparator operation and the analog input pin (figure 77). CER is reset by an MCU reset or in stop mode. Analog input pin selection COMP 0 COMP 1 Not Used Compare enable register (CER: $018) CER0 CER1 × : Don't care CER3 Comparator operation selection Comparator operation not selected: Digital input mode RD0/COMP 0 and RD1/COMP 1 pins function as R port pins

1 Comparator operation selected: Analog input mode RD0/COMP 0 and RD1/COMP 1 pins

function as comparator pins Bit Initial value Read/Write Bit name W CER3 Not Used W CER0 W CER1 Figure 77 Compare Enable Register (CER) Compare data register (CDR: $017): The compare data register (CDR) is a 2-bit read-only register that holds the result of the comparison between the analog input pin and the reference voltage (figure 78). When comparator operation is started (CER3 is set to 1), the result of the comparison between the analog input pin selected by the compare enable register (CER) and the reference voltage is read into the corresponding bit of the compare data register (CDR). The value of the other bits in CDR is undetermined. The CDR value is not retained after the comparator operation (when CER3 = 0), and is undetermined except during comparator operation.

Result of comparison between COMP0 pin and reference voltage COMP 0 pin < reference voltage COMP 0 pin > reference voltage Compare data register (CDR: $017) CDR1 Result of comparison between COMP1 pin and reference voltage COMP 1 pin < reference voltage COMP 1 pin > reference voltage Bit Initial value Read/Write Bit name Not Used Not Used Undetermined R CDR0 Undetermined R CDR1 Figure 78 Compare Data Register (CDR)

Microcomputer with Built-in Programmable ROM 1. Precautions for use of ZTAT TM microcomputer with built-in programmable ROM (1) Precautions for writing to programmable ROM built in ZTAT TM microcomputer In the ZTAT TM microcomputer with built-in plastic mold one-time programmable ROM, incomplete electrical connection between the PROM writer and socket adapter causes writing errors and, makes the computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points: (a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it again. (d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing. (f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e). (g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM writer, socket adapter, etc. for defects. (h) If any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) Precautions when new PROM writer, socket adapter or IC is used When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points before starting the writing process. (a) To ensure stable writing operation, check that the V CC of the power supplied to the PROM writer, power source current capacity of VPP , and current consumption at the time of writing to IC are provided with sufficient margin. (b) To prevent breakdown of the IC, check that the power source voltage between GND-VCC and GND- V PP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the pin connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the socket adapter and check the power noise between the GND-V CC and GND-V PP near the IC connecting

terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power sources depending on the noise generated. In case of high frequency noise, insert a capacitor of low inductance. (d) For stable writing and reading operation, insert the IC into the socket adapter and check the input waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent ICs have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. To avoid these problems, inserting a low inductance capacitor between the GND and power source or inserting a damping resistance to the output data terminal is effective. (e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming all ICs inserted into the socket adapter. (f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases due to erroneous writing because of improper connection. Be sure to check the electrical connection between the PROM writer and socket adapter and IC. (g) If any abnormality is noticed while checking a written program, consult our technical staff. 2. Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. PROM mode is set up by setting the TEST, M 0, and M1 terminals to “Low” level and the RESET terminal to “High” level. Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256. Using a socket adapter for specific use of each product, programming is possible with a general-purpose PROM writer. Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to write to a 16kword of built-in PROM with a general-purpose PROM writer, specify 32kbyte address ($0000-$7FFF). An example of PROM memory map is shown in figure 80. Notes: 1. When programming with a PROM writer, set up each ROM size to the address given in table 24. If it is programmed erroneously to an address given in Table 24 or later, check of writing of PROM may become impossible. Particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. Set the data in unused addresses to $FF. 2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. Be sure to check that they are properly set to the writer before starting the writing process.

1. Two levels of program voltages (VPP) are available for the PROM: 12.5 V and 21 V. Our product employs a VPP of 12.5 V. If a voltage of 21 V is applied, permanent breakdown of the product will result. The VPP of 12.5 V is obtained for the PROM writer by setting it according to the Intel 27256 specifications. Writing/verification Programming of the built-in program ROM employs a high speed programming method. With this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. A basic programming flow chart is shown in figure81 and a timing chart in figure82. For precautions for PROM writing procedure, refer to "ZTAT TM Microcomputer On-chip Programmable ROM Characteristics and Usage Notes." Table 23 Selection of Mode Pins Mode CE OE VPP O 0–O 4 Writing “Low” “High” V PP Data input Verification “High” “Low” V PP Data output Prohibition of programming “High” “High” V PP High impedance Table 24 PROM Writer Program Address ROM size Address 8k $0000~$3FFF 12k $0000~$5FFF 16k $0000~$7FFF

Programmable ROM (HD407A4669) The HD407A4669 is a ZTAT TM microcomputer with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description Pin No. MCU Mode PROM Mode Pin No. MCU Mode PROM Mode FP-64A Pin Name I/O Pin Name I/O FP-64A Pin Name I/O Pin Name I/O 1R E 0/VCref I3 3 R 3 3 I/O

2 TEST I GND – 34 R3 2/TOD I/O

3 OSC 1 IV CC –3 5 R 3 1/TOC I/O

4 OSC 2 O3 6 R 4 0/EVND I/O

5 RESET I V CC –3 7 R 4 1/SCK1 I/O

6 X1 I GND – 38 R4 2/SI1 I/O

7 X2 O 39 R4 3/SO1 I/O

8 GND – GND – 40 R6 0 I/O A 1 I

9D 0 I/O CE I4 1 R 6 1 I/O A 2 I

10 D 1 I/O OE I4 2 R 6 2 I/O A 3 I

11 D 2 I/O V CC –4 3 R 6 3 I/O A 4 I

12 D 3 I/O V CC –4 4 R 7 0 I/O O 0 I/O

13 D 4 I/O 45 R7 1 I/O O 1 I/O

14 D 5 I/O 46 R7 2 I/O O 2 I/O

15 D 9 I/O 47 R7 3 I/O O 3 I/O

16 D 10 I/O A 13 I4 8 R 8 0 I/O O 4 I/O

17 D 11 I/O A 14 I4 9 R 8 1 I/O

18 D 12/STOPC IA 9 I5 0 R 8 2 I/O

19 D 13/INT0 IV PP –5 1 R 8 3 I/O

20 R0 0/INT 1 I/O GND – 52 R9 0 I/O O 4 I/O

21 R0 1/INT 2 I/O GND – 53 R9 1 I/O O 3 I/O

22 R0 2/INT 3 I/O 54 R9 2 I/O O 2 I/O

23 R0 3/INT 4 I/O 55 R9 3 I/O O 1 I/O

24 R1 0 I/O A 5 I5 6 R A 0 I/O O 0 I/O

25 R1 1 I/O A 6 I5 7 R A 1 I/O V CC –

26 R1 2 I/O A 7 I 58 SEL I

27 R1 3 I/O A 8 I5 9 V CC –V CC –

28 R2 0 I/O A 0 I 60 TONEC O

29 R2 1 I/O A 10 I 61 TONER O

30 R2 2 I/O A 11 I6 2 V T ref I

31 R2 3 I/O A 12 I 63 RD0/COMP 0 I

32 R3 0 I/O 64 RD1/COMP 1 I

Notes: 1. I/O: I/O pin, I: Input pin, O: Output pin 2. As there are two each of pins O0 to O4, the respective pairs should be shorted. 3. Unused data pins (O5 to O7) on the PROM programmer side should be handled as shown below on the socket side. VCC O 5, O 6, O7 4. Pin A9 should be handled as shown below on the socket side. VCC Programmer side HD407A4669

(Top view) Figure 79 Pin Arrangement in PROM Mode

$0000 Vector address Zero-page subroutine (64 words) Pattern (4,096 words) Program (16,384 words) $0001 $001F $0080 $007F $2000 $1FFF $0020 $7FFF Bit 4 Bit 8 Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 9 Upper three bits are not to be used (fill them with 111) Upper 5 bits Lower 5 bits $0000 $000F $0010 $003F $0040 $3FFF $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F JMPL instruction (jump to RESET, STOPC routine) JMPL instruction (jump to INT0 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to INT2 routine) JMPL instruction (jump to INT1 routine) JMPL instruction (jump to timer C, INT3 routine) JMPL instruction (jump to timer D, INT4 routine) JMPL instruction (jump to serial 1 routine) $0FFF $1000 11 1 11 1 Figure 80 Memory Map in PROM Mode

Verification OK? Set write/verify modes V = 12.5± 0.3 V V = 6.0± 0.25 V, PPCC Address = 0 n = 0 n + 1 n→ Program t =1 ms± 5%PW Program t = 3n msOPW Last address? n < 25? Yes No No No Address + 1 Address→ Yes Set read mode V = 5.0± 0.5 V, V = V± 0.6 VCC PP CC Read all addresses End Reject No Yes Yes Figure 81 Flowchart of High-Speed Programming

Programming Electrical Characteristics DC Characteristics (VCC = 6.0 V – 0.25 V, VPP = 12.5 V – 0.3 V, GND = 0V, Ta = 25°C – 5°C, unless otherwise specified) Item Pin(s) Symbol Min Typ Max Unit Test Condition Input high voltage level O 0–O 4, A0–A14, OE, CE VIH 2.2 — V CC + 0.3 V Input low voltage level O 0–O 4, A0–A14, OE, CE VIL –0.3 — 0.8 V Output high voltage level O 0–O 4 VOH 2.4 — — V I OH = –200 mA Output low voltage level O 0–O 4 VOL — — 0.4 V I OL = 1.6 mA Input leakage current O 0–O 4, A0–A14, OE, CE ô IILô —— 2 mAV in = 5.25 V/0.5 V VCC current I CC — — 30 mA VPP current I PP — — 40 mA AC Characteristics (VCC = 6.0 V – 0.25 V, VPP = 12.5 V – 0.3 V, GND = 0V, Ta = 25°C – 5°C, unless otherwise specified) Item Symbol Min Typ Max Unit Test Condition Address setup time t AS 2— — ms See figure 82 OE setup time t OES 2— — ms Data setup time t DS 2— — ms Address hold time t AH 0— — ms Data hold time t DH 2— — ms Data output disable time t DF — — 130 ns VPP setup time t VPS 2— — ms Program pulse width t PW 0.95 1.0 1.05 ms CE pulse width during overprogramming tOPW 2.85 — 78.75 ms VCC setup time t VCS 2— — ms Data output delay time t OE 0 — 500 ns Note: Input pulse level: 0.8 V to 2.2 V Input rise/fall time: £ 20 ns Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V

Figure 82 PROM Write/Verify Timing

Microcomputer On-Chip Programmable ROM Characteristics and Useage Notes Principles of Programming/Erasure: A memory cell in a ZTAT TM microcomputer is the same as an EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an SiO 2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0. The charge in a memory cell may decrease with time. This decrease is usually due to one of the following causes:

• Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure principle.
• Heat excites trapped electrons, allowing them to escape.
• High voltages between the control gate and drain may erase electrons. If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However, electron erasure does not often occur because defective devices are detected and removed at the testing stage. Control gate Floating gate Drain SiO2 Source NN++ Control gate Floating gate Drain SiO2 Source NN++ Erasure (1)Write (0) Figure 83 Cross-Sections of a PROM Cell PROM Programming: PROM memory cells must be programmed under specific voltage and timing conditions. The higher the programming voltage VPP and the longer the programming pulse tPW is applied, the more electrons are injected into the floating gates. However, if VPP exceeds specifications, the pn junctions may be permanently damaged. Pay particular attention to overshooting in the PROM programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. The ZTAT TM microcomputer is electrically connected to the PROM programmer by a socket adapter. Therefore, note the following points:

• Check that the socket adapter is firmly mounted on the PROM programmer.
• Do not touch the socket adapter or the LSI during the programming. Touching them may affect the quality of the contacts, which will cause programming errors. PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure section.) ZTAT TM microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but Hitachi recommends that each device be exposed to 150°C at one atmosphere after it is programmed, to ensure its best performance. The recommended screening procedure is shown in figure 84. Note: Exposure time is measured from when the temperature in the heater reaches 150°C. Write the program data and verify the values written Expose to high temperature, without power 150°C – 10°C, 48 h+8 h 0 h– Program read check V = 4.5 V or 5.5 VCC Figure 84 Recommended Screening Procedure Note: If programming errors occur continuously during PROM programming, suspend programming and check for problems in the PROM programmer or socket adapter, using a windowed-package programming or after high-temperature exposure, please inform Hitachi. Write rate: A write rate of 95% or above is guaranteed.

The MCU has three RAM addressing modes, as shown in figure 85 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. For $090 to $25F, a bank setting must be made in the bank register (V: $03F). Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. AP 9 AP 0 W 1 Y0 W register X register Y register RAM address Register Indirect Addressing AP 9 AP 0RAM address Direct Addressing d 9 d0 2nd word of Instruction Opcode 1st word of Instruction AP 9 AP 0RAM address Memory Register Addressing m 3Opcode Instruction 000100 AP 8 AP 7 AP AP 5 AP 46 AP 3 AP 2 AP 1 AP AP AP AP AP AP AP AP87654321 d 8 d7 d6 d 5 d4 d3 d2 d1 AP 8 AP 7 AP 6 AP 5 AP 4 AP 3 AP 2 AP 1 W 0 X3 X2 X1 X0 Y3 Y2 Y1 m 2 m 1 m 0 Figure 85 RAM Addressing Modes

ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 86 and described below. d9 d 8 d7 d6 d 5 d4 d3 d2 d1 d0 2nd word of instruction Opcode 1st word of instruction [JMPL] [BRL] [CALL] PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0PCPCPCPC 10111213Program counter Direct Addressing Zero Page Addressing d5 d 4 d3 d2 d 1 d 0 Instruction [CAL] Opcode PC 98 PC 76 PC 54 PC 3 PC 1 PC 0PCPC 10111213Program counter 00000000 PCPC PC PC PC PC 2 B 1 B 0 A 3 A 2 A 1 A 0 Accumulator Program counter Table Data Addressing PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0PCPCPC 10111213 B 2B 3 B register p3 p0[TBR] Instruction Opcode p2 p1 PC Opcode b7 b6 b 5 b4 b3 b2 b1 b0 Instruction PC 90PCPCPC 111213Program counter Current Page Addressing [BR] PC 10 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PCPC 8 PC p0p1p2p3 Figure 86 ROM Addressing Modes

Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13–PC 0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC 7–PC 0) with eight-bit immediate data. A branch by a BR instruction located at a page boundary differs from other cases: see figure 88. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000– $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC 5–PC 0), and 0s are placed in the eight high- order bits (PC13–PC 6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 88. If bit 8 of the ROM data is 1, the lower eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, the lower eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. Branch destination of a BR instruction on a page boundary: When a BR instruction is on a page boundary (256n + 255), the program counter will advance to the next page because of the hardware architecture. Therefore, when using a BR instruction on a page boundary, the branch destination should be set in the next page (see figure 88). HMCS400 Series cross assemblers are provided with an automatic paging function that automatically turns the ROM page, irrespective of the model.

The MCU has 101 instructions, classified into the following 10 groups:

• Immediate instructions
• Register-to-register instructions
• RAM addressing instructions
• RAM register instructions
• Arithmetic instructions
• Compare instructions
• RAM bit manipulation instructions
• ROM addressing instructions
• Input/output instructions
• Control instructions The functions of these instructions are listed in tables 25 to 34, and an opcode map is shown in table 35. Table 25 Immediate Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Load A from immediate LAI i 100011i 3 i2 i1 i0 i fi A 1/1 Load B from immediate LBI i 100000i 3 i2 i1 i0 i fi B 1/1 Load memory from immediate LMID i,d 011010i 3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i fi M 2/2 Load memory from immediate, increment Y LMIIY i 101001i 3 i2 i1 i0 i fi M, Y + 1 fi Y NZ 1/1

Table 26 Register-Register Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Load A from B LAB 0001001000 B fi A 1/1 Load B from A LBA 0011001000 A fi B 1/1 Load A from W LAW 0100000000 0000000000 W fi A 2/2 * Load A from Y LAY 0010101111 Y fi A 1/1 Load A from SPX LASPX 0001101000 SPX fi A 1/1 Load A from SPY LASPY 0001011000 SPY fi A 1/1 Load A from MR LAMR m 100111m 3 m 2 m 1 m 0 MR (m) fi A 1/1 Exchange MR and A XMRA m 101111m 3 m 2 m 1 m 0 MR (m) « A 1/1 Note: * The assembler automatically provides an operand for the second word of the LAW instruction. Table 27 RAM Address Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Load W from immediate LWI i 00111100i 1 i0 i fi W 1/1 Load X from immediate LXI i 100010i 3 i2 i1 i0 i fi X 1/1 Load Y from immediate LYI i 100001i 3 i2 i1 i0 i fi Y 1/1 Load W from A LWA 0100010000 0000000000 A fi W 2/2 * Load X from A LXA 0011101000 A fi X 1/1 Load Y from A LYA 0011011000 A fi Y 1/1 Increment Y IY 0001011100 Y + 1 fi Y NZ 1/1 Decrement Y DY 0011011111 Y – 1 fi Y NB 1/1 Add A to Y AYY 0001010100 Y + A fi Y OVF 1/1 Subtract A from Y SYY 0011010100 Y – A fi Y NB 1/1 Exchange X and SPX XSPX 0000000001 X « SPX 1/1 Exchange Y and SPY XSPY 0000000010 Y « SPY 1/1 Exchange X and SPX, Y and SPY XSPXY 0000000011 X « SPX,Y « SPY 1/1 Note: * The assembler automatically provides an operand for the second word of the LWA instruction.

Table 28 RAM Register Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Load A from memory LAM(XY) 00100100yx M fi A (X « SPX, Y « SPY) Load A from memory LAMD d 0110010000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M fi A 2/2 Load B from memory LBM(XY) 00010000yx M fi B (X « SPX, Y « SPY) Load memory from A LMA(XY) 00100101yx A fi M (X « SPX, Y « SPY) Load memory from A LMAD d 0110010100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A fi M 2/2 Load memory from A, increment Y LMAIY(X) 000101000x A fi M, Y + 1 fi Y (X « SPX) NZ 1/1 Load memory from A, decrement Y LMADY(X) 001101000x A fi M, Y – 1 fi Y (X « SPX) NB 1/1 Exchange memory and A XMA(XY) 00100000yx M « A (X « SPX, Y « SPY) Exchange memory and A XMAD d 0110000000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M « A 2/2 Exchange memory and B XMB(XY) 00110000yx M « B (X « SPX, Y « SPY) Note: The meanings of (XY) and (X) are as follows: Each instruction marked with (XY) has 4 mnemonics, each with different object codes. For example, different values of x and y of the opcode of the LAM(XY) instruction are given below. Mnemonic y x Function LAM 0 0 None LAMX 0 1 X « SPX LAMY 1 0 Y « SPY LAMXY 1 1 X « SPX, Y « SPY Each instruction marked with (X) has 2 mnemonics, each with different object codes. For example, different values of x of the opcode of the LMAIY(X) instruction are given below. Mnemonic x Function LMAIY 0 None LMAIYX 1 X « SPX

Table 29 Arithmetic Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Add immediate to A AI i 101000i 3 i2 i1 i0 A + i fi A OVF 1/1 Increment B IB 0001001100 B + 1 fi B NZ 1/1 Decrement B DB 0011001111 B – 1 fi B NB 1/1 Decimal adjust for addition D A A 0010100110 1 / 1 Decimal adjust for subtraction D A S 0010101010 1 / 1 Negate A NEGA 0001100000 A + 1 fi A 1/1 Complement B COMB 0101000000 B fi B 1/1 Rotate right A with carry ROTR 0010100000 1 / 1 Rotate left A with carry ROTL 0010100001 1 / 1 Set carry SEC 0011101111 1 fi CA 1/1 Reset carry REC 0011101100 0 fi CA 1/1 Test carry TC 0001101111 C A 1 / 1 Add A to memory AM 0000001000 M + A fi A OVF 1/1 Add A to memory AMD d 0100001000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M + A fi A OVF 2/2 Add A to memory with carry A M C 0000011000 M + A + C A fi A OVF fi CA OVF 1/1 Add A to memory with carry AMCD d 0100011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M + A + CA fi A OVF fi CA OVF 2/2 Subtract A from memory with carry S M C 0010011000 M – A – CA fi A NB fi CA NB 1/1 Subtract A from memory with carry SMCD d 0110011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M – A – CA fi A NB fi CA NB 2/2 OR A and B OR 0101000100 A ¨ B fi A 1/1 AND memory with A ANM 0010011100 A ˙ M fi A NZ 1/1 AND memory with A ANMD d 0110011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A ˙ M fi A NZ 2/2 OR memory with A ORM 0000001100 A ¨ M fi A NZ 1/1 OR memory with A ORMD d 0100001100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A ¨ M fi A NZ 2/2 EOR memory with A EORM 0000011100 A ¯ M fi A NZ 1/1 EOR memory with A EORMD d 0100011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A ¯ M fi A NZ 2/2

Table 30 Compare Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Immediate not equal to memory INEM i 000010i 3 i2 i1 i0 i „ M NZ 1/1 Immediate not equal to memory INEMD i,d 010010i 3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i „ M NZ 2/2 A not equal to memory ANEM 0000000100 A „ M NZ 1/1 A not equal to memory ANEMD d 0100000100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A „ M NZ 2/2 B not equal to memory BNEM 0001000100 B „ M NZ 1/1 Y not equal to immediate YNEI i 000111i 3 i2 i1 i0 Y „ i NZ 1/1 Immediate less than or equal to memory ILEM i 000011i 3 i2 i1 i0 i £ M NB 1/1 Immediate less than or equal to memory ILEMD i,d 010011i 3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i £ M NB 2/2 A less than or equal to memory ALEM 0000010100 A £ M NB 1/1 A less than or equal to memory ALEMD d 0100010100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 A £ M NB 2/2 B less than or equal to memory BLEM 0011000100 B £ M NB 1/1 A less than or equal to immediate ALEI i 101011i 3 i2 i1 i0 A £ i NB 1/1 Table 31 RAM Bit Manipulation Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Set memory bit SEM n 00100001n 1 n0 1 fi M (n) 1/1 Set memory bit SEMD n,d 01100001n 1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 fi M (n) 2/2 Reset memory bit REM n 00100010n 1 n0 0 fi M (n) 1/1 Reset memory bit REMD n,d 01100010n 1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 fi M (n) 2/2 Test memory bit TM n 00100011n 1 n0 M (n) 1/1 Test memory bit TM n,d 01100011n 1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 M (n) 2/2

Table 32 ROM Address Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Branch on status 1 BR b 1 1 b 7 b6 b5 b4 b3 b2 b1 b0 1 1/1 Long branch on status 1 BRL u 010111p 3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Long jump unconditionally JMPL u 010101p 3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Subroutine jump on status 1 CAL a 0111a 5 a4 a3 a2 a1 a0 1 1/2 Long subroutine jump on status 1 CALL u 010110p 3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2/2 Table branch TBR p 001011p 3 p2 p1 p0 1 1/1 Return from subroutine RTN 0000010000 1 / 3 Return from interrupt RTNI 0000010001 1 fi IE, carry restored ST 1/3 Table 33 Input/Output Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles Set discrete I/O latch SED 0011100100 1 fi D (Y) 1/1 Set discrete I/O latch direct SEDD m 101110m 3 m 2 m 1 m 0 1 fi D (m) 1/1 Reset discrete I/O latch RED 0001100100 0 fi D (Y) 1/1 Reset discrete I/O latch direct REDD m 100110m 3 m 2 m 1 m 0 0 fi D (m) 1/1 Test discrete I/O latch TD 0011100000 D ( Y ) 1 / 1 Test discrete I/O latch direct TDD m 101010m 3 m 2 m 1 m 0 D (m) 1/1 Load A from R-port register LAR m 100101m 3 m 2 m 1 m 0 R (m) fi A 1/1 Load B from R-port register LBR m 100100m 3 m 2 m 1 m 0 R (m) fi B 1/1 Load R-port register from A LRA m 101101m 3 m 2 m 1 m 0 A fi R (m) 1/1 Load R-port register from B LRB m 101100m 3 m 2 m 1 m 0 B fi R (m) 1/1 Pattern generation P p 011011p 3 p2 p1 p0 1/2

Table 34 Control Instructions Operation Mnemonic Operation Code Function Status Words/ Cycles No operation NOP 0000000000 1 / 1 Start serial STS 0101001000 1 / 1 Standby mode/watch mode* S B Y 0101001100 1 / 1 Stop mode/watch mode STOP 0101001101 1 / 1 Note: * Only after a transition from subactive mode.

A B C D E F A B C D E F LBI i(4) LYI i(4) LXI i(4) LAI i(4) LBR m(4) LAR m(4) REDD m(4) LAMR m(4) AI i(4) LMIIY i(4) TDD m(4) ALEI i(4) LRB m(4) LRA m(4) SEDD m(4) XMRA m(4) 1-word/2-cycle instruction 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 0123456789A BC DEF NOP XSPX XSPY XSPXY ANEM AM ORM LBM(XY) BNEM LAB IB LMAIY(X) AYY LASPY IY RTN RTNI ALEM AMC EORM NEGA RED LASPX TC INEM i(4) ILEM i(4) YNEI i(4) XMA(XY) LAM(XY) SEM n(2) LMA(XY) REM n(2) SMC TM n(2) ANM ROTR DAA DAS LAYROTL DB DY SEC LBA LYA RECLXA BLEM SYY SED XMB(XY) LMADY(X) TD LWI i(2) TBR p(4)

A B C D E F A B C D E F 1-word/2-cycle instruction 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 0123456789A BC DEF LAW ANEMD AMD ORMD LWA ALEMD AMCD EORMD COMB OR STS SBY STOP INEMD i(4) ILEMD i(4) JMPL p(4) CALL p(4) BRL p(4) XMAD LAMD SEMD n(2) LMAD REMD n(2) SMCD TMD n(2) ANMD LMID i(4) CAL a(6) BR b(8) P p(4)

Item Symbol Value Unit Notes Supply voltage V CC –0.3 to +7.0 V Programming voltage V PP –0.3 to +14.0 V 1 Pin voltage V T –0.3 to (VCC + 0.3) V Total permissible input current (to chip)å Io 100 mA 2 Total permissible output current (from chip) –å Io 50 mA 3 Maximum input current (to chip) I o 4 mA 4, 5 30 mA 4, 6 Maximum output current (from chip) –I o 4 mA 7, 8 20 mA 7, 9 Operating temperature T opr –20 to +75 °C1 0 Storage temperature T stg –55 to +125 °C1 1 Notes: 1. Applies to D13 (VPP ) of the HD407A4669. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to D 0–D 3, R0–R4 and R6–RA. 6. Applies to D4, D5 and D9–D 11 7. The maximum output current is the maximum current flowing out from VCC to each I/O pin. 8. Applies to D4, D5, D9–D 11, R0–R4 and R6–RA. 9. Applies to D0–D 3. 10. The operating temperature indicates the temperature range in which power can be supplied to the LSI (voltage VCC shown in the electrical characteristics tables can be applied). 11. In the case of chips, the storage specification differs from that of the package products. Please consult your Hitachi sales representative for details. Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected.

Electrical Characteristics

DC Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: V CC = 1.8 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404669: V CC = 1.8 to 5.5 V, GND = 0 V, T a = +75°C; HD407A4669: V CC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Input high voltage VIH RESET, SCK1, SI1, INT0, INT1, INT2, INT3, INT4, STOPC, EVND 0.9VCC —V CC + 0.3 V — OSC 1 VCC – 0.3 — V CC + 0.3 V External clock operation Input low voltage V IL RESET, SCK1, SI1, INT0, INT1, INT2, INT3, INT4, STOPC, EVND –0.3 — 0.10V CC V— OSC 1 –0.3 — 0.3 V External clock operation Output high voltage V OH SCK 1, SO1, TOC, TOD VCC – 0.5 — — V –I OH = 0.3 mA Output low voltage VOL SCK 1, SO1, TOC, TOD — — 0.4 V I OL = 0.4 mA I/O leakage current ‰ II L‰ RESET, SCK1, SI1, INT0, INT1, INT2, INT3, INT4, STOPC, EVND, OSC 1, SO 1, TOC, TOD — — 1.0 mAV in = 0 V to VCC 1 Active mode current dissipation (digital input mode) I CC1 VCC — 2.5 5.0 mA V CC = 5.0 V, fOSC = 4 MHz ICC2 VCC — 0.3 1.0 mA V CC = 3.0 V, fOSC = 800 kHz ICC3 VCC — 5.0 9.0 mA HD40A4668, HD40A46612, HD40A4669, HD407A4669: V CC = 5 V, fOSC = 8 MHz

Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Active mode current dissipation (analog compare mode) I CMP1 VCC — 6.5 9.0 mA V CC = 5V, fOSC = 4MHz 3 ICMP2 VCC — 2.8 3.5 mA V CC = 3V, fOSC = 800kHz ICMP3 VCC — 9.0 13.0 mA HD40A4668, HD40A46612, HD40A4669, HD407A4669: V CC = 5V, fOSC = 8MHz Standby mode current dissipation I SBY1 VCC — 1.0 2.0 mA V CC = 5V, fOSC = 4MHz 4 ISBY2 VCC — 0.1 0.3 mA V CC = 3V, fOSC = 800kHz ISBY3 VCC — 2.0 4.0 mA HD40A4668, HD40A46612, HD40A4669, HD407A4669: V CC = 5V, fOSC = 8MHz Subactive mode current dissipation I SUB VCC —1 8 3 5 mAV CC = 3 V, 32 kHz oscillator used Watch mode current dissipation I WTC VCC — 4 7.5 mAV CC = 3 V, 32 kHz oscillator used Stop mode current dissipation I STOP VCC — 0.5 5 mAV CC = 3 V, no 32 kHz oscillator Stop mode retention voltage V STOP VCC 1.5 — — V No 32 kHz oscillator 6 Comparator input reference voltage range VC ref VC ref 0— V CC —1.2 V Notes: 1. Output buffer current is excluded. 2. Power supply current when the MCU is in the reset state and there are no I/O currents. Test conditions: MCU: Reset Pins: RESET at V CC (VCC – 0.3 V to VCC ) TEST at VCC (VCC – 0.3 V to VCC ) 3. Power supply current when pins RD0 and RD1 are in analog input mode and there are no I/O currents. Test conditions: MCU: DTMF not operating Pins: • RD0/COMP 0: At GND (0 V to 0.3 V)

• RD1/COMP 1: At GND (0 V to 0.3 V)
• RE0/VCref: At GND (0 V to 0.3 V)

1. Power supply current when the on-chip timers are operating and there are no I/O currents. Test conditions: MCU: I/O reset Serial interface stopped DTMF not operating Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC – 0.3 V to VCC ) 5. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at GND (0 V to 0.3 V) TEST at VCC (VCC – 0.3 V to VCC ) D 13 at VCC (VCC – 0.3 V to VCC ) for the HD407A4669 6. The required voltage for RAM data retention.

I/O Characteristics for Standard Pins (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: V CC = 1.8 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404669: V CC = 1.8 to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4669: V CC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Input high voltage VIH D 12, D13, R0 to R4, R6 to RA, RD, RE 0.7VCC —V CC + 0.3 V — Input low voltage V IL D 12, D13, R0 to R4, R6 to RA, RD, RE –0.3 — 0.3V CC V— Output high voltage V OH R0 to R4, R6 to RA VCC – 0.5 — — V –I OH = 0.3 mA Output low voltage VOL R0 to R4, R6 to RA — — 0.4 V I OL = 0.4 mA I/O leakage current ‰ II L‰ D 12, R0 to R4, R6 to RA, RD, RE —— 1 mAV in = 0 V to VCC 1 D 13 —— 1 mA HD404668, HD4046612, HD404669, HCD404669, HD40A4668, HD40A46612, HD40A4669: V in = 0V to VCC —— 1 mA HD407A4669: Vin = VCC – 0.3V to VCC —— 2 0 mA HD407A4669: Vin = 0V to 0.3V Pull-up MOS current –IPU R0 to R4, R6 to RA 10 50 150 mAV CC = 3.0 V, Vin = 0 V Input high voltage V IHA COMP 0, COMP 1 VC ref +0.1 — — V Analog compare mode Input low voltage VILA COMP 0, COMP 1 —— VC ref – 0.1 V Analog compare mode Note: 1. Output buffer current is excluded.

I/O Characteristics for High-Current (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: V CC = 1.8 to 5.5 V, GND = 0 V, T a = –20 °C to +75 °C; HCD404669: V CC = 1.8 to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4669: V CC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Input high voltage VIH D 0 to D5, D9 to D 11 0.7VCC —V CC + 0.3 V — Input low voltage VIL D 0 to D5, D9 to D 11 –0.3 — 0.3V CC V— Output high voltage VOH D 0 to D5, D9 to D 11 VCC – 0.5 — — V –I OH = 0.3 mA D 0 to D3 VCC – 2.0 — — V –I OH = 10 mA VCC = 4.5V to 5.5V Output low voltage VOL D 0 to D5, D9 to D 11 — — 0.4 V I OL = 0.4 mA D 4, D5, D9 to D 11 — — 2.0 V I OL = 15 mA, VCC = 4.5 V to 5.5 V I/O leakage current ‰ I I L‰ D 0 to D5, D9 to D 11 —— 1 mAV in = 0 V to VCC 1 Pull-up MOS current –IPU D 4, D5, D9 to D 11 10 50 150 mAV CC = 3 V, Vin = 0 V Pull-down MOS current I PD D 0 to D3 10 50 150 mAV CC = 3 V, Vin = 3 V Note: 1. Output buffer current is excluded.

DTMF Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: V CC = 1.8 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404669: V CC = 1.8 to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4669: V CC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin Min Typ Max Unit Test Condition Notes Tone output voltage (1) VOR TONER 500 660 — mV r ms VTref – GND = 2.0 V, R L = 100 kW, VCC = 2.2 to 5.0V Tone output voltage (2) VOC TONEC 520 690 — mV r ms VTref – GND = 2.0 V, R L = 100 kW, VCC = 2.2 to 5.0V Tone output distortion %DIS — — 3 7 % Short circuit between TONER and TONEC, R L = 100 kW Tone output ratio dBCR — — 2.5 — dB Short circuit between TONER and TONEC, R L = 100 kW Notes: These characteristics are guaranteed with an operating frequency, fOSC , of 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz, or 8 MHz. 1. See figure 89. 2. See figure 90.

AC Characteristics (HD404668, HD4046612, HD404669, HD40A4668, HD40A46612, HD40A4669: V CC = 1.8 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C; HCD404669: V CC = 1.8 to 5.5 V, GND = 0 V, Ta = +75°C; HD407A4669: V CC = 2.2 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Clock oscillation frequency fOSC OSC 1, OSC2 — 400 — kHz 1 — 800 — kHz 1 — 2 — MHz 1 — 3.58 — MHz 1 — 4 — MHz 1 — 7.16 — MHz HD40A4668, HD40A46612, HD40A4669, HD407A4669: V CC = 4.0V to 5.5V — 8 — MHz X1, X2 — 32.768 — kHz Instruction cycle time tcyc —— 8 — m sf OSC = 4 MHz, division by 32 —4 — m sf OSC = 4 MHz, division by 16 —2 — m sf OSC = 4 MHz, division by 8 —1 — m sf OSC = 4 MHz, division by 4 tsubcyc — — 244.14 — m s 32 kHz oscillator used, division by 8 — 122.07 — m s 32 kHz oscillator used, division by 4 Oscillation stabilization time (ceramic oscillator) t RC OSC 1, OSC2 — — 7.5 ms 4, 5 Oscillation stabilization time (crystal oscillator) tRC OSC 1, OSC2 — — 30 ms 4, 5, 12 X1, X2 — — 2 s T a = –10°C to +60°C External clock high width tCPH OSC 1 1100 — — ns f OSC = 400 kHz 6 550 — — ns f OSC = 800 kHz 215 — — ns f OSC = 2 MHz 115 — — ns f OSC = 3.58 MHz 105 — — ns f OSC = 4 MHz 57.5 — — ns f OSC = 7.16 MHz 6, 11 52.5 — — ns f OSC = 8 MHz

Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes External clock low width tCPL OSC 1 1100 — — ns f OSC = 400 kHz 6 550 — — ns f OSC = 800 kHz 215 — — ns f OSC = 2 MHz 115 — — ns f OSC = 3.58 MHz 105 — — ns f OSC = 4 MHz 57.5 — — ns f OSC = 7.16 MHz 6, 11 52.5 — — ns f OSC = 8 MHz External clock rise time tCPr OSC 1 — — 150 ns f OSC = 400 kHz 6 — — 75 ns f OSC = 800 kHz — — 35 ns f OSC = 2 MHz — — 25 ns f OSC = 3.58 MHz — — 20 ns f OSC = 4 MHz — — 12.5 ns f OSC = 7.16 MHz 6, 11 — — 10 ns f OSC = 8 MHz External clock fall time tCPf OSC 1 — — 150 ns f OSC = 400 kHz 6 — — 75 ns f OSC = 800 kHz — — 35 ns f OSC = 2 MHz — — 25 ns f OSC = 3.58 MHz — — 20 ns f OSC = 4 MHz — — 12.5 ns f OSC = 7.16 MHz 6, 11 — — 10 ns f OSC = 8 MHz INT0–INT4, EVND high widths tI H INT0 to INT4, EVND 2—— tcyc/ tsubcyc INT0–INT4, EVND low widths tI L INT0 to INT4, EVND 2—— tcyc/ tsubcyc RESET high width t RSTH RESET 2 — — t cyc —8 STOPC low width t STPL STOPC 1—— t RC —9 RESET fall time t RSTf RESET — — 20 ms — 8 STOPC rise time t STPr STOPC — — 20 ms — 9 Input capacitance C in All pins except D13 — — 15 pF f = 1 MHz Vin = 0 V, D 13 — — 15 pF HD40A4668, HD40A46612, HD40A4669, HCD404669, HD404668, HD4046612, HD404669: f = 1MHz, V in = 0V — — 40 pF HD407A4669: f = 1MHz, Vin = 0V

Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes Analog comparator stabilization time tCSTB COMP 0 to COMP 1 —— 2t cyc VCC = 2.2 V to 5.5V 10 — — 10 t cyc VCC = 1.8 V to less than 2.2V Notes: 1. Set bits 0 and 1 (SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22, SSR23) of system clock select register 2 (SSR2: $02A) according to the system clock frequency used. 2. Set bits 0 and 1 (SSR20, SSR21) of system clock select register 2 (SSR2: $02A) according to the system clock frequency division ratio used. 3. Set bit 2 (SSR12) of system clock select register 1 (SSR1: $029) according to the subsystem clock frequency division ratio used. 4. The oscillation stabilization time is defined as follows: (1) The time required for the oscillation to settle after V CC has reached the minimum specification value at power-on. (2) The time required for the oscillation to settle after RESET input has gone high when stop mode is cleared. (3) The time required for the oscillation to settle after STOPC input has gone low when stop mode is cleared. To ensure enough time for the oscillation to settle at power-on or when stop mode is cleared, input the RESET or STOPC signal for at least time tRC . The oscillation stabilization time will depend on the circuit constants and stray capacitance. The oscillator should be determined in consultation with the oscillator manufacturer. 5. Set bits 0 and 1 (MIS0, MIS1) in the miscellaneous register (MIS: $00C) according to the oscillation stabilization time of the system oscillator. 6. See figure 91. 7. See figure 92. Unit t cyc applies when the MCU is in standby mode or active mode. Unit tsubcyc applies when the MCU is in watch mode or subactive mode. 8. See figure 93. 9. See figure 94. 10. This is the time required for the analog comparator to settle, ensuring that the correct data is read, after pins RD 0 /COMP 0 and RD1/COMP 1 are set to analog input mode. 11. Applies to the HD40A4668, HD40A46612, HD40A4669, and HD407A4669. The test condition is VCC = 4.0 to 5.5 V. 12. Applies to the HD404668, HD4046612, HD404669, HCD404669, HD40A4668, HD40A46612, and HD40A4669. The test condition is VCC = 2.0 to 5.5 V.

R L = 100 kΩ GND R L = 100 kΩ Figure 89 Tone Output Load Circuit TONEC TONER R L = 100 kΩ GND Figure 90 Distortion and dBCR Load Circuit 1/fCP tCPL tCPftCPr tCPH VCC – 0.3 V 0.3 V OSC 1 Figure 91 External Clock Timing tILtIH0.9 VCC

0.1 VCC

INT0 to INT4, EVND Figure 92 Interrupt Timing

0.9 VCC

tSTPL0.9 VCC 0.1VCC VCC – 0.5 V 0.4 V VCC – 0.5 V (0.9 VCC ) * 0.4 V (0.1 VCC ) * SI1 SO 1 SCK1 Note: * VCC – 0.5 V and 0.4 V are the threshold voltages during serial clock output. 0.9 VCC and 0.1 VCC are the threshold voltages during serial clock input. tSCKr Figure 95 Serial Interface Timing

R L = 2.6 kΩ 1S2074 H or equivalent R = 12 kΩC = 30 pF Test point Figure 96 Timing Load Circuit

Please note the following when ordering HD404668, HD4046612, HD40A4668, or HD40A46612 ROM. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404669, HD40A4669). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base. $0000 $000F $0010 $003F $0040 $1FFF $2000 $3FFF 8-kword ROM versions: HD404668, HD40A4668 Write all-1 data to addresses $2000 to $3FFF. Vector addresses Zero page subroutine area (64 words) Program and pattern area (8,192 words) $0000 $000F $0010 $003F $0040 $2FFF $3000 $3FFF 12-kword ROM versions: HD4046612, HD40A46612 Write all-1 data to addresses $3000 to $3FFF. Vector addresses Zero page subroutine area (64 words) Program and pattern area (12,288 words) Not used Note: Write all-1 data in shaded areas. Not used

HD404668/HD4046612/HD404669/HCD404669/HD40A4668/HD40A46612/HD40A4669 Option List Please check off the appropriate applications and enter the necessary information. Date of order / / Customer Department Name ROM code name LSI number (Hitachi entry) 1. ROM Size Standard operation version: HD404668 8-kword High-speed operation version: HD40A4668 Standard operation version: HD4046612 12-kword High-speed operation version: HD40A46612 Standard operation version: HD404669 16-kword High-speed operation version: HD40A4669 Chip version: HCD404669 2. Optional Functions * With 32-kHz CPU operation, with time-base for clock * Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base for clock Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM Code Data Type Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT TM version). The upper bits and lower bits are mixed together. The upper five bits and lower five bits are The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMs 4. System Oscillator (OSC1 and OSC2) Ceramic oscillator f = MHz Crystal oscillator f = MHz External clock f = MHz 5. Stop Mode 6. Package Used FP-64A Not used Chip Note: The specifications of shipped chips differ from of the package product. Please contact our sales staff for details.

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. Hitachi Asia Pte. Ltd.

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