HC908JB16AD, Addendum to MC68HC908JB16 Technical Data - Data Sheet
Document overview
- Manufacturer or author: Freescale Semiconductor, Inc.
- PDF pages: 8
Technical content
Document Number: HC908JB16AD/D Rev. 1, 03/2010 © Freescale Semiconductor, Inc., 2010. All rights reserved. This addendum provides update and additional information to the MC68HC908JB16 Technical Data, Rev. 1.1 (Freescale document number MC68HC908JB16/D). pertaining to the following:
- MC68HC908JB16 – Update to V REG LVI trip point – 20-pin SOIC package MC68HC908JB12 MC68HC908JB16 This section updates data sheet information and introduces the 20-pin SOIC package for the MC68HC908JB16. These updates apply to the 20-pin SOIC only. V REG LVI Trip Point Page 318, entry for minimum VREG LVI trip point voltage has been updated. From: To: Characteristic Symbol Min Typ Max Unit VREG LVI trip point voltage V LVR 2.0 2.2 2.6 V VREG LVI trip point voltage V LVR 1.9 2.2 2.6 V Addendum to MC68HC908JB16 Technical Data
Output Low Voltage Page 318, entry for maximum VOL has been updated. Figure 1. 20-Pin SOIC Pin Assignment Internal pads are unconnected. PTD0/1 pin: PTD0 and PTD1 internal pads are bonded together to PTD0/1 pin. PTD0/1 has a 45 mA sink capability when configured as an output. Pin direction must be configured such that DDRD0 = DDRD1.
Figure 2. 20-Pin SOIC Mechanical Dimensions (Case No. 751D)
- DIMENSIONING AND TOLERANCING PER
- CONTROLLING DIMENSION: MILLIMETER.
- DIMENSIONS A AND B DO NOT INCLUDE
- MAXIMUM MOLD PROTRUSION 0.150
- DIMENSION D DOES NOT INCLUDE
AT MAXIMUM MATERIAL CONDITION.
MCU Block Diagram Figure 3 shows the structure of the MC68HC908JB12. Memory Map Figure 4 shows the memory map of the MC68HC908JB12. not apply to the MC68HC908JB12. Table 1. Summary of MC68HC908JB12 and MC68HC908JB16 Differences Dual Clock Generator Module Not implemented.
- The pin assignments are identical for both devices; see data sheet.
(2) Pins have integrated pullup device. (3) Pins have software configurable pullup device. (4) Pins are open-drain when configured as output. (6) Pins available on 28-pin package only. (7) On 20-pin package, PTD0 and PTD1 are bonded as a single PTD0/1 pin. Figure 3. MC68HC908JB12 Block Diagram
128 Bytes
384 Bytes
448 Bytes
48 Bytes
Figure 4. MC68HC908JB12 Memory Map
PTE4/D– pins are shown in Table 2. Order Numbers These are MC order numbers for MC68HC908JB12. Table 2. Pullup Control on PTE3/D+ and PTE4/D– Pins 1 0 X 1 Do not set this configuration.
- External interrupt function is also enabled on PTE4/D– pin.
Table 3. MC68HC908JB12 Order Numbers
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