HC646

SN54HC646 TI

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SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Independent Registers for A and B Buses /C0068Multiplexed Real-Time and Stored Data /C0068True Data Paths /C0068High-Current 3-State Outputs Can Drive up to 15 LSTTL Loads /C0068Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

description

The ’HC646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus- management functions that can be performed with the ’HC646. Output-enable (OE ) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either or both registers. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The SN54HC646 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC646 is characterized for operation from –40°C to 85°C. Copyright  1997, Texas Instruments IncorporatedUNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 14 15 16 17 SN54HC646 . . . JT OR W PACKAGE SN74HC646 . . . DW OR NT PACKAGE (TOP VIEW) SN54HC646 . . . FK PACKAGE (TOP VIEW) CLKAB SAB DIR GND V CC CLKBA SBA OE 432 1 28 12 13 OE NC NC DIR SAB CLKAB GND NC NC CLKBA SBA V 27 26 CC NC – No internal connection

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Pin numbers shown are for the DW, JT, NT, and W packages. Figure 1. Bus-Management Functions

SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS DATA I/O OPERATION OR FUNCTIONOE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8 OPERATION OR FUNCTION X X ↑ X X X Input Unspecified† Store A, B unspecified† X XX ↑ X X Unspecified † Input Store B, A unspecified † H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus † The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. logic symbol‡ ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, NT, and W packages. 4 B1 6D ≥1 OE G3

3 EN2 [AB]

3 EN1 [BA]

SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997

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logic diagram (positive logic) One of Eight Channels SAB CLKAB SBA CLKBA DIR OE To Seven Other Channels Pin numbers shown are for the DW, JT, NT, and W packages. absolute maximum ratings over operating free-air temperature range† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.

SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions SN54HC646 SN74HC646 UNIT MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage 2 5 6 2 5 6 V VCC = 2 V 1.5 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V VCC = 6 V 4.2 4.2 VCC = 2 V 0 0.5 0 0.5 VIL Low-level input voltage VCC = 4.5 V 0 1.35 0 1.35 V VCC = 6 V 0 1.8 0 1.8 VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V 0 1000 0 1000 tt Input transition (rise and fall) time VCC = 4.5 V 0 500 0 500 ns VCC = 6 V 0 400 0 400 TA Operating free-air temperature –55 125 –40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C SN54HC646 SN74HC646 UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 1.9 1.998 1.9 1.9 VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 V 2 V 0.002 0.1 0.1 0.1 VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 V II Control inputs VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA IOZ A or B VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 mA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 mA C i Control inputs 2 V to 6 V 3 10 10 10 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997

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timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25°C SN54HC646 SN74HC646 UNITVCC MIN MAX MIN MAX MIN MAX UNIT 2 V 0 6 0 4.3 0 5.5 fclock Clock frequency 4.5 V 0 31 0 22 0 27 MHz

6 V 0 36 0 25 0 31

2 V 80 115 95

tw Pulse duration, CLKBA or CLKAB high or low 4.5 V 16 23 19 ns

6 V 14 20 16

↑ ↑

2 V 100 150 125

tsu Setup time, A before CLKAB↑ or B before CLKBA↑ 4.5 V 20 30 25 ns

6 V 17 26 21

↑ ↑

2 V 5 5 5

th Hold time, A after CLKAB↑ or B after CLKBA↑ 4.5 V 5 5 5 ns

6 V 5 5 5

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM TO VCC TA = 25°C SN54HC646 SN74HC646 UNITPARAMETER (INPUT) (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT 2 V 6 11 4.4 5.5 fmax 4.5 V 31 54 22 27 MHz

6 V 36 64 25 31

2 V 65 180 270 225

CLKBA or CLKAB A or B 4.5 V 18 36 54 45

6 V 14 31 46 38

2 V 50 135 205 170

tpd A or B B or A 4.5 V 14 27 41 34 ns

6 V 11 23 35 29

2 V 70 190 285 240

SBA or SAB† A or B 4.5 V 20 38 57 48

6 V 16 32 48 41

2 V 85 245 370 305

ten OE A or B 4.5 V 25 49 74 61 ns

6 V 20 42 63 52

tdis OE A or B 4.5 V 25 49 74 61 ns

2 V 80 245 370 305

ten DIR A or B 4.5 V 25 49 74 61 ns tdis DIR A or B 4.5 V 25 49 74 61 ns

2 V 28 60 90 75

tt Any 4.5 V 8 12 18 15 ns

6 V 6 10 15 13

† These parameters are measured with the internal output state of the storage register opposite that of the bus input. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

SN54HC646, SN74HC646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCLS150B – DECEMBER 1982 – REVISED MAY 1997

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM TO VCC TA = 25°C SN54HC646 SN74HC646 UNITPARAMETER (INPUT) (OUTPUT) VCC MIN TYP MAX MIN MAX MIN MAX UNIT

2 V 90 265 400 330

CLKBA or CLKAB A or B 4.5 V 24 53 80 66

6 V 20 46 68 57

2 V 70 220 335 280

tpd A or B B or A 4.5 V 20 44 67 56 ns

6 V 15 38 57 49

2 V 80 275 415 345

SBA or SAB† A or B 4.5 V 24 55 83 69

6 V 20 47 70 60

2 V 113 330 500 410

OE A or B 4.5 V 33 66 100 82 t

6 V 27 57 85 71

DIR A or B 4.5 V 33 66 100 82

2 V 45 210 315 265

tt Any 4.5 V 17 42 63 53 ns

6 V 13 36 53 43

† These parameters are measured with the internal output state of the storage register opposite that of the bus input. operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance No load 50 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

NOTES: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. characteristics: PRR ≤ 1 MHz, ZO = 50 W , tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms

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