HC646

74HC646 PHILIPS

Document overview

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Technical content

Product specification File under Integrated Circuits, IC06 September 1993 INTEGRATED CIRCUITS 74HC/HCT646 Octal bus transceiver/register; 3-state For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646

FEATURES

• Independent register for A and B buses
• Multiplexed real-time and stored data
• Output capability: bus driver
• ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT646 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT646 consist of bus transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the “A” or “B” bus will be clocked into the registers as the appropriate clock (CP AB and CPBA ) goes to a HIGH logic level. Output enable (OE) and direction (DIR) inputs are provided to control the transceiver function. In the transceiver mode, data present at the high-impedance port may be stored in either the “A” or “B” register, or in both. The select source inputs (S AB and SBA ) can multiplex stored and real-time (transparent mode) data. The direction (DIR) input determines which bus will receive data when OE is active (LOW). In the isolation mode (OE = HIGH), “A” data may be stored in the “B” register and/or “B” data may be stored in the “A” register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The “646” is functionally identical to the “648”, but has non-inverting data paths. QUICK REFERENCE DATA GND = 0 V; T amb =2 5°C; tr =tf= 6 ns Notes 1. C PD is used to determine the dynamic power dissipation (PD inµW): PD =C PD × VCC 2 × fi+ ∑ (CL × VCC 2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC 2 × fo) = sum of outputs C L = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI= GND to VCC For HCT the condition is VI= GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL / tPLH propagation delay An, Bn to Bn, An C L = 15 pF; VCC =5V 1 1 1 3 n s fmax maximum clock frequency 69 85 MHz C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per channel notes 1 and 2 30 33 pF

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1C P AB A to B clock input (LOW-to-HIGH, edge-triggered) 2S AB select A to B source input

3 DIR direction control input

0 to A7 A data inputs/outputs

12 GND ground (0 V)

20, 19, 18, 17, 16, 15, 14, 13 B 0 to B7 B data inputs/outputs

21 OE output enable input (active LOW)

22 S BA select B to A source input

23 CP BA B to A clock input (LOW-to-HIGH, edge-triggered)

24 V CC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646 Fig.4 Functional diagram. FUNCTION TABLE Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH level transition 2. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. INPUTS (1) DATA I/O(2) FUNCTION OE DIR CP AB CP BA SAB SBA A 0 to A7 B 0 to B7 H H X X H or L H or L X X X X input input isolation store A and B data L L L L X X X H or L X X L H output input real-time B data to A bus stored B data to A bus L L H H X H or L X X L H X X input output real-time A data to B bus stored A data to B bus

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646 Fig.5 Logic diagram.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646 DC CHARACTERISTICS FOR 74HC For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver I CC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr =tf= 6 ns; CL =5 0p F SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HC VCC (V) WAVEFORMS+25 −40 to +85 −40 to +125 tPHL / tPLH propagation delay An,Bn to Bn,An 135 170 205 ns 2.0 4.5 6.0 Fig.6 t PHL / tPLH propagation delay CP AB ,CPBA to Bn,An 220 275 330 ns 2.0 4.5 6.0 Fig.7 t PHL / tPLH propagation delay SAB ,SBA to Bn,An 190 240 285 ns 2.0 4.5 6.0 Fig.8 t PZH / tPZL 3-state output enable time OE to An,Bn 175 220 265 ns 2.0 4.5 6.0 Fig.9 t PHZ / tPLZ 3-state output disable time OE to An,Bn 175 220 265 ns 2.0 4.5 6.0 Fig.9 t PZH / tPZL 3-state output enable time DIR to An,Bn 175 220 265 ns 2.0 4.5 6.0 Fig.10 t PHZ / tPLZ 3-state output disable time DIR to An,Bn 175 220 265 ns 2.0 4.5 6.0 Fig.10 t THL / tTLH output transition time 14 ns 2.0 4.5 6.0 Fig.6 and Fig.8 tW clock pulse width HIGH or LOW CP AB or CPBA 100 120 ns 2.0 4.5 6.0 Fig.7 t su set-up time An,Bn to CPAB ,CPBA ns 2.0 4.5 6.0 Fig.7 t h hold time An,Bn to CPAB ,CPBA ns 2.0 4.5 6.0 Fig.7 f max maximum clock pulse frequency 6.0 4.8 4.0 MHz 2.0 4.5 6.0 Fig.7

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (ΔICC ) for a unit load of 1 is given in the family specifications. To determineΔICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT SAB , SBA 0.60 A0 to A7 and B0 to B7 0.75 INPUT UNIT LOAD COEFFICIENT CP AB ,C PBA 1.50 OE DIR 1.50 1.25

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr =tf= 6 ns; CL =5 0p F SYMBOL PARAMETER Tamb (°C) UNIT TEST CONDITIONS 74HCT VCC (V) WAVEFORMS+25 −40 to +85 −40 to +125 tPHL / tPLH propagation delay An,Bn to Bn,An 16 30 38 45 ns 4.5 Fig.6 tPHL / tPLH propagation delay CP AB ,CPBA to Bn,An 23 44 55 66 ns 4.5 Fig.7 tPHL / tPLH propagation delay SAB ,SBA to Bn,An 26 46 58 69 ns 4.5 Fig.8 tPZH / tPZL 3-state output enable time OE to An,Bn 21 40 50 60 ns 4.5 Fig.9 tPHZ / tPLZ 3-state output disable time OE to An,Bn 20 35 44 53 ns 4.5 Fig.9 tPZH / tPZL 3-state output enable time DIR to An,Bn 21 40 50 60 ns 4.5 Fig.10 tPHZ / tPLZ 3-state output disable time DIR to An,Bn 21 35 44 53 ns 4.5 Fig.10 tTHL / tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 and Fig.8 tW clock pulse width HIGH or LOW CP AB or CPBA 16 8 20 24 ns 4.5 Fig.7 tsu set-up time An,Bn to CPAB ,CPBA 12 3 15 18 ns 4.5 Fig.7 th hold time An,Bn to CPAB ,CPBA 5 1 5 5 ns 4.5 Fig.7 fmax maximum clock pulse frequency 30 77 24 20 MHz 4.5 Fig.7

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646 AC WAVEFORMS Fig.6 Waveforms showing the input An, Bn to output Bn, An propagation delays and the output transition times. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.7 Waveforms showing the An,Bn to CPAB , CPBA set-up and hold times, clock CPAB ,CPBA pulse width, maximum clock pulse frequency and the CPAB ,CPBA to output Bn,An propagation delays. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.8 Waveforms showing the input SAB ,SBA to output Bn,An propagation delays and output transition times. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646 Fig.9 Waveforms showing the inputOE to output An,Bn 3-state enable and disable times. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V. Fig.10 Waveforms showing the input DIR to output An, Bn 3-state enable and disable times. (1) HC : V M = 50%; VI= GND to VCC . HCT: VM = 1.3 V; VI= GND to 3 V.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646

APPLICATION INFORMATION

Fig.11 Data storage from A and/or B bus. Fig.12 Real-time transfer from bus A to bus B. Fig.13 Real-time transfer from bus B to bus A.

Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT646 PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.