HC-5502B RENESAS
Document overview
- Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
- PDF pages: 11
Technical content
Features
- Capable of 12V or 5V (V B+) Operation
- Monolithic Integrated Device
- DI High Voltage Process
- Compatible With Worl dwide PBX Performance Requirements
- Controlled Supply of Battery Feed Current for Short Loops (30mA)
- Internal Ring Relay Driver
- Low Power Consumption During Standby
- Switch Hook, Ground Key and Ring Trip Detection Functions
- Selective Denial of Power to Subscriber Loops
Applications
- Solid State Line Interface Circuit for Analog and Digital PBX Systems
- Direct Inward Dial (DID) Trunks
- Voice Messaging PBXs
- Related Literature - AN549, The HC-5502S/4X Telephone Subscriber Line Interface Circuits (SLIC) - AN571, Using Ring Sync with HC-5502A and HC-5504 SLICs Part Number Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # HC3-5502B-5 0 to 75 24 Ld PDIP E24.6 HC4P5502B-5 0 to 75 28 Ld PLCC N28.45 Pinouts HC-5502B (PDIP) TOP VIEW HC-5502B (PLCC) TOP VIEW TIP RING C1* DG RS TF RF BG TX +IN AG OUT VB+ -IN RC PD GKD SHD RD VB- RX RX +IN N/C OUT RC RING TIP TX AG † OPTIONAL -IN RF BG N/C SHD GKD PD BV+ N/C 12 13 14 15 16 17 18 262728123VB- C1† DG N/C RS RD TF OBSOLETE PRODUCT RECOMMENDED REPLACEMENT HC5504B
FN2884 Rev.7.00 Page 2 of 11 August 2003 Absolute Maximum Ratings (Note 1) Thermal Information Supply Voltage Operating Conditions Loop Resistance (R Operating Temperature Range Thermal Resistance (Typical, Note 2) JA (oC/W) (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters TA = 25oC. Min-Max Parameters are Over Operating Temperature Range PARAMETER TEST CONDITIONS MIN TYP MAX UNITS On Hook Power Dissipation I LONG = 0, VB+ = 12V (Note 3) - 135 235 mW Off Hook Power Dissipation R L = 600, ILONG = 0, VB+ = 12V (Note 3) - 450 690 mW Off Hook IB+R L = 600, ILONG = 0, TA = -40oC (Note 3) - - 6.0 mA Off Hook IB+R L = 600, ILONG = 0, TA = 25oC (Note 3) - - 5.3 mA Off Hook IB-R L = 600, ILONG = 0 (Note 3) - - 39 mA Off Hook Loop Current R L = 1200, ILONG = 0 (Note 3) - 21 - mA Off Hook Loop Current R L = 1200, VB- = -42V, ILONG = 0, TA = 25oC (Note 3) 17.5 - - mA Off Hook Loop Current R L = 200, ILONG = 0 (Note 3) 25.5 30 34.5 mA Fault Currents TIP to Ground -1 4- m A RING to Ground -4 7- m A TIP to RING -3 0- m A TIP and RING to Ground - 47 - mA Ring Relay Drive VOL IOL = 62mA - 0.2 0.5 V Ring Relay Driver Off Leakage V RD = 12V, RC = 1 = HIGH, TA = 25oC - - 100 A Ring Trip Detection Period R L = 600, TA = 25oC - 2 3 Ring Cycles Switch Hook Detection Threshold SHD = VOL 10 - - mA SHD = VOH --5 m A
FN2884 Rev.7.00 Page 3 of 11 August 2003 Ground Key Detection Threshold GKD = VOL 20 - - mA GKD = VOH -- 1 0m A Loop Current During Power Denial R L = 200 - 2- m A Dial Pulse Distortion 0-5 m s Receive Input Impedance (Note 4) - 110 - k Transmit Output Impedance (Note 4) - 10 20 2-Wire Return Loss Referenced to 600 +2.16F (Note 4) SRL LO - 15.5 - dB ERL -2 4- d B SRL HI -3 1- d B Longitudinal Balance 1V RMS 200Hz - 3400Hz, (Note 4) IEEE Method oC TA 75oC 2-Wire Off Hook 58 65 - dB 2-Wire On Hook 60 63 - dB 4-Wire Off Hook 50 58 - dB Low Frequency Longitudinal Balance R.E.A. Method, (Note 4) RL = 600, 0oC TA 75oC - - 23 dBrnC -- - 6 7 d B m 0 p Insertion Loss 2-Wire to 4-Wire, 4-Wire to 2-Wire At 1kHz, 0dBm Input Level, Referenced 600 - 0.05 0.2 dB Frequency Response 200 - 3400Hz Referenced to Absolute Loss at 1kHz and 0dBm Signal Level (Note 4) - 0.02 0.05 dB Idle Channel Noise 2-Wire to 4-Wire, 4-Wire to 2-Wire (Note 4) - 1 5 dBrnC -- 8 9 - 8 5 d B m 0 p Absolute Delay 2-Wire to 4-Wire, 4-Wire to 2-Wire (Note 4) - - 2 s Trans Hybrid Loss Balance Network Set Up for 600 Termination at 1kHz 36 40 - dB Overload Level 2-Wire to 4-Wire, 4-Wire to 2-Wire VB+ = 5V 1.5 - - V PEAK VB+ = 12V 1.75 - - V PEAK Level Linearity At 1kHz, (Note 4) Referenced to 0dBm Level 2-Wire to 4-Wire, 4-Wire to 2-Wire +3 to -40dBm - - 0.05 dB -40 to -50dBm - - 0.1 dB -50 to -55dBm - - 0.3 dB Electrical Specifications Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
FN2884 Rev.7.00 Page 4 of 11 August 2003 Power Supply Rejection Ratio 30 - 60Hz, RL = 600 (Note 4) VB+ to 2-Wire 15 - - dB VB+ to Transmit 15 - - dB VB- to 2-Wire 15 - - dB VB- to Transmit 15 - - dB VB+ to 2-Wire 200 - 16kHz, RL = 600 30 - - dB VB+ to Transmit 30 - - dB VB- to 2-Wire 30 - - dB VB- to Transmit 30 - - dB Logic Input Current (RS, RC, PD)0 V VIN 5V - - 100 A Logic Inputs Logic ‘0’ VIL -- 0 . 8 V Logic ‘1’ VIH 2.0 - 5.5 V Logic Outputs Logic ‘0’ VOL ILOAD 800A, VB+ = 12V, 5V - 0.1 0.5 V Logic ‘1’ VOH ILOAD 80A, VB+ = 12V 2.7 5.0 5.5 V ILOAD 40A, VB+ = 5V 2.7 - 5.0 V Electrical Specifications Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Uncommitted Op Amp Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Offset Voltage - 5- m V Input Offset Current - 10 - nA Input Bias Current -2 0- n A Differential Input Resistance (Note 4) - 1 - M Output Voltage Swing R L = 10k, VB+ = 12V - 6.2 6.6 V PEAK RL = 10k, VB+ = 5V - 3- V PEAK Output Resistance A VCL = 1 (Note 4) - 10 - Small Signal GBW (Note 4) - 1 - MHz NOTES: 3. I LONG = Longitudinal Current. 4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance.
FN2884 Rev.7.00 Page 5 of 11 August 2003 Pin Descriptions
28 PIN PLCC 24 PIN DIP SYMBOL DESCRIPTION
2 1 TIP An analog input connected to the TIP (more po sitive) side of the subscriber loop through a 150 feed resistor and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring process. 3 2 RING An analog input connected to the RING (more negative) side of the subscriber loop through a 150 feed resistor and a ring relay contact. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring purposes. 43 V B+ Positive Voltage Source - Most positive supply. V B+ is typically 12V or 5V. 54 C 1 Capacitor #1 - Optional Capacitor used to improve power supply rejection. This pin should be left open if unused. 65 C 3 Capacitor #3 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the loop current limiting function, and for filtering VB- supply. Typical value is 0.3F, 30V.
76 D G
(Note 5) Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SLIC. 9 7 RS Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a positive transition occurs on the negative going zero crossing of the ring voltage source, ensuring that the ring relay is activated and deactivated when the instantaneous ring voltage is near zero. If synchronization is not required, tie to 5V. 10 8 RD Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized. 11 9 TF Tip Feed - A low impedance analog output connected to the TIP terminal through a 150 feed resistor. Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. 12 10 RF Ring Feed - A low impedance analog output c onnected to the RING terminal through a 150 feed resistor. Functions with the TF terminal to provide loop current, feed voice signal to the telephone set, and sink longitudinal current. 13 11 V B- Negative Voltage Source - Most negative supply. V B- is typically -48V with an operational range of - 42V to -58V. Frequently referred to as “battery”. 14 12 BG (Note 1) Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal. 16 13 SHD Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop currents exceeding 10mA and disabled for loop currents less than 5mA. 17 14 GKD Ground Key Detection - A low active LS TTL - compatible logic output. This output is enabled if the DC current into the ring lead exceeds the DC current out of the tip lead by more than 20mA, and disabled if this current difference is less than 10mA. 18 15 PD Power Denial - A low active TTL - Compatible logic input. When enabled the switch hook detect (SHD) and ground key detect (GKD) are not necessarily valid, and the relay driver (RD) output is disabled. 19 16 RC Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output goes low on the next rising edge of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the subscriber is not already off- hook (SHD = 0). 20 17 C 2 Capacitor #2 - An external capacitor to be connected between this terminal and digital ground. Prevents false ground key indications from occurring during ring trip detection. Typical value is 0.15F, 10V. This capacitor is not used if ground key function is not required. 21 18 OUT The analog output of the spare operational amplifier. 23 19 -IN The inverting analog input of the spare operational amplifier. 24 20 +IN The non-inverting analog input of the spare operational amplifier.
FN2884 Rev.7.00 Page 6 of 11 August 2003 Functional Diagram 25 21 RX Receive Input, 4-Wire Side - A high impedance anal og input which is internally biased. Capacitive coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and Ring feed amplifiers, which in turn drive tip and ring through 300 of feed resistance on each side of the line. 26 22 C 4 Capacitor #4 - An external capacitor to be connected between this terminal and analog ground. This capacitor prevents false ground key indication and false ring trip detection from occurring when longitudinal currents are induced onto the subscriber loop from nearby power lines and other noise sources. This capacitor is also required for the proper operation of ring trip detection. Typical value is 0.5F to 1.0F, 20V. This capacitor should be nonpolarized. 27 23 AG (Note 5) Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive input (RX) terminals. 28 24 TX Transmit Output, 4-Wire Side - A low impedanc e analog output which represents the differential voltage across Tip and Ring. Transhybrid balancing must be performed (using the SLIC microcircuit’s spare op amp) beyond this output to completely implement two to four wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is essential. 1, 8, 5, 22 NC No internal connection. NOTE: 5. All grounds (AG, BG, and DG) must be applied before V B+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first. Pin Descriptions (Continued)
2 WIRE
150 RING 150 RF BG 150 TF TIP RD RC RSRING VOLTAGE RING SYNC RING COMMAND RING TRIP SHD GKD TX TRANSMIT OUTPUT OUT +IN -IN RX RECEIVE INPUT SLIC MICROCIRCUIT 150 SWITCH HOOK DETECTION GROUND KEY DETECTION
FN2884 Rev.7.00 Page 7 of 11 August 2003 Schematic Diagram HC-5502B Pin Numbers for DIP Package A-400 TIP FEED AMP A-200 LONG’L I/V AMP A-100 TRANSV’L I/VAMP A-300 RING FEED AMP C3 TX RS RD PD RC SHD GKD OUT-+C1VB+ DIG GND ANA GND BAT GNDVBATC4RCV A-500 OP AMP VB+ VOLTAGE AND CURRENT BIAS NETWORK IB4 VBAT VB+ VB+ QD3 QD36 GK SH RFC R18 R19 R13 VBAT VBAT R14 VB2 VBAT/2 REFERENCE R21 R15 R16 R10 VBAT VBATVB+ R17 VB2 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 IB9VBAT IB10 IB11 VB1 VB2 VB3 VB4 VB5 -5V IB3 VBAT VB+ IB10-5V V B+ VB+ VBAT VBAT VB+ R11 R20 R12 IB7 IB6 IIL LOGIC INTERFACE VB3 VBAT IB1 + - IB8 VBAT +5V VB4 VB+ IB9 IB2 VB5 QD27 QD28 VB1 LOOP CURRENT LIMITING SWITCH HOOK DETECTOR RING TRIP DETECTOR GND SHORTS CURRENT LIMITING VB5 THERMAL LIMITING 87245 IB5 VBAT 10 RF RING TIP TF 21 22 11 12 23 6 3 4 20 19 18 VBAT
FN2884 Rev.7.00 Page 8 of 11 August 2003 Logic Diagram HC-5502B LOGIC GATE SCHEMATIC Overvoltage Protection and Longitudinal Current Protection The SLIC device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. High voltage surge conditions are as specified in Table 1. The SLIC will withstand longitudinal currents up to a maximum or 30mARMS, 15mARMS per leg, without any performance degradation. RELAY DRIVER GKDSHDRD PDRCRS DELAY LOGIC BIAS A B C A B CTTL TO STTL TO R21 GK SH SCHOTTKY LOGIC TTL TO STTL TTL TO STTL TTL TO STTL TTL TO STTL 1 2 4 5 9 12 1411 TABLE 1. PARAMETER TEST CONDITION PERFORMANCE (MAX) UNITS Longitudinal Surge 10s Rise/ 1000 (Plastic) V PEAK 1000s Fall 500 (Ceramic) V PEAK Metallic Surge 10 s Rise/ 1000 (Plastic) V PEAK 1000s Fall 500 (Ceramic) V PEAK T/GND 10 s Rise/ 1000 (Plastic) V PEAK R/GND 1000 s Fall 500 (Ceramic) V PEAK 50/60Hz Current T/GND 11 Cycles 700 (Plastic) V RMS R/GND Limited to 10ARMS 350 (Ceramic) V RMS
C4 = 0.5F to 1.0F, 10%, 20V (Should be nonpolarized). value), ZB = 0 for 600 Terminations (Note 7).
- C 1 is an optional capacitor used to improve VB+ supply rejection. This pin must be left open if unused.
- To obtain the specified transhybrid loss it is necessary for the three legs of the balance network, C6-R1 and R2 and C7-ZB-R3, to match in
- Secondary protection diode bridge recommended is a 2A, 200V type.
- All grounds (AG, BG, and DG) must be applied before V B+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
- Pin numbers given for DIP package.
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
FN2884 Rev.7.00 Page 10 of 11 August 2003 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. e B and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E24.6 (JEDEC MS-011-AA ISSUE B)
24 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.150 1.290 29.3 32.7 5 D1 0.005 - 0.13 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N2 4 2 4 9 Rev. 0 12/93
FN2884 Rev.7.00 Page 11 of 11 August 2003 HC-5502B Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2003. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N28.45 (JEDEC MS-018AB ISSUE A)
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.485 0.495 12.32 12.57 - D1 0.450 0.456 11.43 11.58 3 D2 0.191 0.219 4.86 5.56 4, 5 E 0.485 0.495 12.32 12.57 - E1 0.450 0.456 11.43 11.58 3 E2 0.191 0.219 4.86 5.56 4, 5 N2 8 2 8 6 Rev. 2 11/97