H6060 EMMICRO

Document overview

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Technical content

Features

/boxshadowdwn Self recovering watchdog function: reset goes active after the 1st timeout period, reset goes inactive again after the 2nd timeout period, repeated active reset signal until the system recovers /boxshadowdwn Standard timeout period and power-on reset time (100 ms), externally programmable if required /boxshadowdwn Unregulated DC monitoring (V IN) with 3 standard or programmable trigger voltages for: power-on reset initialization, advanced power-fail warning ( SAVE ), reset at power-down ( RES ) /boxshadowdwn Regulated DC monitoring (V DD): power-on reset initialization enabled only if VDD ≥ 3.5 V /boxshadowdwn Internal voltage reference /boxshadowdwn Works down to 1.6 V supply voltage /boxshadowdwn Push-pull or Open drain outputs /boxshadowdwn Low current consumption /boxshadowdwn SO8 package

Applications

/boxshadowdwn Microprocessor and microcontroller systems /boxshadowdwn Point of sales equipment /boxshadowdwn Telecom products /boxshadowdwn Automotive subsystems Typical Operating Configuration H6060 Fig. 1 Pin Assignment Fig. 2 EM MICROELECTRONIC - MARIN SA

R H6060 Copyright © 2004, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com Absolute Maximum Ratings Parameter Symbol Conditions Voltage VDD to VSS V DD − 0.3 to + 8 V Voltage at any pin to VSS V MIN − 0.3 Voltage at any pin to VDD (except VIN) VINMAX + 0.3 Voltage at VIN to VSS V MIN + 15 V Current at any output I MAX ± 10 mA Storage temperature T STO -65°C to +150°C Table 1 Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Symbol Min. Max. Units Operating temperature Industrial TAI -40 +85 °C Supply voltage V DD 1.6 5.5 V Comparator input voltage Version 13, 14, 15, 16 V IN 0 V DD V Version 11,12 V IN 0 12 V RC-oscillator programm- ing (see Fig. 15) External capacitance∗ C1 1 µF External resistance R1 10 kΩ Table 2 * Leakage < 1µA

Electrical Characteristics

VDD = 5.0 V, TA = −40 to +85 °C, unless otherwise specified Parameter Symbol Test Conditions Min. Typ. Max. Units VDD activation threshold VDD deactivation threshold Supply current Input V IN, TCL Leakage current Input current on pin V IN TCL input low level TCL input high level SAVE , RES , RES outputs Leakage currents Drive currents (all versions) Drive currents (versions 14,16) VON VOFF IDD IIP IIN VIL VIH IOLK IOL IOL IOL IOH IOH IOH TA = 25 °C TA = 25 °C RC open, TCL at VDD or VSS VSS ≤ VIP ≤ VDD; TA = 85 °C Version 12; VIN = 10 V Version 15; V OUT = VDD VOL = 0.4 V VDD = 3.5 V; VOL = 0.4 V VDD = 1.6 V; VOL = 0.4 V VOH = 4.0 V VDD = 3.5 V; VOH = 2.8 V VDD = 1.6 V; VOH = 1.2 V 2.4 3.2 3.2 V ON − 0.3 0.005 100 0.05 3.5 140 180 0.8 V V µA µA µA V V µA mA mA µA mA mA µA 1) Versions: 15 = open drain outputs; 14, 16 = push-pull outputs Table 3 VIN Surveillance Voltage thresholds at TA = 25 °C Version 1) Comparator Reference Input Resistance on VIN (RVIN) Threshold VSH VSL VRL Thresholds Tolerance Ratio Tolerance 14 V DD ∼100MΩ 2.25 2.00 1.75 2) ±5% ±2% 15, 16 Band-gap reference ∼100MΩ 2.00 1.95 1.90 ±10% ±2% 1) Version: 15 = open drain outputs; 14, 16 = push-pull outputs 2) at VDD = 5 V 3) Threshold ratio tolerance is defined as the tolerance of VSH / VSL and VSL / VRL. Table 4

R H6060 Copyright © 2004, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com Timing Characteristics VDD = 5.0 V, TA = −40 °C to +85 °C, unless otherwise specified Parameter Symbol Test Conditions Min. Typ. Max. Units Propagation delays TCL to output pins VIN to output pins Logic transition times on all output pins Timeout period TTCL input pulse width Power-on reset debounce VIN low pulse TDIDO TAIDO TTR TTO TTO TTCL TDB TVINL Excluding debounce time TDB Load 10 kΩ, 100 pF RC open, unshielded, TA = 25 °C RC open, unshielded (not tested) Where debounce time TDB Is guaranteed 150 250 100 TTO/64 500 100 160 200 ns µs ns ms ms ns ms µs Table 5 Timing Waveforms Voltage Reaction: VDD Monitoring Voltage Reaction: VIN Monitoring VDD VON VOFF VIN monitoring enabled Fig. 3 VIN VSH VSL VRL SAVE RES RES TTO TDB TTO TDB TVINL Conditions: VDD > VON. No timeout. Fig. 4 Timer Start Power-on Reset Timer Stop Timer Start Power-on Reset No Power-on Reset (as VIN > VRL)

R H6060 Copyright © 2004, EM Microelectronic-Marin SA 4 www.emmicroelectronic.com Timer Reaction Combined Voltage and Timer Reaction Block Diagram VIN VSH VSL VRL SAVE RES RES TCL Initialisation RES RES Timeout Recover Timer Reset Timer Stop TTO TTO TTO TDB Fig. 6 VDD Band-Gap Reference Save Control Reset Control OSC Timer TCL SAVE RES RES VIN 1 2 VSH VSL VRL VSS RC Fig. 7 Version Connections 11, 12 1 and 3 13, 14 1 15, 16 2 RES RES S TCL Timeout Timer Reset Timer Reset Timer Reset TTO TTO Fig. 5 TTCL TTO TTO Conditions: VIN > VRL after power-up sequence

R H6060 Copyright © 2004, EM Microelectronic-Marin SA 5 www.emmicroelectronic.com Pin Description Pin Name Function

1 V IN Voltage sense input

2 TCL Timer clear input signal

3 RC RC oscillator tuning input

4 V SS GND terminal

5 RES Active low reset output

6 SAVE Save output

7 RES Active high reset output

8 V DD Positive supply voltage terminal

The circuit is powered through the V DD and V SS pins. It monitors both its own VDD supply and a voltage applied to the VIN input. VDD Monitoring During power-up the VIN monitoring is disabled and RES , RES and SAVE stay active low as long as V DD is below VON (3.5 V). As soon as V DD reaches the V ON level, the state of the outputs depend on the watchdog timer and the voltage at V IN relative to the thresholds (see Fig. 4). If the supply voltage VDD falls back below VOFF (VON – 0.3 V) the watchdog timer and the V IN monitoring are disabled and the outputs RES , RES and SAVE become active. The VDD line should be free of voltage spikes. VIN Monitoring The analog voltage comparators compare the voltage applied to V IN (typically connected to the input of the voltage regulator) with the stabilized supply voltage V DD (version 14) or with the bandgap voltage (versions 15, 16) (see Fig. 7). At power-up, when V DD reached VON and VIN reaches the V SH level, the SAVE output goes inactive, and the timer starts running, setting RES and RES in active after the time TTO (see. Fig. 4). If VIN falls below VSL , the SAVE output goes active and stays active until V IN rises again above VSH . If VIN falls below the voltage V RL , RES and RES will become active and the on-chip timer will stop. When V IN rises again above V SH, the timer will initiate a power-up sequence. The RES and RES outputs may however be influenced independently of the voltage VIN by the timer action, see section ″Combined Voltage and Timer Action”. Monitoring the rough DC side of the regulator, as shown in Fig. 11, is the only way to have advanced warning of power-down. Spikes on V IN should be filtered if they are likely to exceed the value (V SL – VRL). The combination of V IN and V DD monitoring provide high system security: if V IN rises much faster than V DD , then the device starts the power-on sequence only when V DD reached V ON (Fig. 10). Short circuits on the regulated supply voltage can be detected. Voltage Thresholds on VIN The H6060 is available with 3 different sets of thresholds: Version 14: monitor the unregulated voltage and are ideal for programming of the VIN voltage thresholds. Fixed resistor values can be used for programming. Version 15, 16: monitor the regulated voltage. They are suited to applications where the unregulated voltage is not available. (The tolerance is ± 10%, see table 4. For tighter tolerances, trimming can be used, see Fig. 9). Monitoring of the unregulated voltage requires version 14. These versions are based on the principle that V DD rises with VIN on power-up an V DD holds up for a certain time after VIN starts dropping on power-down. The versions 11 and 12 have a 100 k Ω nominal resistance from VIN to VSS (internal voltage divider). The versions 14, 15 and 16 have high impedance V IN inputs (see Fig. 7 and Table 4) for external threshold voltage programming by a voltage divider on pin V IN. The levels obtained are proportional to the internal levels V SH, VSL and VRL on the chip itself (see Electrical Specifications).

R H6060 Copyright © 2004, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com Timer Programming With pin RC unconnected, the on-chip RC oscillator together with its divider chain give a timeout T TO of typically 100 ms. To program different T TO, an approximation for calculating component values is given by the formula: ⋅++= DD 1TO R 1V5.5 2)C(320.75T 8.192 R1 min. = 10 kΩ, C1 max. = 1 µF If R1 is in MΩ and C1 in pF, TTO will be in ms. A resistor decreases and a capacitor increases the interval to timeout. Excellent temperature stability of T TO can be achieved by using external components. A precise square wave of period 2 × T TO is generated at the outputs RES and RES when TCL is tied to either V DD or V SS. The oscillator and watchdog timer start running when both V IN is greater than V SH (see Fig. 6) and V DD is greater than VON (see Fig. 3). They will remain running while both V IN is greater than VRL and VDD is greater than VOFF (see Fig. 3). Timer Clearing and RES /RES Action A negative edge or a negative pulse at the TCL input for longer than 150 ns will reset the timer and set RES and RES inactive. If a further TCL signal edge or pulse is applied before T TO timeout, RES and RES will remain inactive and the timer will again be reset to zero (see Fig. 5). If no TCL signal is applied before the T TO timeout, RES and RES will start to generate square waves of period 2 × T TO starting with the inactive state. The watchdog will remain in this state until the next TCL signal appears, or until a fresh power-up sequence. Combined Voltage and Timer Action The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 6. One timeout period after V IN reaches V SH, during power-up, RES and RES go inactive. A TCL pulse will have no effect until this power-on reset delay is completed. After completing the power-up sequence the watchdog timer starts acting. If no TCL pulse occurs, RES and RES go active after one timeout period T TO. After each subsequent timeout period, without a timer clear pulse at TCL , RES and RES change polarity providing square wave signals. A TCL pulse clears the watchdog timer and causes RES and RES to go inactive. A voltage drop below the V RL level overrides the timer and immediately forces RES , RES and SAVE active. Any further TCL pulse has no effect until the next power-up sequence is completed. Typical Applications Microprocessor Watchdog with Power-On Reset and Voltage Monitor

R H6060 Copyright © 2004, EM Microelectronic-Marin SA 7 www.emmicroelectronic.com Voltage Monitor with Spike Suppression Watchdog and Power-On Reset External Programming of RC Oscillator Voltage Regulator RC H6060 11 +12 VDC rough 2.7 kΩ Z-15 330 nF VIN VSS TCL VDD SAVE RES Fig. 11

5 VDC

1) R/F shields for noisy environments.

R H6060 Copyright © 2004, EM Microelectronic-Marin SA 8 www.emmicroelectronic.com

Package Information

Dimensions of 8-Pin SOIC Package Min Nom Max A 1.35 1.63 1.75 A1 0.10 0.15 0.25 B 0.33 0.41 0.51 C 0.19 0.20 0.25 D 4.80 4.93 5.00 E 3.80 3.94 4.00 e 1.27 H 5.80 5.99 6.20 L 0.40 0.64 1.27 2 3 4 5 6 7 8 H L 0 - 8° C E A1 A B e D Dimensions in mm Fig. 15

Ordering Information

When ordering please specify complete part number. Part Number Version Threshold (see Table 4) Output Package Delivery Form Package Marking (first line) Temperature H6060V15SO8A 8-pin SOIC Stick 606015 H6060V15SO8B V15 1.95 Open drain 8-pin SOIC Tape&Reel 606015 H6060V14SO8A 8-pin SOIC Stick 606014 H6060V14SO8B V14 2.00 8-pin SOIC Tape&Reel 606014 H6060V16SO8A 8-pin SOIC Stick 606016 H6060V16SO8B V16 1.95 Push-pull 8-pin SOIC Tape&Reel 606016 -40°C to °85°C Note: Other versions are no longer available EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. © EM Microelectronic-Marin SA, 07/04, Rev. I Fig. 14