H5TC1G43BFR

H5TC1G43BFR HYNIX

Document overview

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Technical content

Rev. 0.1 / Nov. 2009 1Gb DDR3L SDRAM 1Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC1G43BFR-xxA H5TC1G83BFR-xxA H5TC1G63BFR-xxA *Hynix Semiconductor reserves the right to change products or specifications without notice

Rev. 0.1 / Nov. 2009 2

Revision History

Revision No. History Draft Date Remark 0.1 Initial Release Nov. 2009 Preliminary

Rev. 0.1 / Nov. 2009 3

Description

The H5TC1G43BFR-xxA, H5TC1G83BFR-xxA and H5TC1G63BFR-xxA are a 1Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. Hynix DDR3L SDRAM provides back- ward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.) Hynix 1Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information

FEATURES

• This product in compliance with the RoHS directive.
• VDD=VDDQ=1.35V + 0.100 / - 0.067V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 6, 7, 8, 9, 10 supported
• Programmable additive latency 0, CL-1, and CL-2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on the fly
• 8banks
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC
• Auto Self Refresh supported
• JEDEC standard 78ball FBGA(x4/x8)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch

Rev. 0.1 / Nov. 2009 4

ORDERING INFORMATION

• xx means Speed Bin Grade OPERATING FREQUENCY Part No. Configuration Package H5TC1G43BFR-*xxA 256M x 4 78ball FBGA H5TC1G83BFR-*xxA 128M x 8 H5TC1G63BFR-*xxA 64M x 16 96ball FBGA Speed Grade (Marking) Frequency [MHz] Remark (CL-tRCD-tRP)CL5 CL6 CL7 CL8 CL9 CL10 CL11 -G7 O O O DDR3-1066 7-7-7 -H9 O O O O O DDR3-1333 9-9-9

Rev. 0.1 / Nov. 2009 5 Package Ballout/Mechanical Dimension x4 Package Ball out (Top view): 78ball FBGA Package (no support balls) Note: NF(No Function) - This is applied to balls only used in x4 configuration. 1 2 3 4 5 6 7 8 9 A VSS VDD NC NF VSS VDD A B VSS VSSQ DQ0 DM VSSQ VDDQ B C VDDQ DQ2 DQS DQ1 DQ3 VSSQ C D VSSQ NF DQS VDD VSS VSSQ D E VREFDQ VDDQ NF NF NF VDDQ E F NC VSS RAS CK VSS NC F G ODT VDD CAS CK VDD CKE G H NC CS WE A10/AP ZQ NC H J VSS BA0 BA2 NC VREFCA VSS J K VDD A3 A0 A12/BC BA1 VDD K L VSS A5 A2 A1 A4 VSS L M VDD A7 A9 A11 A6 VDD M N VSS RESET A13 A14 A8 VSS N 1 2 3 4 5 6 7 8 9 A B C D E F G H J K L M N Populated ball Ball not populated 3 789 (Top View: See the balls through the Package)

Rev. 0.1 / Nov. 2009 6 x8 Package Ball out (Top view): 78ball FBGA Package (no support balls) 1 2 3 4 5 6 7 8 9 A VSS VDD NC NU/TDQS VSS VDD A B VSS VSSQ DQ0 DM/TDQS VSSQ VDDQ B C VDDQ DQ2 DQS DQ1 DQ3 VSSQ C D VSSQ DQ6 DQS VDD VSS VSSQ D E VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ E F NC VSS RAS CK VSS NC F G ODT VDD CAS CK VDD CKE G H NC CS WE A10/AP ZQ NC H J VSS BA0 BA2 NC VREFCA VSS J K VDD A3 A0 A12/BC BA1 VDD K L VSS A5 A2 A1 A4 VSS L M VDD A7 A9 A11 A6 VDD M N VSS RESET A13 NC A8 VSS N 1 2 3 4 5 6 7 8 9 A B C D E F G H J K L M N Populated ball Ball not populated 3 789 (Top View: See the balls through the Package)

Rev. 0.1 / Nov. 2009 7 x16 Package Ball out (Top view): 96ball FBGA Package (no support balls) 1 2 3 4 5 6 7 8 9 A VDDQ DQU5 DQU7 DQU4 VDDQ VSS A B VSSQ VDD VSS DQSU DQU6 VSSQ B C VDDQ DQU3 DQU1 DQSU DQU2 VDDQ C D VSSQ VDDQ DMU DQU0 VSSQ VDD D E VSS VSSQ DQL0 DML VSSQ VDDQ E F VDDQ DQL2 DQSL DQL1 DQL3 VSSQ F G VSSQ DQL6 DQSL VDD VSS VSSQ G H VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H J NC VSS RAS CK VSS NC J K ODT VDD CAS CK VDD CKE K L NC CS WE A10/AP ZQ NC L M VSS BA0 BA2 A15 VREFCA VSS M N VDD A3 A0 A12/BC BA1 VDD N P VSS A5 A2 A1 A4 VSS P R VDD A7 A9 A11 A6 VDD R T VSS RESET A13 NC A8 VSS T 1 2 3 4 5 6 7 8 9 A B C D E F G H J K L M N Populated ball Ball not populated P T 3 789 (Top View: See the balls through the Package) R

Rev. 0.1 / Nov. 2009 8 Pin Functional Description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. CKE, (CKE0), (CKE1) Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE, are disabled during power- down. Input buffers, excluding CKE, are disabled during Self-Refresh. CS, (CS0), (CS1), (CS2), (CS3) Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. ODT, (ODT0), (ODT1) Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x4/x8 configurations. For x16 configuration, ODT is applied to each DQ, DQSU, DQSU, DQSL, DQSL, DMU, and DML signal. The ODT pin will be ignored if MR1 is programmed to disable ODT. RAS. CAS. WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM, (DMU), (DML) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. BA0 - BA2 Input Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. A0 - A15 Input Address Inputs: Provide the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below). The address inputs also provide the op-code during Mode Register Set commands. A10 / AP Input Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC Input Burst Chop: A12 / BC is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

Rev. 0.1 / Nov. 2009 9 RESET Input Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. DQ Input / Output Data Input/ Output: Bi-directional data bus. DQU, DQL, DQS, DQS, DQSU, DQSU, DQSL, DQSL Input / Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential signals DQS, DQSL, and DQSU, respectively, to provide differential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. TDQS, TDQS Output Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1. NC No Connect: No internal electrical connection is present. NF No Function VDDQ Supply DQ Power Supply: 1.5 V +/- 0.075 V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.5 V +/- 0.075 V VSS Supply Ground VREFDQ Supply Reference voltage for DQ VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration Note: Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination. Symbol Type Function

Rev. 0.1 / Nov. 2009 10 ROW AND COLUMN ADDRESS TABLE 1Gb Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG ÷ 8 where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits Configuration 256Mb x 4 128Mb x 8 64Mb x 16 # of Banks 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10/AP A10/AP A10/AP BL switch on the fly A12/BC A12/BC A12/BC Row Address A0 - A13 A0 - A13 A0 - A12 Column Address A0 - A9,A11 A0 - A9 A0 - A9 Page size 1 1 KB 1 KB 2 KB

Rev. 0.1 / Nov. 2009 11 Absolute Maximum Ratings Absolute Maximum DC Ratings DRAM Component Operating Temperature Range Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V 1,3 VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V 1,3 VIN, VOUT Voltage on any pin relative to Vss - 0.4 V ~ 1.975 V V 1 TSTG Storage Temperature -55 to +100 oC1 , 2 Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat- ing conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. Temperature Range Symbol Parameter Rating Units Notes TOPER Normal Operating Temperature Range 0 to 85 oC 1,2 Extended Temperature Range (Optional) 85 to 95 oC1 , 3 Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measure- ment conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur- ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).

Rev. 0.1 / Nov. 2009 12 AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions - DDR3L (1.35V) operation Symbol Parameter Rating Units Notes Min. Typ. Max. VDD Supply Voltage 1.283 1.35 1.45 V 1,2,3,4 VDDQ Supply Voltage for Output 1.283 1.35 1.45 V 1,2,3,4 Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long period of time (e.g 1 sec) 2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications 3. Under these supply voltages, the device operates to this DDR3L specification 4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (See figure 0) Recommended DC Operating Conditions - DDR3 (1.5V) operation Symbol Parameter Rating Units Notes Min. Typ. Max. VDD Supply Voltage 1.425 1.5 1.575 V 1,2,3 VDDQ Supply Voltage for Output 1.425 1.5 1.575 V 1,2,3 Notes: 1. If maximum limit is exceeded, input levels shall be governed by DDR3L specifications 2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation (See figure 0)

Rev. 0.1 / Nov. 2009 13 Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3 NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands. Ta CK,CK# RESET# Tb Tc Td Te Tf Tg Th Ti Tj Tk MRS1) 1)MRS MRS CKE DON’T CARE READ MRS T = 500us COMMAND ODT BA RTT MR3 MR1 MR0READ MR2 READ Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW VDD, VDDQ (DDR3) VDD, VDDQ (DDR3L) ZQCL VALID VALID VALID VALID Tmin = 200usTmin = 10ns Tmin = 10ns tCKSRX Tmin = 10ns tIS tIS tIS tXPR tMRD tMRD tMRD tMOD tZQinit tDLLK TIME BREAK

Rev. 0.1 / Nov. 2009 14 IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and IDDQ measurements.

• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT , IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied togeth er. Any IDDQ current is not included in IDD cur rents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur- rents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO po wer as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately si nce VDD and VDDQ are using one merged-power layer in Module PCB. For IDD and IDDQ measurements, the following definitions apply:
• ”0” and “LOW” is defined as VIN <= V ILAC(max).
• ”1” and “HIGH” is defined as VIN >= V IHAC(max).
• “MID_LEVEL” is defined as inputs are VREF = VDD/2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Co nditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patte rns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializi ng the DDR3 SDRAM. This includes but is not lim - ited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
• Define D = { CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
• Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}

Rev. 0.1 / Nov. 2009 16 Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Table 2 -Basic IDD and IDDQ Measurement Conditions Symbol DDR3-1066 DDR3-1333 Unit 7-7-7 9-9-9 tCK 1.875 1.5 ns CL 7 9 nCK nRCD 79 n C K nRC 27 33 nCK nRAS 20 24 nCK nRP 79 n C K nFAW 1KB page size 20 20 nCK 2KB page size 27 30 nCK nRRD 1KB page size 4 4 nCK 2KB page size 6 5 nCK nRFC -512Mb 48 60 nCK nRFC-1 Gb 59 74 nCK nRFC- 2 Gb 86 107 nCK nRFC- 4 Gb 160 200 nCK nRFC- 8 Gb 187 234 nCK Symbol Description IDD0 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3. IDD1 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.

Rev. 0.1 / Nov. 2009 17 IDD2N Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. IDD2NT Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: tog- gling according to Table 6; Pattern Details: see Table 6. IDDQ2NT (optional) Precharge Standby ODT IDDQ Current Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current IDD2P0 Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc) IDD2P1 Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc) IDD2Q Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 IDD3N Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5. Symbol Description

Rev. 0.1 / Nov. 2009 18 IDD3P Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 IDDQ4R (optional) Operating Burst Read IDDQ Current Same definition like for IDD4R, however measuring IDDQ current instead of IDD current IDD4R Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7. IDD4W Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8. IDD5B Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Com- mand, Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9. IDD6 Self-Refresh Current: Normal Temperature Range TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Out- put Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL Symbol Description

Rev. 0.1 / Nov. 2009 19 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[ 5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B IDD6ET Self-Refresh Current: Extended Temperature Range TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extend- ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Tempera- ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL IDD6TC Auto Self-Refresh Current TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL IDD7 Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a)f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table 10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10. Symbol Description

Rev. 0.1 / Nov. 2009 20 Table 3 - IDD0 Measurement-Loop Patterna) a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. CK, CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Datab) toggling Static High 0 0 A C T 001100 0 0 00 00 - 1 , 2 D , D 100000 0 0 00 00 - 3,4 D , D 111100 0 0 00 00 - n R A S P R E 001000 0 0 00 00 - 1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 - 1*nRC+3, 4 D , D 111100 0 0 00 F0 - 1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 - 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead

Rev. 0.1 / Nov. 2009 21 Table 4 - IDD1 Measurement-Loop Patterna) a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL. CK, CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Datab) toggling Static High 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - 3,4 D , D 1111000 0 00 0 0 - nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000 nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 - 1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 - 1*nRC+3,4 D , D 1111000 0 00 F 0 - 1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011 1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 - 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead

Rev. 0.1 / Nov. 2009 22 Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna) a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. CK, CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Datab) toggling Static High 0 0 D1 0 0 0 0 0 0 0 0 0 0 - 1D 1 0 0 0 0 0 0 0 0 0 0 - 2D 1111 000 0 0 F0 - 3D 1111 000 0 0 F0 - 1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead CK, CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Datab) toggling Static High 0 0 D1 0 0 0 0 0 0 0 0 0 0 - 1D 1 0 0 0 0 0 0 0 0 0 0 - 2D 1111000 0 0 F 0 - 3D 1111000 0 0 F 0 - 1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 2 8-11 repeat Sub-Loop 0, bu t ODT = 1 and BA[2:0] = 2 3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7

Rev. 0.1 / Nov. 2009 23 Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna) a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. CK, CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Datab) toggling Static High 0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1D 1 0 0 0 0 0 0 0 0 0 0 0 - 2,3 D ,D 1111000 00 0 00 -

4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011

5D 1 0 0 0 0 0 0 0 0 0 F 0 - 6,7 D ,D 1111000 00 0 F 0 - 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7

Rev. 0.1 / Nov. 2009 24 Table 8 - IDD4W Measurement-Loop Patterna) a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. Table 9 - IDD5B Measurement-Loop Patterna) a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL. CK, CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Datab) toggling Static High 0 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000 1D 1 0 0 0 1 0 0 0 0 0 0 0 - 2,3 D ,D 1111100 00 0 00 -

4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011

5D 1 0 0 0 1 0 0 0 0 0 F 0 - 6,7 D ,D 1111100 00 0 F 0 - 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7 CK, CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Datab) toggling Static High 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 - 11 . 2 D , D 1 0 0 0 0 0 0 0 0 0 0 0 - 3,4 D , D 1111000 00 0 F 0 -

Rev. 0.1 / Nov. 2009 25 Table 10 - IDD7 Measurement-Loop Patterna) ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9 a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. CK, CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Datab) toggling Static High 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -

1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000

2 D 1 0 0 0 0 0 00 0 0 0 0 -

... repeat above D Command until nRRD - 1 nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 - nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011 nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 - ... repeat above D Command until 2* nRRD - 1 2 2*nRRD repeat Sub-Loop 0, but BA[2:0] = 2 3 3*nRRD repeat Sub-Loop 1, but BA[2:0] = 3 4 4*nRRD D 1 0 0 0 0 3 00 0 0 F 0 - Assert and repeat above D Command until nFAW - 1, if necessary 5 nFAW repeat Sub-Loop 0, but BA[2:0] = 4 6 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5 7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6 8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7 9 nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 F 0 - Assert and repeat above D Command until 2* nFAW - 1, if necessary 2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 - 2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 2&nFAW+2 D 1 0 0 0 0 0 00 0 0 F 0 - Repeat above D Command until 2* nFAW + nRRD - 1 2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 - 2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nFAW+nRRD+ D 1 0 0 0 0 1 00 0 0 0 0 - Repeat above D Command until 2* nFAW + 2* nRRD - 1 12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2 13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3 14 2*nFAW+4*nRRD D 1 0 0 0 0 3 00 0 0 0 0 - Assert and repeat above D Command until 3* nFAW - 1, if necessary 15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4 16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5 17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6 18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7 19 3*nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 0 0 - Assert and repeat above D Command until 4* nFAW - 1, if necessary

Rev. 0.1 / Nov. 2009 26 IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. IDD Specification Notes: 1. Applicable for MR2 settings A6=0 and A7=0. Temperature range for IDD6 is 0 - 85oC. 2. Applicable for MR2 settings A6=0 and A7=1. Temperature range for IDD6ET is 0 - 95oC. 3. Applicable for MR2 settings A6=1 and A7=0. IDD6TC is measured at 95oC Speed Grade Bin DDR3 - 1066 7-7-7 DDR3 - 1333 9-9-9 Unit Notes Symbol Max. Max. IDD0 75 80 mA x4/x8 IDD01 85 90 mA x4/x8 IDD2P0 10 10 mA x4/x8 IDD2P1 20 20 mA x4/x8 IDD2N 50 55 mA x4/x8 IDD2NT 55 60 mA x4/x8 IDD2Q 50 55 mA x4/x8 IDD3P 35 40 mA x4/x8 IDD3N 55 60 mA x4/x8 IDD4R 115 130 mA x4/x8 IDD4W 115 130 mA x4/x8 IDD5B 175 180 mA x4/x8 IDD6 10 10 mA x4/x8,1 IDD6ET 12 12 mA x4/x8,2 IDD6TC 12 12 mA x4/x8,3 IDD7 170 190 mA x4/x8

Rev. 0.1 / Nov. 2009 27 Input/Output Capacitance Parameter Symbol DDR3L-800 DDR3L-1066 DDR3L-1333 Units Notes Min Max Min Max Min Max Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance delta CK and CK CDCK 0 0.15 0 0.15 0 0.15 pF 2,3,4 Input capacitance delta, DQS and DQS CDDQS 0 0.20 0 0.20 0 0.15 pF 2,3,5 Input capacitance Input capacitance delta Input capacitance delta (All ADD/CMD input-only pins) CDI_ADD_CM D Input/output capacitance delta Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 pF 2,3,12 Notes: 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS. 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE, 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK. 5. Absolute value of CIO(DQS)-CIO(DQS). 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTR applies to ODT, CS and CKE. 8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE. 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS)) 12. Maximum external load capacitance an ZQ pin: 5 pF.

Rev. 0.1 / Nov. 2009 28 Standard Speed Bins DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3L-800 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 31. Speed Bin DDR3-800E Unit Notes CL - nRCD - nRP 6-6-6 Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.5 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CL = 5 CWL = 5 tCK(AVG) Reserved ns 1, 2, 3, 4 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1, 2, 3 Supported CL Settings 6 nCK Supported CWL Settings 5 nCK

Rev. 0.1 / Nov. 2009 29 DDR3L-1066 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 31. Speed Bin DDR3-1066 Unit NoteCL - nRCD - nRP 7-7-7 Parameter Symbol min max Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CL = 5 CWL = 5 tCK(AVG) Reserved ns 1, 2, 3, 4, 5 CWL = 6 tCK(AVG) Reserved ns 4 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1, 2, 3, 5 CWL = 6 tCK(AVG) Reserved ns 1, 2, 3, 4 CL = 7 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4 CL = 8 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1, 2, 3 Supported CL Settings 6, 7, 8 nCK Supported CWL Settings 5, 6 nCK

Rev. 0.1 / Nov. 2009 30 DDR3L-1333 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 31. Speed Bin DDR3-1333 Unit NoteCL - nRCD - nRP 9-9-9 Parameter Symbol min max Internal read command to first data tAA 13.5 (13.125)8 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)8 —n s PRE command period tRP 13.5 (13.125)8 —n s ACT to ACT or REF command period tRC 49.5 (49.125)8 —n s ACT to PRE command period tRAS 36 9 * tREFI ns CL = 5 CWL = 5 tCK(AVG) Reserved ns 1,2, 3,4, 6 CWL = 6, 7 tCK(AVG) Reserved ns 4 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1, 2, 3, 6 CWL = 6 tCK(AVG) Reserved ns 1, 2, 3, 4, 6 CWL = 7 tCK(AVG) Reserved ns 4 CL = 7 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4, 6 Reserved CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4 CL = 8 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1, 2, 3, 6 CWL = 7 tCK(AVG) Reserved ns 1, 2, 3, 4 CL = 9 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1, 2, 3, 4 CL = 10 CWL = 5, 6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1, 2, 3 Reserved ns Supported CL Settings 6, 8, (7), 9, (10) nCK Supported CWL Settings 5, 6, 7 nCK

Rev. 0.1 / Nov. 2009 31 Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.35V +0.100 / - 0.067 V); 1. The CL setting and CWL setting result in tCK(AV G).MIN and tCK(AVG).MAX requirements. When mak- ing a selection of tCK (AVG), both need to be fulf illed: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not pure ly analog - data and strobe output are synchro - nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns], rounding up to the next ‘Supported CL’. 3. tCK(AVG).MAX limits: Calculate tCK (AVG) = t AA.MAX / CLSELECTED and round the resulting tCK tCK(AVG).MAX corresponding to CLSELECTED. 4. ‘Reserved’ settings are not allowed. User must program a different value. 5. Any DDR3-1066 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 6. Any DDR3-1333 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1600 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Hynix DDR3L SRAM devices support down binning to CL=7 and CL=9, and tAA/tRCD/tRP satisfy mini- mum value of 13.125ns. SPD settings are also programmed to match. For example, DDR3 1333H devices supporting down binning to DDR3-1066F shou ld program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR3-1333H or DDR3 1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.

Rev. 0.1 / Nov. 2009 32 Package Dimensions Package Dimension(x4/x8); 78Ball Fine Pitch Ball Grid Array Outline A1 CORNER INDEX AREA (2.750) (1.875) 7.500 0.100± 11.000 0.100± 0.340 0.050± 1.100 0.100± 987 321 A B C D E F G H J K L M N 0.550 0.100± 2.100 0.100± 0.800 X 8 = 6.400 0.800 A1 BALL MARK 1.600 0.800 X 12 = 9.600 0.800 1.600 78xφ0.450 0.050± 0.700 0.100± 0.150 0.050± 2-R0.130 MAX TOP BOTTOM SIDE 3.0 X 5.0 MIN FLAT AREA

Rev. 0.1 / Nov. 2009 33 Package Dimension(x16); 96Ball Fine Pitch Ball Grid Array Outline A1 CORNER INDEX AREA (3.250) (1.875) 7.500 0.100± 13.000 0.100± 0.340 0.050± 1.100 0.100± TOP 98 7 321 A B C D E F G H J K L M N P R T 2.100 0.100± 0.800 X 8 = 6.400 0.800 A1 BALL MARK 1.600 0.800 X 15 = 12.000 0.400 1.600 96xφ0.450 0.050± 0.500 0.100± BOTTOM 0.150 0.050± 2-R0.130 MAX SIDE 0.550 0.100± 3.0 X 5.0 MIN FLAT AREA