Memory

H5MS1G32MFP-J3M

Hynix Semiconductor

1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O

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H5MS1G22MFP-E3M HYNIX

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PDF pages: 63

Technical content

This2document2is2a2general2product2description2and2is2subject2to2change2without2notice.2Hynix2does2not2assume2any2responsibility2for2 use2of2circuits2described.2No2patent2licenses2are2implied. Rev 1.2 / Jun. 2008 1 1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O Specification of 1Gb2(32Mx32bit)2Mobile2DDR2SDRAM Memory Cell Array 2,2Organized2as24banks2of28,388,6082x32

Rev 1.2 / Jun. 2008 2 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Document Title 1GBit (4Bank x 8M x 32bit) MOBILE DDR SDRAM

Revision History

Revision No. History Draft DateRemark 0.1 ,2Initial2Draft Sep.22007 Preliminary 0.2 ,2Defined2IDD62current2spec. Dec.22007 Preliminary 0.3 ,2Insert2IDD82Spec.2value2(see2page23) Dec.22007 P reliminary 0.4 ,2Modify2:2IDD52:2100mA2,,>2120mA 222222222222222IDD62(@45oC,2Full2Bank)2:2450uA2,,>2500uA Jan.22008 Preliminary 1.0 ,2Final2Version Mar.22008 1.1 ,2Modify2:2IDD62(@45oC,2Full2Bank)2:2500uA2,,>2450uA 222222222222222IDD62(@85oC,2One2Bank)2:2550uA2,,>2500uA May.22008 1.2 ,2Insert2DDR4002DC/AC2Characteristics2 Jun.22008

Rev 1.2 / Jun. 2008 3 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series FEATURES SUMMARY

Mobile DDR SDRAM 2,2Double2data2rate2architecture:2two2data2transfer2per2 clock2cycle
Mobile DDR SDRAM INTERFACE 2,2x322bus2width 2,2Multiplexed2Address2(Row2address2and2Column2ad, dress)
SUPPLY VOLTAGE 2,21.8V2device:2VDD2and2VDDQ2=21.7V2to21.95V
MEMORY CELL ARRAY 2,21Gbit2(x322device)2=28M2x24Bank2x2322I/O
DATA STROBE 2,2x322device:2DQS02~2DQS3 2,2Bidirectional,2data2strobe2(DQS)2is2transmitted2and2re, ceived2with2data,2to2be2used2in2capturing2data2at2the2 receiver 2,2Data2and2data2mask2referenced2to2both2edges2of2DQS
LOW POWER FEATURES 2,2PASR2(Partial2Array2Self2Refresh) 2,2AUTO2TCSR2(Temperature2Compensated2Self2Refresh) 2,2DS2(Drive2Strength) 2,2DPD2(Deep2Power2Down):2DPD2is2an2optional2feature, 22222222222so2please2contact2Hynix2office2for2the2DPD2feature
INPUT CLOCK 2,2Differential2clock2inputs2(CK,2CK
Data MASK 2,2DM02~2DM3:2Input2mask2signals2for2write2data 2,2DM2masks2write2data,in2at2the2both2rising2and2 222falling2edges2of2the2data2strobe
MODE RERISTER SET, EXTENDED MODE REGIS- TER SET and STATUS REGISTER READ 2,2Keep2to2the2JEDEC2Standard2regulation2 222(Low2Power2DDR2SDRAM)
CAS LATENCY 2,2Programmable2CAS2latency222or232supported
BURST LENGTH 2,2Programmable2burst2length222/242/282with2both2sequen, tial2and2interleave2mode
AUTO PRECHARGE 2,2Option2for2each2burst2access2
AUTO REFRESH AND SELF REFRESH MODE
CLOCK STOP MODE 2,2Clock2stop2mode2is2a2feature2supported2by2Mobile2DDR2 SDRAM. 2,2Keep2to2the2JEDEC2Standard2regulation2
INITIALIZING THE MOBILE DDR SDRAM 2,2Occurring2at2device2power2up2or2interruption2of2device2 power
Operation Temperature 22222222,2,30oC2~285oC2
PACKAGE 2,2902Ball2Lead2Free2FBGA
ADDRESS TABLE Note)Reduced2Page2size:16,3842rows2by25122columns2by2322bits. Part NumberPage SizeRow Address Column Address H5MS1G22MFP 4KByte A02~2A12 A02~2A9 H5MS1G32MFP1) 2KByte A02~2A13 A02~2A8

Rev 1.2 / Jun. 2008 4 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series

DESCRIPTION

The2Hynix2H5MS1G(2/3)2MFP2Series2is21,073,741,824,bit2CMOS2Low2Power2Double2Data2Rate2Synchronous2DRAM2 (Mobile2DDR2SDRAM),2ideally2suited2for2mobile2applications2which2use2the2battery2such2as2PDAs,22.5G2and23G2cellular2 phones2with2internet2access2and2multimedia2capabilities,2mini,notebook,2hand,held2PCs.2It2is2organized2as24banks2of2 8,388,6082x32. The2HYNIX2H5MS1G(2/3)2MFP2series2uses2a2double,data,rate2architecture2to2achieve2high,speed2operation.2The2dou, ble2data2rate2architecture2is2essentially2a22n2prefetch2architecture2with2an2interface2designed2to2transfer2two2data2per2 clock2cycle2at2the2I/O2pins.2 The2Hynix2H5MS1G(2/3)2MFP2Series2offers2fully2synchronous2operations2referenced2to2both2rising2and2falling2edges2of2 the2clock.2While2all2address2and2control2inputs2are2latched2on2the2rising2edges2of2the2CK2(Mobile2DDR2SDRAM2operates2 from2a2differential2clock:2the2crossing2of2CK2going2HIGH2and2CK2going2LOW2is2referred2to2as2the2positive2edge2of2CK),2 data,2data2strobe2and2data2mask2inputs2are2sampled2on2both2rising2and2falling2edges2of2it2(Input2data2is2registered2on2 both2edges2of2DQS,2and2output2data2is2referenced2to2both2edges2of2DQS,2as2well2as2to2both2edges2of2CK).2The2data2 paths2are2internally2pipelined2and22,bit2prefetched2to2achieve2high2bandwidth.2All2input2voltage2levels2are2compatible2 with2LVCMOS. Read2and2write2accesses2to2the2Low2Power2DDR2SDRAM2(Mobile2DDR2SDRAM)2are2burst2oriented;2accesses2start2at2a2 selected2location2and2continue2for2a2programmed2number2of2locations2in2a2programmed2sequence.2Accesses2begin2with2 the2registration2of2an2ACTIVE2command,2which2is2then2followed2by2a2READ2or2WRITE2command.2The2address2bits2reg, istered2coincident2with2the2ACTIVE2command2are2used2to2select2the2bank2and2the2row2to2be2accessed.2The2address2bits2 registered2coincident2with2the2READ2or2WRITE2command2are2used2to2select2the2bank2and2the2starting2column2location2 for2the2burst2access.2 The2Low2Power2DDR2SDRAM2(Mobile2DDR2SDRAM)2provides2for2programmable2read2or2write2bursts2of22,242or282loca, tions.2An2AUTO2PRECHARGE2function2may2be2enabled2to2provide2a2self,timed2row2precharge2that2is2initiated2at2the2end2 of2the2burst2access.2 As2with2standard2SDRAM,2the2pipelined2and2multibank2architecture2of2Low2Power2DDR2SDRAM2(Mobile2DDR2SDRAM)2 allows2for2concurrent2operation,2thereby2providing2high2effective2bandwidth2by2hiding2row2precharge2and2activation2 times.2 The2Low2Power2DDR2SDRAM2(Mobile2DDR2SDRAM)2also2provides2for2special2programmable2Self2Refresh2options2which2 are2Partial2Array2Self2Refresh2(full,2half,2quarter2and21/82and21/162array)2and2Temperature2Compensated2Self2Refresh.2 A2burst2of2Read2or2Write2cycles2in2progress2can2be2interrupted2and2replaced2by2a2new2burst2Read2or2Write2command2on2 any2cycle2(this2pipelined2design2is2not2restricted2by2a22N2rule).2Only2Read2bursts2in2progress2with2auto2precharge2disa, bled2can2be2terminated2by2a2burst2terminate2command.2Burst2Terminate2command2is2undefined2and2should2not2be2 used2for2Read2with2Autoprecharge2enabled2and2for2Write2bursts.

Rev 1.2 / Jun. 2008 5 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series The2Hynix2H5MS1G(2/3)2MFP2series2has2the2special2Low2Power2function2of2Auto2TCSR2(Temperature2Compensated2 Self2Refresh)2to2reduce2self2refresh2current2consumption.2Since2an2internal2temperature2sensor2is2implemented,2it2ena, bles2to2automatically2adjust2refresh2rate2according2to2temperature2without2external2EMRS2command. Deep2Power2Down2Mode2is2an2additional2operating2mode2for2Low2Power2DDR2SDRAM2(Mobile2DDR2SDRAM).2This2mode2 can2achieve2maximum2power2reduction2by2removing2power2to2the2memory2array2within2Low2Power2DDR2SDRAM2 (Mobile2DDR2SDRAM).2By2using2this2feature,2the2system2can2cut2off2almost2all2DRAM2power2without2adding2the2cost2of2 a2power2switch2and2giving2up2mother,board2power,line2layout2flexibility. All2inputs2are2LVCMOS2compatible.2Devices2will2have2a2VDD2and2VDDQ2supply2of21.8V2(nominal). The2Hynix2H5MS1G(2/3)2MFP2series2is2available2in2the2following2package: 2,290 Ball FBGA [ size : 8mm x 13mm, t=1.0mm max ]

Rev 1.2 / Jun. 2008 6 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series 1Gb Mobile DDR SDRAM ORDERING INFORMATION NOTE 1)2H5MS1G22MFP2:2268,435,456,bit2banks2is2organized2as28,1922rows2by21,0242columns2by2322bits. 2)2H5MS1G32MFP2:2268,435,456,bit2banks2is2organized2as216,3842rows2by25122columns2by2322bits.2,2Reduced2Page2size Part Number Clock FrequencyPage SizeOrganizationInterfacePackage H5MS1G22MFP,E3M1) 200MHz(CL3)2/283MHz(CL2) 4KByte (Normal) 4banks2x28Mb2 x232 LVCMOS 902Ball2FBGA Lead2Free H5MS1G22MFP,J3M1) 166MHz(CL3)2/283MHz(CL2) H5MS1G22MFP,K3M1) 133MHz(CL3)2/283MHz(CL2) H5MS1G22MFP,L3M1) 100MHz(CL3)2/266MHz(CL2) H5MS1G32MFP,E3M2) 200MHz(CL3)2/283MHz(CL2) 2KByte (Reduced) H5MS1G32MFP,J3M2) 166MHz(CL3)2/283MHz(CL2) H5MS1G32MFP,K3M2) 133MHz(CL3)2/283MHz(CL2) H5MS1G32MFP,L3M2) 100MHz(CL3)2/266MHz(CL2)

Rev 1.2 / Jun. 2008 7 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series INFORMATION for Hynix KNOWN GOOD DIE With2the2advent2of2Multi,Chip2package2(MCP),2Package2on2Package2(PoP)2and2System2in2a2Package2(SiP)2applications,2 customer2demand2for2Known2Good2Die2(KGD)2has2increased. Requirements2for2smaller2form2factors2and2higher2memory2densities2are2fueling2the2need2for2Wafer,level2memory2solu, tions2due2to2their2superior2flexibility.2Hynix2Known2Good2Die2(KGD)2products2can2be2used2in2packaging2technologies2 such2as2systems,in,a,package2(SIP)2and2multi,chip2package2(MCP)2to2reduce2the2board2area2required,2making2them2 ideal2for2hand,held2PCs,2and2many2other2portable2digital2applications. Hynix2Mobile2SDRAM2will2be2able2to2continue2its2constant2effort2of2enabling2the2advanced2package2products2of2all2appli, cation2customers. ,2Please2Contact2Hynix2Office2for2Hynix2KGD2product2availability2and2informations.

Rev 1.2 / Jun. 2008 8 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series 90Ball FBGA ASSIGNMENT VSS VDDQ VSSQ VDDQ VSSQ VDD CKE DQ31 DQ29 DQ27 DQ25 DQS3 DM3 CK A11 B C D E F G H A6 A7J A4 DM1K VSSQ DQ30 DQ28 DQ26 DQ24 NC /CK VDDQ DQ17 DQ19 DQ21 DQ23 A13 /WE /CS A10 DQ16 DQ18 DQ20 DQ22 DQS2 DM2 /CAS BA0 DM0 VDD VSSQ VDDQ VSSQ VDDQ VSS /RAS BA1 1 2 3 4 5 6 7 8 9 VSSQ VDDQ VSSQ DQS1 DQ9 DQ11 L M N VDDQ DQ13P VSS DQ15R DQ8 DQ10 DQ12 DQ14 VSSQ DQ7 DQ5 DQ3 DQ1 VDDQ DQS0 DQ6 DQ4 DQ2 DQ0 VDDQ VSSQ VDDQ VSSQ VDD A A12Top view

Rev 1.2 / Jun. 2008 9 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Mobile DDR SDRAM PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CK,2CK INPUT Clock:2CK2and2CK2are2differential2clock2inputs.2All2address2and2control2input2signals2are2 sampled2on2the2crossing2of2the2positive2edge2of2CK2and2negative2edge2of2CK.2Output2(read)2 data2is2referenced2to2the2crossings2of2CK2and2CK2(both2directions2of2crossing).2 CKE INPUT Clock2Enable:2CKE2HIGH2activates,2and2CKE2LOW2deactivates2internal2clock2signals,2device2 input2buffers2and2output2drivers.2Taking2CKE2LOW2provides2PRECHARGE2POWER,DOWN2 and2SELF2REFRESH2operation2(all2banks2idle),2or2ACTIVE2POWER,DOWN2(row2ACTIVE2in2 any2bank).2CKE2is2synchronous2for2all2functions2except2for2SELF2REFRESH2EXIT,2which2is2 achieved2asynchronously. CS INPUT Chip2Select:2CS2enables2(registered2LOW)2and2disables2(registered2HIGH)2the2command2 decoder.2All2commands2are2masked2when2CS2is2registered2HIGH.2CS2provides2for2external2 bank2selection2on2systems2with2multiple2banks.2CS2is2considered2part2of2the2command2 code. RAS,2CAS,2WE INPUT Command2Inputs:2RAS,2CAS2and2WE2(along2with2CS)2define2the2command2being2entered BA0,2BA1 INPUT Bank2Address2Inputs:2BA02and2BA12define2to2which2bank2an2ACTIVE,2READ,2WRITE2or2 PRECHARGE2command2is2being2applied.2BA02and2BA12also2determine2which2mode2register2 is2to2be2loaded2during2a2MODE2REGISTER2SET2command2(MRS,2EMRS2or2SRR). A02~2A13 INPUT Address2inputs:2Provide2the2row2address2for2ACTIVE2commands,2and2the2column2address2 and2AUTO2PRECHARGE2bit2for2READ/WRITE2commands,2to2select2one2location2out2of2the2 memory2array2in2the2respective2bank.2The2address2inputs2also2provide2the2op,code2during2 a2MODE2REGISTER2SET2command.2A102sampled2during2a2PRECHARGE2command2deter, mines2whether2the2PRECHARGE2applies2to2one2bank2(A102LOW)2or2all2banks2(A102HIGH).2 If2only2one2bank2is2to2be2precharged,2the2bank2is2selected2by2BA0,2BA1. For21Gb2(x32),2Row2Address:2A02~2A122and2Column2Address:2A02~2A92with24KByte2page2 size.22Row2Addres2A02~2A132Colum2Address:2A02~2A82with22KByte2page2size. Auto,precharge2flag:2A10 DQ02~2DQ31 I/O Data2Bus:2data2input2/2output2pin DM02~2DM3 INPUT Input2Data2Mask:2DM2is2an2input2mask2signal2for2write2data.2Input2data2is2masked2when2 DM2is2sampled.2HIGH2along2with2that2input2data2during2a2WRITE2access.2DM2is2sampled2 on2both2edges2of2DQS.2Data2Mask2pins2include2dummy2loading2internally,2to2match2the2DQ2 and2DQS2loading.2 For2x322devices,2DM02corresponds2to2the2data2on2DQ0,DQ7,2DM12corresponds2to2the2data2 on2DQ8,DQ15,2DM22corresponds2to2the2data2on2DQ16,DQ23,2and2DM32corresponds2to2the2 data2on2DQ24,DQ31. DQS02~2DQS3 I/O Data2Strobe:2Output2with2read2data,2input2with2write2data.2Edge,aligned2with2read2data,2 center,aligned2with2write2data.2Used2to2capture2write2data.2For2x322device,2DQS02corre, sponds2to2the2data2on2DQ0,DQ7,2DQS12corresponds2to2the2data2on2DQ8,DQ15,2DQS22cor, responds2to2the2data2on2DQ16,DQ23,2and2DQS32corresponds2to2the2data2on2DQ24,DQ31. VDD SUPPLY Power2supply VSS SUPPLY Ground VDDQ SUPPLY I/O2Power2supply VSSQ SUPPLY I/O2Ground NC , No2Connect:2No2internal2electrical2connection2is 2present.

Rev 1.2 / Jun. 2008 10 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series FUNCTIONAL BLOCK DIAGRAM 8Mbit x 4banks x 32 I/O Mobile DDR SDRAM Sense2AMP2&2I/O2Gate Output2Buffer2&2Logic Address Register Mode2Register State2MachineAddress2Buffers Bank2Select Row2Active CAS Latency CLK CKE /CS /RAS /CAS /WE DM0 ~DM3 BA1 BA0 A13 PASR Refresh DQ0 DQ31 Row2decoders Row2decoders Row2decoders Row2decoders Column2decoders 8Mx322Bank0 8Mx322Bank1 8Mx322Bank2 8Mx322Bank3 Memory Cell Array Data2Out2Control Burst Length /CLK 2Input2Buffer2&2Logic DS Data2Strobe Transmitter Data2Strobe Receiver DS DQS0 DQS3 Extended Mode Register Self2refresh logic2&2timer Internal2Row Counter Write2Data2Register 2,bit2Prefetch2Unit Row Pre Decoder Column Pre Decoder Column2Add Counter Burst Counter Column2Active

Rev 1.2 / Jun. 2008 11 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series REGISTER DEFINITION I Mode Register Set (MRS) for Mobile DDR SDRAM BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 02 0 0 0 CAS2Latency BT Burst2Length Burst Type A3 Burst Type

0 Sequential

1 Interleave

A3 = 0 A3=1 20 0 0 Reserved Reserved 20 0 1 2 2 20 1 0 4 4 20 1 1 8 8 21 0 0 Reserved Reserved 21 0 1 Reserved Reserved 21 21 0 Reserved Reserved 21 21 1 Reserved Reserved CAS Latency A6 A5 A4 CAS Latency 0 0222222 0 Reserved 02 022222222 1 Reserved 022222 12222222 0 2 022222 1222222 1 32 122222 02222222 0 Reserved 122222 022222222 1 Reserved 1222222 122222222 0 Reserved2 12222 12222222 1 Reserved222

Rev 1.2 / Jun. 2008 12 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series REGISTER DEFINITION II Extended Mode Register Set (EMRS) for Mobile DDR SDRAM 2222222222222222222222222222222222222222222222222222222222222222222222222222222222 222222222222222222222222222222222222222222222222222222222222222222222222222222 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 0 0 0 0 0 0 DS 0 0 PASR DS (Drive2Strength) A6 A5 Drive Strength 0 0 Full 0 1 Half2(Default) 1 0 Quarter 1 1 Octant PASR (Partial2Array2Self2Refresh) A2 A1 A0 Self Refresh Coverage 0 0 0 All2Banks2(Default) 0 0 1 Half2of2Total2Bank2(BA1=0) 0 1 0 Quarter2of2Total2Bank2(BA1=BA0=0) 0 1 1 Reserved 1 0 0 Reserved 1 0 1 One2Eighth2of2Total2Bank2 (BA12=2BA02=2Row2Address2MSB=0) 1 1 0 One2Sixteenth2of2Total2Bank2 (BA12=2BA02=2Row2Address222MSBs=0) 1 1 1 Reserved

Rev 1.2 / Jun. 2008 13 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series REGISTER DEFINITION III Status Register (SR) for Mobile DDR SDRAM Note) 1.2The2revision2number2starts2at2‘0000’2and2increments2by2‘0001’2each2time2a2change2in2the2manufacturer’s2specification,2IBIS,2or2 222process2occurs. 2.2Low2temperature2out2of2range. 3.2High2temperature2out2of2range2,2no2refresh2rate2can2guarantee2functionality. 4.2The2refresh2rate2multiplier2is2based2on2the2memory’s2temperature2sensor. 5.2Required2average2periodic2refresh2interval2=2tREFI2*2multiplier. 6.2Status2Register2is2only2for2Read.2 7.2To2read2out2Status2Register2values,2BA[1:0]2set2to201b2and2A[13:0]2set2to2all202with2MRS2command2followed2by2Read2command2 with2that2BA[1:0]2and2A[13:0]2are2Don’t2care.2If2the2page2size2is24KByte,2A[12:0]2are2provided. BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DQ15DQ14 DQ13 DQ12 DQ11DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Density , DW Refresh2Rate Revision2Identification Manufa cturers2Identification 0 1 1 0 1 X X X X 1) X1) X1) X1) 0 1 1 0 Density DQ15DQ14 DQ13 Density 0 0 0 128 0 0 1 256 0 1 0 512 0 1 1 1024 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved DW (Device2Width) DQ11 Device Width 0 162bits 1 322bits Refresh Rate DQ10 DQ9 DQ8 Refresh Rate 0 0 x 4 2) 0 1 0 4 0 1 1 2 1 0 0 1 1 0 1 0.5 1 1 0 0.25 1 1 1 0.25 3) Manufacturers Identification DQ3 DQ2 DQ1 DQ0 Manufacturer 0 1 1 0 Hynix x x x x Reserved2or other2companies

Rev 1.2 / Jun. 2008 14 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series COMMAND TRUTH TABLE DM TRUTH TABLE Note: 1.2All2states2and2sequences2not2shown2are2illegal2or2reserved.2 2.2DESLECT2and2NOP2are2functionally2interchangeable. 3.2Autoprecharge2is2non,persistent.2A102High2enables2Autoprecharge,2while2A102Low2disables2Autoprecharge 4.2Burst2Terminate2applies2to2only2Read2bursts2with2auto2precharge2disabled.2This2command2is2undefined2and2should2not2be2used2for2 Read2with2Autoprecharge2enabled,2and2for2Write2bursts. 5.2This2command2is2BURST2TERMINATE2if2CKE2is2High2and2DEEP2POWER2DOWN2entry2if2CKE2is2Low. 6.2If2A102is2low,2bank2address2determines2which2bank2is2to2be2precharged.2If2A102is2high,2all2banks2are2precharged2and2BA0,BA12are2 don't2care. 7.2This2command2is2AUTO2REFRESH2if2CKE2is2High,2and2SELF2REFRESH2if2CKE2is2low. 8.2All2address2inputs2and2I/O2are2''don't2care''2except2for2CKE.2Internal2refresh2counters2control2Bank2and2Row2addressing. 9.2All2banks2must2be2precharged2before2issuing2an2AUTO,REFRESH2or2SELF2REFRESH2command. 10.2BA02and2BA12value2select2among2MRS,2EMRS2and2SRR. 11.2Used2to2mask2write2data,2provided2coincident2with2the2corresponding2data. 12.2CKE2is2HIGH2for2all2commands2shown2except2SELF2REFRESH2and2DEEP2POWER,DOWN. Function CS RAS CAS WE BA A10/AP ADDR Note DESELECT2(NOP) H X X X X X X 2 NO2OPERATION2(NOP) L H H H X X X 2 ACTIVE2(Select2Bank2and2activate2Row) L L H H V Row Row READ2(Select2bank2and2column2and2start2read2burst) L H L H V L Col READ2with2AP2(Read2Burst2with2Autoprecharge) L H L H V H C ol 3 WRITE2(Select2bank2and2column2and2start2write2 burst) L H L L V L Col WRITE2with2AP2(Write2Burst2with2Autoprecharge) L H L L V H Col 3 BURST2TERMINATE2or2enter2DEEP2POWER2DOWN L H H L X X X 4,25 PRECHARGE2(Deactivate2Row2in2selected2bank) L L H L V L X 6 PRECHARGE2ALL2(Deactivate2rows2in2all2Banks) L L H L X H X 6 AUTO2REFRESH2or2enter2SELF2REFRESH L L L H X X X 7,8,9 MODE2REGISTER2SET L L L L V Op2code 10 Function DM DQ Note 2Write2Enable L Valid 11 2Write2Inhibit H X 11

Rev 1.2 / Jun. 2008 15 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series CKE TRUTH TABLE Note: 1.2CKEn2is2the2logic2state2of2CKE2at2clock2edge2n;2CKEn,12was2the2state2of2CKE2at2the2previous2clock2edge. 2.2Current2state2is2the2state2of2LP2DDR2immediately2prior2to2clock2edge2n. 3.2COMMANDn2is2the2command2registered2at2clock2edge2n,2and2ACTIONn2is2the2result2of2COMMANDn. 4.2All2states2and2sequences2not2shown2are2illegal2or2reserved. 5.2DESELECT2and2NOP2are2functionally2interchangeable. 6.2Power2Down2exit2time2(tXP)2should2elapse2before2a2command2other2than2NOP2or2DESELECT2is2issued. 7.2SELF2REFRESH2exit2time2(tXSR)2should2elapse2before2a2command2other2than2NOP2or2DESELECT2is2issued. 8.2The2Deep2Power,Down2exit2procedure2must2be2followed2as2discussed2in2the2Deep2Power,Down2section2of2the2Functional2Description. 9.2The2clock2must2toggle2at2least2one2time2during2the2tXP2period. 10.2The2clock2must2toggle2at2least2once2during2the2tXSR2time. CKEn-1 CKEn Current StateCOMMANDn ACTIONn Note L L Power2Down X Maintain2Power2Down L L Self2Refresh X Maintain2Self2Refresh L L Deep2Power2Down X Maintain2Deep2Power2 Down L H Power2Down NOP2or2DESELECT Exit2Power2Down 5,6,9 L H Self2Refresh NOP2or2DESELECT Exit2Self2Refresh 5,7,1 0 L H Deep2Power2Down NOP2or2DESELECT Exit2Deep2Power2Dow n 5,8 H L All2Banks2Idle NOP2or2DESELECT Precharge2Power2 Down2Entry 5 H L Bank(s)2Active NOP2or2DESELECT Active2Power2Down2 Entry 5 H L All2Banks2Idle AUTO2REFRESH Self2Refresh2entry H L All2Banks2Idle BURST2TERMINATE Enter2Deep2Power2 Down H H See2the2other2Truth2Tables

Rev 1.2 / Jun. 2008 16 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series CURRENT STATE BANKn TRUTH TABLE (COMMAND2TO2BANK2n) Note:2 1.2The2table2applies2when2both2CKEn,12and2CKEn2are2HIGH,2and2after2tXSR2or2tXP2has2been2met2if2the2previous2state2was2Self2Refresh2 or2Power2Down. 2.2DESELECT2and2NOP2are2functionally2interchangeable. 3.2All2states2and2sequences2not2shown2are2illegal2or2reserved. 4.2This2command2may2or2may2not2be2bank2specific.2If2all2banks2are2being2precharged,2they2must2be2in2a2valid2state2for2precharging. 5.2A2command2other2than2NOP2should2not2be2issued2to2the2same2bank2while2a2READ2or2WRITE2Burst2with2auto2precharge2is2enabled.2 6.2The2new2Read2or2Write2command2could2be2auto2precharge2enabled2or2auto2precharge2disabled. Current State Command Action Notes CS RAS CAS WE Description Any H X X X 2DESELECT2(NOP) 2Continue2previous2Operation L H H H 2NOP 2Continue2previous2Operation Idle L L H H 2ACTIVE 2Select2and2activate2row L L L H 2AUTO2REFRESH 2Auto2refresh 10 L L L L 2MODE2REGISTER2SET 2Mode2register2set 10 L L H H 2PRECHARGE 2No2action2if2bank2is2idle Row2Active L H L H 2READ 2Select2Column2&2start2read2burst L H L L 2WRITE 2Select2Column2&2start2write2burst L L H L 2PRECHARGE 2Deactivate2Row2in2bank2(or2banks) 4 Read2 (without2Auto2 recharge) L H L H 2READ 2Truncate2Read2&2 2start2new2Read2burst 5,6 L H L L 2WRITE 2Truncate2Read2&2 2start2new2Write2burst 5,6,13 L L H L 2PRECHARGE 2Truncate2Read,2start2Precharge L H H L 2BURST2TERMINATE 2Burst2terminate 11 Write (without2Auto2 precharge) L H L H 2READ Truncate2Write2&2 start2new2Read2burst 5,6,12 L H L L 2WRITE Truncate2Write2&2 start2new2Write2burst 5,6 L L H L 2PRECHARGE Truncate2Write,2start2Precharge 12

Rev 1.2 / Jun. 2008 17 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series 7.2Current2State2Definitions: 222Idle:2The2bank2has2been2precharged,2and2tRP2has2been2met. 222Row2Active:2A2row2in2the2bank2has2been2activated,2and2tRCD2has2been2met.2 222No2data2bursts/accesses2and2no2register2accesses2are2in2progress. 222Read:2A2READ2burst2has2been2initiated,2with2AUTO2PRECHARGE2disabled,2and2has2not2yet2terminated2or2been2terminated. 222Write:2a2WRITE2burst2has2been2initiated,2with2AUTO2PRECHARGE2disabled,2and2has2not2yet2terminated2or2been2terminated.2 8.2The2following2states2must2not2be2interrupted2by2a2command2issued2to2the2same2bank. 2222DESELECT2or2NOP2commands2or2allowable2commands2to2the2other2bank2should2be2issued2on2any2clock2edge2occurring2 2222during2these2states.2Allowable2commands2to2the2other2bank2are2determined2by2its2current2state2and2Truth2Table3,2 2222and2according2to2Truth2Table24. 2222Precharging:2Starts2with2the2registration2of2a2PRECHARGE2command2and2ends2when2tRP2is2met.2 2222222222222222222222Once2tRP2is2met,2the2bank2will2be2in2the2idle2state. 2222Row2Activating:2Starts2with2registration2of2an2ACTIVE2command2and2ends2when2tRCD2is2met.2 22222222222222222222222222Once2tRCD2is2met,2the2bank2will2be2in2the2''row2active''2state. 2222Read2with2AP2Enabled:2Starts2with2the2registration2of2the2READ2command2with2AUTO2PRECHARGE2enabled2and2ends2 222222222222222222222222222222222222when2tRP2has2been2met.2Once2tRP2has2been2met,2the2bank2will2be2in2the2idle2state. 2222Write2with2AP2Enabled:2Starts2with2registration2of2a2WRITE2command2with2AUTO2PRECHARGE2enabled2and2ends2 2222222222222222222222222222222222222when2tRP2has2been2met.2Once2tRP2is2met,2the2bank2will2be2in2the2idle2state.2 9.2The2following2states2must2not2be2interrupted2by2any2executable2command;2DESELECT2or2NOP2commands2must2be2applied2 2222to2each2positive2clock2edge2during2these2states. 2222Refreshing:2Starts2with2registration2of2an2AUTO2REFRESH2command2and2ends2when2tRFC2is2met.2 22222222222222222222Once2tRFC2is2met,2the2LP2DDR2will2be2in2an2''all2banks2idle''2state. 2222Accessing2Mode2Register:2Starts2with2registration2of2a2MODE2REGISTER2SET2command2and2ends2when2tMRD2has2been2met. 2222222222222222222222222222222222222222Once2tMRD2is2met,2the2LP2DDR2will2be2in2an2''all2banks2idle''2state. 2222Precharging2All:2Starts2with2the2registration2of2a2PRECHARGE2ALL2command2and2ends2when2tRP2is2met.2 22222222222222222222222222Once2tRP2is2met,2the2bank2will2be2in2the2idle2state. 10.2Not2bank,specific;2requires2that2all2banks2are2idle2and2no2bursts2are2in2progress. 11.2Not2bank,specific.2BURST2TERMINATE2affects2the2most2recent2READ2burst,2regardless2of2bank.2 12.2Requires2appropriate2DM2masking. 13.2A2WRITE2command2may2be2applied2after2the2completion2of2the2READ2burst;2otherwise,2a2Burst2terminate2must2be2used2to2end2 22222the2READ2prior2to2asserting2a2WRITE2command.

Rev 1.2 / Jun. 2008 18 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series CURRENT STATE BANKn TRUTH TABLE (COMMAND2TO2BANK2m) Current State Command Action Notes CS RAS CAS WE Description Any H X X X 2DESELECT2(NOP) 2Continue2previous2Operation L H H H 2NOP 2Continue2previous2Operation Idle X X X X 2ANY 2Any2command2allowed2to2bank2m Row2Activating,2 Active,2or2Pre, charging L L H H 2ACTIVE 2Activate2Row L H L H 2READ 2Start2READ2burst 8 L H L L 2WRITE 2Start2WRITE2burst 8 L L H L 2PRECHARGE 2Precharge Read2with2Auto2 Precharge2dis, abled L L H H 2ACTIVE 2Activate2Row L H L H 2READ 2Start2READ2burst 8 L H L L 2WRITE 2Start2WRITE2burst 8,10 L L H L 2PRECHARGE 2Precharge Write2with2Auto2 precharge2dis, abled L L H H 2ACTIVE 2Activate2Row L H L H 2READ 2Start2READ2burst 8,9 L H L L 2WRITE 2Start2WRITE2burst 8 L L H L 2PRECHARGE 2Precharge Read2with2Auto2 Precharge L L H H 2ACTIVE 2Activate2Row L H L H 2READ 2Start2READ2burst 5,8 L H L L 2WRITE 2Start2WRITE2burst 5,8,10 L L H L 2PRECHARGE 2Precharge Write2with2Auto2 precharge L L H H 2ACTIVE 2Activate2Row L H L H 2READ 2Start2READ2burst 5,8 L H L L 2WRITE 2Start2WRITE2burst 5,8 L L H L 2PRECHARGE 2Precharge

Rev 1.2 / Jun. 2008 19 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Note:2 1.2The2table2applies2when2both2CKEn,12and2CKEn2are2HIGH,2and2after2tXSR2or2tXP2has2been2met2if2the2previous2state2was2 222222222222Self2Refresh2or2Power2Down. 2.2DESELECT2and2NOP2are2functionally2interchangeable. 3.2All2states2and2sequences2not2shown2are2illegal2or2reserved. 4.2Current2State2Definitions: 222222222222Idle:2The2bank2has2been2precharged,2and2tRP2has2been2met. 222222222222Row2Active:2A2row2in2the2bank2has2been2activated,2and2tRCD2has2been2met.2No2data2bursts/accesses2and2 222222222222no2register2accesses2are2in2progress. 222222222222Read:2A2READ2burst2has2been2initiated,2with2AUTO2PRECHARGE2disabled,2and2has2not2yet2terminated2or2been2terminated. 222222222222Write:2a2WRITE2burst2has2been2initiated,2with2AUTO2PRECHARGE2disabled,2and2has2not2yet2terminated2or2been2terminated.2 5.2Read2with2AP2enabled2and2Write2with2AP2enabled:2The2read2with2Autoprecharge2enabled2or2Write2with2Autoprecharge2 222222222222enabled2states2can2be2broken2into2two2parts:2the2access2period2and2the2precharge2period.2For2Read2with2AP,2the 222222222222precharge2period2is2defined2as2if2the2same2burst2was2executed2with2Auto2Precharge2disabled2and2then2followed2with2the2 222222222222earliest2possible2PRECHARGE2command2that2still2accesses2all2the2data2in2the2burst.2For2Write2with2Auto2precharge,2the2 222222222222precharge2period2begins2when2tWR2ends,2with2tWR2measured2as2if2Auto2Precharge2was2disabled.2The2access2period2starts2 222222222222with2registration2of2the2command2and2ends2where2the2precharge2period2(or2tRP)2begins.2During2the2precharge2period,2 222222222222of2the2Read2with2Autoprecharge2enabled2or2Write2with2Autoprecharge2enabled2states,2ACTIVE,2PRECHARGE,2READ,2and 222222222222WRITE2commands2to2the2other2bank2may2be2applied;2during2the2access2period,2only2ACTIVE2and2PRECHARGE2commands2 222222222222to2the2other2banks2may2be2applied.2In2either2case,2all2other2related2limitations2apply2(e.g.2contention2between2READ2data2 222222222222and2WRITE2data2must2be2avoided).2 6.2AUTO2REFRESH,2SELF2REFRESH,2and2MODE2REGISTER2SET2commands2may2only2be2issued2when2all2bank2are2idle. 7.2A2BURST2TERMINATE2command2cannot2be2issued2to2another2bank; 222222222222it2applies2to2the2bank2represented2by2the2current2state2only.2 8.2READs2or2WRITEs2listed2in2the2Command2column2include2READs2and2WRITEs2with2AUTO2PRECHARGE2enabled2and2 222222222222READs2and2WRITEs2with2AUTO2PRECHARGE2disabled. 9.2Requires2appropriate2DM2masking. 10.2A2WRITE2command2may2be2applied2after2the2completion2of2data2output,2otherwise2a2BURST2TERMINATE2command2 222222222222must2be2issued2to2end2the2READ2prior2to2asserting2a2WRITE2command.

Rev 1.2 / Jun. 2008 20 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series ABSOLUTE MAXIMUM RATING AC and DC OPERATING CONDITIONS OPERATING CONDITION CLOCK INPUTS (CK,2CK) Address And Command Inputs (A0~An,2BA0,2BA1,2CKE,2CS,2RAS,2CAS,2WE) Data Inputs (DQ,2DM,2DQS) Data Outputs (DQ,2DQS) Parameter Symbol Rating Unit Operating2Case2Temperature TC ,302~285 oC Storage2Temperature TSTG ,552~2150 oC Voltage2on2Any2Pin2relative2to2VSS VIN,2VOUT ,0.32~2VDDQ+0.3 V Voltage2on2VDD2relative2to2VSS VDD ,0.32~22.7 V Voltage2on2VDDQ2relative2to2VSS VDDQ ,0.32~22.7 V Short2Circuit2Output2Current IOS 50 mA Power2Dissipation PD 0.7 W Parameter Symbol Min Typ Max Unit Note Supply2Voltage VDD 1.7 1.8 1.95 V 1 I/O2Supply2Voltage VDDQ 1.7 1.8 1.95 V 1 Operating2Case2Temperature TC ,30 85 oC Parameter Symbol Min Max Unit Note DC2Input2Voltage VIN ,0.3 V DDQ+0.3 V DC2Input2Differential2Voltage VID(DC) 0.4*VDDQ VDDQ+0.6 V 2 AC2Input2Differential2Voltage V ID(AC) 0.6*VDDQ VDDQ+0.6 V 2 AC2Differential2Crosspoint2Voltage VIX 0.4*VDDQ 0.6*VDDQ V 3 Parameter Symbol Min Max Unit Note Input2High2Voltage V IH 0.8*VDDQ VDDQ+0.3 V Input2Low2Voltage VIL ,0.3 0.2*V DDQ V Parameter Symbol Min Max Unit Note DC2Input2High2Voltage V IHD(DC) 0.7*VDDQ VDDQ+0.3 V DC2Input2Low2Voltage VILD(DC) ,0.3 0.3*V DDQ V AC2Input2High2Voltage VIHD(AC) 0.8*VDDQ VDDQ+0.3 V AC2Input2Low2Voltage VILD(AC) ,0.3 0.2*V DDQ V Parameter Symbol Min Max Unit Note DC2Output2High2Voltage2(IOH2=2,0.1mA) V OH 0.9*VDDQ , V DC2Output2Low2Voltage2(IOL2=20.1mA) V OL , 0.1*V DDQ V

Rev 1.2 / Jun. 2008 21 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Leakage Current Note:2 1.2All2voltages2are2referenced2to2VSS2=20V2and2VSSQ2must2be2same2potential2and2VDDQ2must2not2exceed2the2level2of2VDD.2 2.2VID(DC)2and2VID(AC)2are2the2magnitude2of2the2difference2between2the2input2level2on2CK2and2the2input2level2on2CK. 3.2The2value2of2VIX2is2expected2to2be20.5*VDDQ2and2must2track2variations2in2the2DC2level2of2the2same. 4.2VIN2=202to21.8V.2All2other2pins2are2not2tested2under2VIN=0V. 5.2DOUT2is2disabled.2VOUT=202to21.95V.2 AC OPERATING TEST CONDITION Note:21.2The2circuit2shown2on2the2right2represents2the2timing2 load2used2in2defining2the2relevant2timing2parameters2of2 the2part.2It2is2not2intended2to2be2either2a2precise2repre, sentation2of2the2typical2system2environment2nor2a2depic, tion2of2the2actual2load2presented2by2a2production2tester.2 System2designers2will2use2IBIS2or2other2simulation2tools2 to2correlate2the2timing2reference2load2to2system2environ, ment.2Manufacturers2will2correlate2to2their2production2 (generally2a2coaxial2transmission2line2terminated2at2the2 tester2electronics).2For2the2half2strength2driver2with2a2 nominal210pF2load2parameters2tAC2and2tQH2are2 expected2to2be2in2the2same2range.2However,2these2 parameters2are2not2subject2to2production2test2but2are2 estimated2by2design2and2characterization.2Use2of2IBIS2or2other2simulation2tools2for2system2design2validation2is2suggested.2 Input / Output Capacitance Note:2 1.2These2values2are2guaranteed2by2design2and2are2tested2on2a2sample2base2only. 2.2These2capacitance2values2are2for2single2monolithic2devices2only.2Multiple2die2packages2will2have2parallel2capacitive2loads. 3.2Input2capacitance2is2measured2according2to2JEP1472procedure2for2measuring2capacitance2using2a2vector2network2analyzer.2VDD, VDDQ2are2applied2and2all2other2pins2(except2the2pin2under2test)2floating.2DQ's2should2be2in2high2impedance2state.2This2may2be achieved2by2pulling2CKE2to2low2level. 4.2Although2DM2is2an2input,only2pin,2the2input2capacitance2of2this2pin2must2model2the2input2capacitance2of2the2DQ2and2DQS2pins.2This is2required2to2match2signal2propagation2times2of2DQ,2DQS2and2DM2in2the2system. Parameter Symbol Min Max Unit Note 2Input2Leakage2Current I LI ,1 1 uA 4 2Output2Leakage2Current ILO ,1.5 1.5 uA 5 Parameter Symbol Value Unit Note AC2Input2High/Low2Level2Voltage V IH2/2VIL 0.8*VDDQ/0.2*VDDQ V Input2Timing2Measurement2Reference2Level2Voltage V trip 0.5*VDDQ V Input2Rise/Fall2Time tR2/2tF 1 ns Output2Timing2Measurement2Reference2Level2Voltage V outref 0.5*VDDQ V Output2Load2Capacitance2for2Access2Time2Measurement CL pF 1 Parameter Symbol Speed Unit Note Min Max 2Input2capacitance,2CK,2CK CCK 1.5 3.5 pF 2Input2capacitance2delta,2CK,2CK CDCK , 0.25 pF 2Input2capacitance,2all2other2input,only2pins CI 1.5 3 .0 pF 2Input2capacitance2delta,2all2other2input,only2pins CDI , 0.5 pF 2Input/output2capacitance,2DQ,2DM,2DQS CIO 2.0 4.5 pF 4 2Input/output2capacitance2delta,2DQ,2DM,2DQS CDIO , 0. 5 pF 4 Test2Load2for2Full2Drive2Strength2Buffer 222(202pF) Test2Load2for2Half2Drive2Strength2Buffer 222(102pF) Output ZO=50Ω

Rev 1.2 / Jun. 2008 22 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Mobile DDR OUTPUT SLEW RATE CHARACTERRISTICS Note:2 1.2Measured2with2a2test2load2of220pF2connected2to2VSSQ 2.2Output2slew2rate2for2rising2edge2is2measured2between2VILD(DC)2to2VIHD(AC)2and2for2falling2edge2between2VIHD(DC)2to2VILD(AC) 3.2The2ratio2of2pull,up2slew2rate2to2pull,down2slew2rate2is2specified2for2the2same2temperature2and2voltage,2over2the2entire2temperature and2voltage2range.2For2a2given2output,2it2represents2the2maximum2difference2between2pull,up2and2pull,down2drivers2due2to2process variation. Mobile DDR AC OVERSHOOT / UNDERSHOOT SPECIFICATION Note:2 1.2This2specification2is2intended2for2devices2with2no2clamp2protection2and2is2guaranteed2by2design. Parameter Min Max Unit Note Pull,up2and2Pull,Down2Slew2Rate2for2Full2Strength2Driver 0.7 2.5 V/ns 1,22 Pull,up2and2Pull,Down2Slew2Rate2for2Half2Strength2Driver 0.3 1.0 V/ns 1,22 Output2Slew2Rate2Matching2ratio2(Pull,up2to2Pull,down) 0.7 1.4 , 3 Parameter Specification Maximum2peak2amplitude2allowed2for2overshoot 0.5V Maximum2peak2amplitude2allowed2for2undershoot 0.5V The2area2between2overshoot2signal2and2VDD2must2be2less2than2or2equal2to 3V,ns The2area2between2undershoot2signal2and2GND2must2be2less2than2or2equal2to 3V,ns 2.5V 2.0V 1.5V 1.0V 0.5V 0.0V ,0.5V Overshoot Undershoot VDD VSS Max.2Amplitude2=20.5V Max.2Area2=23V,ns Time2(ns) Voltage2(V)

Rev 1.2 / Jun. 2008 23 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series DC CHARACTERISTICS Parameter Symbol Test Condition Max UnitNoteDDR 400 DDR 333 DDR 266 DDR 200 Operating2one2bank2 active,precharge2 current 4KBytes2 Page2Size IDD0 tRC2=2tRC(min);2tCK2=2tCK(min);2CKE2is2HIGH;2 CS2is2HIGH2between2valid2commands;2address2in, puts2are2SWITCHING;2data2bus2inputs2are2STABLE 90 70 60 50 mA 1,26 2KBytes2 Page2Size 80 60 50 50 Precharge2power,down2 standby2current IDD2P all2banks2idle;2CKE2is2LOW;2CS2is2HIGH;2 tCK2=2tCK(min);2address2and2control2inputs2are2 SWITCHING;2data2bus2inputs2are2STABLE 0.4 mA Precharge2power,down standby2current2 with2clock2stop 2IDD2PS all2banks2idle;2CKE2is2LOW;2CS2is2HIGH;2 CK2=2LOW;2CK2=2HIGH;2address2and2control2in, puts2are2SWITCHING;2data2bus2inputs2are2STABLE 0.4 mA Precharge2non2power,down standby2current IDD2N all2banks2idle;2CKE2is2HIGH;2CS2is2HIGH,2 tCK2=2tCK(min);2address2and2control2inputs2are2 SWITCHING;2data2bus2inputs2are2STABLE 15 12 mA Precharge2non2power,down standby2current2 with2clock2stop IDD2NS all2banks2idle;2CKE2is2HIGH;2CS2is2HIGH;2 CK2=2LOW;2CK2=2HIGH;2address2and2control2in, puts2are2SWITCHING;2data2bus2inputs2are2STABLE 8 6 Active2power,down2 standby2current IDD3P one2bank2active;2CKE2is2LOW;2CS2is2HIGH;2 tCK2=2tCK(min);2address2and2control2inputs2are2 SWITCHING;2data2bus2inputs2are2STABLE mA Active2power,down2 standby2current2 with2clock2stop 2IDD3PS one2bank2active;2CKE2is2LOW;2CS 2is2HIGH;2 CK2=2LOW;2CK2=2HIGH;2address2and2control2in, puts2are2SWITCHING;2data2bus2inputs2are2STABLE Active2non2power,down standby2current IDD3N one2bank2active;2CKE2is2HIGH;2CS2is2HIGH;2 tCK2=2tCK(min);2address2and2control2inputs2are2 SWITCHING;2data2bus2inputs2are2STABLE 15 12 mA Active2non2power,down standby2current2 with2clock2stop IDD3NS one2bank2active;2CKE2is2HIGH;2CS2is2HIGH;2 CK2=2LOW;2CK2=2HIGH;2address2and2control2in, puts2are2SWITCHING;2data2bus2inputs2are2STABLE 8 6 mA Operating2burst2read2current IDD4R one2bank2active;2BL=4;2CL=3;2tCK=tCK(min); continuous2read2bursts;2IOUT=0mA;2address2in, puts2are2SWITCHING,250%2data2change2each2 burst2transfer 150 130 110 90 mA Operating2burst2write2current 2IDD4W one2bank2active;2BL=4;2tCK=tCK(min);2continu, ous2write2bursts;2address2inputs2are2SWITCHING;2 50%2data2change2each2burst2transfer 140 120 100 80 mA Auto2Refresh2Current IDD5 tRC=tRFC(min);2tCK=tCK(min);2burst2refresh;2 CKE2is2HIGH;2address2and2control2inputs2are2 SWITCHING;2data2bus2inputs2are2STABLE 120 mA Self2Refresh2Current IDD6 CKE2is2LOW;2CK=LOW;2CK =HIGH;2 Extended2Mode2Register2set2to2all20's;2address2 and2control2inputs2are2STABLE;2data2bus2inputs2 are2STABLE See2Next2Page uA 2 Deep2Power2Down2Current IDD8 Address,2control2and2dat a2bus2inputs2are2STABLE 10 uA 4

Rev 1.2 / Jun. 2008 24 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Note:2 1.2IDD2specifications2are2tested2after2the2device2is2properly2initialized 2.2Input2slew2rate2is21V/ns 3.2Definitions2for2IDD: 2222LOW2is2defined2as2VIN2≤20.12*2VDDQ 2222HIGH2is2defined2as2VIN2≥20.92*2VDDQ 2222STABLE2is2defined2as2inputs2stable2at2a2HIGH2or2LOW2level 2222SWITCHING2is2defined2as 222222222222222,2address2and2command:2inputs2changing2between2HIGH2and2LOW2once2per2two2clock2cycles 222222222222222,2data2bus2inputs:2DQ2changing2between2HIGH2and2LOW2once2per2clock2cycle222222222 2222222222222222222222222222222222222222DM2and2DQS2are2STABLE2 4.2Please2contact2Hynix2office2for2more2information2and2ability2for2DPD2operation.2Deep2Power2Down2operation2is2a2hynix2optional2 function. 5.2All2IDD2values2are2guaranteed2by2full2range2of2operating2voltage2and2temperature.2 2222VDD,2VDDQ2=21.7V2~21.95V.2Temperature2=2,30oC2~2+85oC 6.2H5MS1G22MFP2Series2:24K2Byte2Page2size,2H5MS1G32MFP2Series2:22K2Byte2Page2size DC CHARACTERISTICS -2IDD6 Note:2 1.2Related2numerical2values2in2this245oC2are2examples2for2reference2sample2value2only. 2.2With2a2on,chip2temperature2sensor,2auto2temperature2compensated2self2refresh2will2automatically2adjust2the2interval2of2self,refresh operation2according2to2case2temperature2variations. Temp. (oC) Memory Array Unit

4 Banks 2 Banks 1 Bank

Rev 1.2 / Jun. 2008 25 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series AC CHARACTERISTICS (AC2operating2conditions2unless2otherwise2noted)2(Sheet212of22) Parameter Symbol DDR400 DDR333 DDR266 DDR200 UnitNote Min Max Min Max Min Max Min Max Clock2Half2Period tHP tCL, tCH (Min) tCL, tCH (Min) tCL, tCH (Min) tCL, tCH (Min) , ns 1,2 System2Clock2Cycle2Time 2CL2=23 tCK3 5 , 6.0 , 7.5 , 10 , ns 2CL2=22 tCK2 12 12 12 , 15 , ns DQ2and2DM2Input2Setup2Time tDS 0.54 0.6 0.8 1.1 ns 4,5,6 DQ2and2DM2Input2Hold2Time tDH 0.54 0.6 0.8 1.1 ns 4,5,6 DQ2and2DM2Input2Pulse2Width tDIPW 1.6 , 1.6 , 1.6 , 2.2 , ns 7 Address2and2Control2Input2Setup2Time tIS 0.9 1.1 1.3 1.5 ns 6,8,9 Address2and2Control2Input2Hold2Time tIH 0.9 1.1 1.3 1.5 ns 6,8,9 Address2and2Control2Input2Pulse2Width tIPW 2.2 , 2.2 , 2.6 , 3.0 , ns 7 DQ2&2DQS2Low,impedance2time2from2CK,2CKtLZ 1.0 , 1.0 , 1.0 , 1.0 , ns 10 DQ2&2DQS2High,impedance2time2from2CK,2CKtHZ 5.0 5.0 6.0 7.0 ns 10 DQS2,2DQ2Skew tDQSQ 0.4 0.5 0.6 0.7 ns 11 DQ2/2DQS2output2hold2time2from2DQS tQH tHP2,2 tQHS tHP2,2 tQHS tHP2,2 tQHS tHP2,2 tQHS ns 2 Data2Hold2Skew2Factor tQHS 0.5 0.65 0.75 1.0 ns 2 Write2Command2to21st2DQS2Latching2Transi, DQS2Input2High,Level2Width tDQSH 0.4 0.4 0.4 0.4 tCK DQS2Input2Low,Level2Width tDQSL 0.4 0.4 0.4 0.4 tCK DQS2Falling2Edge2of2CK2Setup2Time tDSS 0.2 0.2 0.2 0.2 tCK DQS2Falling2Edge2Hold2Time2from2CK tDSH 0.2 0.2 0.2 0.2 tCK

Rev 1.2 / Jun. 2008 26 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series AC CHARACTERISTICS (AC2operating2conditions2unless2otherwise2noted)2(Sheet222of22) Parameter Symbol DDR400 DDR333 DDR266 DDR200 UnitNote Min Max Min Max Min Max Min Max MODE2REGISTER2SET2Command2Period tMRD 2 , 2 , 2 , 2 , tCK MRS(SRR)2to2Read2Command2Period tSRR 2 , 2 , 2 , 2 , tCK Minimum2 Time2 between2 Status2 Register Read2to2Next2Valid2Command tSRC CL+1 , CL+1 , CL+1 , CL+1 , tCK Write2Preamble2Setup2Time tWPRES 0 , 0 , 0 , 0 , ns 12 Write2Preamble tWPRE 0.25 , 0.25 , 0.25 , 0.25 , tCK Read2Preamble ACTIVE2to2PRECHARGE2Command2Period tRAS 40 70,00 0 42 70,00 0 45 70,00 0 50 70,00 0 ns ACTIVE2to2ACTIVE2Command2Period tRC 55 , 60 , 75 , 80 , ns AUTO2REFRESH2to2ACTIVE/AUTO2REFRESH2 Command2Period tRFC 110 , 110 , 110 , 110 , ns ACTIVE2to2READ2or2WRITE2Delay tRCD 15 , 18 , 22.5 , 30 , ns 15 PRECHARGE2Command2Period tRP 15 , 18 , 22.5 , 30 , ns 15 ACTIVE2Bank2A2to2ACTIVE2Bank2B2Delay tRRD 10 , 12 , 15 , 15 , ns WRITE2Recovery2Time tWR 15 , 15 , 15 , 15 , ns Auto2Precharge2Write2Recovery2+2Precharge Time tDAL (tWR/tCK)2+2(tRP/tCK) tCK 16 Internal2Write2to2Read2Command2Delay tWTR 2 , 1 , 1 , 1 , tCK Self2Refresh2Exit2to2next2valid2Command2De, lay tXSR 140 , 140 , 140 , 140 , ns Exit2Power2Down2to2next2valid2Command2De, lay tXP tIS2+2 2CLK , tIS2+2 1CLK , tIS2+2 1CLK , tIS2+2 1CLK , ns CKE2 min.2Pulse2Width2(High2and2Low) tCKE 1 , 1 , 1 , 1 , tCK Average2Periodic2Refresh2Interval tREFI , 7.8 , 7.8 , 7.8 , 7.8 us 17 Refresh2Period tREF , 64 , 64 , 64 , 64 ms

Rev 1.2 / Jun. 2008 27 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Note:2 1.2Min2(tCL,2tCH)2refers2to2the2smaller2of2the2actual2clock2low2time2and2the2actual2clock2high2time2as2provided2to2the2device2 222(i.e.2this2value2can2be2greater2than2the2minimum2specification2limits2for2tCL2and2tCH) 2.2tQH2=2tHP2,2tQHS,2where2tHP2=2minimum2half2clock2period2for2any2given2cycle2and2is2defined2by2clock2high2or2clock2low2(tCL,2tCH).2 tQHS2accounts2for21)2the2pulse2duration2distortion2of2on,chip2clock2circuits;2and22)2the2worst2case2push,out2of2DQS2on2one2transition2 followed2by2the2worst2case2pull,in2of2DQ2on2the2next2transition,2both2of2which2are,2separately,2due2to2data2pin2skew2and2output2 pattern2effects,2and2p,channel2to2n,channel2variation2of2the2output2drivers. 3.2The2only2time2that2the2clock2frequency2is2allowed2to2change2is2during2clock2stop,2power,down2or2self,refresh2modes. 4.2The2transition2time2for2DQ,2DM2and2DQS2inputs2is2measured2between2VIL(DC)2to2VIH(AC)2for2rising2input2signals,2and2VIH(DC)2to2 VIL(AC)2for2falling2input2signals. 5.2DQS,2DM2and2DQ2input2slew2rate2is2specified2to2prevent2double2clocking2of2data2and2preserve2setup2and2hold2times.2Signal2transitions2 through2the2DC2region2must2be2monotonic. 6.2Input2slew2rate2≥21.02V/ns.2 7.2These2parameters2guarantee2device2timing2but2they2are2not2necessarily2tested2on2each2device. 8.2The2transition2time2for2address2and2command2inputs2is2measured2between2VIH2and2VIL. 9.2A2CK/CK2differential2slew2rate2of22.02V/ns2is2assumed2for2this2parameter. 10.2tHZ2and2tLZ2transitions2occur2in2the2same2access2time2windows2as2valid2data2transitions.2These2parameters2are2not2referred2to2a2 specific2voltage2level,2but2specify2when2the2device2is2no2longer2driving2(HZ),2or2begins2driving2(LZ). 11.2tDQSQ2consists2of2data2pin2skew2and2output2pattern2effects,2and2p,channel2to2n,channel2variation2of2the2output2drivers2for2any2 given2cycle. 12.2The2specific2requirement2is2that2DQS2be2valid2(HIGH,2LOW,2or2some2point2on2a2valid2transition)2on2or2before2this2CK2edge.2A2valid2 transition2is2defined2as2monotonic2and2meeting2the2input2slew2rate2specifications2of2the2device.2When2no2writes2were2previously2in2 progress2on2the2bus,2DQS2will2be2transitioning2from2Hi,Z2to2logic2LOW.2If2a2previous2write2was2in2progress,2DQS2could2be2HIGH,2 LOW,2or2transitioning2from2HIGH2to2LOW2at2this2time,2depending2on2tDQSS. 13.2The2maximum2limit2for2this2parameter2is2not2a2device2limit.2The2device2operates2with2a2greater2value2for2this2parameter,2but2system2 performance2(bus2turnaround)2will2degrade2accordingly. 14.2A2low2level2on2DQS2may2be2maintained2during2High,Z2states2(DQS2drivers2disabled)2by2adding2a2weak2pull,down2element2in2the2 system.2It2is2recommended2to2turn2off2the2weak2pull,down2element2during2read2and2write2bursts2(DQS2drivers2enabled). 15.2Speed2bin2(CL,tRCD,tRP)2=23,3,3 16.2Minimum23CLK2of2tDAL(=2tWR+tRP)2is2required2because2it2need2minimum22CLK2for2tWR2and2minimum21CLK2for2tRP. 2222tDAL2=2(tWR/tCK)2+2(tRP/tCK):2for2each2of2the2terms2above,2if2not2already2an2integer,2round2to2the2next2higher2integer. 17.2A2maximum2of2eight2Refresh2commands2can2be2posted2to2any2given2Low2Power2DDR2SDRAM2(Mobile2DDR2SDRAM),2meaning2that2 the2maximum2absolute2interval2between2any2Refresh2command2and2the2next2Refresh2command2is28*tREFI. 18.2All2AC2parameters2are2guaranteed2by2full2range2of2operating2voltage2and2temperature.2 2222VDD,2VDDQ2=21.7V2~21.95V.2Temperature2=2,30oC ~ 85oC

Rev 1.2 / Jun. 2008 28 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Mobile DDR SDRAM OPERATION State2Diagram IDLE ALL2BANK PCG. AUTO REFRESH SELF REFRESH PCG. POWER DOWN (E)MRS SET WRITE READ Precharge ALL ACTIVE POWER DOWN ROW ACTIVE MRS, EMRS REFS CKEL REFA CKEH ACT CKEL CKEH WRITE WRITE READ REFSX COMMAND2Input AUTOMATIC Sequence DEEP POWER DOWN POWER ON PCG. ALL BANKS Power applied DPDS DPDSX BURST STOP WRITEA READ READA BST READ2AWRITE2A WRITEA READA READ PRE PRE PRE SRR READ SRR READ READA ACT2: Active BST2:2 Burst CKEL2:2 Enter2Power,Down CKEH2:2 Exit2Power,Down DPDS2:2 Enter2Deep2 Power,Down DPDSX2:2 Exit2Deep2Power, DownEMRS EMRS2:2 Ext.2Mode2Reg.2 Set MRS2:2 Mode2Register2Set PRE2:2 Precharge PREALL2: 2Precharge2All2 Banks REFA22:2 Auto2Refresh REFS2:2 Enter2Self2Refresh REFSX2:2 Exit2Self2Refresh READ2:2 Read2w/o2Auto2 Precharge READA2:2 Read2with2Auto2 Precharge WRITE2:2 Write2w/o2Auto2 Precharge WRITEA2:2 Write2with2Auto2 Precharge SRR2:2 Status2Register2 Read

Rev 1.2 / Jun. 2008 29 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series DESELECT The2DESELECT2function2(CS2=2High)2prevents2new2commands2from2being2executed2by2the2Mobile2DDR2SDRAM.2The2 Mobile2DDR2SDRAM2is2effectively2deselected.2Operations2already2in2progress2are2not2affected. NO2OPERATION The2NO2OPERATION2(NOP)2command2is2used2to2perform2a2NOP2to2a2Mobile2DDR2SDRAM2that2is2selected2(CS2=2Low).2 This2prevents2unwanted2commands2from2being2registered2during2idle2or2wait2states.2Operations2already2in2progress2are2 not2affected.2(see2to2next2figure) ACTIVE The2Active2command2is2used2to2activate2a2row2in2a2particular2bank2for2a2subsequent2Read2or2Write2access.2The2value2of2 the2BA0,BA12inputs2selects2the2bank,2and2the2address2provided2on2A0,A132(only22KByte2page2size.2If2the24KBytes2page2 size,2A0~A122are2provided)2selects2the2row.2(see2to2next2figure) Before2any2READ2or2WRITE2commands2can2be2issued2to2a2bank2within2the2Mobile2DDR2SDRAM,2a2row2in2that2bank2 must2be2opened.2This2is2accomplished2via2the2ACTIVE2command,2which2selects2both2the2bank2and2the2row2to2be2acti, vated. The2row2remains2active2until2a2PRECHARGE2(or2READ2with2AUTO2PRECHARGE2or2WRITE2with2AUTO2PRECHARGE)2com, mand2is2issued2to2the2bank. A2PRECHARGE2(or2READ2with2AUTO2PRECHARGE2or2WRITE2with2AUTO2PRECHARGE)2command2must2be2issued2before2 opening2a2different2row2in2the2same2bank. CS A0~A13 WE CAS Don't Care CLK CLK CKE BA0,BA1 Bank Address Row Address Don't Care RA BA NOP2Command ACTIVE2Command RAS CS A0~A13 WE CAS CLK CLK CKE BA0, BA1 RAS (High) (High)

Rev 1.2 / Jun. 2008 30 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Once2a2row2is2Open2(with2an2ACTIVE2command)2a2READ2or2WRITE2command2may2be2issued2to2that2row,2subject2to2the2 tRCD2specification.2tRCD2(MIN)2should2be2divided2by2the2clock2period2and2rounded2up2to2the2next2whole2number2to2 determine2the2earliest2clock2edge2after2the2ACTIVE2command2on2which2a2READ2or2WRITE2command2can2be2entered.2 A2subsequent2ACTIVE2command2to2a2different2row2in2the2same2bank2can2only2be2issued2after2the2previous2active2row2 has2been2closed2(precharge).2The2minimum2time2interval2between2successive2ACTIVE2commands2to2the2same2bank2is2 defined2by2tRC. A2subsequent2ACTIVE2command2to2another2bank2can2be2issued2while2the2first2bank2is2being2accessed,2which2results2in2 a2reduction2of2total2row,access2overhead.2The2minimum2time2interval2between2successive2ACTIVE2commands2to2differ, ent2banks2is2defined2by2tRRD. Don't Care Once2a2row2is2Open(with2an2ACTIVE2command)2a2READ2o r2WRITE2command2may2be2issued2to2that2row,2subject2 to2the2 tRCD2specification.2tRCD2(MIN)2should2be2divided2by 2the2clock2period2and2rounded2up2to2the2next2whole2 number2to2 determine2the2earliest2clock2edge2after2the2ACTIVE2 command2on2which2a2READ2or2WRITE2command2can2be2ent ered. /CLK CLK NOP NOPNOPNOP tRCD Command Address Write2A With2A/P Bank2B ACT NOPBank2A ACT Bank2A Col Bank2B Row Bank2A Row Bank2A ACT Bank2A Row tRRD tRC

Rev 1.2 / Jun. 2008 31 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series READ2/2WRITE2COMMAND The2READ2command2is2used2to2initiate2a2Burst2Read2to2an2active2row.2The2value2of2BA02and2BA12selects2the2bank2and2 address2inputs2select2the2starting2column2location.2 The2value2of2A102determines2whether2or2not2auto2precharge2is2used.2If2auto2precharge2is2selected,2the2row2being2 accessed2will2be2precharged2at2the2end2of2the2read2burst;2if2auto2precharge2is2not2selected,2the2row2will2remain2open2 for2subsequent2access.2The2valid2data,out2elements2will2be2available2CAS2latency2after2the2READ2command2is2issued.2 The2Mobile2DDR2drives2the2DQS2during2read2operations.2The2initial2low2state2of2the2DQS2is2known2as2the2read2preamble2 and2the2last2data,out2element2is2coincident2with2the2read2postamble.2DQS2is2edge,aligned2with2read2data.2Upon2com, pletion2of2a2burst,2assuming2no2new2READ2commands2have2been2initiated,2the2I/O's2will2go2high,Z. The2WRITE2command2is2used2to2initiate2a2Burst2Write2access2to2an2active2row.2The2value2of2BA0,2BA12selects2the2bank2 and2address2inputs2select2the2starting2column2location.2 The2value2of2A102determines2whether2or2not2auto2precharge2is2used.If2auto2precharge2is2selected,2the2row2being2 accessed2will2be2precharged2at2the2end2of2the2write2burst;2if2auto2precharge2is2not2selected,2the2row2will2remain2open2 for2subsequent2access.2Input2data2appearing2on2the2data2bus,2is2written2to2the2memory2array2subject2to2the2DM2input2 logic2level2appearing2coincident2with2the2data.2If2a2given2DM2signal2is2registered2low,2the2corresponding2data2will2be2 written2to2the2memory;2if2the2DM2signal2is2registered2high,2the2corresponding2data,inputs2will2be2ignored,2and2a2write2 will2not2be2executed2to2that2byte/column2location.2The2memory2controller2drives2the2DQS2during2write2operations.2The2 initial2low2state2of2the2DQS2is2known2as2the2write2preamble2and2the2low2state2following2the2last2data,in2element2is2write2 postamble.2Upon2completion2of2a2burst,2assuming2no2new2commands2have2been2initiated,2the2I/O's2will2stay2high,Z2 and2any2additional2input2data2will2be2ignored. When2READ2or2WRITE2command2issues,2the2A0~A82(column2address)2are2provided2if2only22KBytes2page2size2as2shown2 below2figure.2If2the2page2size2is24KBytes,2the2A0~A92(column2address)2are2provided.2 22222222222222222222222222222222222222222222222222222222222222222222222READ2/2WRITE2COMMAND Don't Care CA BA High to enable Auto Precharge Low to disable Auto Precharge Read Command Write Command CA BA CLK CLK CKE CLK CLK CKE (High) (High) CS A0~A8 WE CAS A10 RAS BA0, BA1 CS A0~A8 WE CAS A10 RAS BA0, BA1

Rev 1.2 / Jun. 2008 32 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series READ The2basic2Read2timing2parameters2for2DQ2are2shown2next2figure2(Basic2Read2Timing2Parameters).2They2apply2to2all2 Read2operations.2During2Read2bursts,2DQS2is2driven2by2the2Mobile2DDR2SDRAM2along2with2the2output2data.2The2initial2 Low2state2of2the2DQS2is2known2as2the2read2preamble;2the2Low2state2coincident2with2last2data,out2element2is2known2as2 the2read2postamble.2 222222222222222222222222222222222222222222222222222222Basic2Read2Timing2Parameters Don Don+1 Don+2 Don+3 /CLK CLK tCK tCK tCH tCL tRPRE tDQSCK tDQSQ max tAC tLZ tQH tDQSCK tQH tQH tHZ tQH tRPRE tDQSCK tLZ tDQSCK tRPST tAC tDQSQ2max Don Don+1 Don+2 Don+3 DQS DQ DQS DQ Don't Care 1)2Do2n 2:2Data2Out2from2column2n 2)2All2DQ2are2vaild2tAC2after2the2CK2edge 2222All2DQ2are2vaild2tDQSQ2after2the2DQS2edge,2rega rdless2of2tAC2 tRPSTtACm ax tACm in tQH tHZ

Rev 1.2 / Jun. 2008 33 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series The2first2data,out2element2is2edge2aligned2with2the2first2rising2edge2of2DQS2and2the2successive2data,out2elements2are2 edge2aligned2to2successive2edges2of2DQS.2This2is2shown2in2next2figure2with2a2CAS2latency2of222and23.2 Upon2completion2of2a2read2burst,2assuming2no2other2READ2command2has2been2initiated,2the2DQ2will2go2to2High,Z. 22222222222222222222222222222222222222222222222222Read2Burst2Showing2CAS2Latency /CLK CLK Don Don READ NOP NOP NOP NOP NOP BA,2 Col2n CL2=3 CL2=2 Don't2Care 1)2Don 2:2Data2out2from2column2n 2)2BA,2Col2n 2=2Bank2A,2Column2n 3)2Burst2Length2=24;232subseqnent2elements2of2Data2Out2appear2in2the2programmed2order2following2Do2n 4)2Shown2with2nominal2tAC,2tDQSCK2and2tDQSQ Command Address DQS DQ DQS DQ

Rev 1.2 / Jun. 2008 34 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series READ2to2READ Data2from2a2read2burst2may2be2concatenated2or2truncated2by2a2subsequent2READ2command.2The2first2data2from2the2 new2burst2follows2either2the2last2element2of2a2completed2burst2or2the2last2desired2element2of2a2longer2burst2that2is2 being2truncated.2The2new2READ2command2should2be2issued2X2cycles2after2the2first2READ2command,2where2X2equals2 the2number2of2desired2data,out2element2pairs2(pairs2are2required2by2the22n2prefetch2architecture). 222222222222222222222222222222222222222222222222222222222222222Consecutive2Read2Bursts A2READ2command2can2be2initiated2on2any2clock2cycle2following2a2previous2READ2command.2Non,consecutive2Reads2are2 shown2in2the2first2figure2of2next2page.2Random2read2accesses2within2a2page2or2pages2can2be2performed2as2shown2in2 second2figure2of2next2page. /CLK CLK Don Don READ NOP READ NOP NOP NOP BA,2 Col2n CL2=3 CL2=2 Don't2Care 1)2Don 2(or2b ):2Data2out2from2column2n2(or2column2b) 2)2BA,2Col2n2(b) 2=2Bank2A,2Column2n2(b) 3)2Burst2Length2=242or282(if24,2the2bursts2are2conc atenated;2if28,2the2second2burst2interrupts2the2fir st) 4)2Read2bursts2are2to2an2active2row2in2any2bank 5)2Shown2with2nominal2tAC,2tDQSCK2and2tDQSQ Command Address DQS DQ DQS DQ BA,2 Col2b Dob Dob

Rev 1.2 / Jun. 2008 35 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series 22222222222222222222222222222222222222222222222222222222222222Non,Consecutive2Read2Bursts 22222222222222222222222222222222222222222222222222222222222222222Random2Read2Bursts /CLK CLK Do n Do n READ NOP NOP READ NOP NOP BA,2 Col2n CL2=3 CL2=2 Don't2Care 1)2Do n 2(or2b ):2Data2out2from2column2n2(or2column2b) 2)2BA,2Col2 n2(b) 2=2Bank2A,2Column2n2(b) 3)2Burst2Length2=24;232subsequent2elements2of2Data2 Out2appear2in2the2programmed2order2following2Do2 n2(b) 4)2Shown2with2nominal2tAC,2tDQSCK2and2tDQSQ Comm and Address DQS DQ DQS DQ BA,2 Col2b Do b /CLK CLK D on D ox'Do n READ READ READ READ NO P NO P BA,2 Col2 n CL2= 3 CL2= 2 Don't2Care 1)2D on, 2etc:2D ata2out2from 2colum n2n,2etc 2222222222222222222n',2x',2etc2:2Data2O ut2elem ents, 2accoding2to2the2program m d2burst2order 2)2BA,2Col2 n 2= 2Bank2A,2Colum n2n 3)2Burst2Length2= 22,242or282in2cases2show n2(if2burs t2of242or28,2the2burst2is2interrupted) 4)2Read2are2to2active2row s2in2any2banks Com m and Address DQ S D Q DQ S D Q BA,2 Col2 b D ob BA,2 Col2 x BA,2 Col2 g Do n' D ox D ox' Do b' D og D og' Do n' D ox Do b Do b'

Rev 1.2 / Jun. 2008 36 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series READ2BURST2TERMINATE Data2from2any2READ2burst2may2be2truncated2with2a2BURST2TERMINATE2command.2The2BURST2TERMINATE2latency2is2 equal2to2the2read2(CAS)2latency,2i.e.,2the2BURST2TERMINATE2command2should2be2issued2X2cycles2after2the2READ2com, mand2where2X2equals2the2desired2data,out2element2pairs. 2222222222222222222222222222222222222222222222222222222222Terminating2a2Read2Burst /CLK CLK READ BURST Terminate NOP NOP NOP NOP BA,2 Col2n CL2=3 CL2=2 Don't2Care 1)2Don 2:2Data2out2from2column2n 2)2BA,2Col2n2 =2Bank2A,2Column2n 3)2Cases2shown2are2bursts2of242or282terminated2afte r222data2elements 4)2Shown2with2nominal2tAC,2tDQSCK2and2tDQSQ Command Address DQS DQ DQS DQ

Rev 1.2 / Jun. 2008 37 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series READ2to2WRITE Data2from2READ2burst2must2be2completed2or2truncated2before2a2subsequent2WRITE2command2can2be2issued.2If2trun, cation2is2necessary,2the2BURST2TERMINATE2command2must2be2used,2as2shown2in2next2fig.2for2the2case2of2nominal2 tDQSS. 22222222222222222222222222222222222222222222222222222222222222222Read2to2Write /CLK CLK Don Don READ BST NOP WRITE NOP BA,2 Col2n CL2=3 CL2=2 Don't2Care 1)2DO2n 2=2Data2Out2from2column2n;2DI2b2=2Data2In2to2column 2b 2)2Burst2length2=242or282in2the2cases2shown;2if2the 2burst2length2is22,2the2BST2command2can2be2ommitted 3)2Shown2with2nominal2tAC,2tDQSCK2and2tDQSQ Command Address DQS DQ DQS DQ BA,2 Col2b NOP DM READ BST NOP NOP NOP BA,2 Col2n Command Address BA,2 Col2b WRITE tDQSS DI2b DI2b

Rev 1.2 / Jun. 2008 38 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series READ2to2PRECHARGE A2Read2burst2may2be2followed2by2or2truncated2with2a2PRECHARGE2command2to2the2same2bank2(provided2Auto2Pre, charge2was2not2activated).2The2PRECHARGE2command2should2be2issued2X2cycles2after2the2READ2command,2where2X2 equal2the2number2of2desired2data,out2element2pairs.2 Following2the2PRECHARGE2command,2a2subsequent2command2to2the2same2bank2cannot2be2issued2until2tRP2is2met.2 Note2that2part2of2the2row2precharge2time2is2hidden2during2the2access2of2the2last2data,out2elements.In2the2case2of2a2 Read2being2executed2to2completion,2a2PRECHARGE2command2issued2at2the2optimum2time2(as2described2above)2pro, vides2the2same2operation2that2would2result2from2Read2burst2with2Auto2Precharge2enabled.2 The2disadvantage2of2the2PRECHARGE2command2is2that2it2requires2that2the2command2and2address2buses2be2available2at2 the2appropriate2time2to2issue2the2command.2The2advantage2of2the2PRECHARGE2command2is2that2it2can2be2used2to2 truncate2bursts. 222222222222222222222222222222222222222222222222222222222222READ2to2PRECHARGE /CLK CLK Don Don READ NOP PRE NOP NOP ACT BA,2 Col2n CL2=3 CL2=2 Don't2Care 1)2DO2n 2=2Data2Out2from2column2n 2)2Cases2shown2are2either2uninterrupted2burst2of24, 2or2interrupted2bursts2of28 3)2Shown2with2nominal2tAC,2tDQSCK2and2tDQSQ 4)2Precharge2may2be2applied2at2(BL2/22)2tCK2after2the2READ2command. 5)2Note2that2Precharge2may2not2be2issued2before2tRA S2ns2after2the2ACTIVE2command2for2applicable2banks. 6)2The2ACTIVE2command2may2be2applied2if2tRC2has2been2met. Command Address DQS DQ DQS DQ Bank2 (A2or2All) BA,2 Row tRP

Rev 1.2 / Jun. 2008 39 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Write Input2data2appearing2on2the2data2bus,2is2written2to2the2memory2array2subject2to2the2DM2input2logic2level2appearing2 coincident2with2the2data.2If2a2given2DM2signal2is2registered2Low,2the2corresponding2data2will2be2written2to2the2memory;2 if2the2DM2signal2is2registered2High,2the2corresponding2data2inputs2will2be2ignored,2and2a2write2will2not2be2executed2to2 that2byte2/2column2location. Basic2Write2timing2parameters2for2DQ2are2shown2in2Figure;2they2apply2to2all2Write2operations. 22222222222222222222222222222222222222222222222222222Basic2Write2Timing2Parameters During2Write2bursts,2the2first2valid2data,in2element2will2be2registered2on2the2first2rising2edge2of2DQS2following2the2 WRITE2command,2and2the2subsequent2data2elements2will2be2registered2on2successive2edges2of2DQS.2The2Low2state2of2 DQS2between2the2WRITE2command2and2the2first2rising2edge2is2called2the2write2preamble,2and2the2Low2state2on2DQS2 following2the2last2data,in2element2is2called2the2write2postamble.2 The2time2between2the2WRITE2command2and2the2first2corresponding2rising2edge2of2DQS2(tDQSS)2is2specified2with2a2rel, atively2wide2range2,2from275%2to2125%2of2a2clock2cycle.2Next2fig.2shows2the2two2extremes2of2tDQSS2for2a2burst2of24.2 Upon2completion2of2a2burst,2assuming2no2other2commands2have2been2initiated,2the2DQ2will2remain2high,Z2and2any2 additional2input2data2will2be2ignored. /CLK CLK tCK tCH tCL DI2n DI2n DQS DQS DQ,2DM DQ,2DM tDQSS tDQSH tDSH tDSH tWPST tWPRES tDS tDH tWPRE tDS tDH tWPRES tWPRE tDQSS tDQSH tWPST tDSS tDSS tDQSL Don't Care 1)2DI2n:2Data2in2for2column2n 2)232subsequent2elements2of2Data2in2are2applied2in2 the2programmed2order2following2DI2n 3)2tDQSS2:2each2rising2edge2of2DQS2must2fall2within 2the2+/,252(percentage)2window2of2the2corresponding 2positive2clock2edge tDQSL Case21: tDQSS2=2min Case22: tDQSS2=2max

Rev 1.2 / Jun. 2008 40 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series 222222222222222222222222222222222222222222222222222Write2Burst2(min.2and2max.2tDQSS) /CLK CLK WRITE NOP NOP NOP NOP BA,2 Col2b tDQSS min Don't2Care 1)2DI2b2=2Data2In2to2column2b 2)232subsequent2elements2of2Data2In2are2applied2in2 the2programmed2order2following2DI2b 3)2A2non,interrupted2burst2of242is2shown 4)2A102is2low2with2the2WRITE2command2(Auto2Precharg e2is2disabled) Command Address DQS DQ DQS DQ NOP DM DM tDQSS max

Rev 1.2 / Jun. 2008 41 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series WRITE2to2WRITE Data2for2any2WRITE2burst2may2be2concatenated2with2or2truncated2with2a2subsequent2WRITE2command.2In2either2case,2 a2continuous2flow2of2input2data,2can2be2maintained.2The2new2WRITE2command2can2be2issued2on2any2positive2edge2of2 the2clock2following2the2previous2WRITE2command.The2first2data,in2element2from2the2new2burst2is2applied2after2either2 the2last2element2of2a2completed2burst2or2the2last2desired2data2element2of2a2longer2burst2which2is2being2truncated.2The2 new2WRITE2command2should2be2issued2X2cycles2after2the2first2WRITE2command,2where2X2equals2the2number2of2 desired2data,in2element2pairs. 2222222222222222222222222222222222222222222222222222222222Concatenated2Write2Bursts /CLK CLK WRITE NOP WRITE NOP NOP BA,2 Col2b tDQSSmin Don't2Care 1)2DI2b 2(n )2=2Data2In2to2column2b2(column2n) 2)232subsequent2elements2of2Data2In2are2applied2in2the2programmed2order2following2DI2b.2 222232subsequent2elements2of2Data2In2are2applied2in2the2programmed2order2following2DI2n. 3)2Non,interrupted2bursts2of242are2shown. 4)2Each2WRITE2command2may2be2to2any2active2bank Command Address DQS DQ DQS DQ NOP DM DM BA,2 Col2n DI b DI n DI b DI n tDQSSmax

Rev 1.2 / Jun. 2008 42 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series 222222222222222222222222222222222222222222222222222Non,Concatenated2Write2Bursts 2222222222222222222222222222222222222222222222222222222222222Random2Write2Cycles /CLK CLK WRITE NOP NOP WRITE NOP BA,2 Col2b Don't2Care 1)2DI2b 2(n )2=2Data2In2to2column2b2(or2column2n). 2)232subsequent2elements2of2Data2In2are2applied2in2 the2programmed2order2following2DI2 b 222232subsequent2elements2of2Data2In2are2applied2in 2the2programmed2order2following2DI2 n 3)2Non,interrupted2bursts2of242are2shown. 4)2Each2WRITE2command2may2be2to2any2active2bank2and 2may2be2to2the2same2or2different2devices. Command Address DQS DQ NOP DI b DM tDQSS max DI n BA,2 Col2n /CLK CLK WRITE WRITE WRITE WRITE NOP BA,2 Col2b Don't2Care 1)2DI2b2etc.2=2Data2In2to2column2b,2etc.2 ;2b',2etc.2=2the2next2Data2In2following2DI2b,2etc.2 according2to2the2programmed2burst2order 2)2Programmed2burst2length2=22,242or282in2cases2sho wn.2If2burst2of242or28,2burst2would2be2truncated. 3)2Each2WRITE2command2may2be2to2any2active2bank2and 2may2be2to2the2same2or2different2devices. Command Address WRITE BA,2 Col2n BA,2 Col2x BA,2 Col2a BA,2 Col2g DQS DM tDQSS max DQ Di b Di Di x Di Di n Di Di a Di

Rev 1.2 / Jun. 2008 43 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series WRITE2to2READ Data2for2any2Write2burst2may2be2followed2by2a2subsequent2READ2command.2To2follow2a2Write2without2truncating2the2 write2burst,2tWTR2should2be2met2as2shown2in2Figure.2 Data2for2any2Write2burst2may2be2truncated2by2a2subsequent2READ2command2as2shown2in2Figure.2Note2that2the2only2 data,in2pairs2that2are2registered2prior2to2the2tWTR2period2are2written2to2the2internal2array,2and2any2subsequent2data,in2 must2be2masked2with2DM. /CLK CLK WRITE NOP NOP NOP NOP BA,2 Col2b Don't2Care 1)2DI2b 2=2Data2In2to2column2b2.232subsequent2elements2of2Data2In2are2applied2in2the2programmed2order2following2DI2b. 2)2A2non,interrupted2burst2of242is2shown. 3)2tWTR2is2referenced2from2the2positive2clock2edge2after2the2last2Data2In2pair. 4)2A102is2LOW2with2the2WRITE2command2(Auto2Precharge2is2disabled) 5)2The2READ2and2WRITE2commands2are2to2the2same2device2but2not2necessarily2to2the2same2bank. Command Address DQS DQ READ DM tDQSSmax BA,2 Col2n tWTR CL=3 NOP Di b

Rev 1.2 / Jun. 2008 44 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series 2222222222222222222222222222222222222222222222222222222Interrupting2Write2to2Read /CLK CLK WRITE NOP NOP READ NOP BA,2 Col2b Don't2Care 1)2DI2b 2=2Data2In2to2column2b.2DO2n 2=2Data2Out2from2column2n. 2)2An2interrupted2burst2of242is2shown,222data2elements2are2written.2 222232subsequent2elements2of2Data2In2are2applied2in2the2programmed2order2following2DI2b. 3)2tWTR2is2referenced2from2the2positive2clock2edge2after2the2last2Data2In2pair. 4)2A102is2LOW2with2the2WRITE2command2(Auto2Precharge2is2disabled) 5)2The2READ2and2WRITE2commands2are2to2the2same2device2but2not2necessarily2to2the2same2bank. Command Address DQS DQ NOP DM tDQSSmax tWTR CL=3 NOP DI b BA,2 Col2n Don

Rev 1.2 / Jun. 2008 45 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series WRITE2to2PRECHARGE Data2for2any2WRITE2burst2may2be2followed2by2a2subsequent2PRECHARGE2command2to2the2same2bank2(provided2Auto2 Precharge2was2not2activated).2To2follow2a2WRITE2without2truncating2the2WRITE2burst,2tWR2should2be2met2as2shown2in2 Fig. 2222222222222222222222222222222222222222222222222222222Non,Interrupting2Write2to2Precharge /CLK CLK WRITE NOP NOP NOP PRE BA,2 Col2b Don't2Care 1)2DI2b2(n)2=2Data2In2to2column2b2(column2n) 222232subsequent2elements2of2Data2In2are2applied2in2the2programmed2order2following2DI2b.2 2)2A2non,interrupted2bursts2of242are2shown. 3)2tWR2is2referenced2from2the2positive2clock2edge2after2the2last2Data2In2pair. 4)2A102is2LOW2with2the2WRITE2command2(Auto2Precharge2is2disabled) Command Address DQS DQ NOP DM tDQSSmax BA (A2or2All) tWR DI b

Rev 1.2 / Jun. 2008 46 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Data2for2any2WRITE2burst2may2be2truncated2by2a2subsequent2PRECHARGE2command2as2shown2in2Figure. Note2that2only2data,in2pairs2that2are2registered2prior2to2the2tWR2period2are2written2to2the2internal2array,2and2any2subse, quent2data,in2should2be2masked2with2DM,2as2shown2in2next2Fig.2Following2the2PRECHARGE2command,2a2subsequent2 command2to2the2same2bank2cannot2be2issued2until2tRP2is2met. 2222222222222222222222222222222222222222222222222222222222Interrupting2Write2to2Precharge /CLK CLK WRITE NOP NOP NOP NOP BA,2 Col2b Don't2Care 1)2DI2b2=2Data2In2to2column2b2. 2)2An2interrupted2burst2of242or282is2shown,222data2elements2are2written. 3)2tWR2is2referenced2from2the2positive2clock2edge2after2the2last2desired2Data2In2pair. 4)2A102is2LOW2with2the2WRITE2command2(Auto2Precharge2is2disabled) 5)2*12=2can2be2Don't2Care2for2programmed2burst2length2of24 6)2*22=2for2programmed2burst2length2of24,2DQS2becomes2Don't2Care2at2this2point Command Address DQS DQ PRE DM tDQSSmax tWR DI b *1*1*1*1 BA (A2or2All)

Rev 1.2 / Jun. 2008 47 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series BURST2TERMINATE The2BURST2TERMINATE2command2is2used2to2truncate2read2bursts2(with2auto2precharge2disabled).2The2most2recently2 registered2READ2command2prior2to2the2BURST2TERMINATE2command2will2be2truncated,2as2shown2in2the2Operation2sec, tion2of2this2datasheet.2Note2the2BURST2TERMINATE2command2is2not2bank2specific.2This2command2should2not2be2used2 to2terminate2write2bursts. The2below2figure2shows2in2case2of22KByte2page2size.2If2the2page2size2is24KByte,2A0~A122are2provided. 22222222222222222222222222222222222222222222222222222222222222222BURST2TERMINATE2COMMAND Don't Care CS A0~A13 WE CAS CLK CLK CKE BA0,BA1 RAS (High)

Rev 1.2 / Jun. 2008 48 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series PRECHARGE The2PRECHARGE2command2is2used2to2deactivate2the2open2row2in2a2particular2bank2or2the2open2row2in2all2banks.2 Another2command2to2the2same2bank2(or2banks)2being2precharged2must2not2be2issued2until2the2precharge2time2(tRP)2is2 completed.2 If2one2bank2is2to2be2precharged,2the2particular2bank2address2needs2to2be2specified.2If2all2banks2are2to2be2precharged,2 A102should2be2set2high2along2with2the2PRECHARGE2command.2If2A102is2high,2BA02and2BA12are2ignored.2A2PRECHARGE2 command2will2be2treated2as2a2NOP2if2there2is2no2open2row2in2that2bank,2or2if2the2previously2open2row2is2already2in2the2 process2of2precharging. The2below2figure2shows2in2case2of22KByte2page2size.2If2the2page2size2is24KByte,2A0~A9,2A112and2A122are2provided. 2222222222222222222222222222222222222222222222222222222222222222222222PRECHARGE2command AUTO2PRECHARGE Auto2Precharge2is2a2feature2which2performs2the2same2individual2bank2precharge2function2as2described2above,2but2with, out2requiring2an2explicit2command.2 This2is2accomplished2by2using2A102(A10=high),2to2enable2auto2precharge2in2conjunction2with2a2specific2Read2or2Write2 command.2This2precharges2the2bank/row2after2the2Read2or2Write2burst2is2complete.2 Auto2precharge2is2non2persistent,2so2it2should2be2enabled2with2a2Read2or2Write2command2each2time2auto2precharge2is2 desired.2Auto2precharge2ensures2that2a2precharge2is2initiated2at2the2earliest2valid2stage2within2a2burst.2 The2user2must2not2issue2another2command2to2the2same2bank2until2the2precharge2time2(tRP)2is2completed. D o n 't C a re BA B a n k A d d ress A 1 0 d e fin es th e p re ch arg e m o d e w h en a p re cha rg e co m m a n d , a re ad co m m an d o r a w rite co m m a n d is issu e d . If A 1 0 = H ig h w h en a p rech arg e co m m a nd is issu e d , all b a n ks a re p rech arg e d . If A 1 0 = Lo w w h e n a p rech arg e co m m a nd is issu e d , o n ly th e b an k th at is sele cte d b y B A 1 / B A 0 is p rech arg e d . If A 1 0 = H ig h w h en rea d o r w rite co m m an d , au to - p rech arg e fu n ctio n is en a b le d . W h ile A 1 0 = L o w , au to - p rech arg e fu n ctio n is d isab le d . C S A 0 ~ A 9 , A 1 1 ~ A 1 3 W E C A S C L K C L K C K E B A 0 , B A 1 R A S A 1 0 (High)

Rev 1.2 / Jun. 2008 49 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series AUTO2REFRESH2AND2SELF2REFRESH Mobile2DDR2devices2require2a2refresh2of2all2rows2in2any2rolling264ms2interval.2Each2refresh2is2generated2in2one2of2two2 ways:2by2an2explicit2AUTO2REFRESH2command,2or2by2an2internally2timed2event2in2SELF2REFRESH2mode: -2AUTO2REFRESH.2 This2command2is2used2during2normal2operation2of2the2Mobile2DDR.2It2is2non2persistent,2so2must2be2issued2each2time2a2 refresh2is2required.2The2refresh2addressing2is2generated2by2the2internal2refresh2controller.The2Mobile2DDR2requires2 AUTO2REFRESH2commands2at2an2average2periodic2interval2of2tREFI.2 To2allow2for2improved2efficiency2in2scheduling2and2switching2between2tasks,2some2flexibility2in2the2absolute2refresh2 interval2is2provided.2A2maximum2of2eight2AUTO2REFRESH2commands2can2be2posted2to2any2given2Mobile2DDR,2and2the2 maximum2absolute2interval2between2any2AUTO2REFRESH2command2and2the2next2AUTO2REFRESH2command2is28*tREFI. ,SELF2REFRESH.2 This2state2retains2data2in2the2Mobile2DDR,2even2if2the2rest2of2the2system2is2powered2down2(even2without2external2clock, ing).2Note2refresh2interval2timing2while2in2Self2Refresh2mode2is2scheduled2internally2in2the2Mobile2DDR2and2may2vary2 and2may2not2meet2tREFI2time. ''Don't2Care''2except2CKE,2which2must2remain2low.2An2internal2refresh2cycle2is2scheduled2on2Self2Refresh2entry.2The2pro, cedure2for2exiting2Self2Refresh2mode2requires2a2series2of2commands.2First2clock2must2be2stable2before2CKE2going2high. NOP2commands2should2be2issued2for2the2duration2of2the2refresh2exit2time2(tXSR),2because2time2is2required2for2the2com, pletion2of2any2internal2refresh2in2progress.2 The2use2of2SELF2REFRESH2mode2introduces2the2possibility2that2an2internally2timed2event2can2be2missed2when2CKE2is2 raised2for2exit2from2self2refresh2mode.2Upon2exit2from2SELF2REFRESH2an2extra2AUTO2REFRESH2command2is2recom, mended.2In2the2self2refresh2mode,2two2additional2power,saving2options2exist.2They2are2Temperature2Compensated2Self2 Refresh2and2Partial2Array2Self2Refresh2and2are2described2in2the2Extended2Mode2Register2section. The2Self2Refresh2command2is2used2to2retain2cell2data2in2the2Mobile2SDRAM.2In2the2Self2Refresh2mode,2the2Mobile2SDRAM operates2refresh2cycle2asynchronously.2 The2Self2Refresh2command2is2initiated2like2an2Auto2Refresh2command2except2CKE2is2disabled2(Low).2The2Mobile2DDR2 can2accomplish2an2special2Self2Refresh2operation2by2the2specific2modes2(PASR)2programmed2in2extended2mode2regis, ters.2The2Mobile2DDR2can2control2the2refresh2rate2automatically2by2the2temperature2value2of2Auto2TCSR2(Temperature2 Compensated2Self2Refresh)2to2reduce2self2refresh2current2and2select2the2memory2array2to2be2refreshed2by2the2value2of2 PASR2(Partial2Array2Self2Refresh).2The2Mobile2DDR2can2reduce2the2self2refresh2current(IDD6)2by2using2these2two2 modes.2 The2figure2of2next2page2shows2in2case2of22KByte2page2size.2If2the2page2size2is24KByte,2A0~A122are2provided.

Rev 1.2 / Jun. 2008 50 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Don't2Care Auto2Refresh2Command Self2Refresh2Command CS A0~A13 WE CAS CLK CLK CKE BA0, BA1 RAS CS A0~A13 WE CAS CLK CLK CKE BA0, BA1 RAS (High)

Rev 1.2 / Jun. 2008 51 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series 222222222222222222222222222222222222222222222222222222222222222222222222222SELF2REFRESH2ENTRY2AND2EXIT /CLK CLK Enter Self Refresh Mode PRE NOP ARF NOP NOP NOP ARF NOP ACT Pre All CKE Command Address A10(AP) DQ BA2A Row2n Row2n High-Z Exit Self Refresh Mode Any Command (Auto Refresh Recommended) Cont't Care tRP tRFC tXSR tRFC

Rev 1.2 / Jun. 2008 52 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series MODE2REGISTER2SET The2Mode2Register2and2the2Extended2Mode2Register2are2loaded2via2the2address2bits.2BA02and2BA12are2used2to2select2 among2the2Mode2Register,2the2Extended2Mode2Register2and2Status2Register.2See2the2Mode2Register2description2in2the2 register2definition2section.2The2MODE2REGISTER2SET2command2can2only2be2issued2when2all2banks2are2idle2and2no2 bursts2are2in2progress,2and2a2subsequent2executable2command2cannot2be2issued2until2tMRD2is2met. The2below2figure2shows2in2case2of22KByte2page2size.2If2the2page2size2is224KByte,2A0~A122are2provided.

22222222222222222222222222222222222222222222222222222222222222222222 MODE REGISTER SET COMMAND

Code2=2Mode2Register2/2Extended2Mode2Register2selection2 (BA0,2BA1)2and2op,code2(A02,2An) 222222222222222222222222222222222222222222222222222222222222222222222222222222222222tMRD DEFINITION MRS NOP Valid Code Valid tMRD /CLK CLK Command Address Don't Care D on't Care Code Code CS A0~A13 W E CAS CLK CLK CKE BA0,BA1 RAS (High)

Rev 1.2 / Jun. 2008 53 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Mode Register The2mode2register2contains2the2specific2mode2of2operation2of2the2Mobile2DDR2SDRAM.2This2register2includes2the2selec, tion2of2a2burst2length(2,242or28),2a2cas2latency(22or23),2a2burst2type.2The2mode2register2set2must2be2done2before2any2 activate2command2after2the2power2up2sequence.2Any2contents2of2the2mode2register2be2altered2by2re,programming2the2 mode2register2through2the2execution2of2mode2register2set2command. Mode Register Set BURST LENGTH Read2and2write2accesses2to2the2Mobile2DDR2SDRAM2are2burst2oriented,2with2the2burst2length2being2programmable,2as2 shown2in2Page10.2The2burst2length2determines2the2maximum2number2of2column2locations2that2can2be2accessed2for2a2 given2READ2or2WRITE2command.2Burst2lengths2of22,242or282locations2are2available2for2both2the2sequential2and2the2 interleaved2burst2types.2 BURST TYPE Accesses2within2a2given2burst2may2be2programmed2to2be2either2sequential2or2interleaved. CAS LATENCY The2CAS2latency2is2the2delay2between2the2registration2of2a2READ2command2and2the2availability2of2the2first2piece2of2out, put2data.2If2a2READ2command2is2registered2at2a2clock2edge2n2and2the2latency2is232clocks,2the2first2data2element2will2be2 valid2at2n2+22tCK2+2tAC.2If2a2READ2command2is2registered2at2a2clock2edge2n2and2the2latency2is222clocks,2the2first2data2 element2will2be2valid2at2n2+2tCK2+2tAC. CLK CLK Precharge All2Bank Mode Register SetCMD tCK Command (any) 0 1 2 3 4 5 6 tRP 2 CLK min

Rev 1.2 / Jun. 2008 54 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Extended Mode Register The2Extended2Mode2Register2contains2the2specific2features2of2self2refresh2operation2of2the2Mobile2DDR2SDRAM.2 The2Extended2Mode2Register2is2programmed2via2the2MODE2REGISTER2SET2command2(with2BA1=12and2BA0=0)2and2 will2retain2the2stored2information2until2it2is2reprogrammed,2the2device2is2put2in2Deep2Power,Down2mode,2or2the2device2 loses2power.2The2Extended2Mode2Register2should2be2loaded2when2all2Banks2are2idle2and2no2bursts2are2in2progress,2and2 subsequent2operation2should2only2be2initiated2after2tMRD.2Violating2these2requirements2will2result2in2unspecified2opera, tion. The2Extended2Mode2Register2is2written2by2asserting2low2on2CS,2RAS,2CAS,2WE2and2high2on2BA0.2The2state2of2address2 pins2A02~2A132(or2A122which2depends2on2page2size)2and2BA12in2the2same2cycle2as2CS,2RAS,2CAS2and2WE2going2low2are2 written2in2the2extended2mode2register.2The2Extended2Mode2Register2must2be2loaded2when2all2banks2are2idle2and2no2 bursts2are2in2progress,2and2the2controller2must2wait2the2specified2time2before2initiating2any2subsequent2operation.2Vio, lating2either2of2these2requirements2will2result2in2unspecified2operation. This2register2includes2the2selection2of2partial2array2to2be2refreshed2(full2array,2half2array,2quarter2array,2etc.).2The2 extended2mode2register2set2must2be2done2before2any2activate2command2after2the2power2up2sequence.2Any2contents2of2 the2mode2register2be2altered2by2re,programming2the2mode2register2through2the2execution2of2extended2mode2register2 set2command. PARTIAL ARRAY SELF REFRESH (PASR) With2PASR,2the2self2refresh2may2be2restricted2to2a2variable2portion2of2the2total2array.2The2whole2array2(default),21/22 array,21/42array,21/82array2or21/162array2could2be2selected. DRIVE STRENGTH (DS) The2drive2strength2could2be2set2to2full2or2half2via2address2bits2A52and2A6.2The2half2drive2strength2is2intended2for2lighter loads2or2point,to,point2environments.

Rev 1.2 / Jun. 2008 55 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Status2Register2Read The2Status2Register2contains2the2specific2die2information2such2as2density,2device2type,2data2bus2width,2refresh2rate,2 revision2ID2and2manufacturers.2The2Status2Register2is2only2for2READ.2Below2figure2is2Status2Register2Read2Timing2Dia, gram.2 To2read2out2the2Status2Register2values,2BA[1:0]2set2to201b2and2A[13:0]2set2to2all202with2MRS2command2followed2by2 Read2command2with2that2BA[1:0]2and2A[13:0]2are2Don’t2care.2If2the2page2size2is24KByte,2A[12:0]2are2provided. Note) 1.2SRR2can2only2be2issued2after2power,up2sequence2is2complete. 2.2SRR2can2only2be2issued2with2all2banks2precharged. 3.2SRR2CL2is2unchanged2from2value2in2the2mode2register. 4.2SRR2BL2is2fixed2at22. 5.2tSRR2=222CLK2(min) 6.2tSRC2=2CL2+21.2(min2time2between2READ2to2next2valid2command) 7.2No2commands2other2than2NOP2and2DESELECT2are2allowed2between2the2SRR2and2the2READ. CMD tCK tRP tSRR NOP MRS NOP READ NOP NOP NOP CMD Register Value Out tSRC CLK CLK CMD BA[1:0] Add DQS DQ[15:0] CL = 3 Don’t care PRE All or PRE

Rev 1.2 / Jun. 2008 56 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series POWER2DOWN Power2down2occurs2if2CKE2is2set2low2coincident2with2Device2Deselect2or2NOP2command2and2when2no2accesses2are2in2 progress.2If2power2down2occurs2when2all2banks2are2idle,2it2is2Precharge2Power2Down.2 If2Power2down2occurs2when2one2or2more2banks2are2Active,2it2is2referred2to2as2Active2power2down.2The2device2cannot2 stay2in2this2mode2for2longer2than2the2refresh2requirements2of2the2device,2without2losing2data.2The2power2down2state2is2 exited2by2setting2CKE2high2while2issuing2a2Device2Deselect2or2NOP2command.2 A2valid2command2can2be2issued2after2tXP.2For2Clock2stop2during2power2down2mode,2please2refer2to2the2Clock2Stop2sub, section2in2Operation2section2of2this2datasheet.2 NOTE:2This2case2shows2CKE2low2coincident2with2NO2OPERATION.2 2222222222Alternately2POWER2DOWN2entry2can2be2achieved2with2CKE2low2coincident2with2Device2DESELECT. DEEP2POWER2DOWN The2Deep2Power2Down2(DPD)2mode2enables2very2low2standby2currents.2All2internal2voltage2generators2inside2the2 Mobile2DDR2SDRAM2are2stopped2and2all2memory2data2is2lost2in2this2mode.2 All2the2information2in2the2Mode2Register2and2the2Extended2Mode2Register2is2lost.2Next2Figure,2DEEP2POWER2DOWN2 COMMAND2shows2the2DEEP2POWER2DOWN2command2All2banks2must2be2in2idle2state2with2no2activity2on2the2data2bus2 prior2to2entering2the2DPD2mode.2While2in2this2state,2CKE2must2be2held2in2a2constant2low2state. To2exit2the2DPD2mode,2CKE2is2taken2high2after2the2clock2is2stable2and2NOP2command2must2be2maintained2for2at2least2 2002us.2After22002us2a2complete2re,initialization2routing2is2required2following2steps242through2112as2defined2in2POWER, UP2and2INITIALIZATION2SEQUENCES.2DPD2is2an2optional2feature,2so2please2contact2Hynix2office2for2DPD2feature. The2below2figure2shows2in2case2of22KByte2page2size.2If2the2page2size2is24KByte,2A0~A122are2provided. Don't Care Don't Care DEEP2POWER2DOWN2ENTRY2COMMAND2POWER,DOWN2ENTRY2COMMAND CS A0~A13 WE CAS CLK CLK CKE BA0, BA1 RAS CS A0~A13 WE CAS CLK CLK CKE BA0, BA1 RAS

Rev 1.2 / Jun. 2008 57 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Mobile2DDR2SDRAM2Deep2Power2Down2Entry2and2Exit Before2entering2deep2power2down2the2DRAM2must2be2in2an2all2banks2idle2state2with2no2activity2on2the2data2bus.2Upon2 entering2deep2power2down2all2data2will2be2lost.2While2in2deep2power2down2CKE2must2be2held2in2a2constant2low2state.2 Upon2exiting2deep2power2down2NOP2command2must2be2maintained2for2200us.2After2200us2a2complete2initialization2 routine2is2required2following2steps242through2112as2defined2in2POWER,UP2and2INITIALIZATION2SEQUENCES. Mobile DDR SDRAM Deep Power-Down Entry and Exit Note: 1.2Clock2must2be2stable2before2exiting2deep2power2down2mode.2That2is,2the2clock2must2be2cycling2within2specifications2by2Ta0.2 2.2Device2must2be2in2the2all2banks2idle2state2prior2to2entering2Deep2Power2Down2mode.2 3.2200us2is2required2before2any2command2can2be2applied2upon2exiting2DPD.2 4.2DPD2=2Deep2Power2Down2command.2 5.2Upon2exiting2Deep2Power2Down2a2precharge2all2command2must2be2issued2followed2by2two2auto2refresh2commands2and2a2load2 mode2register2sequence. DON'T CARE NOP DPD4 NOP VALID5 VALID T0 T1 Ta01 Ta1 Tb1 tCK tIH tIS tCH tCL tIS tIH tIS tIH tIS tRP2 Deep Power Down Mode Exit Deep Power Down Mode T=200us3 CK CK CKE COM ADD DQS DQ DM tIS

Rev 1.2 / Jun. 2008 58 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series CAS LATENCY DEFINITION CAS2latency2definition2of2Mobile2DDR2SDRAM2must2be2must2be2loaded2when2all2banks2are2idle,2and2the2controller2must2 wait2the2specified2time2before2initiating2the2subsequent2operation.2 CAS2latency2definition:2with2CL2=232the2first2data2element2is2valid2at2(22*2tCK2+2tAC)2after2the2clock2at2which2the2READ2 command2was2registered2(See2Figure22)2 CAS LATENCY DEFINITION NOTE 222222221.2DQ2transitioning2after2DQS2transition2define2tDQSQ2window. 222222222.2All2DQ2must2transition2by2tDQSQ2after2DQS2transitions,2regardless2of2tAC. 222222223.2tAC2is2the2DQ2output2window2relative2to2CK,2and2is2the2long2term2component2of2DQ2skew. Read NOP NOP NOP NOP T0 T1 T3 T4 T5T2 T2n T3n T4n T5n T6 NOP NOP T2 T2n T3 T3n T4 T4n T5 T5nAll2DQ2values,2 collectively2 CL = 3 tLZ tRPRE tLZ tDQSCK tDQSCK tRPST DQS CMD CK CK tAC tDQSQ

Rev 1.2 / Jun. 2008 59 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Clock Stop Mode Clock2stop2mode2is2a2feature2supported2by2Mobile2DDR2SDRAM2devices.2It2reduces2clock,related2power2consumption during2idle2periods2of2the2device. Conditions:2the2Mobile2DDR2SDRAM2supports2clock2stop2in2case:

2The2last2access2command2(ACTIVE,2READ,2WRITE,2PRECHARGE,2AUTO2REFRESH2or2MODE2REGISTER2SET)2has2 executed2to2completion,2including2any2data,out2during2read2bursts;2the2number2of2required2clock2pulses2per2access2 command2depends2on2the2device's2AC2timing2parameters2and2the clock2frequency;
The2related2timing2condition2(tRCD,2tWR,2tRP,2tRFC,2tMRD)2has2been2met;2
CKE2is2held2HIGH.22222222 When2all2conditions2have2been2met,2the2device2is2either2in2''idle''2or2''row2active''2state,2and2clock2stop2mode2may2be2 entered2with2CK2held2LOW2and2CK2held2HIGH.2Clock2stop2mode2is2exited2when2the2clock2is2restarted.2NOPs2command2 have2to2be2issued2for2at2least2one2clock2cycle2before2the2next2access2command2may2be2applied.2Additional2clock2pulses2 might2be2required2depending2on2the2system2characteristics.2 Figure12illustrates2the2clock2stop2mode:
2Initially2the2device2is2in2clock2stop2mode;
2The2clock2is2restarted2with2the2rising2edge2of2T02and2a2NOP2on2the2command2inputs;
With2T12a2valid2access2command2is2latched;2this2command2is2followed2by2NOP2commands2in2order2to2allow2for2clock2 stop2as2soon2as2this2access2command2has2completed;
Tn2is2the2last2clock2pulse2required2by2the2access2command2latched2with2T1.
2The2timing2condition2of2this2access2command2is2met2with2the2completion2of2Tn;2therefore2Tn2is2the2last2clock2pulse2 required2by2this2command2and2the2clock2is2then2stopped. Clock Stop Mode CK ADD CMD NOP NOP NOPNOP Valid Clock2 Stopped Exit2Clock Stop2Mode Valid Command Enter2Clock Stop2Mode Don't2Care (High,Z) CK CMD T0 T1 T2 Tn CKE DQ, DQS Timing2Condition

Rev 1.2 / Jun. 2008 60 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series Data mask1,2) Mobile2DDR2SDRAM2uses2a2DQ2write2mask2enable2signal2(DM)2which2masks2write2data.2 Data2masking2is2only2available2in2the2write2cycle2for2Mobile2DDR2SDRAM.2Data2masking2is2available2during2write,2but2 data2masking2during2read2is2not2available.2 DM2command2masks2burst2write2data2with2reference2to2data2strobe2signal2and2it2is2not2related2with2read2data.2DM2com, mand2can2be2initiated2at2both2the2rising2edge2and2the2falling2edge2of2the2DQS.2DM2latency2for2write2operation2is2zero. For2x322data2I/O,2Mobile2DDR2SDRAM2is2equipped2with2DM0,2DM1,2DM22and2DM32which2control2DQ0~DQ7,2 DQ8~DQ15,2DQ16~DQ232and2DQ24~DQ312respectively. Note: 1)2Mobile2SDR2SDRAM2can2mask2both2read2and2write2data,2but2the2read2mask2is2not2supported2by2Mobile2DDR2SDRAM.2 2)2Differences2in2Functions2and2Specifications2(next2table) Data Masking (Write cycle: BL=4) Item Mobile DDR SDRAM Mobile SDR SDRAM Data2mask Write2mask2only Write2mask/Read2mask WRITE WRITE DM CMD CK CK D0 D1 D3 D0 D1 D3 Hi,Z DQS DQ Data2 Masking Data2 Masking tDQSS tDQSL tDS tDH tDQSH Hi,Z

Rev 1.2 / Jun. 2008 61 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series POWER-UP AND INITIALIZATION SEQUENCES Mobile2DDR2SDRAM2must2be2powered2up2and2initialized2in2a2predefined2manner.2Operations2procedures2other2thank2 those2specified2may2result2in2undefined2operation.2If2there2is2any2interruption2to2the2device2power,2the2initialization2 routine2should2be2followed.2The2steps2to2be2followed2for2device2initialization2are2listed2below.2

Step1:2Provide2power,2the2device2core2power2(VDD)2and2the2device2I/O2power2(VDDQ)2must2be2brought2up2simulta, neously2to2prevent2device2latch,up.2Although2not2required,2it2is2recommended2that2VDD2and2VDDQ2are2from2 the2same2power2source.2Also2assert2and2hold2CLOCK2ENABLE2(CKE)2to2a2LVCMOS2logic2high2level.
Step22:2Once2the2system2has2established2consistent2device2power2and2CKE2is2driven2high,2it2is2safe2to2apply2stable2 clock.
Step23:2There2must2be2at2least2200us2of2valid2clocks2before2any2command2may2be2given2to2the2DRAM.2During2this2 time2NOP2or2DESELECT2commands2must2be2issued2on2the2command2bus.
Step24:2Issue2a2PRECHARGE2ALL2command.
Step25:2Provide2NOPs2or2DESELECT2commands2for2at2least2tRP2time.
Step26:2Issue2an2AUTO2REFRESH2command2followed2by2NOPs2or2DESELECT2command2for2at2least2tRFC2time.2Issue2 the2second2AUTO2REFRESH2command2followed2by2NOPs2or2DESELECT2command2for2at2least2tRFC2time.2 2222222222222222Note2as2part2of2the2initialization2sequence2there2must2be2two2auto2refresh2commands2issued.2The2typical2 flow2is2to2issue2them2at2Step26,2but2they2may2also2be2issued2between2steps2102and211.
Step27:2Using2the2MRS2command,2load2the2base2mode2register.2Set2the2desired2operating2modes.
Step28:2Provide2NOPs2or2DESELECT2commands2for2at2least2tMRD2time.
Step29:2Using2the2MRS2command,2program2the2extended2mode2register2for2the2desired2operating2modes.2Note2the2 order2of2the2base2and2extended2mode2register2programming2is2not2important.
Step210:2Provide2NOP2or2DESELCT2commands2for2at2least2tMRD2time.
Step211:2The2DRAM2has2been2properly2initialized2and2is2ready2for2any2valid2command.

Rev 1.2 / Jun. 2008 62 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series The2Initialization2flow2sequence2is2below.2 Initialization Waveform Sequence VDD VDDQ /CLK CLK CKE CMD DM ADDR A10 BA0, BA1 DQ, DQS T=200usec tRP tMRDtRFC tMRD VDD/VDDQ Powered up CLOCK stable Auto Refresh NOP ARFPRE MRSARF ACTMRS CODE RACODE CODE RACODE BA0=L BA1=L BABA0=L BA1=H tRFC Load Mode Register tCH tCL tCK ALL BANKS tIS tIH tIS tIH tIS tIH tIS tIH DON'T CARE High-Z Precharge All Auto Refresh Load Extended Mode Register

Rev 1.2 / Jun. 2008 63 Mobile DDR SDRAM 1Gbit (32M x 32bit) H5MS1G22MFP2Series2/2H5MS1G32MFP2Series

PACKAGE INFORMATION

90 Ball 0.8mm pitch 8mm FBGA [8.0 x 13.0 mm2, t=1.0mm max] Unit2[mm]0.8 0.34 +/,20.05 0.802Typ. 1.002max 0.45 +/,20.05 A12INDEX2MARK 13.02Typ. Bottom View 0.902 11.22Typ. 6.402Typ. 8.002Typ. 0.8Typ. 0.80 0.90.

Selected Specification

Hynix Semiconductor H5MS1G32MFP-J3M overview.

Summary

1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O

Description

1Gbit MOBILE DDR SDRAM based on 8M x 4Bank x32 I/O

Source title H5MS1G32MFP-J3M Datasheet(PDF) - Hynix Semiconductor

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