GPY0030C-HS01x Datasheet | DigiCamel IC Datasheet

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Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 17

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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus. DATA SHEET May 05, 2015 Version 1.2 GGPPYY00003300CC AAuuddiioo DDrriivveerr

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Version: 1.2 Table of Contents PAGE

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Version: 1.2 AUDIO DRIVER 1. GENERAL DESCRIPTION The GPY0030C is an audio driver , in which gain can be adjusted by external resistor (Maximum gain is 20) and emb edded the anti-pop circuit to minimize the turn -on and turn -off pop noise. Normally, it is applied for GPC series, GPF series, GPL series and other GENERALPLUS products. The GPY0030C is easily to be used in variety of applications and products. 2. FEATURES  Wide operating range: 2.4V – 6.8V  Bridge-Tied Load  Low distortion: THD+N = 0.15% (Typ.) (For VDD = 5.0V, RL = 8.0 & Pout = 500mW)  High output power: POUT = 825mW (For VDD = 5.0V, THD+N =1.0%, f =1.0KHz & RL = 8.0)  Low standby current: 1.0A  Minimize the turn-on and turn-off pop noise 3. BLOCK DIAGRAM 5kΩ 55kΩ 5kΩ 55kΩ BIAS VDD INN ACIN SPN SPP CE VREF GND GND VDD 8

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Version: 1.2 4. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description Electrical Characteristics SPN 1 O Audio output negative - SPP 2 O Audio output positive - VSS 3 I Power VSS - INN 4 I Signal input negative - ACIN 5 I Signal input positive - VREF 6 O Reference voltage VDD/2 CE 7 I Chip enable - VDD 8 I Power VDD 2.4V - 6.8V 4.1. PAD Assignment This IC substrate should be connected to VSS Note: To assure IC operates properly, please bond all of VDD and VSS pins. 4.2. Package Pin Assignment

1 SPN

2 SPP

3 VSS

4 INN

= Thermal PAD (Connected to GND plane for better heat dissipation)

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Version: 1.2 5. ELECTRICAL SPECIFICATIONS 5.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 7.0V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0℃ to + 60℃ Operating junction Temperature Range TJ -40℃ to + 150℃ Storage Temperature TSTO -50℃ to + 150℃ Note: Stresses beyond those given in the Absolute Maximum Rating table may cause permanent damage to the device. For normal operational conditions , see AC/DC Electrical Characteristics. 5.2. Thermal Characteristics Characteristics Symbol Value Unit 5.3. DC Characteristics (TA = 25℃) Item Test Conditions Symbol Min. Typ. Max. Unit Operation Voltage VDD 2.4 - 6.8 V Shutdown Current CE=VSS ISTBY - 0.1 1.0 uA Operating Current VDD = 5.0V, CE=VDD, No Load IDD - 2.5 - mA Reference Voltage VDD=5.0V VREF - VDD /2 - V Input Resister(CE) CE=VDD RCE - 40 - kΩ Input Current(CE) CE=2.3V at VDD=5.0V ICE - 85 - uA Total Harmonic Distortion + Noise VDD = 5.0V, RL = 8.0, POUT = 500mW THD+N - 0.15 - % Signal to Noise Ratio VDD=5.0V, Av= -1, f=1.0KHz & RL=8.0 SNR 100 dB Output Power (Note2) VDD=5.0V, THD+N=1%, f=1.0KHz & RL=8.0 POUT - 825 - mW VDD=5.0V, THD+N=10%, f=1.0KHz & RL=8.0 POUT - 1000 - mW Output Offset Voltage VIN=0V VOS - 30 - mV Power Rejection Ratio f = 1kHz PSRR - 70 - dB Enable Time VDD = 5.0V, CIN=1.0uF, CVREF=4.7uF TON - 50 90 ms VDD = 5.0V, CIN=1.0uF, CVREF=2.2uF - 32 60 ms Shutdown Time VDD = 5.0V, CIN=1.0uF, CVREF=4.7uF TOFF - 40 80 ms VDD = 5.0V, CIN=1.0uF, CVREF=2.2uF - 25 50 ms Note1: Output power = (VO(PEAK)2/2/RL; VO(PEAK) = (VI(PEAK))*GAIN; So we can get the input range from output power, output loading and audio driver’s gain. Note2: Proper thermal dissipation must be considered for desired output power and operating voltage. Please refer to Table-2. Note3: tON is the time from CE high (chip enable) to SPP or SPN output. ACIN CE TON SPP-SPN

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Version: 1.2 5.4. Typical Performance Characteristics 5.4.1. THD+N vs. Frequency 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%)

5 THD+N vs Frequency

Frequency (Hz) 100 1k 10k 20k 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) Frequency (Hz) 100 1k 10k 20k 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) Frequency (Hz) 100 1k 10k 20k 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) Frequency (Hz) 100 1k 10k 20k 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) Frequency (Hz) 100 1k 10k 20k 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) 0.01 0.1 THD+N (%) Frequency (Hz) 100 1k 10k 20k VDD=5.0V Po=300mW RL=8Ω AV=20 AV=10 AV=2 VDD=5.0V Po=250mW RL=16Ω AV=20 AV=10 AV=2 VDD=5.0V Po=200mW RL=32Ω AV=20 AV=10 AV=2 VDD=3.3V Po=100mW RL=8Ω AV=10 AV=20 AV=2 VDD=3.3V Po=100mW RL=16Ω AV=10 AV=2 AV=20 VDD=3.3V Po=75mW RL=32Ω AV=10 AV=20 AV=2

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Version: 1.2 5.4.2. THD+N vs. Output Power 0.01 0.1 1 Output Power (W) 0.01 0.1 THD+N (%) 0.01 0.1 1 0.01 0.1 0.01 0.1 1 0.01 0.1 THD+N vs Output Power 0.01 0.1 1 Output Power (W) 0.01 0.1 THD+N (%) 0.01 0.1 1 0.01 0.1 0.01 0.1 1 0.01 0.1 THD+N vs Output Power 0.01 0.1 1 Output Power (W) 0.01 0.1 THD+N (%) 0.01 0.1 1 0.01 0.1 0.01 0.1 1 0.01 0.1

10 THD+N vs Output Power

0.01 0.1 1 Output Power (W) 0.01 0.1 THD+N (%) 0.01 0.1 1 0.01 0.1 0.01 0.1 1 0.01 0.1 0.01 0.1 1 Output Power (W) 0.01 0.1 THD+N (%) 0.01 0.1 1 0.01 0.1 0.01 0.1 1 0.01 0.1 0.01 0.1 1 Output Power (W) 0.01 0.1 THD+N (%) 0.01 0.1 1 0.01 0.1 0.01 0.1 1 0.01 0.1 VDD=5.0V R L=8Ω Av=20 BW < 80kHz f=20k f=1k f=20 VDD=5.0V R L=16Ω Av=20 BW < 80kHz f=20k f=1k f=20 VDD=5.0V R L=32Ω Av=20 B W < 80kHz f=20k f=1k f=20 VDD=3.3V R L=8Ω Av=20 BW < 80kHz f=20k f=1k f=20 VDD=3.3V R L=16Ω Av=20 BW < 80kHz f=20k f=1k f=20 VDD=3.3V R L=32Ω Av=20 BW < 80kHz f=20k f=1k f=20

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Version: 1.2 5.4.3. Output Power vs. Supply Voltage 2.5 3 3.5 4 4.5 5 5.5 Supply Voltage (V) 0.2 0.4 0.6 0.8 1.2 0.1 0.3 0.5 0.7 0.9 1.1 1.3 Output Power (W) 2.5 3 3.5 4 4.5 5 5.5 Supply Voltage (V) 0.2 0.4 0.6 0.8 1.2 0.1 0.3 0.5 0.7 0.9 1.1 1.3 Output Power (W) Output Power vs Supply Voltage 2.5 3 3.5 4 4.5 5 5.5 Supply Voltage (V) 0.2 0.4 0.6 0.8 0.1 0.3 0.5 0.7 0.9 Output Power (W) 2.5 3 3.5 4 4.5 5 5.5 Supply Voltage (V) 0.2 0.4 0.6 0.8 0.1 0.3 0.5 0.7 0.9 Output Power (W) Output Power vs Supply Voltage 2.5 3 3.5 4 4.5 5 5.5 Supply Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.05 0.15 0.25 0.35 0.45 0.55 Output Power (W) 2.5 3 3.5 4 4.5 5 5.5 Supply Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.05 0.15 0.25 0.35 0.45 0.55 Output Power (W) Output Power vs Supply Voltage 5.4.4. Noise 20 100 1k 10k 20k 10u 100u 1m Noise Floor Frequency (Hz) Output Noise Voltage (Vrms) 20 100 1k 10k 20k 10u 100u 1m Noise Floor Frequency (Hz) Output Noise Voltage (Vrms) RL=32Ω f=1kHz BW < 80kHz THD+N=1% THD+N=10% RL=16Ω f=1kHz BW < 80kHz THD+N=1% THD+N=10% RL=8Ω f=1kHz BW < 80kHz THD+N=1% THD+N=10% VDD=5.0v RL=8Ω BW < 22kHz BW < 80kHz Av=2 Av=10 Av=20 VDD=3.3v RL=8Ω BW < 22kHz BW < 80kHz Av=2 Av=10 Av=20

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Version: 1.2 5.4.5. Output Noise Spectrum VDD=5.0v, RL=8Ω BW < 22kHz, Av = -1

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Version: 1.2 6. APPLICATION CIRCUIT 1. Double-end VDD CE VREF ACIN GPY0030C Speaker 100 + VDD SPN SPP VSS INN CIN=1µF RI Gain = 2* 50000 5000+RI 2.PWM Speaker VDD GPY0030C SPN SPP VSS INN VDD CE VREF ACIN RI RI 10k +100  (20k) (1000p) (50k) (50k) Gain = 2* 50000 5000+RI (5~50k) (5~50k) CIN=1µF CIN=1µF CVREF=1µF (Optional. Refer to table 6.1.) CVREF=1µF (Optional. Refer to table 6.1.) (Optional. Refer to table 6.1.) (Optional. Refer to table 6.1.) (Optional. Refer to table 6.1.)

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Version: 1.2 6.1. BTL Amplifier Efficiency The following equations are basis for amplifier efficiency calculation. Efficiency = = (1) Where POUT = = (2) VO.RMS = (3) PSUP = VDD x IDD.AVG = VDD x (4) Efficiency of a BTL configuration: = (5) PD = PSUP - POUT (6) Table-1 Efficiency vs. Output Power in 3.3V 8Ω BTL System POUT (W) Efficiency (%) VP (V) PD (W) 0.125 33.6 1.41 0.26 0.250 47.6 2.00 0.29 0.375 58.3 2.45* 0.28 * High-peak voltage values cause the THD to increase. 6.2. Power Dissipation Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single -ended. Equation 7 states the maximum power dissipation point for a single-ended mode operating at a given supply voltage and driving a specified output load. PD.MAX = (VDD) /(2π RL) Single -Ended (7) However, a direct consequence of the increased power delivered to the load by bridge ampli fier is an incre ment in internal power dissipation point for a bridge amplifier operating at the same condition. PD.MAX = 4(VDD) /(2π RL) Bridge -Mode (8) Since the GPY0030C has two operational amplifiers in one package, the maximum internal power dissipation is four times that of a single -end amplifier. The maximum power dissipation from equation 8 must not be greater than the po wer dissipation that results from the equation 9. PD.MAX = (TJ.MAX-TJ) /θJA (9) For SOP -8 package with and without thermal pad, the thermal resistance (θJA) is equal to 60°C/W and 160°C/W, respectively. Since the maximum junction temperature (T J.MAX) of GPY0030C is 150°C and ambient temperature (T A) is defined by the power system design, the maximum power dissipation which the IC package is able to handle from equation 9 . Once the power dissipation is greater than the maximum limit (P D.MAX), either the supply voltage (VDD) must be decreased, the load impedance (RL) must be increased, or the θJA must be reduced with heat-sink. Example: V DD=6.0V, Load=8Ω, T A=30°C, GPY0030C SOP-8 without thermal pad (θJA=160°C/W). From equation 9: /(2π RL) = 0.913W Decrease Power Voltage VDD to 5V. /(2π RL) = 0.634W 6.3. Thermal Pad Considerations The thermal pad must be connected to ground. The package with thermal pad of the GPY0030C requires special attention on thermal design. If the thermal design issues are not properly addressed, the temperature beyond which damage occurs to the GPY0030C (150°C). The GPY0030C may not function or meet expected performance at this temperature. Thermal pad on the bottom of the GPY0030C should be soldered down to a copper pad on the circuit boa rd. Heat can be conducted away from the thermal pad through the copper plane to ambient. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be required to keep the GPY0030C junction temperature below maximum junction temperature (150°C). Output Power Input Power POUT PSUP VO.RMS RL VP 2RL VP 2VP πRL POUT PSUP πVP 4VDD

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Version: 1.2 Table-2 Output Power vs. Junction Temperature in BTL System (TA=25°C) Output Power POUT (W) Efficiency (%) Internal Dissipatio n PD (W) Power From Supply PSUP (W) VOUT Peak-to-Peak VP (V) Junction Temperature TJ (°C) SOP-8 SOP-8-P COB DIP-8 VDD = 3.3V, Load=8Ω System VDD = 5V, Load=8Ω System VDD = 6.8V, Load=8Ω System * TJ must be less than TJ.MAX (150°C). ** TJ = θJA x PD + TA ; θJA(SOP-8) = 160°C/W ; θJA(SOP-8-P) = 60°C/W ; θJA(COB) = 180°C/W ; θJA(DIP-8) = 110°C/W

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Version: 1.2 7. PACKAGE/PAD LOCATIONS 7.1. Ordering Information Product Number Package Type GPY0030C - C Chip form GPY0030C - HS01x Green Package – SOP-8 (150mil) GPY0030C - HS14x Green Package – SOP-8-P With Thermal PAD (150mil) GPY0030C - HD01x Green Package – PDIP-8 (300mil) Note: Package form number (x = 1 - 9, serial number). 7.2. Package Information 7.2.1. SOP-8 D y 1 4 pin 1 index b e c E X H A detail X Symbol Dimension in inch Min. Typ. Max. A 0.053 - 0.069 A1 0.004 - 0.010 b - 0.016 - D 0.189 - 0.196 E 0.150 - 0.157 e - 0.050 - H 0.228 - 0.244 L1 0.016 - 0.050 y - - 0.004

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Version: 1.2 7.2.2. SOP-8-P Symbol Dimension in inch Min. Typ. Max. A 0.053 - 0.067 A1 0.000 - 0.006 D 0.189 0.196 D1 0.077 - 0.090 E 0.150 - 0.157 E1 0.077 - 0.090 H 0.228 - 0.244 L 0.016 - 0.050 e1 - 0.016 - e2 - 0.050 - Φ1 8º Thermal PAD UNIT: INCH

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Version: 1.2 7.2.3. PDIP-8 All units are in mil. 1mil = 25.4m A2 Body Thickness c Lead Thickness E1 Body Width b Lead Width D1 Body Length L1 Lead Length e Lead Pitch PDIP-8-300 c e b A2 cE1 bD1 Body Size L1 e Lead Size 130±5 10Typ250±4 18±2374±10 130±15 100Typ 5 8

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Version: 1.2 8. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulat ed in the terms of sale only. GENERA LPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet s and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical l ife support equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.

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Version: 1.2 9. REVISION HISTORY Date Revision # Description Page May 05, 2015 1.2 Modify 5.5 DC Characteristics Table. Add 5.4.5 Output Noise Spectrum. Jun. 26, 2013 1.1 Modify 7.1 Ordering Information. 12 Mar. 12, 2013 1.0 Modify section 6.3. 16 Oct 11, 2012 0.1 Original 16

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