GPUSB101A-NnnV-C Datasheet | DigiCamel IC Datasheet

Manufacturer Specifications

Compare GPUSB101A-NnnV-C variants.

Select a manufacturer to view its specifications, local PDF, and searchable HTML text.

1 manufacturers / 1 documents

Manufacturer	Series	Package	Documents	Available	Select specification
Generalplus Technology ...	-	-	1	PDF HTML	Viewing

Online Datasheet

Read the Generalplus Technology ... document online.

DATASHEET SEARCH SITE

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 37

Technical content

GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GGPPUUSSBB110011AA Sep 24, 2014 Version 1.4 UUSSBB BBrriiddggee CCoonnttrroolllleerr In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.

2 Sep 24, 2014

Version: 1.4 Table of Contents PAGE

3 Sep 24, 2014

Version: 1.4

4 Sep 24, 2014

Version: 1.4 USB BRIDGE CONTROLLER 1. GENERAL DESCRIPTION The GPUSB101A carries an 8-bit processor, 16K bytes OTP ROM, 256 bytes working SRAM, six 64 bytes buffer SRAM, 2 set 12-bit timers, and 20 general I/Os. The general I/Os can be programmed as parallel bus or SPI. There are three main functions for the bridge IC. USB to parallel bus USB to SPI Parallel bus to SPI 2. APPLICATION FIELD USB Bulk transfer for download USB Isochronous IN transfer for MIC in (needs extra ADC) USB Isochronous OUT transfer for speaker out(needs extra DAC) USB Interrupt IN transfer for small data communication 3. FEATURES Working Voltage: 2.4V - 3.6V (without USB) 3 . 0 V - 3 . 6 V ( w i t h U S B ) IOA, IOB Working Voltage: 2.4V - 5.5V IOC Working Voltage: 2.4V - 3.6V CPU Speed: 0.09375MHz - 12MHz ROM Size: 16 K bytes OTP ROM RAM Size: 256 bytes working SRAM S i x 6 4 b y t e s b u f f e r S R A M Two 12-bit timers/counters On-chip Voltage Regulator: 3.3 V output USB Specification 2.0 compliant; full-speed (12 Mbps) USB supports Bulk IN, Bulk OUT, Interrupt IN, Isochronous IN and Isochronous OUT transfer mode 20 GPIO port (Parallel bus and SPI share with GPIO) Supports parallel bus 4 bit mode (5 pin for control and 4 pin for data) Supports parallel bus 8 bit mode (5 pin for control and 8 pin for data) Supports SPI master mode Supports SPI slave mode Supports SPI transparent mode (Host IC can control SPI slave device through bridge IC ) 4. BLOCK DIAGRAM HOST IC SPI PLL CLK_DIV USB PHY 6502 +Timer + Int CPU_USB IF UDC SPI M/S SPI Flash PC BUS_SEL 12 M OTP 16K CPU RAM 256 B BUF0 64 B BUF2 64 B BUF1 64 B I/O BUF4 64 B BUF5 64 B Parallel Bus BUF3

64 B SPI slave

5 Sep 24, 2014

Version: 1.4 5. SIGNAL DESCRIPTIONS Pad Name PIN NO. LQFP64 PIN NO. Type Description XI 6 6 I Oscillator cry stal input XO 7 7 O Oscillator cr ystal output V50_REG 2 2 P Regulator power 5V input VSS_REG 3 3 G Regulator power ground input V33_REG 1 1 P Regulator power 3.3V output RESETB 9 9 I System reset pin (active low) TEST 8 8 I TEST Mode selection pin, high is test mode and low is normal mode (Pad internal pull low VDD 10 10 P Positive power supply for core and IOC (2.4V~3.6V) VSS 11 11 G Ground reference for core AVDD3 4 4 P Positive power supply for analog circuit AVSS3 5 5 G Ground reference for analog circuit V33_USB 41 45 P USB power 3.3V input VSS_USB 38 42 G USB power ground input DPLS 40 44 I/O USB DPLS DMNS 39 43 I/O USB DMNS IOA[7:0] 22-19, 36-33 22-19, 40-37 I/O bi-directional I/O ports, power sou rce from IOVDD5(2.4V~5.5V) IOB[7:0] 32-27, 24-23 36,31-27, 24-23, I/O bi-directional I/O ports, power sou rce from IOVDD5(2.4V~5.5V) IOC[3:0] 18-15 18-15 I/O bi-directional I/O port s, power source from VDD(2.4V~3.6V) OTPSCK 13 13 I OTP writer clock input (Pad internal pull low) OTPSDA 14 14 I/O OTP writer data input/output (Pad internal pull low) IOVDD5 25 25 P IOA and IOB power source input (2.4V~5.5V) IOVSS5 26 26 G IOA and IOB power source ground input OTPPARA 12 12 I OTP test pin (Pad internal pull low) VPP 37 41 P OTP high voltage power supply for programming Total: 41 Pads

6 Sep 24, 2014

Version: 1.4 5.1. PIN Map AVDD3 AVSS3 XI XO TEST V33_REG V50_REG VSS_REG RESETB VDD VSS OTPPARA OTPSCK OTPSDA 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IOVDD5 IOVSS5 DPLS DMNS VSS_USB VPP NC NC V33_USB NC NC NC NC 60 59 58 57 56 55 54 53 52 51 50 49 48 NC 616263 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC IOC0 IOC1 IOC2 IOC3 IOB0 IOB1 IOB2 IOB3 IOB4 IOB5 IOB6 IOB7 IOA4 IOA5 IOA6 IOA7 IOA0 IOA1 IOA2 IOA3 GPUSB101A LQFP64 NC DPLS TEST VDD V33_USB DMNS VPP IOA1OTPSCK RESETB XO XI AVDD3 V50_REG V33_REG GPUSB101A 11IOA7 OTPSDA IOVSS5 IOVDD5 NC

7 Sep 24, 2014

Version: 1.4 5.2. PAD Assignment

8 Sep 24, 2014

Version: 1.4 6. FUNCTIONAL DESCRIPTIONS 6.1. Power Saving Mode The GPUSB101A features a power saving mode(or called standby mode) for low power application. To enter standby mode, the desired key wakeup port(IOA[7:0]) must be configured to input first. And read the P_IOA_Data to latch the IOA state before entering the standby mode. 6.2. PLL (Phase Lock Loop) The purpose of PLL is to provide stable output frequency which reference a base frequency (from crystal). The PLL output frequency is 48MHz. It is used for USB device core. 6.3. I/O Three I/O ports are built in GPUSB101A - PortA, PortB and PortC, total has 20 bit-programmable I/Os. The PortA is a general purpose I/O with programmable wakeup capability, i.e. IOA [7:0] is the key wakeup port. To activate key wakeup function, latch data on P_IOA_Data and enable the key wakeup function. Wakeup is triggered when the PortA state is different from at the time latched. Furthermore, the I/O ports can be operated at 5V level(only PortA and PortB), higher than the CPU core which is a 3.3V level system. Suppose system operating voltage is running at 3.3V, then IOVDD5 (power for I/O) operates from 3.3V to 5.5V. In such condition, the I/O pad is capable of operating from 0V through IOVDD5. The following diagram is an I/O schematic. Although data can be written into the same register through Port_Data and Port_Buffer, they can be read from different places, Buffer (R) and Data (R). Register Control logic pull high pull low Pin pad Buffer(R) Data(R) Port_Data(W) Port_Buffer(W) Port_DIR(R/W) Port_ATTR(R/W) In addition to a general purpose I/O port function, PortA/B/C also shares some special function s. A summary of PortA/B/C special functions is listed as follows: Port A Port A IOA[7] IOA[6] IOA[5] IOA[4] IOA[3] IOA[2] IOA[1] IOA[0] Wakeup ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ Parallel - - - para_int para_wrb para_rdb para_csb para_cdb Port B Port B IOB[7] IOB [6] IOB[5] IOB [4] IOB [3] IOB [2] IOB [1] IOB [0] Parallel para_data[7] para_data[6] para_data[5] para_data[4] para_data[3] para_data[2] para_data[1] para_data[0] SPI slave spi_rxd spi_txd spi_clk spi_csb - - - - Port C Port C IOC [3] IOC [2] IOC [1] IOC [0] SPI master spi_rxd spi_txd spi_clk spi_csb

9 Sep 24, 2014

Version: 1.4 6.4. Parallel Bus There is a parallel bus slave side on GPUSB101A. The host IC as a parallel bus master role. Host IC can use GPIO toggle to im plement signals like section 6.4.3. According to hos t IC GPIOs number. The customer can select 8 bit mode (5 control pin and 8 data pi n) or 4 bit mode (5 control pin and 4 data pin). Besides Para_int is input pin, others control pin are output pin. If the GPUSB101A has request to host IC. GPUSB101A may issues Parallel_int pin then host IC must polling the status register and knows what request from GPUSB101A.

6.4.1 The description of parallel bus I/O

Pad name Type IO Description Para_cdb I IOA[0] Parallel bus for command or data transfer (high is command and low is data) Para_csb I IOA[1] Parallel bus chip enable (active low) Para_rdb I IOA[2] Parallel bus write enable (active low) Para_wrb I IOA[3] Parallel bus read enable (active low) Para_int O IOA[4] Parallel bus interrupt out Para_data[7:0] I/O IOB[7:0] Parallel bus bi-directional data

6.4.2 The function of parallel bus

Para_cdb Para_wrb Para_rdb Description 1 0 1 Write command register 1 1 0 Read st atus register 0 0 1 Write dat a 0 1 0 Read dat a Note1: command register is read only bridge IC. Note2: st atus register is read only for host IC.

6.4.3 Timing diagram

para_csb para_cdb para_wrb para_data[7:0] command T1 T2 T3 T4 T6 Read status para_csb para_cdb para_rdb para_data[7:0] status T1 T2 T7 T8 T6 Write data para_csb para_cdb para_wrb para_data[7:0] 1st data 2nd data last data T1 T2 T3 T4 T6T5 Read data para_csb para_cdb para_rdb para_data[7:0] T1 T2 T7 T8 T6T5 2nd data last data1st data

10 Sep 24, 2014

Version: 1.4

6.4.4 Timing constrain

Min. Typ. Max. Unit cdb to csb delay time T1 100 - - ns csb to wrb(rdb) delay time T2 100 - - ns wrb to data setup time T3 100 - - ns wrb to data hold time T4 200 - - ns wrd to csb delay time T5 100 - - ns csb to cdb delay time T6 100 - - ns Data out stable time T7 300 - - ns Latch data hold time T8 0 - - ns

11 Sep 24, 2014

Version: 1.4 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Min. Max. Unit IOA , IOB PAD Supply Voltage IOVDD5 -0.3 5.5 V IOC PAD Supply Voltage VDD -0.3 3.6 V Analog Supply Voltage AVDD3 -0.3 3.6 V Core Supply Voltage VDD -0.3 3.6 V ESD Protection(HBM) VESD 2K - V Operating Temperature Range TA 0 +60 ℃ Storage Temperature Range TSTO -50 +150 ℃ Note: Stresses beyond those given in the Absolute Maximum Rating tabl e may cause permanent damage to the device. For normal operational conditions, see DC Electrical Characteristics. 7.2. DC Characteristics (VDD = 3.3V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Test Co ndition Core Operating Voltage VDD 2.4 3.3 3.6 V IOA, IOB PAD Operating Voltage IOVDD5 2.4 - 5.5 V IOC PAD Operating Voltage VDD 2.4 3.3 3.6 V Analog Operating Voltage AVDD3 2.4 - 3.6 V Operating Current IOP - 4.3 6 mA FCPU = 12MHz @ 3.3V(Typ.), USB OFF ISTBY1 - 3 5 μA VDD = 3.3V, whole chip with regulator ON Standby Current ISTBY2 - 1 3 μA VDD = 3.3V, whole chip with regulator OFF Input High Level (IOA,IOB) VIH1 0.7Vdd - - V Input Low Level (IOA,IOB) VIL1 - - 0.3Vdd V Input High Level (IOC) VIH2 0.7Vdd - - V Input Low Level (IOC) VIL2 - - 0.3Vdd V -2 - - VOH = 0.9*IOVDD5, IOVDD5=3.3V Output High Current (IOA,IOB) IOH1 -4 - - mA VOH = 0.9*IOVDD5, IOVDD5=5V 3 - - VOL = 0.1*IOVDD5, IOVDD5=3.3V Output Sink Current (IOA,IOB) IOL1 6 - - mA VOL = 0.1*IOVDD5, IOVDD5=5V Output High Current (IOC) IOH2 -2 - - mA VOH = 0.9*VDD, VDD=3.3V Output Sink Current (IOC) IOL2 3 - - mA VOL = 0.1*VDD, VDD=3.3V - 170 - Vin = GND, IOVDD5=3.3V Pull-up Resistor (IOA,IOB) RPU1 - 95 - KΩ Vin = GND, IOVDD5=5V - 160 - Vin = IOVDD5, IOVDD5=3.3V Pull-down Resistor (IOA,IOB) RPD1 - 95 - KΩ Vin = IOVDD5, IOVDD5=5V Pull-up Resistor(IOC) RPU2 - 110 - KΩ Vin = GND, VDD=3.3V Pull-down Resistor(IOC) RPD2 - 130 - KΩ Vin = VDD, VDD=3.3V 7.3. Regulator Characteristics Unit Characteristics Symbol Min. Typ. Max. Unit Test Condition Input Voltage V50_REG 2.4 - 5.5 V Maximum Current Output IREGO - - 60 mA V50_REG>=3.3V, VDROP<0.2V

12 Sep 24, 2014

Version: 1.4 Unit Characteristics Symbol Min. Typ. Max. Unit Test Condition Output Voltage V33_REG 3.0 3.3 3.6 V Note1 Drop Voltage VDROP - - 200 mV V50_REG=3.3V, IREGO=60mA Standby Current IREGS - - 2 uA Note1: When input voltage below 3.3V will limit the output of the regulator to V50_REG- VDROP.

13 Sep 24, 2014

Version: 1.4 8. APPLICATION CIRCUITS GPUSB101A

14 Sep 24, 2014

Version: 1.4 9. PACKAGE/ORDERING INFORMATION 9.1. Ordering Information Product Number Package Type GPUSB101A-NnnV-C Chip form GPUSB101A-NnnV-QL02x Halogen Free 64 pin LQFP Package GPUSB101A-NnnV-HG02x Green Package - SSOP 20 (209mil) Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package for m number (x = 1 - 9, serial number). 9.2. Package Information LQFP 64 Symbols Min. Nom. Max. A - - 1.60 A1 0.05 - 0.15

15 Sep 24, 2014

Version: 1.4 Symbols Min. Nom. Max. A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c1 0.09 - 0.16 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 e 0.50 BSC L 0.45 0.60 0.75 L1 1.00 REF S 0.20 REF θ 3.5° REF θ1 5.0° REF θ2 12° REF θ3 12° REF R1 0.16 REF R2 0.15 REF Thermally enhanced dimension(shown in mm) E2 D2 Pad Size Min. Max. Min. Max. 210x21E 4.27 5.33 4.27 5.33 260x26E 5.28 6.60 5.28 6.60 Notes: 1. JEDEC Outline: MS-026 BCD MS-026 BCD-HD(Thermally Enhanced Variations Only) 2. Dimensions D1 and E1 do not include mold protrusion. Allowabl e protrusi on is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Dimension b does not include dambar protrusion. Allowable damba r protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm.

16 Sep 24, 2014

Version: 1.4 SSOP 20 Millimeter Symbol Min. Nom. Max. A -- -- 2.0 A1 0.05 -- -- A2 1.65 1.75 1.85 b 0.22 -- 0.38 c 0.09 -- 0.21 D 6.90 7.20 7.50 E 7.40 7.80 8.20 E1 5.00 5.30 5.60 e 0.65 BSC L 0.55 0.75 0.95 L1 1.25 REF R1 0.09 -- -- θ° 0 ° 4 ° 8 °

17 Sep 24, 2014

Version: 1.4 10. GPUSB101A USER'S GUIDE 10.1. Introduction 10.1.1. Features GPUSB101A is a bridge IC which provides the interface between PC and a host controller through USB1.1 Vender Command. When PC detects that GPUSB101A is plugged in, PC will indicate that a new USB device is inserted on device manager, and the PC application can access that new USB device via Generalplus USB driver. In GPUSB101A, there are 4 interfaces to interface with a host controller, including SPI interface, Parallel Bus 8 bit interface, Parallel Bus 4 bit interface, and Software UART. Moreover, the communication protocol between GPUSB101A and PC follows the USB1.1 specification. By GPUSB101A, PC is able to write, read and erase SPI Flash as a mass storage device and then the host controller can access SPI Flash either through SPI int erface of the host controller or through the interfaces of GPUSB101A. Moreover, the application program on PC also can interact with the host controller to perform some applications such as playin g songs, driving LEDs or motors through USB vender commands. Interface I/O Function SPI 8 1. PC Download data to SPI flash 2. PC access HO ST IC 3. HOST IC access SPI flash Parallel 8 bit 13 1. PC Download data to SPI flash 2. PC access HO ST IC 3. HOST IC access SPI flash Parallel 4 bit 9 1. PC Download data to SPI flash 2. PC access HO ST IC 3. HOST IC access SPI flash S/W UART 2 1. PC access HOST IC 10.2. System Function Diagram 10.2.1. SPI interface: 4 GPIO + 4 SPI Application Path Class Transfer Note Download PC Æ G PUSB101A Æ SPI Master mode Æ SPI flash Mass storage Bulk Vendor command PC link Host IC PC Æ G PUSB101A Æ SPI Slave mode Æ Host IC Mass storage Bulk Vendor command Host IC access flash Host IC Æ SPI/ Transparent mode Æ SPI flash Mass storage Bulk Vendor command

18 Sep 24, 2014

Version: 1.4 10.2.2. Parallel Bus 8 bit interface: 5 GPIO control pin + 8 GPIO data pin Application Path Class Transfer Note Download PC Æ G PUSB101A Æ SPI Master mode Æ SPI flash Mass storage Bulk Vendor command PC link Host IC PC Æ G PUSB101A Æ Parallel bus 8 bit Æ Host IC Mass storage Bulk Vendor command Host IC access flash GPIC Æ Parallel bus 8 bit Æ GPUSB101A Æ SPI Master mode Æ SPI flash Mass storage Bulk Vendor command

19 Sep 24, 2014

Version: 1.4 10.2.3. Parallel Bus 4 bit interface: 5 GPIO control pin + 4 GPIO data pin Application Path Class Transfer Note Download PC Æ G PUSB101A Æ SPI Master mode Æ SPI flash Mass storage Bulk Vendor command PC link Host IC PC Æ G PUSB101A Æ Parallel bus 4 bit Æ Host IC Mass storage Bulk Vendor command Host IC access flash GPIC Æ Parallel bus 4 bit Æ GP USB101A Æ SPI Master mode Æ SPI flash Mass storage Bulk Vendor command

20 Sep 24, 2014

Version: 1.4 10.2.4. Software UART: 2 GPIO pin Application Path Class Transfer Note PC link Host IC PC Æ G PUSB101A Æ I/O(S/W UART) Æ Host IC Mass storage Bulk Vendor command

21 Sep 24, 2014

Version: 1.4 10.3. USB Bulk Only Command Protocol GPUSB101A must receive USB vendor command from USB Host (PC). The command format is following USB mass storage device class command. Figure 1 - Command/Data/Status Flow shows the flow for Command T ransport, Data-In, Data-Out and Status Transport. The followin g sections define Command and Status Transport. 10.3.1. Command Block Wrapper (CBW) The CBW shall start on a packet boundary and shall end as a short pa cket with exactly 31 (1Fh) bytes transferred. Fields appea r aligned to byte offsets equal to a multiple of their byte size. All subsequent data and the CSW shall start at a new packet boundary. All CBW transfers shall be ordered with the LSB (b yte 0) first (little endian). Refer to the USB Specification Terms and Abbreviations for clarification. TABLE 7.3.1. Command Block Wrapper

22 Sep 24, 2014

Version: 1.4 dCBWSignature: Signature that helps identify this data packet as a CBW. The signature field shall contain the value 43425355h (little endian), indicating a CBW. dCBWTag: A Command Block Tag sent by the host. The device shall echo the contents of this field back to the host in the dCSWTag field of the associated CSW. The dCSWTag positively associates a CSW with the corresponding CBW. dCBWDataTransferLength: The number of bytes of data that the host expects to transfer on the Bulk-In or Bulk-Out endpoint (as indicated by the Direction bit) during the execution of this comm and. If this field is zero, the device and the host shall transfer no data between the CBW and the associated CSW, and the device shall ignore the value of the Direction bit in bmCBWFlags. bmCBWFlags: The bits of this field are defined as follows: Bit 7 Direction - the device shall ignore this bit if the dCBWDat aTransferLength field is zero, otherwise: 0 = Data-Out from host to the device, 1 = Data-In from the device to the host. Bit 6 Obsolete. The host shall set this bit to zero. Bits 5...0 Reserved - the host shall set these bits to zero. bCBWLUN: The device Logical Unit Number (LUN) to which the command block is being sent. For devices that support multiple LUNs, the host shall place into this fiel d the LUN to which this command block is addressed. Otherwise, t he host shall set this field to zero. bCBWCBLength: The valid length of the CBWCB in bytes. This defines the valid length of the command block. The only legal values are 1 through 16 (01h through 10h). All other values are reserved. CBWCB: The command block to be executed by the device. The device shall interpret the first bCBWCBLength bytes in this field as a command block as defined by the command set identified by bInterfaceSubClass. If the command set supported by the device uses command blocks of fewer than 16 (10h) bytes in length, the significant bytes shall be transferr ed first, beginning with the byte at offset 15 (Fh). The device shall ignore the content of the CBWCB field past the byte at offset (15 + bCBWCBLength - 1). 10.3.2. Command Status Wrapper (CSW) The CSW shall start on a packet boundary and shall end as a short packet with exactly 13 (0Dh) bytes transferred. Fields appear aligned to byte offsets equal to a multiple of their byte size. All CSW transfers shall be ordered with the LSB (byte 0) first (little endian). Refer to the USB Specification Terms and Abbreviations for clarification. TABLE 7.3.2. Command Status Wrapper

23 Sep 24, 2014

Version: 1.4 dCSWSignature: Signature that helps identify this data packet as a CSW. The signature field shall contain the value 53425355h (little endian), indicating CSW. dCSWTag: The device shall set this field to the value received in the dCBWTag of the associated CBW. dCSWDataResidue: For Data-Out the device shall report in the dCSWDataResidue the difference between the amounts of data expected as stated in the dCBWDataTransferLength, and the actual amount of data processed by the device. For Da ta-In the device shall report in the dCSWDataResidue the difference between the amount of data expected as stated in the dCBWDataTransferLength and the actual amount of relevant data sent by the device. The dCSWDataResidue shall not exceed the value sent in the dCBWDataTransferLength. bCSWStatus: bCSWStatus indicates the success or failure of the command. The device shall set this byte to zero if the command completed successfully. A non-zero value shall indicate a failure during command execution according to the following table: 10.4. Vender Command PC <-> GPUSB Command Block Wrapper 15 th byte-30 th byte Byte Bit 7 6 5 4 3 2 1 0 Operation Code (MSB) Reserved (MSB) Transfer Length Command OP Co de Description Get IC Version F0 10 Generalplus verify SPI Flash Read FD 28 SPI Flash physical read SPI Flash Write FD 2A SPI Flash physical write SPI Flash Sector Erase FD 20 SPI Flash sector erase, erase size = 64K B ytes SPI Flash Chip Erase FD FF SPI Flash sector erase, erase size = 4M Bytes Set Vender ID FF F0 Generalplus verify Reserved write Ex xx. PC write data to Host IC Reserved read Dx xx PC read data from Host IC

24 Sep 24, 2014

Version: 1.4 10.4.1. Get IC version Command Block Wrapper 15 th byte-30 th byte Byte Bit 7 6 5 4 3 2 1 0 F0 10 (MSB) Reserved (MSB) Reserved Operation Code Function Comment *CBW Byte 15: 0xF0 *CBW Byte 16: 0x10 *CBW Byte 29-30: GP Tag 0xF010 Set vendor ID *IN 11 Bytes for IC Version information 10.4.2. SPI Flash Read Command Block Wrapper 15 th byte-30 th byte Byte Bit 7 6 5 4 3 2 1 0 FD 28 (MSB) LBA (Logical Block Address) 6 06 (MSB) Transfer Length (scoters) 1 scoters = 512 bytes

25 Sep 24, 2014

Version: 1.4 Operation Code Function Comment 0XFD28 SPI flash Physical Read *CBW Byte 15: 0XFD *CBW Byte 16: 0x28 *CBW Byte 17: High word High byte Address *CBW Byte 18: High word Low byte Address *CBW Byte 19: Low word High byte Address *CBW Byte 20: Low word Low byte Address *CBW Byte 21: 0x06. it mean SPI Nor Flash *CBW Byte 22: High Operation Data Length *CBW Byte 23: Low Operation Data Length *CBW Byte 29-30: GP Tag 10.4.3. SPI Flash Write Command Block Wrapper 15 th byte-30 th byte Byte Bit 7 6 5 4 3 2 1 0 FD 2A (MSB) LBA (Logical Block Address) 6 06 (MSB) Transfer Length (sectors) 1 sectors = 512 bytes Operation Code Function Comment 0XFD2A SPI flash Physical Write *CBW Byte 15: 0xFD *CBW Byte 16: 0x2A *CBW Byte 17: High word High byte Address *CBW Byte 18: High word Low byte Address *CBW Byte 19: Low word High byte Address *CBW Byte 20: Low word Low byte Address *CBW Byte 21: 0x06 .it mean SPI NorFlash *CBW Byte 22: High Operation Data Length *CBW Byte 23: Low Operation Data Length *CBW Byte 29-30: GP Tag

26 Sep 24, 2014

Version: 1.4 10.4.4. SPI Flash Sector Erase Command Block Wrapper 15 th byte-30 th byte Byte Bit 7 6 5 4 3 2 1 0 FD 20 (MSB) LBA (Logical Block Address) 6 06 (MSB) Transfer Length (sectors) 1 sectors = 512 bytes Operation Code Function Comment 0XFD20 SPI flash Physical scoter erase, erase size = 64K B ytes(GPR25L320A) *CBW Byte 15: 0xFD *CBW Byte 16: 0x20 *CBW Byte 17: High word High byte Address *CBW Byte 18: High word Low byte Address *CBW Byte 19: Low word High byte Address *CBW Byte 20: Low word Low byte Address *CBW Byte 21: 0x06 .it mean SPI Nor Flash *CBW Byte 22: High Operation Data Length *CBW Byte 23: Low Operation Data Length *CBW Byte 29-30: GP Tag 10.4.5. SPI Flash Chip Erase Command Block Wrapper 15 th byte-30 th byte Byte Bit 7 6 5 4 3 2 1 0 FD FF (MSB) LBA ( Logical Block Address ) 6 06 (MSB) Transfer Length (sectors) 1 sectors = 512 bytes

27 Sep 24, 2014

Version: 1.4 Operation Code Function Comment 0XFDFF SPI flash Physical scoter erase, erase size = 4MB ytes(GPR25L320A) *CBW Byte 15: 0xFD *CBW Byte 16: 0xFF *CBW Byte 17: High word High byte Address *CBW Byte 18: High word Low byte Address *CBW Byte 19: Low word High byte Address *CBW Byte 20: Low word Low byte Address *CBW Byte 21: 0x06 .it mean SPI Nor Flash *CBW Byte 22: High Operation Data Length *CBW Byte 23: Low Operation Data Length *CBW Byte 29-30: GP Tag 10.4.6. Set Vender ID Command Block Wrapper 15th byte-30th byte Byte Bit 7 6 5 4 3 2 1 0 FF F0 (MSB) Reserved (MSB) Transfer Length (bytes) Operation Code Function Comment *CBW Byte 15: 0xFF *CBW Byte 16: 0xF0 *CBW Byte 29-30: GP Tag 0xFFF0 Set vendor ID *IN 10 Bytes for IC Version information This command can make sure Generalplus device.

28 Sep 24, 2014

Version: 1.4 10.4.7. Reserved write Command Block Wrapper 15th byte-30th byte Byte Bit 7 6 5 4 3 2 1 0 EX XX (MSB) Reserved (MSB) Reserved Operation Code Function Comment 0xEX XX Reserved write *CBW Byte 15: 0xEX *CBW Byte 16: 0xXX *CBW Byte 29-30: GP Tag Example: 1. Application: PC + GPUSB101A + GPF8 2. PC issue customer command 0xE000 to GPF8 3. *CBW Byte 15 = 0xE0 & *CBW Byte 16 = 0x00, 4. GPUSB101A will transfer two bytes data 0xE0, 0x00 to GPF8, and then continue transfer N b ytes data to GPF8. N = CBW Byte 8- 11 dCBWDataTransferLength: 10.4.8. Reserved Read Command Block Wrapper 15th byte-30th byte Byte Bit 7 6 5 4 3 2 1 0 DX XX (MSB) Reserved (MSB) Reserved

29 Sep 24, 2014

Version: 1.4 Operation Code Function Comment 0xDX XX Reserved read *CBW Byte 15 :0xDX *CBW Byte 16 :0xXX *CBW Byte 29-30: GP Tag Example: 1. Application: PC + GPUSB101A + GPF8 2. PC issue to read GPF8 status 3. *CBW Byte 15 = 0xD0 & *CBW Byte 16 = 0x00, 4. GPUSB101A will transfer two bytes data 0xD0, 0x00 to GPF8, and then continue transfer N bytes data from GPF8. N = CBW Byte 8-1 1 dCBWDataTransferLength: 10.5. GPUSB Interface Protocol Command List GPUSB -> Host IC Command OP Co de Description USB Plug in C0 00 USB plug in issue PC suspend C0 01 USB Plug out or PC suspend issue PC resume C0 02 PC resume issue Vender command Write EX XX Customer define Vender command Read DX XX Customer define Example Vender command Write 1. E0 00: KEY 1 (PC issue PLAY) 2. E0 01: KEY 2 (PC issue NEXT) 3. E0 02: KEY 3 (PC issue PREVIOUS) Example Vender command Read 1. D0 00: status1 (PC read Host IC I/O status) 2. D0 01: status2 (PC read Host IC Program status) Host IC -> GPUSB Command OP Co de Description SPI transparent mode B0 01 Host IC issue GPUSB101A SPI transparent mode

30 Sep 24, 2014

Version: 1.4 10.6. GPUSB Program Flow

31 Sep 24, 2014

Version: 1.4 10.6.1. SPI interface protocol Example 1. If GPUSB101A command Host IC to do something, op code = E0 01, Data = 12H, 34H, 56H, 78H 2. GPUSB101A command REQ1 = Hi, and wait Ack1 = Hi (when Host IC receive REQ1 = Hi, Host IC must stop access SPI Flash data, and command ACK1 = Hi) 3. When Ack1 = Hi, GPUSB101A will issue SPI Slave mode and command REQ1 = Low 4. Then Host IC can start SPI TX protocol, and latch two bytes OP CODE = E0 01, command ACK1 = low 5. GPUSB101A continue command REQ1 = Hi, wait Ack1 = Hi 6. Host IC command ACK1 = Hi, GPUSB101A command REQ1 = Low 7. Then Host IC can start SPI TX protocol, and latch four bytes data =12H, 34H, 56H, 78H, command ACK1 = low 8. OP code must be two bytes, data transfer max = 64bytes/frame

32 Sep 24, 2014

Version: 1.4 MSB LSB SPICLK SPICSN SPITX SPIOE 8 bits MSB LSBSPIRX MSB MSB Fig1. Master Mode, SPO = 0, SPH = 0 10.6.2. Parallel bus 8 bit mode Write command: para_csb para_cdb para_wrb para_data[7:0] command T1 T2 T3 T4 T6

33 Sep 24, 2014

Version: 1.4 Read status: para_csb para_cdb para_rdb para_data[7:0] status T1 T2 T7 T8 T6 Write data: para_csb para_cdb para_wrb para_data[7:0] 1st data 2nd data last data T1 T2 T3 T4 T6T5 Read data: para_csb para_cdb para_rdb para_data[7:0] T1 T2 T7 T8 T6T5 2nd data last data1st data

34 Sep 24, 2014

Version: 1.4 10.6.3. Parallel bus 4 bit mode Write command: para_csb para_cdb para_wrb para_data[3:0] command LSB command MSB Read status: para_csb para_cdb para_rdb para_data[3:0] status LSB status MSB Note: After Para_rdb falling edge, para_data is output until para_csb rising edge. Write data: para_csb para_cdb para_wrb para_data[3:0] 1st data LSB 2nd data LSB last data LSB 1st data MSB 2nd data MSB last data MSB

35 Sep 24, 2014

Version: 1.4 Read data: para_csb para_cdb para_rdb para_data[3:0] 1st data LSB 2nd data LSB last data LSB 1st data MSB 2nd data MSB last data MSB Timing constrain Unit Characteristics Symbol Min. Typ. Max. Unit cdb to csb delay time T1 100 - - ns csb to wrb(rdb) delay time T2 100 - - ns wrb to data setup time T3 100 - - ns wrb to data hold time T4 200 - - ns wrd to csb delay time T5 100 - - ns csb to cdb delay time T6 100 - - ns Data out stable time T7 300 - - ns Latch data hold time T8 0 - - ns Note: The 4 bit mode time constrain is the same as 8 bit mode. 10.6.4. S/W UART mode UART Data Frame Format

36 Sep 24, 2014

Version: 1.4 11. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered b y the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.

37 Sep 24, 2014

Version: 1.4 12. REVISION HISTORY Date Revision # Description Page SEP 24, 2014 1.4 1. Modify section 5.2 Pin Map. 2. Modify section 9.1 Ordering Information. 3. Modify section 9.2 Package Information. MAY 13, 2011 1.3 Modify 6.4.2 The function of parallel bus. 9 JUN. 13, 2008 1.1 1. Add pin description of VDD power range. 2. Add section 5.2 Pin Map. 3. Modify section 7.2 DC Characteristics of I OH, IOL, RPU & RPD. 4. Add section 7.3 Regulator Characteristics. 5. Modify section 9.1 Ordering Information. 6. Add section 9.2 Package Information. 2. Modify section 5.1 PAD Assignment. OCT. 23, 2007 0.1 Original 33

Selected Specification

Generalplus Technology ... GPUSB101A-NnnV-C overview.

Summary

USB Bridge Controller

Description

USB Bridge Controller

Source title GPUSB101A-NnnV-C Datasheet(PDF) - Generalplus Technology Inc.

Related Parts

More parts from the same family.

Browse manufacturer