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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of devi ce specifications before plac ing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GGPPTT11000000AA General Touch Sensor Controller APR. 30, 2012 Version 1.1 In addition, GENERALPLUS products are not authorized for use as critical components in life s upport devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
© Generalplus Technology Inc. Proprietary & Confidential 2 Apr. 30, 2012 Version: 1.1 Table of Contents PAGE 6.5.2. Serial Interface (I 8.1. CONNECTED TO HOST THROUGH I
© Generalplus Technology Inc. Proprietary & Confidential 3 Apr. 30, 2012 Version: 1.1 GENERAL TOUCH SENSOR CONTROLLER 1. GENERAL DESCRIPTION The GPT1000A, a general purpose touch sensor controller, equips an 8-bit CMOS microprocessor, 8K-byte embedded flash, and 256-byte working SRAM. It allows the control of 24 IOs configurable as capacitive sensi ng buttons or GPIOs. Moreover, three PWMs are built-in to support hardware LED control with hold and dimming function. The PWM can output to IOB or IOC individually to produce fancy LED effect with simple program. To communicate with host devices, the GPT1000A equips SPI or I2C interfaces. The GPT1000A operates at a wide voltage range of 2.6V – 5.5V. The maximum CPU frequency runs up to 8MHz. Sleep mode and halt mode are also provided to optimize system performance and power consumption. The In-Circuit Emulation (ICE) function is built-in with on-chip re-programmable non-volatile memory. 2. FEATURES 8-bit microprocessor with ICE function ─ Embedded flash 8K bytes ─ SRAM 256 bytes Clock ─ Built-in 8MHz ROSC ─ Built-in 30KHz ROSC for time-base function ─ /1, /2, /4, /8, /16, /32 of 8MHz clock output for CPU Operating Voltage: 2.6V ~ 5.5V Industrial Temperature Range: -40℃ ~ 85℃ Operation Modes ─ Operating mode, Sleep mode, and Halt mode Timer/Counter ─ 8-bit timers with selective clock sources ─ Programmable auto sleep timer Power management for system reliability ─ Low-Voltage-Reset function ─ Power-On-Reset function ─ Watchdog reset (derived from 30KHz clock) Eight Interrupt / Wakeup sources (INT / WP) ─ Timer overflow ─ Counter ─ IOA[7:0], IOB[7:0], IOC[7:0] key-changed ─ Serial interface interrupt ─ Sensor counter interrupt ─ External interrupt Up to 24 I/Os ─IOA[7:0]:programmable as GPIO/Wakeup-able IO/external INT ─ IOB[7:0]:programmable as GPIO/Wakeup-able IO/PWM output ─ IOC[7:0]:programmable as GPIO/Wakeup-able IO/PWM output Capacitive sensors ─ Supports max. 24 capacitive sensor I/Os of individual keys. ─ Built-in auto sleep/wakeup function to minimize power consumption during sensing operation. Three PWMs with programmable hold-time and fade-out time for LED drive SPI slave interface supports different polarity and phase modes I2C slave interface Note: (1)The frequency deviation for built-in 8MHz ROSC is +-10% at room temperature. (2)The frequency deviation for built-in 30KHz ROSC is +-15% at room temperature. 3. APPLICATION FIELD Home appliance, MP3 capacitive touch pad controller, toy, general touch application, or general purpose controller.
© Generalplus Technology Inc. Proprietary & Confidential 4 Apr. 30, 2012 Version: 1.1 4. BLOCK DIAGRAM
© Generalplus Technology Inc. Proprietary & Confidential 5 Apr. 30, 2012 Version: 1.1 5. SIGNAL DESCRIPTIONS Package No. Mnemonic PIN No. QFN32 LQFP32 SSOP20 (HG082) SSOP20 (HG083) SOP16 Type Description IOA[7:0] 27-30, 22-19 26-29, 21-18 26-29, 21-18 13-16, 12-9 1-2, 16-13 11-14, 7-10 I/O 8-bit I/O port, each pin can be set as an input or output individually. Input mode: Each one of IOA [7:0] is a CMOS input with programmable internal pull-low resistors. Output mode: CMOS output. All pins are capable of wakeup and external interrupt function is available on IOA2 or IOA4. IOA can be programmed as special function IO for I C(IOA[1:0]) or SPI(IOA[3:0]) interface, or sensor IO inputs. IOB[7:0] 26-23, 9-12 25-22, 8-11 25-22, 8-11 - 20-17, 5-8 1-3, 16 I/O 8-bit I/O port, every two pins can be set as an input or output individually. Input mode: Every two pins can be programmed as CMOS input pin with internal pull-low resistors. Output mode: Every two pins can be programmed as CMOS output or open-drain output. IOB can be programmed as PWM output or sensor IO inputs. IOC[7:0] 31-32, 1-2, 5-8 30-32, 1, 4-7 30-32, 1, 4-7 17-20 16-13 - I/O 8-bit I/O port, every two pins can be set as an input or output individually. Input mode: Every two pins can be programmed as CMOS input pin with internal pull-low resistors. Output mode: Every two pins can be programmed as CMOS output or open-drain output. IOC can be programmed as PWM output or sensor IO inputs. RESETB 4 3 3 2 4 15 I System reset input. It is LOW-active and with internal pull-high resistor. All of the internal registers are reset to the default state when this pin is set to Low level. TEST 3 2 2 1 3 - I IC Test pin: It is HIGH-active and with internal pull-low resistor. User must leave this pin opened to work in normal mode. ICECLK 16 15 15 6 - - I ICE clock signal. Should be connected to ground if not in development mode. ICESDA 15 14 14 5 - - I/O ICE data signal. Should be kept floating if not in development mode VDD5V 13 12 12 3 9 4 I IO and regulator power input. VSS5V 18 17 17 8 12 6 I IO and regulator ground input. VDD3V 14 13 13 4 10 5 O Regulator output for core logic circuit power. VSS3V 17 16 16 7 11 6 I Ground input pin for core logic circuit.
© Generalplus Technology Inc. Proprietary & Confidential 6 Apr. 30, 2012 Version: 1.1 5.1. PAD Assignment This IC substrate should be connected to VSS or kept floating. Note1: To ensure IC functions properly, bond all VDD and VSS pins. Note2: The 0.1μF capacitor between VDD and VSS should be placed to IC as close as possible.
© Generalplus Technology Inc. Proprietary & Confidential 7 Apr. 30, 2012 Version: 1.1 5.2. Package PIN Assignment 5.2.1. QFN32
© Generalplus Technology Inc. Proprietary & Confidential 8 Apr. 30, 2012 Version: 1.1 5.2.2. LQFP32
© Generalplus Technology Inc. Proprietary & Confidential 9 Apr. 30, 2012 Version: 1.1 5.2.3. SSOP20(HG082) IOC4 IOA4 IOC5 IOC6 IOC7 IOA5 IOA6 IOA7VSS5V VSS3V ICECLK ICESDA VDD3V VDD5V RESETB TEST GPT1000A IOA1 IOA0 IOA3 IOA2
© Generalplus Technology Inc. Proprietary & Confidential 10 Apr. 30, 2012 Version: 1.1 5.2.4. SSOP20(HG083) IOB7 IOA3 IOB6 IOB5 IOB4 IOA2 IOA1 IOA0IOB0 IOB1 IOB2 IOB3 RESETB TEST IOA6 IOA7 GPT1000A 11VDD3V VDD5V VSS5V VSS3V
© Generalplus Technology Inc. Proprietary & Confidential 11 Apr. 30, 2012 Version: 1.1 5.2.5. SOP16 IOB3 IOA6 RESETB IOA4 IOA5 IOA7 IOA3 IOA2IOA1 IOA0 VSS3V/VSS5V VDD3V VDD5V IOB0 IOB1 IOB2 GPT1000A
© Generalplus Technology Inc. Proprietary & Confidential 12 Apr. 30, 2012 Version: 1.1 6. FUNCTIONAL DESCRIPTIONS 6.1. CPU The microprocessor in GPT1000A is a high performance 8-bit processor equipped with Accumulator, Program Counter, X and Y Register, Stack pointer and Processor Status Register (the same as the 6502 instruction structure). Up to 8.0MHz CPU speed is able to achieve the best performance. 6.2. Memory The GPT1000A contains internal SRAM and flash, where the SRAM size is 256-byte and the flash size is 8K-byte. The SRAM starts from address $0040 to $01FF where the area $0140 to $01FF is double mapped as shown in following figure. The built-in flash area is from 0x200 to 0x21FF. The on-chip programmability makes GPT1000A more flexible and easy to develop an application. 6.2.1. Memory mapping 6.3. I/O Port There are 24 IOs (IOA7-0, IOB7-0 and IOC7-0) in GPT1000A. IOA is bit-controlled and IOB and IOC are controlled by registers every two bits. They can be programmed as input (pure input or pull-low) or output buffer. When programmed as output buffers, IOA, IOB and IOC can be selected as either buffer outputs or open-drain outputs. In addition to ordinary I/O function, IOA is also shared with some special functions such as SPI or I C interface, external interrupt inputs, timer external clock inputs or IR transmitter outputs. Both IOB and IOC can be high-sink PWM outputs to directly drive LEDs with hold and dimming hardware control. 6.3.1. I/O Configuration Please refer to the GPT1000A programming guide -- I/O Configuration for more information. All I/Os are set as input mode without pull-low after RESET. 6.4. PWM In GPT1000A, three PWMs are built-i n. And with IO’s high sink ability, external LEDs can be di rectly driven. Moreover, the hardware hold and dimming control is supported to ease the use for users. 6.5. Serial Interfaces 6.5.1. Serial Interface (SPI Interface) A Serial Peripheral Interface (S PI) is supported in GPT1000A. There are four control signals in SPI including CS_n, SCLK (SCK), MOSI (SDI), and MISO (SDO). They are shared with IOA3-IOA0. Four types of operating mode can be selected through registers. They are supported as follows:
© Generalplus Technology Inc. Proprietary & Confidential 13 Apr. 30, 2012 Version: 1.1 6.5.2. Serial Interface (I 2C Interface) A Serial Inter-IC bus Interface (I C) is also supported in GPT1000A. Only two wires, SCK and SDA, are needed to implement the protocol, and they are shared with IOA1-IOA0. = master writes to slave. = slave writes to master Whenever a byte of data is received or transmitted, an IRQ is generated to notify CPU for next operation.
© Generalplus Technology Inc. Proprietary & Confidential 14 Apr. 30, 2012 Version: 1.1 6.6. Low Voltage Reset The GPT1000A has a Low Voltage Reset (LVR) function. In general, the CPU becomes unstable and malfunctioned when the power voltage drops below specific operating voltage. With the unique design of Low Voltage Reset in GPT1000A, it is able to reset all functions to the initial operation (stable) state if the VDD power-supply voltage drops below 2.6V. (The LVR function is the same as Power ON Reset or External Reset.) 6.7. Timer/Counter The GPT1000A has a built-in 8-bit timer/counter. It is a up-count and reloadable counter. When the counter rolls from $FF to $00, the carry (overflow) signal will reload user’s preset value into timer automatically and up-count again. At the same time, the carry signal will generate an INT signal if the corresponding bit is enabled in the INT ENABLE Register. User can read the counter value while it is running without influencing the timer/counter or reset it. Moreover, the counter overflow signal becomes a toggle output to IOA4 or IOA5 to support the application such as IR carrier frequency generating. There is also a built-in timer for automatically sleep/wake-up system inside GPT1000A. The sleep timer can be programmed from 0.9765ms to 62.5ms to fit performance and power needs. Clock source of Timer/Counter can be selected as follows: Timer/Counter Clock Source TMR 8-bit Timer 8MHz, 2MHz, 500KHz, 250KHz, 125KHz, external clock input from IOA5 or IOA3
© Generalplus Technology Inc. Proprietary & Confidential 15 Apr. 30, 2012 Version: 1.1 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 5.5V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA -40℃ to +85℃ Storage Temperature TSTO -50℃ to +150℃ Note: Stresses beyond those given in the Absolute Maximum Rating tabl e may cause operational errors or damage to the device. For normal operational conditions, see AC/DC Electrical Characteristics. 7.2. DC Characteristics (VDD5V = 3.3V, TA = 25℃) Limit Characteristics Symbol Min. Typ. Max. Unit Condition Operating Voltage 1 VDD5V 2.6 - 5.5 V For regulator input and IO power Operating Voltage 2 VDD3V 2.5 3.3 - V Regulator output for core power CPU Operating Speed FCPU 0.25 - 8 MHz VDD3V=2.5 ~ 3.3V Operating Current IOP1 - 5 6 mA VDD3V=3.3V, FCPU=8MHz Halt Mode Current IHALT - 50 100 μA CPU sleep and wakeup every 256ms, VDD3V=3.3V Standby Current ISTB B - - 2 μA VDD3V=3.3V, all off Input High Level VIH 0.7*VDD5V - - V VDD5V=3.3V Input Low Level VIL - - 0.3*VDD5V V VDD5V=3.3V IO Output High Current IOH -5 - - mA VOH =2.31V, VDD5V=3.3V IO Output Sink Current IOL 15 - - mA VOL =0.99V, VDD5V=3.3V Pull Low Resistor RLOW - 200 - KΩ VDD5V=3.3V 7.3. AC Characteristics Parameter Min Max Unit Description FSCK - 400 KHz SCK clock frequency THD_STA 0.6 - us Hold time for START condition TSU_STA 0.6 - us Setup time for START condition TSU_STP 0.6 - us Setup time for STOP condition Tf - 0.3 us Data/Clock rise time Tr - 0.3 us Data/Clock fall time TLOW 1.3 - us Low period of SCK clock THIGH 0.6 - us High period of SCK clock TSU_DAT 100 - ns Data setup time THD_DAT 300 - ns Data hold time TBUF 1.3 - us Data free time between START and STOP condition
© Generalplus Technology Inc. Proprietary & Confidential 16 Apr. 30, 2012 Version: 1.1
© Generalplus Technology Inc. Proprietary & Confidential 17 Apr. 30, 2012 Version: 1.1 8. APPLICATION CIRCUIT 8.1. Connected to Host through I2C GPT1000A PAD0 PAD1 500K~1M PAD2 PAD3 500K~1M PAD4 PAD5 500K~1M PAD6 PAD7 500K~1M IOB0 IOB1 IOB2 IOB3 IOB4 IOB5 IOB6 IOB7 IOA0 [I2C-SCL] VDD5V 1K 1K IOA1 [I2C-SDA] IOA[7:2] IOA[7:2] IOC[7:0]IOC[7:0] SCL SDA VDD5V VSS5V 0.1uF 100uF 0.1uF RESET RESETB VSS3V 2.2uF VDD5V VDD3V ICECLK 50K VDD5V 100K Note: ICECLK should be connected VSS when not in development mode.
© Generalplus Technology Inc. Proprietary & Confidential 18 Apr. 30, 2012 Version: 1.1 8.2. Connected to Host through SPI Note1: ICECLK should be connected VSS when not in development mode. Note2: In SPI application, IOA1 should be connected VSS via 50K resistor.
© Generalplus Technology Inc. Proprietary & Confidential 19 Apr. 30, 2012 Version: 1.1 9. PACKAGE / PAD LOCATIONS 9.1. Ordering Information Product Number Package Type GPT1000A - NnnV - C Chip form GPT1000A - NnnV - QV04x Halogen Free Package - QFN 32 (5x5x0.75mm) GPT1000A - NnnV - QL21x Halogen Free Package - LQFP 32 (7x7x1.4mm) GPT1000A - NnnV - HG08x Green Package - SSOP 20 (150mil) GPT1000A - NnnV - HS03x Green Package - SOP 16 (150mil) Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). Note3: Package form number (x = 0 - 9, serial number). Note4: There are two types in SSOP20, difference pin assignment in each package. Pin assignment and product number please checks with page9 and page10.
© Generalplus Technology Inc. Proprietary & Confidential 20 Apr. 30, 2012 Version: 1.1 9.2. Package Information 9.2.1. QFN32
© Generalplus Technology Inc. Proprietary & Confidential 21 Apr. 30, 2012 Version: 1.1 9.2.2. LQFP32
© Generalplus Technology Inc. Proprietary & Confidential 22 Apr. 30, 2012 Version: 1.1 9.2.3. SSOP20
© Generalplus Technology Inc. Proprietary & Confidential 23 Apr. 30, 2012 Version: 1.1 9.2.4. SOP16
© Generalplus Technology Inc. Proprietary & Confidential 24 Apr. 30, 2012 Version: 1.1 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indem nification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in t his publication or regarding the freedom of the described chip(s) from patent infringem ent. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Acco rdingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal co mmercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional proc essing by GENERALPLUS for such applications. Please note th at application circuits illustrated in this document are for reference purposes only.
© Generalplus Technology Inc. Proprietary & Confidential 25 Apr. 30, 2012 Version: 1.1 11. REVISION HISTORY Date Revision # Description Page APR. 30, 2012 1.1 1. Remove TSSOP16 package information. 2. Add SSOP20 product number. 9-10 AUG. 26, 2011 1.0 Modify 8. APPLICATION CIRCUITS. 18, 19 APR. 18, 2011 0.6 1. Modify “Signal Description”. 2. Modify 32K ROSC as 30K ROSC. 3. Add TSSOP16 package information. 4. Modify “Application Circuit”. 4~5 6,13,20,25 18~19 NOV. 04, 2010 0.5 1. Modify SOP16 package information. 2. Add I C AC characteristics 5,11,14 APR. 19, 2010 0.4 1. Add SSOP20(2) and SOP16 package information. 10~11, 18,22 JAN. 07, 2010 0.3 1. Add LQFP32 and SSOP20 package information. 2. Modify DC characteristics of IOH/IOL measurement condition. 8~9, 16, 18~19 OCT. 27, 2009 0.2 Remove SOP32 package information. 8, 14 SEP. 29, 2009 0.1 Original 19