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GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus. DATA SHEET Jul. 06, 2015 Version 1.0 GGPPRR2255LL66440033FF 3V, 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

Supports Serial Peripheral Interface -- Mode 0 and Mode 3
67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O read mode) structure or 16,777,216 x 4 bits (four I /O mode) structure
2048 Equal Sectors with 4K bytes each Any Sector can be erased individually
256 Equal Blocks with 32K bytes each Any Block can be erased individually
128 Equal Blocks with 64K bytes each Any Block can be erased individually
Power Supply Operation 2.65 ~ 3.6 volt for read, erase, and program operations
Latch-up protected to 100mA from -1V to Vcc +1V 1.2. PERFORMANCE
High Performance VCC = 2.65~3.6V Normal read 50MHz Fast read FAST_READ, DREAD, QREAD: 133MHz with 8 dummy cycles 2READ: 80MHz with 4 dummy cycle, 133MHz with 8 dummy cycle 4READ: 80MHz with 6 dummy cycle, 133MHz with 10 dummy cycle Configurable dummy cycle number for 2READ and 4READ operation 8/16/32/64 byte Wrap-Around Burst Read Mode
Low Power Consumption
Typical 100,000 erase/program cycles
20 years data retention 1.3. SOFTWARE FEATURES
Input Data Format 1-byte Command code
Advanced Security Features Block lock protection The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase instructions
Additional 8K-bit bit security OTP Features unique identifier Factory locked identifiable, and customer lockable
Auto Erase and Auto Program Algorithms Automatically erases and verifies data at selected sector Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programmed should have page in the erased state first.)
Status Register Feature
Command Reset
Program/Erase Suspend
Program/Erase Resume
Electronic Identification JEDEC 1-byte Manufacturer ID and 2-byte Device ID RES command for 1-byte Device ID
Support Serial Flash Discoverable Parameters (SFDP) mode 1.4. HARDWARE FEATURES
SCLK Input Serial clock input
SI/SIO0 Serial Data Input or Serial Data Input/Output for 2 x I/O mode or Serial Data Input/Output for 4 x I/O mode
SO/SIO1 Serial Data Output or Serial Data Input/Output for 2 x I/O mode or Serial Data Input/Output for 4 x I/O mode
WP#/SIO2 Hardware write protection or serial data Input/Output for 4 x I/O mode
HOLD#/SIO3 To pause the device without deselecting the device or serial data Input/Output for 4 x I/O mode
PACKAGE 8-pin SOP (200mil) All devices are RoHS Compliant and Halogen-free 2. GENERAL DESCRIPTION GPR25L6403F is 64Mb bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in four I/O mode, the structure becomes 16,777,216 bits x 4. When it is in two I/O mode, the structure becomes 33,554,432 bits x 2. GPR25L6403F feature a serial peripheral interface and software protocol allowing operation on a simple 3 -wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial

© Generalplus Technology Inc. Proprietary & Confidential 5 Jul. 06, 2015 Version: 1.0 data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. GPR25L6403F, MXSMIO ® (Serial Multi I/O) flash memory, provides sequential read operation on the whole chip and multi-I/O features. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis. Erase command is executed on 4K -byte sector, 32K -byte/64K-byte block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the ch ip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode. The GPR25L6403F utilizes Macronix's proprietary memory cell , which reliably stores memory contents even after 100,000 program and erase cycles. 3. PIN CONFIGURATIONS 3.1. 8-PIN SOP (200mil) 4. PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1xI/O)/ Serial DataInput & Output (for 2xI/O mode and 4xI/O mode) SO/SIO1 Serial Data Output (for 1xI/O)/Serial Data Input & Output (for 2xI/O mode and 4xI/O mode) SCLK Clock Input WP#/SIO2 Write protection Active Low or Serial Data Input & Output (for 4xI/O mode) HOLD#/SIO3 To pause the device without deselectingthe device or Serial data Input/Output for 4 x I/O mode VCC + 3.0V Power Supply GND Ground NC No Connection Note: 1. The HOLD# pin has internal pull up.

© Generalplus Technology Inc. Proprietary & Confidential 7 Jul. 06, 2015 Version: 1.0 6. DATA PROTECTION During power transition, th ere may be some false system level signals which result in inadvertent erasure or programming. The device is designed to protect itself from these accidental write cycles. The state machine will be reset as standby mode automatically during power up. In addition, the control register architecture of the device constrains that the memory contents can only be changed after specific command sequences have completed successfully. In the following, there are several features to protect the system from the acci dental write cycles during VCC power -up and power-down or from system noise.

Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.
Write Enable (WREN) command: WREN command is req uired to set the Write Enable Latch bit (WEL) before other command to change data.
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from Deep Power Down mode comman d (RDP) and Read Electronic Signature command (RES). I. Block lock protection - The Software Protected Mode (SPM) uses (TB, BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The protected area definition is shown as table of "Table 1. Protected Area Sizes", the protected areas are more flexible which may protect various areas by setting value of TB, BP0-BP3 bits. - The Hardware Protected Mode (HPM) uses WP#/SIO2 to protect the (BP3, BP2, BP1, BP0, TB) bits and SRWD bit. Table1. Protected Area Sizes Protected Area Sizes (T/B bit = 0) Status bit Protect Level BP3 BP2 BP1 BP0 64Mb 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 127th) 0 0 1 0 2 (2blocks, block 126th-127th) 0 0 1 1 3 (4blocks, block 124th-127th) 0 1 0 0 4 (8blocks, block 120th-127th) 0 1 0 1 5 (16blocks, block 112th-127th) 0 1 1 0 6 (32blocks, block 96th-127th) 0 1 1 1 7 (64blocks, block 64th-127th) 1 0 0 0 8 (128blocks, protect all) 1 0 0 1 9 (128blocks, protect all) 1 0 1 0 10 (128blocks, protect all) 1 0 1 1 11 (128blocks, protect all) 1 1 0 0 12 (128blocks, protect all) 1 1 0 1 13 (128blocks, protect all) 1 1 1 0 14 (128blocks, protect all) 1 1 1 1 15 (128blocks, protect all) Protected Area Sizes (T/B bit = 1) Status bit Protect Level BP3 BP2 BP1 BP0 64Mb 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 0th) 0 0 1 0 2 (2blocks, block 0th-1st) 0 0 1 1 3 (4blocks, block 0th-3rd) 0 1 0 0 4 (8blocks, block 0th-7th)

© Generalplus Technology Inc. Proprietary & Confidential 8 Jul. 06, 2015 Version: 1.0 Status bit Protect Level BP3 BP2 BP1 BP0 64Mb 0 1 0 1 5 (16blocks, block 0th-15th) 0 1 1 0 6 (32blocks, block 0th-31st) 0 1 1 1 7 (64blocks, block 0th-63rd) 1 0 0 0 8 (128blocks, protect all) 1 0 0 1 9 (128blocks, protect all) 1 0 1 0 10 (128blocks, protect all) 1 0 1 1 11 (128blocks, protect all) 1 1 0 0 12 (128blocks, protect all) 1 1 0 1 13 (128blocks, protect all) 1 1 1 0 14 (128blocks, protect all) 1 1 1 1 15 (128blocks, protect all) Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0. II. Additional 8K-bit secured OTP for unique identifier: to provide 8K-bit One-Time Program area for setting device unique serial number - Which may be set by factory or system maker. The 8K-bit secured OTP area is composed of two rows of 4K -bit. Customer could lock the first 4K-bit OTP area and factory could lock the other. - Security register bit 0 indicates whether the 2 nd 4K-bit is locked by factory or not. - Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command to set customer lock-down bit1 as "1". Please refer to table of "Table 7. Security Register Definition" for security register bit definition and table of "Table 2. 8K-bit Secured OTP Definition" for address range definition. - To program 8K-bit secured OTP by entering s ecured OTP mode (with ENSO command), and going through normal program procedure, and then exiting secured OTP mode by writing EXSO command. Note: Once lock-down whatever by factory or customer, the corresponding secured area cannot be changed any more. Wh ile in 8K -bit Secured OTP mode, array access is not allowed. Table2. 8K-bit Secured OTP Definition Address range Size Lock-down xxx000~xxx1FF 4096-bit Determined by Customer xxx200~xxx3FF 4096-bit Determined by Factory

Before a command is issued, status register should be checked

to ensure device is ready for the intended operation.

When incorrect command is inputted to this device, it enters

falling edge. In standby mode, SO pin of the device is High-Z.

When correct command is inputted to this device, it enters
For standard single data rate serial mode, in put data is latched
For the following instruc tions: RDID, RDSR, RDSCUR, READ,

instruction will be rejected and not executed.

While a Write Status Register, Program, or Erase operation is in

Figure 1. Serial Modes Supported (for Normal Serial mode) CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported.

© Generalplus Technology Inc. Proprietary & Confidential 11 Jul. 06, 2015 Version: 1.0 9. HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select (CS#) keeping low and starts o n falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low). Figure1. Hold Condition Operation During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will keep high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock (SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. Note: The HOLD feature is disabled during Quad I/O mode.

© Generalplus Technology Inc. Proprietary & Confidential 12 Jul. 06, 2015 Version: 1.0 10. COMMAND DESCRIPTION Table4. Command Sets Read Command I/O 1 1 2 2 4 4 Command READ (normal read) FAST READ (fast read data) 2READ (2 x I/O read command) DREAD (1I / 2O read command) 4READ (4 x I/O read command) QREAD (1I/4O read command) 1st byte 03 (hex) 0B (hex) BB (hex) 3B (hex) EB (hex) 6B (hex) 2nd byte ADD1(8) ADD1(8) ADD1(4) ADD1(8) ADD1(2) ADD1(8) 3rd byte ADD2(8) ADD2(8) ADD2(4) ADD2(8) ADD2(2) ADD2(8) 4th byte ADD3(8) ADD3(8) ADD3(4) ADD3(8) ADD3(2) ADD3(8) 5th byte Dummy(8) Dummy* Dummy(8) Dummy* Dummy(8) Action n bytes read out until CS# goes high n bytes read out until CS# goes high n bytes read out by 2 x I/O until CS# goes high n bytes read out by Dual Output until CS# goes high Quad I/O read with configurable dummy cycles Note: *Dummy cycle number will be different, depending on the bit6 (DC) setting of Configuration Register. Please refer to "Configuration Register" Table. Other Commands Command WREN (write enable) WRDI (write disable) RDSR (read status register) RDCR (read configuration register) WRSR (write status/ configuration register) 4PP (quad page program) SE (sector erase) 1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) 38 (hex) 20 (hex) 2nd byte Values ADD1 ADD1 3rd byte Values ADD2 ADD2 4th byte ADD3 ADD3 Action sets the (WEL) write enable latch bit resets the (WEL) write enable latch bit to read out the values of the status register to read out the values of the configuration register to write new values of the configuration/ status register quad input to program the selected page to erase the selected sector Command BE 32K (block erase 32KB) BE (block erase 64KB) CE (chip erase) PP (page program) DP (Deep power down) RDP (Release from deep power down) PGM/ERS Suspend (Suspends Program/ Erase) 1st byte 52 (hex) D8 (hex) 60 or C7 (hex) 02 (hex) B9 (hex) AB (hex) 75/B0 (hex) 2nd byte ADD1 ADD1 ADD1 3rd byte ADD2 ADD2 ADD2 4th byte ADD3 ADD3 ADD3 Action to erase the selected 32KB block to erase the selected 64KB block to erase whole chip to program the selected page enters deep power down mode release from deep power down mode program/erase operation is interrupted by suspend command

© Generalplus Technology Inc. Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 2: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the reset operation will be disabled. sending WREN instruction code→ CS# goes high. The SIO[3:1] are don't care. Figure 3. Write Enable (WREN) Sequence (Command 06) sending WRDI instruction code→ CS# goes high.

© Generalplus Technology Inc. Proprietary & Confidential 15 Jul. 06, 2015 Version: 1.0 are "0" as default. Which is un-protected. QE bit. The Quad Enable (QE) bit, non -volatile bit, while it is "0" (factory default), it performs non -Quad and WP# is enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into four I/O mode ( QE=1), the feature of HPM will be disabled. SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hard ware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0 ) are read only. The SRWD bit defaults to be "0". Status Register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SRWD (status register write protect) QE (Quad Enable) BP3 (level of protected block) BP2 (level of protected block) BP1 (level of protected block) BP0 (level of protected block) WEL (write enable latch) WIP (write in progress bit) 1=status register write disable 1= Quad Enable 0=not Quad Enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit volatile bit volatile bit Note: see the "Table 1. Protected Area Sizes". Configuration Register The Configuration Register is able to change th e default status of Flash memory. Flash memory will be configured after the CR bit is set. ODS bit The output driver strength ODS bit are volatile bits, which indicate the output driver level of the device. The Output Driver Strength is defaulted=1 when delivered from factory. To write the ODS bit requires the Write Status Register (WRSR) instruction to be executed. TB bit The Top/Bottom (TB) bit is a OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as “0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory device. To write the TB bit requires the Write Status Regi ster (WRSR) instruction to be executed. Configuration Register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reserved DC (Dummy Cycle) Reserved Reserved TB (top/bottom selected) Reserved Reserved ODS x 2READ/4READ DummyCycle x x 0=Top area protect 1=Bottom area protect (Default=0) x x 0,Output driver strength=1 1,Output driver strength=1/4 (Default=0) x volatile x x OTP x x volatile Note: See "Dummy Cycle and Frequency Table", with "Don't Care" on other Reserved Configuration Registers. Dummy Cycle and Frequency Table DC Numbers of Dummy Cycles Freq. (MHz) 2READ 0 (default) 4 80 @ 2.65V ≦ VCC < 3V 104 @ VCC ≧ 3V 1 8 133 4READ 0 (default) 6 80 @ 2.65V ≦ VCC < 3V 104 @ VCC ≧ 3V 1 10 133

© Generalplus Technology Inc. Figure 8. Write Status Register (WRSR) Sequence (Command 01) checked out during the Write Status Register cycle is in progress. Table 5. Protection Modes BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM).

When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters th e hardware protected mode (HPM).

WP#/SIO2 to against data modification. If the system goes into four I/O mode, the feature of HPM will be disabled.

© Generalplus Technology Inc. Table 6. ID Definitions The SIO[3:1] are don't care. The SIO[3:1] are don't care. condition) and continuously. The SIO[3:1] are don't care. Figure 31. Read Security Register (RDSCUR) Sequence it indicates non-factory lock; "1" indicates factory- lock. Secured OTP area cannot be updated any more. to "1". PSB is cleared to "0" after program operation resumes. cleared to "0" after erase operation resumes.

© Generalplus Technology Inc. Table 7. Security Register Definition goes low→ sending WRSCUR instruction → CS# goes high. The SIO[3:1] are don't care. instruction will be rejected and not executed. Figure 32. Write Security Register (WRSCUR) Sequence or Block Erase operation to allow access to the memory array. programmed or the sector or block being erased ( "Table 8. Table 8. Readable Area of Memory While a Program or Erase Program/ Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to "Table 15. AC Characteristics" for tPSL and tESL timings. and RST can be issued at any time after the Suspend instruction.

© Generalplus Technology Inc. Proprietary & Confidential 32 Jul. 06, 2015 Version: 1.0 Description Comment Add (h) (Byte) DW Add (Bit) Data (h/b) (Note1) Data (h) (1-1-2) Fast Read Number of Wait states 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 3Ch 04:00 0 1000b 08h (1-1-2) Fast Read Number of Mode Bits Mode Bits: 000b: Not supported; 010b: 2 bits 07:05 000b (1-1-2) Fast Read Opcode 3Dh 15:08 3Bh 3Bh (1-2-2) Fast Read Number of Wait states 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 3Eh 20:16 0 0100b 04h (1-2-2) Fast Read Number of Mode Bits Mode Bits: 000b: Not supported; 010b: 2 bits 23:21 000b (1-2-2) Fast Read Opcode 3Fh 31:24 BBh BBh (2-2-2) Fast Read 0=not support 1=support 40h 00 0b EEh Unused 03:01 111b (4-4-4) Fast Read 0=not support 1=support 04 0b Unused 07:05 111b Unused 43h:41h 31:08 FFh FFh Unused 45h:44h 15:00 FFh FFh (2-2-2) Fast Read Number of Wait states 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 46h 20:16 0 0000b 00h (2-2-2) Fast Read Number of Mode Bits Mode Bits: 000b: Not supported; 010b: 2 bits 23:21 000b (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh Unused 49h:48h 15:00 FFh FFh (4-4-4) Fast Read Number of Wait states 0 0000b: Not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 4Ah 20:16 0 0000b 00h (4-4-4) Fast Read Number of Mode Bits Mode Bits: 000b: Not supported; 010b: 2 bits 23:21 000b (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5)0Ch: 4KB 4Ch 07:00 0Ch 0Ch Sector Type 1 erase Opcode 4Dh 15:08 20h 20h Sector Type 2 Size Sector/block size = 2^N bytes 00h: N/A; 0Fh: 32KB; 10h: 64KB 4Eh 23:16 0Fh 0Fh Sector Type 2 erase Opcode 4Fh 31:24 52h 52h Sector Type 3 Size Sector/block size = 2^N bytes 00h: N/A; 0Fh: 32KB; 10h: 64KB 50h 07:00 10h 10h Sector Type 3 erase Opcode 51h 15:08 D8h D8h Sector Type 4 Size 00h: N/A, This sector type doesn't exist 52h 23:16 00h 00h Sector Type 4 erase Opcode 53h 31:24 FFh FFh

© Generalplus Technology Inc. Table 13. Parameter Table (1): Macronix Flash Parameter Tables Note 1: h/b is hexadecimal or binary. Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. SFDP Table are reserved by Macronix.

© Generalplus Technology Inc. Proprietary & Confidential 34 Jul. 06, 2015 Version: 1.0 11. POWER-ON STATE The device is at the following states after power-up: - Standby mode - Write Enable Latch (WEL) bit is reset The device must not be selected during power -up and power-down stage until the VCC reaches the following levels: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull -up resistor on CS# may ensure a safe and proper power-up/down level. An internal Power -on Reset (POR) circuit may p rotect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF)

Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
Typical value is calculated by simulation.
The value guaranteed by characterization, not 100% tested in production.

133 MHz

© Generalplus Technology Inc. Proprietary & Confidential 38 Jul. 06, 2015 Version: 1.0 Symbol Alt. Parameter Min. Typ. Max. Unit tPSL (4) Program Suspend Latency 20 us tPRS (5) Latency between Program Resume and next Suspend 0.3 100 us tERS (6) Latency between Er ase Resume and next Suspend 0.3 200 us tRCR Recovery Time from Read 20 us tRCP Recovery Time from Program 20 us tRCE Recovery Time from Erase 12 ms tDP CS# High to Deep Power-down Mode 10 us tRES1 CS# High to Standby Mode without Elect ronic Signature Read 100 us tRES2 CS# High to Standby Mode with Electronic Signature Read 100 us tW Write Status Register Cycle Time 40 ms tBP Byte-Program 10 50 us tPP Page Program Cycle Time 0.33 1.2 ms tSE Sector Erase Cycle Time (4KB) 25 200 ms tBE32K Block Erase Cycle Time (32KB) 0.14 0.6 s tBE Block Erase Cycle Time (64KB) 0.25 1 s tCE Chip Erase Cycle Time 20 60 s tWSR Write Security Register Time 1 ms Notes: 1. tCH + tCL must be greater than or equal to 1/ fC. 2. The value guaranteed by characterization, not 100% tested in production. 3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 4. Latency time is required to complete Erase/Program Suspend operation until WIP bit is "0". 5. For tPRS, minimum timing must be observed before issuing the next program suspend command. However, a period equal to or longer than the typical timing is required in order for the program operation to make progress. 6. For tERS, minimum timing must be observed bef ore issuing the next erase suspend command. However, a period equal to or longer than the typical timing is required in order for the erase operation to make progress.

© Generalplus Technology Inc. Proprietary & Confidential 43 Jul. 06, 2015 Version: 1.0 15. ERASE AND PROGRAMMING PERFORMANCE Parameter Typ. (1) Max. (2) Unit Write Status Register Cycle Time 40 ms Sector Erase Time (4KB) 25 200 ms Block Erase Time (64KB) 0.25 1 s Block Erase Time (32KB) 0.14 0.6 s Chip Erase Time 20 60 s Byte Program Time (via page program command) 10 50 us Page Program Time 0.33 1.2 ms Erase/Program Cycle 100,000 cycles Notes: 1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern. 2. Under worst conditions of 85°C and 2.65V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 16. Data Retention Parameter Condition Min. Max. UNIT Data retention 55˚C 20 - years 17. LATCH-UP CHARACTERISTICS Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V Current -100mA +100mA Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

© Generalplus Technology Inc. Proprietary & Confidential 44 Jul. 06, 2015 Version: 1.0 18. PACKAGE/PAD LOCATIONS 18.1. Ordering Information Product Number Package Type GPR25L6403F-QS13x SOP 8L 200mil-Halogen Free Package Note: x = 1 - 9, serial number.

© Generalplus Technology Inc. Proprietary & Confidential 45 Jul. 06, 2015 Version: 1.0 18.2. Package Information 18.2.1. Package Outline for SOP 8L (200MIL) 18.2.1.1. Dimensions (Inch dimensions are derived from the original mm dimensions) DWG. NO. Revision Reference Issue Date JEDEC EIAJ 6110-1406 5

© Generalplus Technology Inc. Proprietary & Confidential 46 Jul. 06, 2015 Version: 1.0 19. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical lif e support equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please n ote that application circuits illustrated in this document are for reference purposes only.

Selected Specification

Generalplus Technology ... GPR25L6403F-QS13x overview.

Summary

3V, 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

Description

3V, 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY

Source title GPR25L6403F-QS13x Datasheet(PDF) - Generalplus Technology Inc.

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