GPR1024A GENERALPLUS

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GENERALPLUS T ECHNOLOGY I NC. re serves the rig ht to change t his documentation w ithout p rior n otice. I nformation pr ovided by GENE RALPLUS TECHNOLOGY INC. is believ ed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no w arranty for any errors which may appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. GGPPRR11002244AA 112288KK xx 88 BBiittss BBuuss FFllaasshh SEP. 11, 2006 Version 1.0 In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.

© Generalplus Technology Inc. Proprietary & Confidential 2 SEP. 1 1, 2006 Version: 1.0

  1. GENERAL DESCRIPTION GPR1024A, a high-performance 1M-bit bus FLAS H organized as 128K-byte, emb eds a Bus Mem ory Inte rface (B MI) and a serial interface (SIF ). GPR1024A allows GPL13X & GPLB3X MC U t o access it s F LASH memory via BUS memory or 1- bit ser ial interface. In 2.7V to 3.6V po wer, GPR10 24A is able to operat e up to 5.0M Hz. Maximum current of read operation is 1.0mA and maximum current of program/erase is 4.0mA. 2. FEATURES „ 1M-bit (128K x 8 bits). „ Endurance: 20,000 Cycles (min) „ Data Retention: 10 years under Room Temperature „ 128 separate sectors for erase operation and 1K-byte per sector „ Working voltage: 2.7V - 3.6V „ Operating frequency: 5.0MHz „ Operating current: 1.0mA (max.) for re ad and 4 .0mA (max.) for program/erase „ Standby current: 1.0µA (max.) „ TTL-compatible I/O „ Bus memory interface or serial interface 3. BLOCK DIAGRAM This device cont ains six com ponents - Bus M emory Interf ace (BMI), Serial Interface (SIF) , C ommand Interfa ce (CIF), timer , program & erase controller (PECON), and a 1M-bit FLASH. The CF[4:0] and SE L determine the device configuration. When BMI is selected, MC 0 and MC1 b ehave as the Re ad/Write control signal and AD[7:0] are the bi-directional Address/Data bus. BMI executes these signals and gen erates chip enable ( CE ), output enable ( OE ), write enable ( WE ), and FLASH memory address in READ mode. In WRITE mode, BMI also generates FLASH data. CIF interprets signals generated by BMI. If CIF recei ves READ command, it will perform read oper ation from FLASH directly. If CIF receives PROGRAM, ERAS E or MASS ERASE, it for wards these commands to PECON to execute these commands. When SIF is chosen, SCK acts as serial clock and SDA as 1-bit serial I/O. If READ command is received, SIF will also r ead from flash memory dir ectly. If PRO GRAM, ERASE or MASS ERASE is received, SIF al so forwards these commands to EPCO N. When EPCON i s acti ve, i t needs a 2 00 KHz cl ock, provided b y the TIMER block shown in block diagram. Ctrl Addr Data Addr,DataBus Memory Interface Serial- Interface CIF TIMER PECON R,P,E,ME R,P,E,ME XE,YE, SE,OE, ERASE, PROG, MAS1, NVSTR, IFREN Data Status MC[1:0] AD[7:0] CF[4:0] SCK SDA Data 128K x 8 FLASH © Generalplus Technology Inc. Proprietary & Confidential 3 SEP. 1 1, 2006 Version: 1.0
  1. SIGNAL DESCRIPTIONS Mnemonic PIN No. Type Description CF1 - 4 CF0 13 - 16 I Configuration bonding option AD0 - 7 2 – 9 I/O Bus Interface Address/Data I/O MC0 - 1 20 - 21 I Bus Interface write/read control signal SEL 23 I Bus Interface/Serial Interface selection RESET 22 I Reset (low active) SDA 10 I/O Serial Interface data I/O SCK 18 I Serial Interface Clock VDD 1, 17 I Power Supply (2.7V ~ 3.6V) VSS 11 I Ground NC 0, 12 I No connection © Generalplus Technology Inc. Proprietary & Confidential 4 SEP. 1 1, 2006 Version: 1.0
  1. FUNCTIONAL DESCRIPTIONS 5.1. Bus Memory Interface (BMI) 5.1.1. BMI description In the use of Bus Memor y Interface, pins are co nnected as t able below: Name Description CF0 - CF4 Configuration bonding option AD0 - AD7 Bus Interface address/data I/O MC0 - MC1 Bus Interface write/read control signal SEL Connected to GND RESET Reset (low active) SCK Connected to GND SDA Connected to GND VDD Power supply (2.7V ~ 3.6V) VSS GND BMI, an i nterface between GPR1024A and GPL13X or GPLB3X MCU, i s i ntended to provi de fl exible and effi cient memory management. BMI contains an 8-bi t bi-directional Address/Data bus, AD bus, which i s mul tiplexed b y t wo contr ol si gnals - MC0 and MC1. MC0 determines operation mode (Read or Write), and MC1 decides AD bus to be address or data bus. See the following table for MC0 and MC1 configuration. MC1 MC0 AD BUS L L Data for Write L H Data for Read H L AL H H AH AH: high byte address AL: low byte address. The simple timing waveform is as follows: MC0 Read Cycle: MC1 AD AH AL DATA for read Write Cycle: MC0 MC1 AD AH AL DATA for write MC0 falling edge => latch AH. MC1 falling edge => (1) latch AL. (2) if MC0=1Æ READ; if MC0=0 Æ WRITE. MC1 rising edge => if READ, set AD bus to Hi. If WRITE, latch DATA for WRITE. © Generalplus Technology Inc. Proprietary & Confidential 5 SEP. 1 1, 2006 Version: 1.0

5.1.2. BMI AC characteristics Read Cycle AD AH DATA for READ MC1 MC0 CPU_CK tMCAH T/4 tM1M0 tMCAL T/2 AL tPM1 tRHZ Write Cycle AD AH AL tMCAH tMCAL tMCW tWHZ MC1 MC0 T/2 DATA for Write Characteristic Symbol Min. Max. Unit Read cycle Read cycle period T 250 - ns MC0 falling to AH end tMCAH 15 - ns MC1 falling to MC0 rising tM1M0 -20 10 ns MC1 falling to AL end tMCAL - 35 ns Data latch to MC1 falling tPM1 20 35 ns MC1 rising to AD Hi-Z tRHZ - 5.0 ns Write Cycle MC0 rising to MC1 rising tMCW 15 20 ns MC1 rising to AD Hi-Z tRHZ 15 - ns © Generalplus Technology Inc. Proprietary & Confidential 6 SEP. 1 1, 2006 Version: 1.0

5.1.4. BMI configuration setting The Bus Memory Interface (BMI) has four modes - A, C, E, and G. The configuration settings are illustrated in the CF[2:0], where CF indicates the phy sical pi n, see T able 1. For th e ph ysical pi ns, simply apply logic high (1) or low (0) to the pins to participate the settings. More over, the C F[4:3] determi nes t he bank control register ($00 ) confi guration, see the T able 2 fo r detailed setups. Note that the c hange of bank i s accompl ished b y gi ven the corresponding value to the $00. For example, to access the Bank0, a value of “00h” must be given to $00 in addition to a logic value of “00” should be given to the external pins, CF[4:3]. Table 1: CF[2:0], configuration of BMI mode BMI Type CF2 CF1 CF0 Volume ID $0D[1:0] A 0 0 0 00 C 0 1 0 01 E 1 0 0 xx G 1 1 0 01 Table 2: CF[4:3], configuration of bank setting. “b” is for extender memory bank select. Type CF4 CF3 Bank switch 0 0 00XXXXbb 0 1 01XXXXbb 1 0 10XXXXbb A, C, E 1 1 11XXXXbb 1 0 10XXXXbb G 1 1 11XXXXbb 5.1.5. BMI register description The BMI uses MCU address from 4000h to FFFFh and duplicates some registers of GPL13X and GPLB3X into GPR1024A as bank switch. The register usage and mapping table is as below: Memory Bank Switch ($00, BSW) b7 b6 b5 b4 b3 b2 b1 b0 * * - - - - BSW1 BSW0 * $00[7:6] must be set the same value as the logic setting of CF[4:3]. Volume ID ($0D, VOL) b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - VOL1 VOL0 External Memory Mapping ($0B.1, EXC) b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - EXC - MCU address mapping of $C000 - $FFFF b1: EXC = 0: Map to internal ROM = 1: Map to external Bus Flash Note: GENERALPLUS recommend s always keep this bit to “0” when bus flash is applied. 5.1.6. BMI memory mapping ROM (Bank)L 0 H 0 L $00000 - $03FFF $04000 - $07FFF 1 H 1 L $08000 - $0BFFF $0C000 - $0FFFF ROM (Bank)H 3 H 3 L 3 $18000 - $1BFFF $1C000 - $1FFFF 2 H 2 L $10000 - $13FFF $14000 - $17FFF $4000 - $7FFF $8000 - $BFFF FLASH ViewMCU View[AH,AL] © Generalplus Technology Inc. Proprietary & Confidential 7 SEP. 1 1, 2006 Version: 1.0

5.1.7. BMI command sequence 5.1.7.1. Bus memory interface command sequence Bus cycle st nd rd th th thCommand sequence addr data addr data addr data addr data addr data Read device ID 5555h AAh AAAAh 55h 5555h 90h 8000h/ 8001h ID (read) Read status 5555h AAh AAAAh 55h 5555h 70h Any addr. Status (1) Return to normal mode (RESET) XXXX F0h Read RA RD (read) Byte program 5555h AAh AAAAh 55h 5555h A0h PA (2) PD (3) Sector Erase 5555h AAh AAAAh 55h 5555h 80h 5555h AAh AAAAh 55h EA (4) 30h Mass erase 5555h AAh AAAAh 55h 5555h 88h 5555h AAh AAAAh 55h 5555h 10h Note1: Status: b7 for 0/1: busy/ready, b3 for 0/1: fail/success Note2: PA: program byte address Note3: PD: program data Note4: EA: sector erase address (gray bits in next table) 5.1.7.2. Read device ID command output Address Data Manufacture code 00000h C7h Device code 00001h D5h 5.1.7.3. BMI read command sequence Start Write VOL Write BSW Read data from address Read completed FLASH is already at normal operation © Generalplus Technology Inc. Proprietary & Confidential 8 SEP. 1 1, 2006 Version: 1.0

5.1.7.4. BMI byte program command sequence Start Write VOL Write BSW FLASH is already at normal operation Write data AAh to address 5555h Write data 55h to address AAAAh Write data A0h to address 5555h Enter program mode Program data to address Bit7=1? Bit3=1? No Yes Program completed Write F0h to any address Return to normal mode Read any byte Enter status-polling mode FLASH accept no command (including RESET command) when it's busy. Detect end of programming or fail Ready status: accept reset only Exit from status-polling Program time: tPGM © Generalplus Technology Inc. Proprietary & Confidential 9 SEP. 1 1, 2006 Version: 1.0

5.1.7.5. BMI sector erase (1K byte) command sequence Start Write VOL Write BSW FLASH is already at normal operation Write data AAh to address 5555h Write data 55h to address AAAAh Write data 80h to address 5555h Enter sector-erase mode Bit7=1? Bit3=1? No Yes Erase completed Write F0h to any address Return to normal mode Read any byte Enter status-polling mode FLASH accept no command (including RESET command) when it's busy. Detect end of erase Ready status: accept reset only Exit from status-polling Write data AAh to address 5555h Write data 55h to address AAAAh Write data 30h to sector address (EA) which is going to be erased Erase time: tERASE © Generalplus Technology Inc. Proprietary & Confidential 10 SEP. 1 1, 2006 Version: 1.0

5.1.7.6. BMI mass erase command sequence Start Write VOL Write BSW FLASH is already at normal operation Write data AAh to address 5555h Write data 55h to address AAAAh Write data 80h to address 5555h Enter mass-erase mode Bit7=1? Bit3=1? No Yes Erase completed Write F0h to any address Return to normal mode Read any byte Enter status-polling mode FLASH accept no command (including RESET command) when it's busy. Detect end of erase Ready status: accept reset only Exit from status-polling Write data AAh to address 5555h Write data 55h to address AAAAh Erase time: tERASE Write data 10h to address 5555h © Generalplus Technology Inc. Proprietary & Confidential 11 SEP. 1 1, 2006 Version: 1.0

5.1.7.7. Enter status-polling mode from normal mode Start Write volume ID Write bank 00 FLASH is already at normal operation These two steps will detect which chip is selected Write data AAh to address 5555h Write data 55h to address AAAAh Write data 70h to address 5555h Enter status-polling mode Read data from address End of reading? No Yes FLASH is ready Write F0h to any address Return to normal mode Enter status-polling mode FLASH except no command but reset Exit from status polling © Generalplus Technology Inc. Proprietary & Confidential 12 SEP. 1 1, 2006 Version: 1.0

5.1.7.8. Erase algorithm for improving endurance performance Start ERASE procedure (sector erase, mass erase or information block erase) FLASH is already at normal operation Erase time = tERASE No Yes ERASE procedure Erase completed Add 1 phase after verify erase OK Verify the entire memory array to be FFh or not 5.2. Serial Interface (SIF) When using serial Interface, pins are connected as table below: Name Description CF0 - CF4 NC AD0 - AD7 NC MC0 - MC1 NC SEL Connected to VDD RESET Reset (low active) SCK Serial clock SDA Serial data I/O VDD Power supply (2.7V ~ 3.6V) VSS GND 5.2.1. Bit transfer One clock pulse is generated for each data bit transmission. The data on SDA l ine must be st able duri ng the HIG H cl ock peri od. The HIGH or LOW on the data line can only be changed when the clock signal on the SCK line is LOW. SDA SCK change of data allowed data line stable; data valid Within the procedure of the GENERALPLUS Seri al Interface, unique si tuation ari ses for ST ART (S) a nd STOP (P) condi tions. A HIG H to L OW transi tion on SDA l ine whi le SCK i s HI GH indicates a START condition. A LOW to HIGH transition on SDA line while SCK is HIGH means STOP condition. START condition (S) SDA SCK STOP condition (P) © Generalplus Technology Inc. Proprietary & Confidential 13 SEP. 1 1, 2006 Version: 1.0

5.2.2. Instruction set READ with random address access: READ command i s a st art bi t fol lowed b y a n 8-bi t opcode (A[24:17]=10000000) and a 17-bi t address (A[16:0]). Af ter receiving READ command, the SDA li ne should be set to the high-impedance state. G PR1024A will begin shifting out the data address (MSB fi rst) at the falling edge of th e SCK clock and the output data bit will be stable after certain time delay (tACC). Af ter 8 data bi ts are sh ifted out, a stop bi t is needed t o termi nate the command. S 10000000 A16 - A0 D7 - D0 P Start bit Stop bit READ with auto-address-count: READ with auto-address-count command i s the same as READ except that af ter fi rst 8 dat a bi ts are shi fted out, no stop bi t i s inserted befor e the ne xt SCK fal ling edge. G PR1024A will automatically increase the address by 1 and it s data content will be shifted out, preceded b y the clock cycle. The procedure will continue until a stop bit is received. S 10000000 A16 - A0 D7 - D0 D7 - D0 D7 - D0 P addr addr+1 addr+n Start bit Stop bit Byte program: BYTE PR OGRAM command i s a st art bi t fol lowed b y an 8 -bit opcode (A[24:17 ]=00000000), a 17-bi t address ( A[16:0]) and an 8-bit data (D[7:0]). After receiving BYTE PROGRAM command, a specified interval (tPGM) is needed to program data into FLASH. After all, a stop bit terminates the command. S 00000000 A16 - A0 D7 - D0 P Start bit Stop bit Sector erase: SECTOR E RASE command is a st art bit follow ed b y an 8 -bit opcode (A[24:1 7]=01000000) and a 17-bi t ad dress (A[16:0]). A16 to A10 are used to i dentify which sector to be erased. A9 to A0 are DO N’T CARE. Af ter receiving SE CTOR ERASE command, a sp ecified i nterval (t ERASE) i s nee ded to e rase the selected sector in the FLASH. Finally, a stop bi t terminates the command. S 01000000 A16 - A0 P Start bit Stop bit Mass erase: MASS ERASE command is a st art bit followed by an 8-bit opcode (A[24:17]=01100000) and a 17 -bit address (A[16:0]). A16 to A0 are DO N’T CA RE. After receiving MASS ERAS E command, a specified interval (tERASE) is needed to erase the mai n block in the FLASH. Then, a stop bit terminates the command. S 01100000 A16 - A0 P Start bit Stop bit © Generalplus Technology Inc. Proprietary & Confidential 14 SEP. 1 1, 2006 Version: 1.0

Characteristic Symbol Max. Min. Unit Period of SCK tC - 400 ns Low Period of SCK Clock tLOW - 170 ns High Period of SCK Clock tHIGH - 170 ns Address Setup Time tAS - 100 ns Address Hold Time tAH - 20 ns READ Access Time tACC 100 - ns READ Data Hold Time tDH - 20 ns PROGRAM Data Setup Time tPDS - 100 ns PROGRAM Data Hold Time tPDH - 20 ns PROGRAM Time tPGM - 125 us ERASE Time tERASE - 13.5 ms Rise Time of SCK tRCK 15 - ns Fall Time of SCK tFCK 15 - ns Rise Time of SDA tRDA 15 - ns Fall Time of SDA tFDA 15 - ns SDA SCK start stop tRDA tRCKtFCK tFDA Read command A24 A23 D7A0 D6 D5 D4 D3 D2 D1 D0SDA SCK stopstart tACC tDH Read command with auto-address-count A24 A23 D7A0 D6 D0 D7 D0 D7 D0 D0D7SDA SCK addr stopstart addr+1 addr+n tC tHIGH tLOW tAS tAH © Generalplus Technology Inc. Proprietary & Confidential 15 SEP. 1 1, 2006 Version: 1.0

+ wait time (=tPGM) Sector erase and mass erase command A24 A23 A1A2 A0SDA SCK stopstart + wait time (=tERASE) © Generalplus Technology Inc. Proprietary & Confidential 16 SEP. 1 1, 2006 Version: 1.0

  1. ELECTRICAL SPECIFICATIONS 6.1. Absolute Maximum Ratings* Characteristics Symbol Ratings Supply Voltage to Ground Potential VDD -0.5V ~ 4.5V Ambient Operating Temperature TA -10℃ ~ 80 ℃ Storage Temperature TSTG -65℃ ~ 150℃ Output Voltage VOUT -0.5V ~ VDD+0.5V Input Voltage VIN -0.5V ~ VDD+0.5V Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions, see AC/DC Electrical Characteristics. 6.2. Recommended DC Operating Conditions (VDD =2.7V - 3.6V, TA = 0 - 70℃) Limit Characteristics Symbol Min. Typ. Max. Unit Supply Voltage VDD 2.7 3.0 3.6 V Supply Voltage VSS - 0 - V Input High Voltage VIH 2.2 - VDD+0.3 V Input Low Voltage VIL -0.3 - 0.4 V 6.3. DC Characteristics (VDD = 2.7V - 3.6V, TA = 0 - 70℃) Limit Characteristic Symbol Min. Typ. Max. Unit Test Condition Output High Voltage VOH 2.3 - - V IOH = -1.0mA Output Low Voltage VOL - - 0.3 V IOL = 1.0mA Input Leakage Current II(L) - - 1.0 A Output Leakage Current IO(L) - - 1.0 A Operating Supply Current (f = 4.0MHz), CL = 80pF ICC - - 4.0 mA Standby Current (CMOS) ISB - - 1.0 A MC0 = MC1 = VDD AD[0:7] = VSS © Generalplus Technology Inc. Proprietary & Confidential 17 SEP. 1 1, 2006 Version: 1.0
  1. APPLICATION CIRCUITS 7.1. BMI Cascade Access Mode To e xpand memory i n GPR1024A, a cascade access mode is designed to i dentify l ocal memor y and e xpanded memor y. It i s defined b y th e confi guration control si gnal, menti oned i n the previous secti on. Fo r ol d version of SPL seri es, i t i s recommended to expand only to volume 1 (The built-in volume ID is fixed to 1 for Type C and Type G). BFI MEMORY VOLUME 0 Type A local memory BFI MEMORY VOLUME 1 Type C,G expanded memory AD MC0 MC1 © Generalplus Technology Inc. Proprietary & Confidential 18 SEP. 1 1, 2006 Version: 1.0

7.2. Bus Interface MC0 MC1 AD[7:0] CF[4:3] GPR1024A MC0 MC1 AD[7:0] CF[4:3]=00b MC0 MC1 AD[7:0] CF[4:3] GPR1024A MC0 MC1 AD[7:0] CF[4:3] GPR1024A CF[4:3]=01b CF[4:3]=11b © Generalplus Technology Inc. Proprietary & Confidential 19 SEP. 1 1, 2006 Version: 1.0

  1. PACKAGE/PAD LOCATIONS 8.1. PAD Assignment and Locations 0 1 2 3 4 5 6 7 8 9 10 11 23 22 21 20 19 18 17 16 15 14 13 12 NC VDD AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 SDA VSS SEL RESET MC1 MC0 CF0 SCK VDD CF4 CF3 CF2 CF1 NC Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 8.2. Ordering Information Product Number Package Type GPR1024A-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). © Generalplus Technology Inc. Proprietary & Confidential 20 SEP. 1 1, 2006 Version: 1.0
  1. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated ci rcuits sol d b y Generalplus Technology a re covered b y the warranty a nd patent i ndemnification provisions stipulated in th e terms of sal e only. GENERALPLUS makes no warranty, e xpress, statutory i mplied or b y descri ption rega rding th e i nformation i n this publication or regarding the free dom of t he described chip(s) from p atent infringement. FUR THERMORE, GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter the specifications and pri ces at any ti me without noti ce. Accordingly, the reader i s cautioned to verify that the data sheets and othe r information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. A pplications in volving unusual environment al or reli ability requirement s, e.g. milit ary equipment or medical lif e su pport equipment, are s pecifically not re commended without additional processing by GENERALPLUS for such appl ications. Please note that application circuits illustrated in this document are for reference purposes only. © Generalplus Technology Inc. Proprietary & Confidential 21 SEP. 1 1, 2006 Version: 1.0
  1. REVISION HISTORY Date Revision # Description Page SEP. 11, 2006 1.0 Original Note: The GPR1024A data sheet v1.0 is a continued version of SPR1024A data sheet v1.3. © Generalplus Technology Inc. Proprietary & Confidential 22 SEP. 1 1, 2006 Version: 1.0