Microcontroller

GPM8F1019A

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30/20-pin Microcontroller with 128/64/32/18KB Flash Memory

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Generalplus Technology Inc. reserves the right to change this documentation without prior notice. Information provided by Generalplus Techno logy Inc. is believed to be accurate and reliable. However, Generalplus Technology Inc. makes no warranty for any errors which may appear in this document. Contact Generalplus Technology Inc. to obtain the latest version of device specifications before placing your order. No responsibili ty is assumed by Generalplus Technology Inc. for any infringement of patent or other rights of t hird parties which may result from its use. In addition, Generalplus products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus. DATA SHEET Jan. 21, 2015 Version 1.0 GGPPMM88FF11112299AA GGPPMM88FF11006655AA GGPPMM88FF11003333AA GGPPMM88FF11001199AA 3300//2200--ppiinn MMicrocontroller wwiitthh 112288//6644//3322//1188KKBB FFllaasshh MMeemmoorryy

© Generalplus Technology Inc. Proprietary & Confidential 5 Jan. 21, 2015 Version: 1.0 30/20 PIN 8-BIT MICROCONTROLLER WITH 128/64/32/18KB FLASH 1. GENERAL DESCRIPTION The GPM8F1129A/GPM8F1065A/GPM8F1033A/GPM8F1019A, a highly integrated microcontroller, integrates a pipelined 1T 8051 CPU, 1.5K-byte XRAM, 256-byte IDM SRAM and 128K/64K/32K/18K-byte program Flash memory. It also contains a maximum of 23 programmable multi -functional I/Os, Timer0/1/2, UART0, SPI (master), I2C, and CMDT for a variety of applications. It operates over a wide voltage range from 1.8V through 5.5V and wide temperature range from -5℃ ~ 70℃. It features t wo power management modes for power saving purpose. To make development and debug work more easily, an on-chip debug circuit is included to facilitate full speed in-system debug. For more details about GPM8F series, please refer to the feature list in the following section. 2. FEATURES  CPU  High speed, high performance 1T 8051  100% software compatible with industry standard 8051  Pipeline RISC architecture enhances executing instructions 10 times faster than standard 8051  Up to 16MHz clock operation  Memories  1.5K bytes XRAM  256 bytes internal Data Memory (IDM) SRAM  Up to 128/64/32/18K bytes Flash with high endurance  Minimum of 100K progam/erase cycles  Minimum of 10 years data retention  Page size 1kB  Programming lock level for software security  Clock Management  Internal oscillator: 16MHz±1.5% @ 2.0V~5.5V  Crystal input with 1MHz~16MHz  Slow Clock  Internal oscillator: 4KHz  Power Management  One STOP mode for power saving  One IDLE mode for only peripheral operation  Interrupt Management  Up to 9 internal interrupt sources  Up to 5 external interrupt sources  Up to 8 keyboard Interrupt sources  Reset Management  Power On Reset (POR)  Low Voltage Reset (LVR)  Pad Reset (PAD_RST)  Watchdog Reset (WDT_RST)  Software Reset (S/W_RST)  Stop mode Reset (STOP_RST)  Miss Clock Reset (MISS_CLK_RST)  Flash Related Error Reset (FLASH_ERR_RST)  Programmable Watchdog Timer  A time-base generator  An event timer  System supervisor  I/O Ports  Max. 23 multifunction bi-directional I/Os  Each incorporate with pull-up resistor, pull-down resistor, output high, output low or floating input, depending on the settings in the corresponding registers  I/O ports with 12mA current sink  I/O ports with 12mA current drive  Two 16-bit Timer/Counter (Timer 0/1)  Timer mode with clock source selectable  Auto reload 8-bit timers  One Powerful Timer2 with 16-bit Compare/Capture Unit  Timer mode with clock source selectable  Auto reload 16-bit timers  Event capturing  Digital signals generator  Pulse width modulation and measurement  UART0  One synchronous mode  Three asynchronous modes  SPI (master mode)  Programmable phase and polarity of master clock  Programmable master clock frequency  Auto read/write function  Max SPI clock: 4MHz (FOSC /4) @16MHz  I2C (master/slave mode)  Carrier Modulator/Demodulator Timer (CMDT)  One 8-bit Timer A for carrier generation and detection  One 16-bit Timer B for envelop generation and detection  Drives IR_TX pin for remote control communication  Receive IR signal from IR_RX pin  Built-in Low Voltage Reset  Trigger level: 1.9V  Built-in low Voltage Detect  Programmable level: 2.3V, 2.5V, 3.3V, 3.5V

© Generalplus Technology Inc. Proprietary & Confidential 6 Jan. 21, 2015 Version: 1.0  On-chip Debug Unit  C compatible Development Tools Part NO. Voltage(V) Speed (MHz) Flash (Byte) IDM (Byte) XDM (Byte) CMDT IR Tx/Rx CPU OSC. IO No. PKG INT XTAL GPM8F1129A 1.8~5.5 16 128K 256 1.5k  Tx/Rx   23/15 SSOP30/SSOP20 GPM8F1065A 1.8~5.5 16 64K 256 1.5k  Tx/Rx   23/15 SSOP30/SSOP20 GPM8F1033A 1.8~5.5 16 32K 256 1.5k  Tx/Rx   23/15 SSOP30/SSOP20 GPM8F1019A 1.8~5.5 16 18K 256 1.5k  Tx/Rx   23/15 SSOP30/SSOP20 3. BLOCK DIAGRAM 3.1. GPM8F1129A Timer 2 (P13)XTI (P12)XTO Interrupt Management XTAL circuit 256-byte IDM 128K bytes Flash P2[3:0] Watchdog Timer Regulator & POR & LVR RESET Management 1.5K Bytes XRAM Timer 01 Power saving controller DATA BUS VDD VSS 8-bit CPU & ICE PORT 3[4:0]P3[4:0] ADDR BUS PORT 2[3:0] CMDT UART SPI (Master Mode ) I2C PORT 0[7:0] PORT 1[7:2]P1[7:2] P0[7:0] VREG ICESCK /RESET ICESDA IR_TX(P21 or P34) Internal OSC IR_RX(P20)

© Generalplus Technology Inc. Proprietary & Confidential 7 Jan. 21, 2015 Version: 1.0 3.2. GPM8F1065A Timer 2 (P13)XTI (P12)XTO Interrupt Management XTAL circuit 256-byte IDM 64K bytes Flash P2[3:0] Watchdog Timer Regulator & POR & LVR RESET Management 1.5K Bytes XRAM Timer 01 Power saving controller DATA BUS VDD VSS 8-bit CPU & ICE PORT 3[4:0]P3[4:0] ADDR BUS PORT 2[3:0] CMDT UART SPI (Master Mode ) I2C PORT 0[7:0] PORT 1[7:2]P1[7:2] P0[7:0] VREG ICESCK /RESET ICESDA IR_TX(P21 or P34) Internal OSC IR_RX(P20)

© Generalplus Technology Inc. Proprietary & Confidential 8 Jan. 21, 2015 Version: 1.0 3.3. GPM8F1033A Timer 2 (P13)XTI (P12)XTO Interrupt Management XTAL circuit 256-byte IDM 32K bytes Flash P2[3:0] Watchdog Timer Regulator & POR & LVR RESET Management 1.5K Bytes XRAM Timer 01 Power saving controller DATA BUS VDD VSS 8-bit CPU & ICE PORT 3[4:0]P3[4:0] ADDR BUS PORT 2[3:0] CMDT UART SPI (Master Mode ) I2C PORT 0[7:0] PORT 1[7:2]P1[7:2] P0[7:0] VREG ICESCK /RESET ICESDA IR_TX(P21 or P34) Internal OSC IR_RX(P20)

© Generalplus Technology Inc. Proprietary & Confidential 9 Jan. 21, 2015 Version: 1.0 3.4. GPM8F1019A Timer 2 (P13)XTI (P12)XTO Interrupt Management XTAL circuit 256-byte IDM 18K bytes Flash P2[3:0] Watchdog Timer Regulator & POR & LVR RESET Management 1.5K Bytes XRAM Timer 01 Power saving controller DATA BUS VDD VSS 8-bit CPU & ICE PORT 3[4:0]P3[4:0] ADDR BUS PORT 2[3:0] CMDT UART SPI (Master Mode ) I2C PORT 0[7:0] PORT 1[7:2]P1[7:2] P0[7:0] VREG ICESCK /RESET ICESDA IR_TX(P21 or P34) Internal OSC IR_RX(P20)

© Generalplus Technology Inc. Proprietary & Confidential 10 Jan. 21, 2015 Version: 1.0 4. SIGNAL DESCRIPTIONS SSOP30: Type: I = Input, O = Output, S = Supply Pin Name SSOP30 Type Description NC 1 NA Not connected P23 2 I/O Port 2’s bit 3/ I2CSDA VREG 3 S Regulator output ICESDA 4 I/O ICE data input/output ICESCK 5 I/O ICE clock input/ RESET P12 6 I/O Port 1’s bit 2/ XTO VSS 7 S Ground P13 8 I/O Port 1’s bit 3/ XTI VDD 9 S Power 5V input P14 10 I/O Port 1’s bit 4/ MOSI P15 11 I/O Port 1’s bit 5/ SPSCK P16 12 I/O Port 1’s bit 6/ MISO P17 13 I/O Port 1’s bit 7/ SPCSB P30 14 I/O Port 3’s bit 0/ RXD/ INT3 P31 15 I/O Port 3’s bit 1/ TXD/ INT4 P32 16 I/O Port 3’s bit 2/ INT0 P00 17 I/O Port 0’s bit 0/ KBI_0 P01 18 I/O Port 0’s bit 1/ KBI_1 P02 19 I/O Port 0’s bit 2/ KBI_2 P03 20 I/O Port 0’s bit 3/ KBI_3 P04 21 I/O Port 0’s bit 6/ KBI_4 P05 22 I/O Port 0’s bit 7/ KBI_5 P06 23 I/O Port 0’s bit 6/ KBI_6 P07 24 I/O Port 0’s bit 7/ KBI_7 P33 25 I/O Port 3’s bit 3/ INT1 P34 26 I/O Port 3’s bit 4/ INT2/ CMPO/ IR_TX P20 27 I/O Port 2’s bit 0/ IR_RX P21 28 I/O Port 2’s bit 1/ IR_TX P22 29 I/O Port 2’s bit 2/ I2CSCK NC 30 NA Not connected

© Generalplus Technology Inc. Proprietary & Confidential 11 Jan. 21, 2015 Version: 1.0 SSOP20: Type: I = Input, O = Output, S = Supply Pin Name SSOP20 Type Description VREG 1 S Regulator output ICESDA 2 I/O ICE data input/output ICESCK 3 I/O ICE clock input/ RESET VSS 4 S Ground VDD 5 S Power 5V input P34 6 I/O Port 3’s bit 4/ INT2/ CMPO/ IR_TX P33 7 I/O Port 3’s bit 3/ INT1 P30 8 I/O Port 3’s bit 0/ RXD/ INT3 P31 9 I/O Port 3’s bit 1/ TXD/ INT4 P32 10 I/O Port 3’s bit 2/ INT0 P00 11 I/O Port 0’s bit 0/ KBI_0 P01 12 I/O Port 0’s bit 1/ KBI_1 P02 13 I/O Port 0’s bit 2/ KBI_2 P03 14 I/O Port 0’s bit 3/ KBI_3 P04 15 I/O Port 0’s bit 6/ KBI_4 P05 16 I/O Port 0’s bit 7/ KBI_5 P06 17 I/O Port 0’s bit 6/ KBI_6 P07 18 I/O Port 0’s bit 7/ KBI_7 P20 19 I/O Port 2’s bit 0/ IR_RX P21 20 I/O Port 2’s bit 1/ IR_TX

© Generalplus Technology Inc. Proprietary & Confidential 12 Jan. 21, 2015 Version: 1.0 P04/KBI4 P03/KBI3 VREG SSOP 20 VDD P30/INT3/RxD P02/KBI2 P01/KBI1 P00/KBI0 P31/INT4/TxD ICESCK /RESET ICESDA /P11 VSS P34/INT2/CCP 0 P33/INT1 P32/INT0 P05/KBI5 P07/KBI7 P06/KBI6 P20/IR_RX P21/IR_TX 4.1. PIN Map SSOP30: VDD VSS P05/KBI5 P04/KBI4 P03/KBI3 VREG SSOP 30 ICESCK /RESET ICESDA SPCSB /P17 P22/I2CSCK INT3/RxD/P30 P02/KBI2 P01/KBI1 P00/KBI0 P07/KBI7 P06/KBI6 INT4/TxD/P31 P33/INT1 P34/INT2/CMPO I2CSDA /P23 P20/IR_RX SPSCK /P15 MISO /P16 MOSI /P14 P32/INT0 XTO/P12 XTI/P13 15 16 P21/IR_TX 1 30NC NC SSOP20: Note: The pins which are not used is SSOP20 must be configured to avoid current leakage.

© Generalplus Technology Inc. Proprietary & Confidential 13 Jan. 21, 2015 Version: 1.0 5. FUNCTION DESCRIPTION 5.1. CPU The CPU is an ultra -high performance, high speed embedded microcontroller. Pipelined architecture enables the CPU 10 times faster than standard architecture. Th is performance can also be exploited to great advantage in low power application where the core can be clocked over ten times slower than original implementation for no performance penalty. The CPU is fully compatible with industry standard 8051 microcontroller, maintaining all instruction mnemonics and binary compatibility. It incorporates some great architectural enhancements, allowing the CPU instructions execution with high performance and high speed. 5.1.1. CPU Features  100 % software compatible with industry 8051  24 times faster multiplication operation  12 times faster addition operation The CPU is fully compatible with industry standard 8051 microcontroller, maintaining all instruction mnemonics and binary compatibility. It incorporates some great arc hitectural enhancements, allowing the CPU instructions execution with high performance and high speed. The arithmetic section of the processor performs extensive data manipulation and is comprised of an 8-bit arithmetic logic unit (ALU), an ACC(0xE0) reg ister, B(0xF0) register and PSW(0xD0) register. 5.1.2. Arithmetic Logic Unit (ALU) The ALU performs the arithmetic and logic operations during one instruction execution. Typical arithmetic operations are addition, subtraction, multiplication and division. Additional operations are such as increment, decrement, BCD -decimal-add-adjust and compare. Within logic unit, operation such as AND, OR, Exclusive OR, complement and rotation are performed. The Boolean processor performs the bit operations as set, clear, complement, jump -if-not-set, jump -if-set-and-clear and move to/from carry. 5.1.3. Accumulator A register The accumulation is the 8 -bit general-purpose register, which can be operated with data transfer, temporary saving, condition judgment, etc. 5.1.4. B Register The B register is used during multiply ing and dividing operations. In other cases, it may be used as normal SFR. 5.1.5. Program Status Word (PSW) The PSW contains several bits that reflect the current state of the CPU which is similar to the flag-register of general CPU. 5.1.6. Program Counter (PC) The program counter is a 16 -bit wide register. It consists of two 8-bit registers which are PCH and PCL. This register indicates the address of next instruction to be executed. In Reset state, the content of 0x0000 is stored into program counter. The GPM8F1129A supports both LARGE mode and FLAT mode. The program counter is a 16 -bit register in LARGE mode, but 23-bit register in FLAT mode. Switching between LARGE and FLAT modes is performed by appropriate writ ing into AM b it of ACON (0x9D) register. ACC Address: 0xE0 Accumulator A Register Bit 7 6 5 4 3 2 1 0 Function ACC[7:0] Default 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 7:0 ACC[7:0] R/W Accumulator A Table 5-1 The ACC register

© Generalplus Technology Inc. Proprietary & Confidential 14 Jan. 21, 2015 Version: 1.0 B Address: 0xF0 B Register Bit 7 6 5 4 3 2 1 0 Function B[7:0] Default 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 7:0 B[7:0] R/W B Table 5-2 The B register PSW Address: 0xD0 Program Status Word Register Bit 7 6 5 4 3 2 1 0 Function CY AC F0 RS1 RS0 OV F1 P Default 0 0 0 0 0 0 0 0 Bit Function Type Description Condition

7 CY R/W Carry flag

6 AC R/W Auxiliary carry flag

4:3 RS[1:0] R/W Register bank select bits RS[1:0] Function description

00 Bank 0, data address 0x00-0x07

01 Bank 1, data address 0x08-0x0F

10 Bank 2, data address 0x10-0x17

11 Bank 3, data address 0x18-0x1F

2 OV R/W Overflow flag

0 P R/W Parity flag

Table 5-3 The PSW register ACON Address: 0x9D Address Control Register Bit 7 6 5 4 3 2 1 0 Function -- -- -- -- -- -- AM -- Default 0 0 0 0 0 0 0 0 Bit Function Type Description Condition 7:2 -- R/W Reserved

1 AM R/W Addressing Mode

0: 16-bit Addressing Mode - LARGE 1: 23-bit Contiguous Addressing Mode - FLAT 0 -- R/W Reserved Table 5-4 The ACON register (GPM8F1129A only)

© Generalplus Technology Inc. Proprietary & Confidential 15 Jan. 21, 2015 Version: 1.0 5.2. Memory 5.2.1. Introduction The GPM8F 1129/1065/1033/1019A has three separated address spaces for program memory and data memory. The program memory is on-chip, re-programmable Flash memory and contains up to 128/ 64/ 32/ 18K bytes spaces. The data memory is divided into 1.5K bytes of external RAM, 256 bytes IDM SRAM with 128 bytes of SFR which can be read and written. The upper IDM and SFR use the same access address in different access ways , described in Figure 5-2. 5.2.2. Program Memory Allocation The GPM8F1129/ 1065/ 1033/ 1019A implement 128/ 64/ 32/ 18KB program memory size. The program memory allocation is divided into four parts, including first page, normal page, data flash and loader zone. The address space between 0x 00000 and 0x03FF is called FIRST_PAGE. It is used for reset vector, IRQ vectors, passwords and CONFIG_BYTE. The CONFIG_BYTE is located in 0x008F of program memory. The content of CONFIG_BYTE also can be read from CONFIG_ BYTE register (0xB7) of SFR. The definition of CONFIG_BYTE is shown in Table 5-5. The address space between 0x 88 and 0x8b is used for passwords (i.e. PASSWD0~PASSWD3). If CONFIG_BYTE[0] is programmed to be ‘0’, the whole chip memory is protected and any page erase or program by two wire serial interface is not allowed. The only thing user can do is to erase the entire chip. A user can choose to allow or disallow the rea d operation of whole chip memory in code lock state by setting CONFIG_BYTE[3] to “0”. If CONFIG_BYTE[3] is set to “0” and user-entered password s match contents of PASSWD0~PASSWD3, the whole chip memory can be read even in code lock state. The address space between 0x0400 and 0x01CFFF/0xCFFF/0x4FFF/0x17FF is used for user code area. The last 12K bytes are used for data flash and loader zone. After each reset, CPU starts execution in the program memory at location 0x0000 or loader zone based on the value of 0x8E in Flash or 0xCF in SFR . The value of JMP_LZ is 0xFF in default, and CPU will jump to loader zone after reset . Each interrupt has its own start address for service routine. The Flash memory can be programmed in -system, through the SCK/SDA interface or by software using the MOVX instruction when PWE= 1. Flash data cannot be programmed from a ‘0’ to a ‘1’, and can only be recognized by erase operation. Therefore, flash data will typically be erased (set to 0xFF) before being programmed. The write and erase operations are executed using PSIDLE (Pseudo-idle) mode to be automatically timed by hardware without data polling to determine the end of the write and erase operation. For software security consideration, user can set the programmable Flash level by FL_LEVEL register to limit the code area that avoids inadvertently erased or written by software; the protected region is called READONLY_PAGE. The GPM8F1129/ 1065/ 1033/ 1019A implements three control bytes for bo ot loader applications (i.e. JMP_LZ , LZ_SEL and DF_SEL). The JMP_LZ/LZ_SEL/DF_SEL is allocated in 0x8E/0x8D/0x8C of program memory. The reset vector of GPM8F1129/ 1065/ 1033/ 1019A can be changed to 0x1FC00/ 0xFC00/ 0x7C00/ 0x4400 by writing #0xFF to JM P_LZ (0x8E of program memory). The LZ_SEL is used to protect the content of loader zone. The DF_SEL is used to protect the content of data flash when CPU is executing loader code. CPU should execute “JLMP 0x1FC00 (GMP8F1129A) / 0xFC00(GMP8F1065A) / 0x7C00(GMP8F1033A) / 0x4400(GMP8F1019A)” instruction or write #0xFF to JMP_LZ before executing loader code. The FIRST_PAGE can be programmed or erased, when the loader code is in progress, Table 5-8, Table 5-9 and Table 5-10 show the definition of JMP_LZ, LZ_SEL and DF_SEL respectively. GPM 8F1129A Normal Page First Page 0x1FFFF 0x00000 0x003FF 0x00400 Data Flash + Loader Zone (12KBytes ) 0x1D000 0x1CFFF GPM8F1065A Normal Page First Page 0xFFFF 0x0000 0x03FF 0x0400 Data Flash + Loader Zone (12KBytes ) 0xD000 0xCFFF GPM 8F1033A Normal Page First Page 0x7FFF 0x0000 0x03FF 0x0400 Data Flash + Loader Zone (12KBytes ) 0x5000 0x4FFF GPM 8F1019A Normal Page First Page 0x47FF 0x0000 0x03FF 0x0400 Data Flash + Loader Zone (12KBytes ) 0x1800 0x17FF Figure 5-1 Program memory organization

© Generalplus Technology Inc. Proprietary & Confidential 16 Jan. 21, 2015 Version: 1.0 CONFIG_BYTE Address: 0xB7 CONFIG_BYTE Register Bit 7 6 5 4 3 2 1 0 Function -- -- -- -- PWENB -- IOSEL CODE_UNLOCK Default 1 1 1 1 1 1 1 1 Bit Function Type Description Condition 7:4 -- R Reserved

3 PWENB R/W Password mechanism enable bit

0: Passwords mechanism enable 1: Passwords mechanism disable 2 -- R Reserved

1 IOSEL R/W IO initial state selection bit

0: Input pull high 1: floating

0 CODE_UNLOCK R/W Program memory protection enable bits

0: CODE is locked 1: CODE is unlocked Note: default value of CONFIG_BYTE = 0xFF Table 5-5 CONFIG_BYTE description FL_LEVEL Address: 0xED Flash Level Register Bit 7 6 5 4 3 2 1 0 Function FLASH_LEVEL[6:0] Default 1 1 1 1 1 1 1 1 Bit Function Type Description Condition 7 -- R/W Reserved 6:0 FLASH_LEVEL[6:0] R/W FLASH_LEVEL, it determines the number of 1K page is read only, shown in the following table. Note 1. Only FLASH_LEVEL[4:0] is useful in GPM8F1019A Note 2. Only FLASH_LEVEL[4:0] is useful in GPM8F1033A Note 3. Only FLASH_LEVEL[5:0] is useful in GPM8F1065A Note 4. Only FLASH_LEVEL[6:0] is useful in GPM8F1129A Table 5-6 The FL_LEVEL register FLASH_LEVEL Note FLASH_LEVEL Note 0x00 no page is read only 0x40 address < 0x10400 is read only 0x01 address < 0x800 is read only 0x41 address < 0x10800 is read only 0x02 address < 0xC00 is read only 0x42 address < 0x10C00 is read only 0x03 address < 0x1000 is read only 0x43 address < 0x11000 is read only 0x04 address < 0x1400 is read only 0x44 address < 0x11400 is read only 0x05 address < 0x1800 is read only 0x45 address < 0x11800 is read only 0x06 address < 0x1C00 is read only 0x46 address < 0x11C00 is read only 0x07 address < 0x2000 is read only 0x47 address < 0x12000 is read only 0x08 address < 0x2400 is read only 0x48 address < 0x12400 is read only 0x09 address < 0x2800 is read only 0x49 address < 0x12800 is read only

© Generalplus Technology Inc. Proprietary & Confidential 17 Jan. 21, 2015 Version: 1.0 FLASH_LEVEL Note FLASH_LEVEL Note 0x0A address < 0x2C00 is read only 0x4A address < 0x12C00 is read only 0x0B address < 0x3000 is read only 0x4B address < 0x13000 is read only 0x0C address < 0x3400 is read only 0x4C address < 0x13400 is read only 0x0D address < 0x3800 is read only 0x4D address < 0x13800 is read only 0x0E address < 0x3C00 is read only 0x4E address < 0x13C00 is read only 0x0F address < 0x4000 is read only 0x4F address < 0x14000 is read only 0x10 address < 0x4400 is read only 0x50 address < 0x14400 is read only 0x11 address < 0x4800 is read only 0x51 address < 0x14800 is read only 0x12 address < 0x4C00 is read only 0x52 address < 0x14C0 is read only 0x13 address < 0x5000 is read only 0x53 address < 0x15000 is read only 0x14 address < 0x5400 is read only 0x54 address < 0x15400 is read only 0x15 address < 0x5800 is read only 0x55 address < 0x15800 is read only 0x16 address < 0x5C00 is read only 0x56 address < 0x15C00 is read only 0x17 address < 0x6000 is read only 0x57 address < 0x16000 is read only 0x18 address < 0x6400 is read only 0x58 address < 0x16400 is read only 0x19 address < 0x6800 is read only 0x59 address < 0x16800 is read only 0x1A address < 0x6C00 is read only 0x5A address < 0x16C00 is read only 0x1B address < 0x7000 is read only 0x5B address < 0x17000 is read only 0x1C address < 0x7400 is read only 0x5C address < 0x17400 is read only 0x1D address < 0x7800 is read only 0x5D address < 0x17800 is read only 0x1E address < 0x7C00 is read only 0x5E address < 0x17C00 is read only 0x1F address < 0x8000 is read only 0x5F address < 0x18000 is read only 0x20 address < 0x8400 is read only 0x60 address < 0x18400 is read only 0x21 address < 0x8800 is read only 0x61 address < 0x18800 is read only 0x22 address < 0x8C00 is read only 0x62 address < 0x18C00 is read only 0x23 address < 0x9000 is read only 0x63 address < 0x19000 is read only 0x24 address < 0x9400 is read only 0x64 address < 0x19400 is read only 0x25 address < 0x9800 is read only 0x65 address < 0x19800 is read only 0x26 address < 0x9C00 is read only 0x66 address < 0x19C00 is read only 0x27 address < 0xA000 is read only 0x67 address < 0x1A000 is read only 0x28 address < 0xA400 is read only 0x68 address < 0x1A400 is read only 0x29 address < 0xA800 is read only 0x69 address < 0x1A800 is read only 0x2A address < 0xAC00 is read only 0x6A address < 0x1AC00 is read only 0x2B address < 0xB000 is read only 0x6B address < 0x1B000 is read only 0x2C address < 0xB400 is read only 0x6C address < 0x1B400 is read only 0x2D address < 0xB800 is read only 0x6D address < 0x1B800 is read only 0x2E address < 0xBC00 is read only 0x6E address < 0x1BC00 is read only 0x2F address < 0xC000 is read only 0x6F address < 0x1C000 is read only 0x30 address < 0xC400 is read only 0x70 address < 0x1C400 is read only 0x31 address < 0xC800 is read only 0x71 address < 0x1C800 is read only 0x32 address < 0xCC00 is read only 0x72 address < 0x1CC00 is read only 0x33 address < 0xD000 is read only 0x73 address < 0x1D000 is read only 0x34 address < 0xD400 is read only 0x74 address < 0x1D400 is read only 0x35 address < 0xD800 is read only 0x75 address < 0x1D800 is read only 0x36 address < 0xDC00 is read only 0x76 address < 0x1DC00 is read only

© Generalplus Technology Inc. Proprietary & Confidential 18 Jan. 21, 2015 Version: 1.0 FLASH_LEVEL Note FLASH_LEVEL Note 0x37 address < 0xE000 is read only 0x77 address < 0x1E000 is read only 0x38 address < 0xE400 is read only 0x78 address < 0x1E400 is read only 0x39 address < 0xE800 is read only 0x79 address < 0x1E800 is read only 0x3A address < 0xEC00 is read only 0x7A address < 0x1EC00 is read only 0x3B address < 0xF000 is read only 0x7B address < 0x1F000 is read only 0x3C address < 0xF400 is read only 0x7C address < 0x1F400 is read only 0x3D address < 0xF800 is read only 0x7D address < 0x1F800 is read only 0x3E address < 0xFC00 is read only 0x7E address < 0x1FC00 is read only 0x3F address < 0x10000 is read only 0x7F address < 0x20000 is read only Table 5-7 The description of FL_LEVEL register JMP_LZ Address: 0x008E (Program Memory) Jump to Loader Zone Control Register Bit 7 6 5 4 3 2 1 0 Function JMP_LZ[7:0] Default 1 1 1 1 1 1 1 1 Bit Function Type Description Condition 7:0 JMP_LZ[7:0] R/W CPU jumps to loader zone control bits #0x55: After each reset, CPU starts execution in the program memory at location 0x0000 #0xFF: After each reset, CPU starts execution in the program memory at location 0x1FC00 (GPM8F1129A)/ 0xFC00(GPM8F1065A)/ 0x7C00(GPM8F1033A)/ 0x4400(GPM8F1019A) Table 5-8 The JMP_LZ register LZ_SEL Address: 0x008D (Program Memory) Loader Zone Area Control Register Bit 7 6 5 4 3 2 1 0 Function -- -- -- -- -- LZ_SEL[2:0] Default 1 1 1 1 1 1 1 1 Bit Function Type Description Condition 7:3 -- R Reserved 2:0 LZ_SEL[2:0] R/W Loader zone area control bits GPM8F1129A:

000 No loader zone selected

001 The size of loader zone is 1K bytes (0x1FC00~0x1FFFF)

and it cannot be programmed by software.

010 The size of loader zone is 2K bytes (0x1F800~0x1FFFF)

and it cannot be programmed by software.

011 The size of loader zone is 3K bytes (0x1F400~0x1FFFF)

and it cannot be programmed by software.