RAA211320 RENESAS

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
  • PDF pages: 24

Technical content

Datasheet sections

  • 1.1 Block Diagram
  • 2.1 Pin Assignments
  • 2.2 Pin Descriptions
  • 3.1 Absolute Maximum Ratings
  • 3.2 Thermal Information
  • 3.3 Recommended Operating Conditions
  • 3.4 Electrical Specifications
  • 5.1 Soft-Start
  • 5.2 Undervoltage Lockout
  • 5.3 Enable Control
  • 5.4 Overcurrent Protection (OCP)
  • 5.5 V OUT Undervoltage Protection (UVP)
  • 5.6 Over-Temperature Protection (OTP)
  • 5.7 System Level Fault Summary
  • 6.1 Output Voltage Feedback Resistor Divider
  • 6.2 Inductor Selection
  • 6.3 Input Capacitor Selection
  • 6.4 Output Capacitor Selection
  • 6.5 BOOT Refresh and Capacitor Selection

Features

▪ 4.5V to 30V input supply range ▪ Up to 2A output current ▪ Integrated high-side (125mΩ) and low-side (75mΩ) MOSFETs ▪ 400μA quiescent current ▪ Minimum on-time of 70ns ▪ Minimum off-time of 225ns ▪ 0.765V reference voltage with 2% accuracy ▪ PFM mode under light load condition ▪ Current mode Constant On-Time (COT) control with internal compensation ▪ Internal 0.8ms soft start time ▪ Protection: Low-Side Overcurrent (LSOC) limit, input Undervoltage Lockout (UVLO), Over-Temperature Protection (OTP), Output Undervoltage Protection (OUVP) with Hiccup Mode ▪ Accurate EN threshold ▪ 6 LD TSOT23 package Figure 1. Typical Application Circuit Diagram

Figure 2. Typical Application Circuit Diagram with VIN UVLO Programming by ENABLE Table 1. Bill of Materials for Typical Application Circuit (3.3V VOUT)

11 C IN 10µF CAP CER 10µF 35V X7R 1206 GMK316AB7106KL-TR

61 R FB2 10k 1% resistor 0603 Generic

1.1 Block Diagram

Figure 3. Functional Block Diagram

R16DS0082EU0101 Rev.1.01 Page 5 May 18, 2023 RAA211320 Datasheet 2. Pin Information

2.1 Pin Assignments

2.2 Pin Descriptions

Pin Number Pin Name Description

1 GND Ground

2 SW Switch node pin. Connect this pin to the inductor. 3V I N Voltage input for the IC. Connect to a suitable voltage source within the IC operating range to this pin. Place a ceramic capacitor from VIN to GND close to the IC for decoupling. 4F B Feedback input pin for the regulator. The output voltage is set by an external resistor divider connected to FB. FB voltage is 0.765V during normal operation. 5E N This pin Enable and Disable the IC. A resistor divider from VIN can be connected to EN to program VIN UVLO. Drive EN with impedance less than 10kΩ. 6 BST Bootstrap supply pin. Connect a 0.1 μF capacitor from BST to SW. GND SW VIN BST EN FB

R16DS0082EU0101 Rev.1.01 Page 6 May 18, 2023 RAA211320 Datasheet 3. Specifications

3.1 Absolute Maximum Ratings

Caution: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.

3.2 Thermal Information

Parameter Minimum Maximum Unit VIN -0.3 32 V EN -0.3 VIN + 0.3 V SW -0.7 VIN + 0.3 V SW (20ns transient) -3 VIN + 2 V BST -S W + 5 . 5 V All other pins -0.3 5 V Human Body Model (HBM) (Tested per JS-001-2017) - 2 kV Charged Device Model (CDM) (Tested per JS-002-2018) - 750 V Latch-Up (Tested per JESD78E; Class 2, Level A) - 100 mA Parameter Package Symbol Conditions Typical Value Unit Thermal Resistance 6 Ld TSOT23 θ JA[1] 1. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379. Junction to air 105 °C/W θJA_EVB[2] 2. θJA_EVB is measured in free air with the component mounted on the RTKA211320DE0020BU evaluation board. Junction to air, evaluation board 50 °C/W θJC[3] 3. For θJC, the case temperature measurement location is the center of top of package. Junction to case 45 °C/W Parameter Minimum Maximum Unit Maximum Junction Temperature -40 +150 °C Maximum Storage Temperature Range -65 +150 °C Pb-Free Reflow Profile see TB493

R16DS0082EU0101 Rev.1.01 Page 7 May 18, 2023 RAA211320 Datasheet

3.3 Recommended Operating Conditions

3.4 Electrical Specifications

Parameter Minimum Maximum Unit Input Voltage, VIN 4.5 30 V Output Voltage, VOUT 0.765 16 V Output Current, IOUT 02 A Junction Temperature, TJ -40 +125 °C TA = TJ = -40°C to +125°C, VIN = 12V, unless otherwise noted. Typical values are at TA = +25°C. Parameter Symbol Test Conditions Min [1] Typical Max [1] Unit Supply Voltage VIN Voltage Range V IN -4 . 5 - 3 0 V Quiescent Current I Q EN = 2V, VFB = 0.8V, no switching - 400 - µA Shutdown Current I SH EN = 0V, VIN = 12, no switching - 1.5 10 µA VIN Undervoltage Lockout - VIN Rising - 4.3 4.55 V VIN Undervoltage Hysteresis - VIN Falling - 425 - mV Enable Voltage EN Threshold Voltage VEN EN rising 1.2 1.3 1.45 V Enable Voltage Hysteresis - - - 100 - mV Enable Shutdown Threshold VENL - - 0.7 - V EN Pin Resistance to GND REN VEN = 2V - 2000 - k Ω Switching Frequency and Timer Control Switching Frequency Range f SW VFB = 0.765V, VOUT = 1.05V, IOUT =1 A , VIN =1 2 V - 475 - kHz Minimum Off-Time t OFF_MIN VFB = 0.75V - 225 330 ns Minimum On-Time t ON_MIN -- 7 0 - n s Internal Soft-Start Time - - - 0.8 - ms Feedback Voltage Feedback Voltage Reference V FB VIN = 12V, EN = 2V, 25°C 0.75 0.765 0.78 V Feedback Voltage Line Regulation - - - 0.005 - %/V Internal Integrated MOSFETs High-Side On-Resistance r DS(ON)_H VBST-VSW = 5.1V - 125 - m Ω Low-Side On-Resistance r DS(ON)_L -- 7 5 - m Ω

R16DS0082EU0101 Rev.1.01 Page 8 May 18, 2023 RAA211320 Datasheet Current Limit and Protection Current Limit I LIM_L Valley current, low-side FET, valid when tOFF > 100ns 1.75 2.3 3 A UVP FB_UV Fault threshold, VFB falling, soft-start completed - 500 - mV Hiccup Soft-Start Done Time t HICCUP_ON -- 1 - m s Hiccup Power Off-Time t HICCUP_OFF -- 1 3 - m s Thermal Shutdown TSD - - 170 - °C Thermal hysteresis ΔTSD - - 40 - °C 1. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TA = TJ = -40°C to +125°C, VIN = 12V, unless otherwise noted. Typical values are at TA = +25°C. (Cont.) Parameter Symbol Test Conditions Min [1] Typical Max [1] Unit

the on-time of the high-side FET based on the sensed value of VIN and VOUT.

5.1 Soft-Start

ramps up from 0V to its nominal value of 0.765V in 0.8ms. protection only occurs after soft-start is completed.

5.2 Undervoltage Lockout

5.3 Enable Control

that allows the internal circuitry of the IC to shut down. Drive EN with impedance less than 10kΩ. Figure 39. Max IOUT vs Ambient Temp (VOUT = 3.3V) Figure 40. Max I OUT vs Ambient Temp (VOUT = 5V)

set with the resistor divider based on Equation 1, where VINR is the rising threshold of VIN UVLO, see Figure 41. Choose REN1 and REN2 so that REN1 || REN2 is less than 10kΩ.

5.4 Overcurrent Protection (OCP)

until the LSOC condition clears.

5.5 V OUT Undervoltage Protection (UVP)

engages Hiccup mode operation at an interval of 13ms (see Figure 36).

5.6 Over-Temperature Protection (OTP)

total power dissipation by turning off the regulator when the IC junction temperature exceeds 170°C (typical). Figure 41. Timing Diagram with EN Turn On and VIN UVLO Turn Off

5.7 System Level Fault Summary

device then resumes normal operation according to the state of the EN pin. Table 2 lists the recommended component selections for typical applications.

6.1 Output Voltage Feedback Resistor Divider

values for typical VOUT applications. (RFB1 + RFB2) is 5kΩ to 150kΩ. reset state when UVLO is satisfied. until the current falls below LSOC limit. Table 2. Recommended Components Selection for Typical Application

zero-load condition, Equation 4, where RFB1 and RFB2 are in kΩ. input voltage is determined by DMAX, which is a function of minimum-off time and switching frequency.

6.2 Inductor Selection

voltage and current are approximated by Equation 5 and Equation 6. reference Table 2 for selecting the inductor value for typical VOUT applications. normal operation. Renesas recommends using inductors with soft saturation characteristics. Figure 42. Operating Range for VIN and VOUT

R16DS0082EU0101 Rev.1.01 Page 19 May 18, 2023 RAA211320 Datasheet

6.3 Input Capacitor Selection

The input capacitor in a buck converter maintains the input voltage by suppressing the voltage ripple induced by discontinuous switching current. Approximate the required RMS current rating IIN(RMS) of the input capacitor with Equation 7, where IOUT(MAX) is the maximum average load current and D is the duty ratio. When D equals 0.5, IIN(RMS) has the highest value which is IOUT(MAX)/2. The voltage rating of the input capacitor must be higher than the maximum input voltage. Calculate the required capacitance CIN of the input capacitor, to ensure the expected peak-to-peak input voltage ripple ΔVIN, by using Equation 8 where fSW is the switching frequency. The required capacitance also has the maximum value when D equals 0.5. Renesas recommends using low ESR/low ESL ceramic capacitors across the input of the regulator. When selecting the ceramic capacitors for power supply applications, consider that the effective capacitance reduces with DC bias voltage across it; therefore, you need to consult the capacitor datasheet to understand the impact of this effect. Renesas recommends using X5R/X7R dielectric ceramic capacitors because of their small temperature coefficient. If the input to the regulator is directed through a high-impedance path, Renesas recommends adding an electrolytic capacitor (in addition to the ceramic capacitor) to dampen the input voltage oscillation effects.

6.4 Output Capacitor Selection

Output capacitor selection impacts the steady state and transient performance of the buck converter. Factors such as output ripple voltage, output voltage excursion during transients, and control loop stability should be considered when selecting the output capacitor. Renesas recommends using the X5R/X7R dielectric ceramic for the output capacitor. When selecting the ceramic capacitor, consider that the effective capacitance reduces with DC bias voltage across it. The effective capacitance of the ceramic capacitor is used when determining the output voltage ripple. The required capacitance COUT(RIPPLE) is calculated using Equation 9, where ΔIL is the inductor peak-to-peak current ripple and fSW is the switching frequency: To meet the output voltage variation requirements during load step up and load step down transients, the required capacitance COUT(STEPUP) is calculated using Equation 10, and COUT(STEPDOWN) is calculated using Equation 11, where ISTEP is the transient load step and ΔVOUT is the expected voltage variation during the transient. (EQ. 7) (EQ. 8) (EQ. 9) (EQ. 10) (EQ. 11) CIN I OUT MAX D1 D – COUT RIPPLE  IL COUT STEPUP LI STEP IL  2 COUT STEPDOWN LI STEP IL  2

R16DS0082EU0101 Rev.1.01 Page 20 May 18, 2023 RAA211320 Datasheet To have a stable control loop with adequate gain margin, phase margin, and bandwidth, calculate the required capacitance COUT(LOOP) using Equation 12, where COUT(LOOP) is in μF and VOUT is in V. Select the output capacitors so that prior stated requirements are met: the total capacitance should be greater than the highest value calculated in Equation 9, Equation 10, Equation 11, or Equation 12. See Table 2 for recommended values of output capacitor for typical VOUT applications.

6.5 BOOT Refresh and Capacitor Selection

After EN and before the start-up process, approximately 85µs is driven high, and the RAA211320 turns on the internal BOOT voltage regulator. This action charges the boot capacitor before the start-up process begins. BOOT UVLO function is provided to prevent the turn on of HS FET at low BOOT Voltages. When the BOOT voltage is below 2.5V, the regulator skips the HS pulse and provides the LS pulse until BOOT voltage rises above 2.5V. A capacitor is needed between the BST pin and the SW pin to provide gate voltage for the high-side internal MOSFET. For most applications, Renesas recommends using a ceramic capacitor greater than 10V X5R/X7R 0.1µF as the bootstrap capacitor. 7. Component Placement and Layout Suggestions The printed circuit board (PCB) layout is critical for properly operating the RAA211320. Renesas recommends the following guidelines to achieve good performance. ▪ Use a combination of a bulk capacitor and smaller ceramic capacitors with low ESL for input capacitors, and place them as close as possible to the IC. Place the input ceramic capacitor(s) as close as possible to the IC. ▪ Keep the power loop (input ceramic capacitor, IC VIN, and PGND pins) as small as possible to minimize switch node voltage ringing caused by parasitic inductance in the PCB traces. Minimizing loop size also results in better EMI performance. ▪ Place bootstrap capacitors close to the IC between BST and SW pins on the same side of the PCB as the IC. Renesas recommends using a 0.1μF ceramic capacitor. ▪ Keep the phase node copper area small to reduce the parasitic capacitance but large enough to handle the load current. Place the inductor close to the regulator. ▪ Route the output voltage feedback signal away from SW and BST. Place feedback resistors close to the FB pin of the regulator. ▪ Place an output capacitor close to the inductor. (EQ. 12) COUT LOOP F 162.7 VOUT

Figure 43. Example Layout for RAA211320

R16DS0082EU0101 Rev.1.01 Page 22 May 18, 2023 RAA211320 Datasheet 8. Package Outline Drawing For the most recent package outline drawing, see P6.064C. P6.064C

6 Lead Thin Small Outline Transistor (TSOT) Plastic Package

Rev 2, 12/20

R16DS0082EU0101 Rev.1.01 Page 23 May 18, 2023 RAA211320 Datasheet 9. Ordering Information 10. Revision History Part Number[1][2] 1. These Pb-free plastic packaged products empl oy special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 2. For Moisture Sensitivity Level (MSL), see the RAA211320 device page. For more information about MSL, see TB363. Part Marking[3] 3. The part marking is located on the bottom of the part. Package Description (RoHS Compliant) Pkg. Dwg. # Carrier Type [4] 4. See TB347 for details about reel specifications. Temp Range RAA2113204GP3#JA0 320 6Ld TSOT-23 P6.064C Reel, 3k -40 to +125°C RTKA211320DE0030BU RAA21 1320 Evaluation Board Revision Date Description

1.01 May 18, 2023

Corrected Note in the Thermal Information section. Updated the output voltage minimum from 0.786V to 0.765V in the Recommended Operating Conditions section. Removed VOUT Voltage Range from the EC table. Updated Figure 40. 1.00 Apr 12, 2023 Initial release.

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