G1N

RL78-G1M RENESAS

Document overview

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Technical content

R01DS0378EJ0100 Rev.1.00 1 of 28 May 29, 2020 R01DS0378EJ0100 Rev.1.00 May 29, 2020 RL78/G1M, G1N RENESAS MCU Datasheet 1. OUTLINE

1.1 Features

Ultra-low power consumption technology

• V DD = single power supply voltage of 2.0 to 5.5 V (Use this product within the voltage range from 2.25 to

5.5 V because the detection voltage (V

SPOR) of the selectable power-on-reset (SPOR) circuit should also be considered.)

• HALT mode
• STOP mode RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed from high speed (0.05 µs: @ 20 MHz operation with high-speed on-chip oscillator) to low speed (1.0 µs: @

1 MHz operation)

• Address space: 1 MB
• General-purpose registers: 8-bit register × 8
• On-chip RAM: 512 B to 1 KB Code flash memory
• Code flash memory: 4 KB to 8 KB
• On-chip debug function High-speed on-chip oscillator
• Select from 20 MHz, 10 MHz, 5 MHz, 2.5 MHz, and

1.25 MHz

• High accuracy: ±2.0% (V DD = 2.0 to 5.5 V, TA = 20 to +85°C) Operating ambient temperature
• TA = 40 to +85°C Power management and reset function
• On-chip selectable power-on-reset (SPOR) circuit Serial interface
• CSI: 1 channel
• UART: 1 channel Timer
• 8-/16-bit timer: 4 channels
• 12-bit interval timer: 1 channel
• Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator)
• Real-time output function: 8 channels (RL78/G1M only) A/D converter
• 8/10-bit resolution A/D converter (V DD = 2.4 to 5.5 V)
• Analog input: 8 channels I/O port
• I/O port: 18 (N-ch open drain output [V DD withstand voltage]: 14) (P-ch open drain output [VDD withstand voltage]: 6)
• High current pin (RL78/G1N only)
• Can be set to N-ch open drain and on-chip pull-up resistor
• On-chip key interrupt function
• On-chip clock output/buzzer output controller Others
• On-chip BCD (binary-coded decimal) correction circuit

RL78/G1M, G1N 1. OUTLINE R01DS0378EJ0100 Rev.1.00 2 of 28 May 29, 2020  ROM, RAM capacities Flash ROM RAM 20 Pins RL78/G1M RL78/G1N

8 KB 1 KB R5F11W68ASM

4 KB 512 B R5F11W67ASM

Remark The functions mounted depend on the product. See 1.6 Outline of Functions.

RL78/G1M, G1N 1. OUTLINE R01DS0378EJ0100 Rev.1.00 3 of 28 May 29, 2020

1.2 List of Part Numbers

Figure 1-1. Part Number, Memory Size, and Package of RL78/G1M, G1N Part No. R 5 F 11W 6 7 A SM #30 Package type: Packaging specification Product name: Renesas MCU Renesas semiconductor product SM : 20-pin, TSSOP, 0.65 mm pitch #10, 30 : Tray (TSSOP) #50 : Embossed Tape (TSSOP) ROM capacity: 7 : 4 KB 8 : 8 KB Pin count: 6 : 20-pin Fields of application: A : Consumer applications, TA = -40°C to 85°C D : Industrial applications, TA = -40°C to 85°C Memory type: F : Flash memory RL78/G1M group : 11W RL78/G1N group : 11Y Table 1-1. List of Ordering Part Numbers Pin Count Package Fields of ApplicationNote Part Number RENESAS Code 20 pins 20-pin plastic TSSOP (4.4 × 6.5 mm, 0.65 mm pitch) A R5F11W67ASM#10, R5F11W68ASM#10 R5F11W67ASM#30, R5F11W68ASM#30 R5F11W67ASM#50, R5F11W68ASM#50 R5F11Y67ASM#10, R5F11Y68ASM#10 R5F11Y67ASM#30, R5F11Y68ASM#30 R5F11Y67ASM#50, R5F11Y68ASM#50 PTSP0020JI-A D R5F11W67DSM#10, R5F11W68DSM#10 R5F11W67DSM#30, R5F11W68DSM#30 R5F11W67DSM#50, R5F11W68DSM#50 R5F11Y67DSM#10, R5F11Y68DSM#10 R5F11Y67DSM#30, R5F11Y68DSM#30 R5F11Y67DSM#50, R5F11Y68DSM#50 Note For the fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/G1M, G1N. Caution The part number represents the number at the time of publication. Be sure to review the latest part number through the target product page in the Renesas Electronics Corp. website.

RL78/G1M, G1N 1. OUTLINE R01DS0378EJ0100 Rev.1.00 4 of 28 May 29, 2020

1.3 Pin Configuration (Top View)

1.3.1 RL78/G1M products

• 20-pin plastic TSSOP (4.4 × 6.5 mm, 0.65 mm pitch) P40/KR0/TOOL0/(PCLBUZ0)/(TI01/TO01) P16/ANI7/TI02/TO02/KR7/(SCK00) P15/ANI6/INTP2/(SI00/RxD0) P14/ANI5/TI03/INTP3 P13/ANI4/TO03/KR6 P12/ANI3/TI01/TO01/KR5 P11/ANI2/TO00/KR4/(INTP1) P10/ANI1/SCK00/PCLBUZ0/KR3/(SO00/TxD0 P07/ANI0/SI00/RxD0/KR2/RTIO07 P06/SO00/TxD0/INTP1/RTIO06 P125/KR1/RESET P137/TI00/INTP0 P00/INTP5/RTIO00 P01/INTP4/RTIO01 P02/RTIO02 P03/RTIO03 P04/RTIO04 P05/RTIO05 V SS VDD RL78/G1M (Top View) Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-7 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G1M, G1N User’s Manual.

1.3.2 RL78/G1N products

• 20-pin plastic TSSOP (4.4 × 6.5 mm, 0.65 mm pitch) P40/KR0/TOOL0/(PCLBUZ0)/(TI01/TO01) P16/ANI7/TI02/TO02/KR7/(SCK00)/(TxD0) P15/ANI6/INTP2 P14/ANI5/TI03/INTP3 P13/ANI4/TO03/KR6 P12/ANI3/TI01/TO01/KR5 P11/ANI2/TO00/KR4/(INTP1) P10/ANI1/SCK00/PCLBUZ0/KR3 P07/ANI0/SI00/RxD0/KR2 P06/SO00/TxD0/INTP1 P125/KR1/RESET P137/TI00/INTP0/(SI00/RxD0) P00/INTP5/(KR0)/(SCK00) P01/INTP4/(SO00/TxD0) P02 P03 P04 P05 V SS VDD RL78/G1N (Top View) Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-7 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G1M, G1N User’s Manual.

RL78/G1M, G1N 1. OUTLINE R01DS0378EJ0100 Rev.1.00 5 of 28 May 29, 2020

1.4 Pin Identification

ANI0 to ANI7 : Analog input INTP0 to INTP5 : External interrupt input KR0 to KR7 : Key return P00 to P07 : Port 0 P10 to P16 : Port 1 P40 : Port 4 P125 : Port 12 P137 : Port 13 PCLBUZ0 : Programmable clock output/buzzer output RESET : Reset RTIO00 to RTIO07 : Real-time output RxD0 : Receive data SCK00 : Serial clock input/output SI00 : Serial data input SO00 : Serial data output TI00 to TI03 : Timer input TO00 to TO03 : Timer output TOOL0 : Data input/output for tool TxD0 : Transmit data ANI0 to ANI7 : Analog input V DD : Power supply VSS : Ground

RL78/G1M, G1N 1. OUTLINE R01DS0378EJ0100 Rev.1.00 6 of 28 May 29, 2020

1.5 Block Diagram

1.5.1 RL78/G1M products

512 B/1 KB

TAU (4 ch) ch03 ch01 ch00 ch02 TI01 / TO01 TI02 / TO02 TI03 / TO03 SCK00 SO00 TI00 / TO00 P10 to P167 RL78-S1 8RTIO0 to RTIO7 P40 TAU0 (2 ch) Code flash

4 KB/8 KB

1.25 to 20 Hz Port 0 Port 1 Port 4 Port 12 Port 13 Buzzer/clock output control Key return 8 ch Interrupt control 6 ch Watchdog timer 12-bit interval timer Low-speed on-chip oscillator

RL78/G1M, G1N 1. OUTLINE R01DS0378EJ0100 Rev.1.00 7 of 28 May 29, 2020

1.5.2 RL78/G1N products

TAU (4 ch) P10 to P16 TAU0 (2 ch) Code flash 1.25 to 20 Hz Port 0 Port 1 Port 4 Port 12 Port 13 Buzzer/clock output control Key return 8 ch Interrupt control 6 ch Watchdog timer 12-bit interval timer Low-speed on-chip oscillator

RL78/G1M, G1N 1. OUTLINE R01DS0378EJ0100 Rev.1.00 8 of 28 May 29, 2020

1.6 Outline of Functions

This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 20-pin RL78/G1M Products RL78/G1N Products R5F11W67ASM R5F11W67DSM R5F11W68ASM R5F11W68DSM R5F11Y67ASM R5F11Y67DSM R5F11Y68ASM R5F11Y68DSM Code flash memory 4 KB 8 KB 4 KB 8 KB RAM 512 B 1 KB 512 B 1 KB Main system clock High-speed on-chip oscillator clock

• 1.25 to 20 MHz (V DD = 2.7 to 5.5 V)
• 1.25 to 5 MHz (VDD = 2.0 to 5.5 VNote 1) Low-speed on-chip oscillator clock 15 kHz ±15% General-purpose register 8-bit register × 8 Minimum instruction execution time 0.05 µs (20 MHz operation) Instruction set ● Data transfer (8 bits)
• Adder and subtractor/logical operation (8 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc. I/O port Total 18 CMOS I/O 16 (N-ch open-drain output (VDD tolerance): 14) P-ch open-drain output (high current pin): 6 CMOS input 2 Timer 16-bit timer 4 channels Watchdog timer 1 channel 12-bit interval timer 1 channel Timer output 4 channels (PWM outputs: 3Note 2) Real-time output 8 channels – Clock output/buzzer output 1 2.44 kHz to 10 MHz: (Peripheral hardware clock: fMAIN = 20 MHz operation) 8-/10-bit resolution A/D converter 8 channels Serial interface CSI: 1 channel, UART: 1 channel Vectored interrupt sources Internal 12 External 7 Key interrupt 8 Notes 1. Use this product within the voltage range from 2.25 to 5.5 V because the detection voltage (V SPOR) of the selectable power-on-reset (SPOR) circuit should also be considered. 2. The number of outputs varies, depending on the setting of channels in use and t he number of the master (refer to 6.9.4 Operation as multiple PWM output function in the RL78/G1M, G1N User’s Manual).

RL78/G1M, G1N 1. OUTLINE R01DS0378EJ0100 Rev.1.00 9 of 28 May 29, 2020 (2/2) Item 20-pin RL78/G1M Products RL78/G1N Products R5F11W67ASM R5F11W67DSM R5F11W68ASM R5F11W68DSM R5F11Y67ASM R5F11Y67DSM R5F11Y68ASM R5F11Y68DSM Reset ● Reset by RESET pin

• Internal reset by watchdog timer
• Internal reset by selectable power-on-reset
• Internal reset by illegal instruction executionNote 1
• Internal reset by data retention lower limit voltage Selectable power-on-reset circuit ● Detection voltage On-chip debug function Provided Power supply voltage VDD = 2.0 to 5.5 VNote 2 Operating ambient temperature T A = -40 to + 85°C Notes 1. The illegal instruction is generated wh en instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the on-chip debug emulator. 2. Use this product within the voltage range from 2.25 to 5.5 V because the detection voltage (V SPOR) of the selectable power-on-reset (SPOR) circuit should also be considered.

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 10 of 28 May 29, 2020 2. ELECTRICAL SPECIFICATIONS Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on- chip debug function in products designate d for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. Refer to 2.1 Port Functions and 2.2 Functions Other than Port Pins in the RL78/G1M, G1N User’s Manual. 3. Use this product within the voltage range fr om 2.25 to 5.5 V because the detection voltage (V SPOR) of the selectable power-on-reset (SPOR) circuit should also be considered.

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 11 of 28 May 29, 2020

2.1 Absolute Maximum Ratings

(TA = 25°C) Parameter Symbols Conditions Ratings Unit Supply voltageNote 1 V DD –0.5 to +6.5 V Input voltageNote 1 V I1 –0.3 to VDD + 0.3Note 2 V Output voltageNote 1 V O1 –0.3 to VDD + 0.3 V Output current, high I OH1 Per pin P00 to P05 RL78/G1M –40 mA RL78/G1N –130 mA P06, P07, P10 to P16, P40 –40 mA Total of all pins P00 to P05 RL78/G1M –70 mA RL78/G1N –160 mA P06, P07, P10 to P16, P40 RL78/G1M –100 mA RL78/G1N –100 mA Output current, low I OL1 Per pin 40 mA Total of all pins P00 to P05 RL78/G1M 70 mA RL78/G1N 90 mA P06, P07, P10 to P16, P40 RL78/G1M 100 mA RL78/G1N 170 mA Operating ambient temperature T A –40 to +85 °C Storage temperature T stg –65 to +150 °C Notes 1. VSS is used as the reference potential. 2. Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maximum ra ting is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, t he characteristics of alternate-function pins are the same as those of the port pins. 2. The reference voltage is VSS.

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 12 of 28 May 29, 2020

2.2 Oscillator Characteristics

2.2.1 On-chip oscillator characteristics

(TA = –40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator oscillation frequencyNotes 1, 2 fIH 1.25 20 MHz High-speed on-chip oscillator oscillation frequency accuracy Low-speed on-chip oscillator oscillation frequency Note 3 fIL 15 kHz Low-speed on-chip oscillator clock frequency accuracy –15 +15 % Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 2 of option byte (000C2H). 2. This only indicates the oscillator characteristics. See AC Characteristics for instruction execution time. 3. This only indicates the oscillator characteristics.

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 13 of 28 May 29, 2020

2.3 DC Characteristics

2.3.1 Pin characteristics of RL78/G1M

(TA = –40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, highNote 1 IOH1 Per pin for P00 to P07, P10 to P16, P40 –10 Note 2 mA Total of P00 to P05 (When duty ≤ 70%) Note 3 4.0 V ≤ VDD ≤ 5.5 V –50 mA 2.7 V ≤ VDD < 4.0 V –10 mA 2.0 V ≤ VDD < 2.7 V –7.5 mA Total of P06, P07, P10 to P16, P40 (When duty ≤ 70%) Note 3 4.0 V ≤ VDD ≤ 5.5 V –80 mA 2.7 V ≤ VDD < 4.0 V –16 mA 2.0 V ≤ VDD < 2.7 V –12 mA Total of all pins (When duty ≤ 70%)Note 3 –130 mA Output current, low I OL1 Per pin for P00 to P07, P10 to P16, P40 20 Note 2 mA Total of P00 to P05 (When duty ≤ 70%) Note 4 4.0 V ≤ VDD ≤ 5.5 V 60 mA 2.7 V ≤ VDD < 4.0 V 9 mA 2.0 V ≤ VDD < 2.7 V 1.8 mA Total of P06, P07, P10 to P16, P40 (When duty ≤ 70%) Note 4 4.0 V ≤ VDD ≤ 5.5 V 100 mA 2.7 V ≤ VDD < 4.0 V 15 mA 2.0 V ≤ VDD < 2.7 V 3 mA Total of all pins (When duty ≤ 70%)Note 4 160 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. 2. Do not exceed the total current value. 3. Specification under conditi ons where the duty factor ≤ 70%. The output current value that has ch anged to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

• Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 80% and I OH = -10.0 mA Total output current of pi ns = (-10.0 × 0.7)/(80 × 0.01) ≈ -8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. Specification under conditi ons where the duty factor ≤ 70%. The output current value that has ch anged to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≈ 8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P06 and P10 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port.

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 14 of 28 May 29, 2020

2.3.2 Pin characteristics of RL78/G1N

(TA = –40 to +85°C, 4.5 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, highNote 1 IOH1 Total of all pins (When duty ≤ 70%)Note 3 4.5 V ≤ VDD ≤ 5.5 V –160 mA Total of P00 to P05 (When duty ≤ 70%) Note 3 4.5 V ≤ VDD ≤ 5.5 V –140 mA Total of P06, P07, P10 to P16, P40 (When duty ≤ 70%) Note 3 4.5 V ≤ VDD ≤ 5.5 V –80 mA Per pin (COM) for P00 to P05Note 5 4.5 V ≤ VDD ≤ 5.5 V –120 Note 2 mA Per pin (SEG, other) for P06, P07, P10 to P16, P40 4.5 V ≤ V DD ≤ 5.5 V –10 Note 2 mA Output current, low I OL1 Total of all pins (When duty ≤ 70%)Note 4 4.5 V ≤ VDD ≤ 5.5 V 160 mA Total of P00 to P05 (When duty ≤ 70%) Note 4 4.5 V ≤ VDD ≤ 5.5 V 80 mA Total of P06, P07, P10 to P16, P40 (When duty ≤ 70%) Note 4 4.5 V ≤ VDD ≤ 5.5 V 150 mA Per pin (SEG) for P06, P07, P10 to P15 Note 6 4.5 V ≤ VDD ≤ 5.5 V 15 mA Per pin (COM, other) for P00 to P05, P16, P40 4.5 V ≤ V DD ≤ 5.5 V 20 Note 2 mA Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. 2. Do not exceed the total current value. 3. Specification under conditi ons where the duty factor ≤ 70%. The output current value that has ch anged to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

• Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 80% and I OH = -10.0 mA Total output current of pins = (-10.0 × 0.7)/(80 × 0.01) ≈ -8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. Specification under conditi ons where the duty factor ≤ 70%. The output current value that has ch anged to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≈ 8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin.

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 15 of 28 May 29, 2020 Notes 5. Specification under conditions where (t1/t2*100%) ≤ 25%. The output current when the condition changes to a value in the range of (t1/t2*100%) > 25% can be calculated from the following expression (after replacing (t1/t2*100%) with n%).

• Total output current of pins = (IOH × 0.25)/(n × 0.01) <Example> Where n = 60% and IOH = -120.0 mA Total output current of pins = (-120.0 × 0.25)/(60 × 0.01) = -50 mA However, the current does not depend on the number of COM signals. A current higher than the absolute maximum rating must not flow into one pin. The waveforms for 6 COM signals are shown below. Output Waveforms for 6 COM Signals COM0 : COM1 : COM2 : COM3 : COM4 : COM5 : Notes 6. Specification under conditions where (t1/t2*100%) ≤ 25%. The output current when the condition changes to a value in the range of (t1/t2*100%) > 25% can be calculated from the following expression (after replacing (t1/t2*100%) with n%).
• Total output current of pins = (IOL × 0.25)/(n × 0.01) <Example> Where n = 60% and IOL = 15.0 mA Total output current of pins = (15.0 × 0.25)/(60 × 0.01) = 6.25 mA However, the current does not depend on the number of COM signals. A current higher than the absolute maximum rating must not flow into one pin. Caution P06, P07, P10 to P15 do not output high level in N-ch open-drain mode. Set P-ch open drain of P00 to P05 to off state (high impedance) during A/D conversion (RL78/G1N). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port.

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2.3.3 Common items

(TA = –40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high V IH1 0.8 VDD V DD V Input voltage, low V IL1 0 0.2 V DD V Output voltage, highNote 1 VOH1 P00 to P05 I OH = –10 mA 4.0 V ≤ VDD ≤ 5.5 V V DD – 1.5 V DD V IOH = –3 mA 4.0 V ≤ VDD ≤ 5.5 V V DD – 0.7 V DD V IOH = –2 mA 2.7 V ≤ VDD ≤ 5.5 V V DD – 0.6 V DD V IOH = –1.5 mA 2.0 V ≤ VDD ≤ 5.5 V V DD – 0.5 V DD V IOH = –120 mANote 3 4.5 V ≤ VDD ≤ 5.5 V V DD – 1.0 V DD V VOH2 P06, P07, P10 to P16, P40 I OH = –10 mA 4.0 V ≤ VDD ≤ 5.5 V V DD – 1.5 V DD V IOH = –3 mA 4.0 V ≤ VDD ≤ 5.5 V V DD – 0.7 V DD V IOH = –2 mA 2.7 V ≤ VDD ≤ 5.5 V V DD – 0.6 V DD V IOH = –1.5 mA 2.0 V ≤ VDD ≤ 5.5 V V DD – 0.5 V DD V Output voltage, low Note 2 VOL1 P00 to P05, P16, P40 IOL = 20 mA 4.0 V ≤ VDD ≤ 5.5 V 0 1.5 V IOL = 1.5 mA 2.7 V ≤ VDD ≤ 5.5 V 0 0.4 V IOL = 0.6 mA 2.0 V ≤ VDD ≤ 5.5 V 0 0.4 V VOL2 P06, P07, P10 to P15 IOL = 20 mA 4.0 V ≤ VDD ≤ 5.5 V 0 1.5 V IOL = 1.5 mA 2.7 V ≤ VDD ≤ 5.5 V 0 0.4 V IOL = 0.6 mA 2.0 V ≤ VDD ≤ 5.5 V 0 0.4 V IOL = 15 mANote 4 4.5 V ≤ VDD ≤ 5.5 V 0 0.6 V Input leakage current, high I LIH1 P00 to P07, P10 to P16, P40, P41, P125, P137 V I = VDD 1 µA Input leakage current, low I LIL1 P00 to P07, P10 to P16, P40, P41, P125, P137 V I = VSS –1 µA On-chip pull-up resistance R U V I = VSS 10 20 100 kΩ On-chip pull-down resistance Note 5 RO V I = VDD 100 200 kΩ Notes 1. The value under the condition which sa tisfies the high-level output current (IOH1). 2. The value under the condition which satisfies the low-level output current (IOL1). 3. P-ch open-drain (RL78/G1N only) 4. N-ch open-drain 5. RL78/G1N only. Caution The maximum value of V IH is VDD even in N-ch open-drain mode. Do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port.

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 17 of 28 May 29, 2020

2.3.4 Supply current characteristics

(TA = –40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply currentNote 1 I DD1 Operating mode Basic operation f IH = 20 MHz V DD = 3.0 V, 5.0 V 1.05 mA Normal operation f IH = 20 MHz V DD = 3.0 V, 5.0 V 2.19 2.95 fIH = 5 MHz V DD = 3.0 V, 5.0 V 1.13 1.56 IDD2Note 2 HALT mode fIH = 20 MHz V DD = 3.0 V, 5.0 V 390 980 µA fIH = 5 MHz V DD = 3.0 V, 5.0 V 300 640 IDD3Note 3 STOP mode Note 4 V DD = 3.0 V 0.61 Note 5 2.35 µA 12-bit interval timer operating current I TMKANotes 6, 7 0.31 µA Watchdog timer operating current I WDTNotes 6, 7 0.31 µA A/D converter operating current I ADCNote 6 When conversion at maximum speed VDD = 5.0 V 1.30 1.90 mA VDD = 3.0 V 0.50 mA Notes 1 . Total current flowing into V DD, including the input leakage current flowin g when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, I/O port, and on-chip pull-up/pull-down resistors. 2. During HALT instruction execution by flash memory. 3. When watchdog timer and A/D converter are stopped. The values below the MAX. column include the leakage current. 4. Condition applies at any temperature. 5. Value at VDD = 3 V, TA = 25°C. 6. Current flowing into VDD. 7. Excluding the operating current of the low-speed on-chip oscillator (fIL). Remarks 1. f IL: Low-speed on-chip oscillator clock frequency 2. Temperature condition of the typical value is T A = 25°C

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 18 of 28 May 29, 2020

2.4 AC Characteristics

(TA = –40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY Main system clock (fMAIN) operation 2.7 V ≤ VDD ≤ 5.5 V 0.05 0.8 µs 2.0 V ≤ VDD ≤ 5.5 V 0.2 0.8 µs TI00 to TI03 input high-level width, low-level width t TIH, tTIL Noise filter is not used 1/f MCK+10 ns TO00 to TO03 output frequency f TO 4.0 V ≤ VDD ≤ 5.5 V 10 MHz 2.7 V ≤ VDD < 4.0 V 5 MHz 2.0 V ≤ VDD < 2.7 V 2.5 MHz PCLBUZ0 output frequency f PCL 4.0 V ≤ VDD ≤ 5.5 V 10 MHz 2.7 V ≤ VDD < 4.0 V 5 MHz 2.0 V ≤ VDD < 2.7 V 2.5 MHz RESET low-level width t RSL 10 µs Remark f MCK: Timer array unit operation clock frequency (Operation clock to be set by the timer clock select register 0 (TPS0) and the CKS0n1 bit of timer mode register 0nH (TMR0nH). n: Channel number (n = 0 to 3)) Minimum Instruction Execution Time during Main System Clock Operation 1.0 0.1 5.52.7 0.01 0.05 0.2 0.8 Cycle time TCY [ms] When the high-speed on-chip oscillator clock is selected Supply voltage VDD [V] TCY vs VDD

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 19 of 28 May 29, 2020 AC Timing Test Points VIH/VOH VIL/VOL Test points VIH/VOH VIL/VOL TI/TO Timing TI00 to TI03 tTIL tTIH TO00 to TO03 1/fTO RESET Input Timing RESET tRSL

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 20 of 28 May 29, 2020

2.5 Serial Interface Characteristics

2.5.1 Serial array unit

(1) UART mode (dedicated ba ud rate generator output) (TA = –40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate fMCK/6 bps Theoretical value of the maximum transfer rate f CLK = fMCK = 20 MHz

3.3 Mbps

UART mode connection diagram RL78 microcontroller User's device TXD0 RXD0 RX TX UART mode bit width (reference) TXD0 1/transfer rate High-/low-bit width Baud rate error tolerance RXD0 Remark f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS0n bit of the serial mode register 0nH (SMR0nH). n: Channel number (n = 0, 1))

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 21 of 28 May 29, 2020 (2) CSI mode (master mode, SCKp...internal clock output) (TA = –40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY1 t KCY1 ≥ 4/fCLK 2.7 V ≤ VDD ≤ 5.5 V 200 ns 2.0 V ≤ VDD ≤ 5.5 V 800 ns SCKp high-/low-level width t KH1, tKL1 2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 – 18 ns 2.0 V ≤ VDD ≤ 5.5 V tKCY1/2 – 50 ns SIp setup time (to SCKp↑)Note 1 t SIK1 2.7 V ≤ VDD ≤ 5.5 V 47 ns 2.0 V ≤ VDD ≤ 5.5 V 110 ns SIp hold time (from SCKp↑)Note 1 t KSI1 19 ns Delay time from SCKp↓ to SOp outputNote 2 tKSO1 C = 30 pF Note 3 25 ns Notes 1. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP 0n = 1. The SIp setup time becomes “to SCKp↓” and SIp hold time becomes “from SCKp↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0. 2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes “from SCKp↑” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0. 3. C is the load capacitance of the SCKp and SOp output lines. Remark p: CSI number (p = 00), n: Channel number (n = 0)

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 22 of 28 May 29, 2020 (3) CSI mode (slave mode, SCKp…external clock input) (TA = –40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCKp cycle time tKCY2 2.7 V ≤ VDD ≤ 5.5 V f MCK > 16 MHz 8/f MCK ns fMCK ≤ 16 MHz 6/f MCK ns 2.0 V ≤ VDD ≤ 5.5 V 6/fMCK ns SCKp high-/low-level width tKH2, tKL2 2.0 V ≤ VDD ≤ 5.5 V tKCY/2 ns SIp setup time (to SCKp↑)Note 1 tSIK2 2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+20 ns 2.0 V ≤ VDD ≤ 5.5 V 1/fMCK+30 ns SIp hold time (from SCKp↑) Note 1 tKSI2 2.0 V ≤ VDD ≤ 5.5 V 1/fMCK+31 ns Delay time from SCKp↓ to SOp outputNote 2 tKSO2 C = 30 pF Note 3 2.7 V ≤ VDD ≤ 5.5 V 2/f MCK+50 ns 2.0 V ≤ VDD ≤ 5.5 V 2/f MCK+110 ns Notes 1. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CK P0n = 1. The SIp setup time becomes “to SCKp↓” and the SIp hold time becomes “from SCKp↓” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0. 2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1. The delay time to SOp output becomes “from SCKp↑” when DAP0n = 0 and CKP0n = 1, or DAP0n = 1 and CKP0n = 0. 3. C is the load capacitance of the SOp output lines. Remarks 1. p: CSI number (p = 00), n: Channel number (n = 0) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS0n bit of the serial mode register 0nH (SMR0nH). n: Channel number (n = 0))

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 23 of 28 May 29, 2020 CSI mode connection diagram RL78 microcontroller User's device SCK00 SO00 SCK SI00 SO SI CSI mode serial transfer timing (When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1.) SI00 SO00 tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 Input data tKSO1, 2 Output data SCK00

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 24 of 28 May 29, 2020

2.6 Analog Characteristics

2.6.1 A/D converter characteristics

(Target ANI pin: ANI0 to ANI7) (TA = –40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNotes 1, 2, 3 AINL 10-bit resolution V DD = 5 V ±1.7 ±3.1 LSB VDD = 3 V ±2.3 ±4.5 LSB Conversion time tCONV 10-bit resolution Target pin: ANI0 to ANI7 2.7 V ≤ VDD ≤ 5.5 V 3.4 18.4 µs 2.4 V ≤ VDD ≤ 5.5 VNote 5 4.6 18.4 Zero-scale errorNotes 1, 2, 3, 4 E ZS 10-bit resolution V DD = 5 V ±0.19 %FSR VDD = 3 V ±0.39 %FSR Full-scale errorNotes 1, 2, 3, 4 E FS 10-bit resolution V DD = 5 V ±0.29 %FSR VDD = 3 V ±0.42 %FSR Integral linearity errorNotes 1, 2, 3 ILE 10-bit resolution V DD = 5 V ±1.8 LSB VDD = 3 V ±1.7 LSB Differential linearity errorNotes 1, 2, 3 DLE 10-bit resolution V DD = 5 V ±1.4 LSB VDD = 3 V ±1.5 LSB Analog input voltage VAIN Target pin: ANI0 to ANI7 0 V DD V 2. These values are the results of characteristic evaluation and are not checked for shipment. 3. Excludes quantization error (±1/2 LSB). 4. This value is indicated as a ratio (%FSR) to the full-scale value. 5. Set the LV0 bit in the A/D converte r mode register 0 (ADM0) to 0 when conversion is done in the operating voltage range of 2.4 V ≤ VDD < 2.7 V. Cautions 1. Arrange wiring and insert the capacitor so that no noise appears on the power supply/ground line. 2. Do not allow any pulses that rapidly change such as digital signals to be input/output to/from the pins adjacent to the conversion pin during A/D conversion. 3. Set P-ch open drain of P00 to P05 to off stat e (high impedance) during A/D conversion (RL78/G1N).

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 25 of 28 May 29, 2020

2.6.2 SPOR circuit characteristics

(TA = –40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection supply voltage V SPOR0 Power supply rise time 4.08 4.28 4.45 V Power supply fall time 4.00 4.20 4.37 V VSPOR1 Power supply rise time 2.76 2.90 3.02 V Power supply fall time 2.70 2.84 2.96 V VSPOR2 Power supply rise time 2.44 2.57 2.68 V Power supply fall time 2.40 2.52 2.62 V VSPOR3 Power supply rise time 2.05 2.16 2.25 V Power supply fall time 2.00 2.11 2.20 V Minimum pulse widthNote T SPW 300 µs Note Time required for the reset operation by the SPOR when VDD becomes under VSPOR. Caution Set the detection voltage (V SPOR) in the operating voltage range. The operating voltage range depends on the setting of the user option byte (000C2H). The operating voltage range is as follows: When the CPU operating frequency is from 1.25 MHz to 20 MHz: V DD = 2.7 to 5.5 V When the CPU operating frequency is from 1.25 MHz to 5 MHz: V DD = 2.0 to 5.5 V

2.6.3 Power supply voltage rising slope characteristics

(TA = –40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope S VDD 54 V/ms

2.6.4 RAM data retention characteristics

(TA = –40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention power supply voltage V DDDR 1.9 5.5 V Caution Data in RAM are retained until the power supply voltage becomes under the minimum value of the data retention power supply voltage (VDDDR). Note that data in the RESF register might not be cleared even if the power supply voltage becomes under the minimum value of the data retention power supply voltage (VDDDR). STOP mode SPOR reset period (RAM and RESF data retention) Normal operation VDD VDDDR Rising of VSPOR Falling of VSPOR STOP instruction execution

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 26 of 28 May 29, 2020

2.7 Flash Memory Programming Characteristics

(TA = 0 to +40°C, 4.5 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Code flash memory rewritable timesNotes 1, 2, 3 Cerwr Retained for 20 years (T A = 85°C) 1000 Times Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewr ite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer. 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation.

2.8 Dedicated Flash Memory Programmer Communication (UART)

(TA = 0 to +40°C, 4.5 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate 115,200 bps Remark The transfer rate during flash memory programming is fixed to 115,200 bps.

RL78/G1M, G1N 2. EL ECTRICAL SPECIFICATIONS R01DS0378EJ0100 Rev.1.00 27 of 28 May 29, 2020

2.9 Timing of Entry to Flash Memory Programming Modes

Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT SPOR reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level t SU SPOR reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released t HD SPOR reset must be released before the external reset is released. 1 ms RESET TOOL0 tSUINIT tHD tSU <4> 1-byte data for setting mode <1> The low level is input to the TOOL0 pin. <2> The external reset is released (SPOR rese t must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of entry to the flash memory programming mode by UART reception. Remark t SUINIT: Communication for the initial setting must be completed within 100 ms (68 ms at T A = –40 to +85°C) after the external reset is released during this period. tSU: Time to release the exte rnal reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low le vel after the external reset is released

RL78/G1M, G1N 3. PACKAGE DRAWINGS R01DS0378EJ0100 Rev.1.00 28 of 28 May 29, 2020 3. PACKAGE DRAWINGS 3.1 20-Pin Products 1120 ddd C B A B E e 20X b bbb C B A DA aaa C C SEATING PLANE C Detail of Lead End H L θ 0.25 GAUGE PLANE ccc AA2A1 S Reference Symbol Dimension in Millimeters Min. Nom. Max. A 1.20 A1 0.05 0.15 A2 0.80 1.00 1.05 b0 . 1 9 0.30 C 0.09 0.127 0.20 D 6 . 4 06 . 5 06 . 6 0 E1 4.30 4.40 4.50 E6 . 4 0 B S C e0 . 6 5 B S C L1 1.00 REF L 0 . 5 00 . 6 00 . 7 5 S0 . 2 0 θ 0° 8° aaa 0.10 bbb 0.10 ccc 0.05 ddd 0.20 P-TSSOP20-4.40x6.50-0.65 PTSP0020JI-A 0.08 NOTES: 1.DIMENSION 'D' AND 'E1' DOES NOT INCLUDE MOLD FLASH. 2.DIMENSION 'b' DOES NOT INCLUDE TRIM OFFSET. 3.DIMENSION 'D' AND 'E1' TO BE DETERMINED AT DATUM PLANE H .

Rev. Date Description Page Summary 1.00 May 29, 2020  First Edition issued. All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system- evaluation test for the given product.

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