G13 integrated circuit reference — Local datasheet available

Memory

G13

3 manufacturer specifications

True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory,…

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RL78_V01 RENESAS

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Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 207

Technical content

True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz R01DS0131EJ0350 Rev.3.50 1 of 200 Jun 30, 2020 R01DS0131EJ0350 Rev.3.50 Jun 30, 2020 1. OUTLINE

1.1 Features

Ultra-low power consumption technology  VDD = single power supply voltage of 1.6 to 5.5 V  HALT mode  STOP mode  SNOOZE mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz operation with high-speed on-chip oscillator) to ultra-low speed (30.5 μs: @ 32.768 kHz operation with subsystem clock)  Address space: 1 MB  General-purpose registers: (8-bit register × 8) × 4 banks  On-chip RAM: 2 to 32 KB Code flash memory  Code flash memory: 16 to 512 KB  Block size: 1 KB  Prohibition of block erase and rewriting (security function)  On-chip debug function  Self-programming (with boot swap function/flash shield window function) Data Flash Memory  Data flash memory: 4 KB to 8 KB  Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.  Number of rewrites: 1,000,000 times (TYP.)  Voltage of rewrites: V DD = 1.8 to 5.5 V High-speed on-chip oscillator  Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz,

6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz

 High accuracy: +/- 1.0 % (VDD = 1.8 to 5.5 V, TA = -20 to +85°C) Operating ambient temperature  TA = -40 to +85°C (A: Consumer applications, D: Industrial applications )  TA = -40 to +105°C (G: Industrial applications) Power management and reset function  On-chip power-on-reset (POR) circuit  On-chip voltage detector (LVD) (Select interrupt and reset from 14 levels) DMA (Direct Memory Access) controller  2/4 channels  Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks Multiplier and divider/multiply-accumulator  16 bits × 16 bits = 32 bits (Unsigned or signed)  32 bits ÷ 32 bits = 32 bits (Unsigned)  16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) Serial interface  CSI: 2 to 8 channels  UART/UART (LIN-bus supported): 2 to 4 channels  I 2C/Simplified I2C communication: 3 to 10 channels Timer  16-bit timer: 8 to 16 channels  12-bit interval timer: 1 channel  Real-time clock: 1 channel (calendar for 99 years, alarm function, and clock correction function)  Watchdog timer: 1 channel (operable with the dedicated low-speed on-chip oscillator) A/D converter  8/10-bit resolution A/D converter (V DD = 1.6 to 5.5 V)  Analog input: 6 to 26 channels  Internal reference voltage (1.45 V) and temperature sensor Note 1 I/O port  I/O port: 16 to 120 (N-ch open drain I/O [withstand voltage of 6 V]: 0 to 4, N-ch open drain I/O [VDD withstand voltage Note 2/EVDD withstand voltage Note 3]: 5 to 25)  Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor  Different potential interface: Can connect to a 1.8/2.5/3 V device  On-chip key interrupt function  On-chip clock output/buzzer output controller Others  On-chip BCD (binary-coded decimal) correction circuit Notes 1. Can be selected only in HS (high-speed main) mode 2. Products with 20 to 52 pins 3. Products with 64 to 128 pins Remark The functions mounted depend on the product. See 1.6 Outline of Functions. <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 2 of 200 Jun 30, 2020 Ο ROM, RAM capacities Flash ROM Data flash RAM RL78/G13 20 pins 24 pins 25 pins 30 pins 32 pins 36 pins 128 KB

8 KB 12

– – – R5F100AG R5F100BG R5F100CG – – – – R5F101AG R5F101BG R5F101CG KB

8 KB 8 KB – – – R5F100AF R5F100BF R5F100CF

– – – – R5F101AF R5F101BF R5F101CF KB

4 KB 4 KB

R5F1006E R5F1007E R5F1008E R5F100AE R5F100BE R5F100CE – R5F1016E R5F1017E R5F1018E R5F101AE R5F101BE R5F101CE KB

4 KB 3 KB

R5F1006D R5F1007D R5F1008D R5F100AD R5F100BD R5F100CD – R5F1016D R5F1017D R5F1018D R5F101AD R5F101BD R5F101CD KB

4 KB 2 KB R5F1006C R5F1007C R5F1008C R5F100AC R5F100BC R5F100CC

– R5F1016C R5F1017C R5F1018C R5F101AC R5F101BC R5F101CC KB

4 KB 2 KB R5F1006A R5F1007A R5F1008A R5F100AA R5F100BA R5F100CA

– R5F1016A R5F1017A R5F1018A R5F101AA R5F101BA R5F101CA Flash ROM Data flash RAM RL78/G13 40 pins 44 pins 48 pins 52 pins 64 pins 80 pins 100 pins 128 pins 512 KB

8 KB 32 KB

– R5F100FL R5F100GL R5F100JL R5F100LL R5F100ML R5F100PL R5F100SL – – R5F101FL R5F101GL R5F101JL R5F101LL R5F101ML R5F101PL R5F101SL 384 KB

8 KB 24 KB – R5F100FK R5F100GK R5F100JK R5F100LK R5F100MK R5F100PK R5F100SK

– – R5F101FK R5F101GK R5F101JK R5F101LK R5F101MK R5F101PK R5F101SK 256 KB

8 KB 20 KB

– R5F100FJ R5F100GJ R5F100JJ R5F100LJ R5F100MJ R5F100PJ R5F100SJ – – R5F101FJ R5F101GJ R5F101JJ R5F101LJ R5F101MJ R5F101PJ R5F101SJ 192 KB

8 KB 16 KB R5F100EH R5F100FH R5F100GH R5F100JH R5F100LH R5F100MH R5F100PH R5F100SH

– R5F101EH R5F101FH R5F101GH R5F101JH R5F101LH R5F101MH R5F101PH R5F101SH 128 KB

8 KB 12 KB R5F100EG R5F100FG R5F100GG R5F100JG R5F100LG R5F100MG R5F100PG –

– R5F101EG R5F101FG R5F101GG R5F101JG R5F101LG R5F101MG R5F101PG – KB

8 KB 8 KB R5F100EF R5F100FF R5F100GF R5F100JF R5F100LF R5F100MF R5F100PF –

– R5F101EF R5F101FF R5F101GF R5F101JF R5F101LF R5F101MF R5F101PF – KB R5F100EE R5F100FE R5F100GE R5F100JE R5F100LE – – – – R5F101EE R5F101FE R5F101GE R5F101JE R5F101LE – – – KB R5F100ED R5F100FD R5F100GD R5F100JD R5F100LD – – – – R5F101ED R5F101FD R5F101GD R5F101JD R5F101LD – – – KB

4 KB 2 KB R5F100EC R5F100FC R5F100GC R5F100JC R5F100LC – – –

– R5F101EC R5F101FC R5F101GC R5F101JC R5F101LC – – – KB

4 KB 2 KB R5F100EA R5F100FA R5F100GA – – – – –

– R5F101EA R5F101FA R5F101GA – – – – – Note The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L): Start address FF300H R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L): Start address FEF00H R5F100xJ, R5F101xJ (x = F, G, J, L, M, P): Start address FAF00H R5F100xL, R5F101xL (x = F, G, J, L, M, P, S): Start address F7F00H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944).

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 3 of 200 Jun 30, 2020

1.2 List of Part Numbers

Figure 1-1. Part Number, Memory Size, and Package of RL78/G13 F : Flash memory 100 : Data flash is provided 101 : Data flash is not providedNote2 RL78/G13 group ROM capacity: Package type: Renesas MCU Renesas semiconductor product Pin count: Fields of application: Memory type: Packaging specifications #U0, #00, #20 : Tray (HWQFN, VFBGA, WFLGA) #V0, #10, #30 : Tray (LFQFP, LQFP, TSSOP20, LSSOP20, LSSOP30) #W0, #40 : Embossed Tape (HWQFN, VFBGA, WFLGA) #X0, #50 : Embossed Tape (LFQFP, LQFP, TSSOP, LSSOP) SM: TSSOP, 0.65-mm pitch SP : LSSOP, 0.65-mm pitch FP : LQFP, 0.80-mm pitch FA : LQFP, 0.65-mm pitch FB : LFQFP, 0.50-mm pitch NA : HWQFN, 0.50-mm pitch LA : WFLGA, 0.50-mm pitch Note1 BG : VFBGA, 0.40-mm pitchNote1 ROM number (Omitted with blank products) A : Consumer applications, operating ambient temperature : -40°C to +85°C D : Industrial applications, operating ambient temperature : -40°C to +85°C G : Industrial applications, operating ambient temperature : -40°C to +105°C A : 16 KB C : 32 KB D : 48 KB E : 64 KB F : 96 KB G : 128 KB H : 192 KB J : 256 KB K : 384 KB Note2 L : 512 KBNote2 6 : 20-pin 7 : 24-pin 8 : 25-pin Note1 A : 30-pin B : 32-pin C : 36-pin Note1 E : 40-pin F : 44-pin G : 48-pin J : 52-pin L : 64-pin M : 80-pin P : 100-pin S : 128-pin Note2 R 5 F 1 0 0 L E A x x x F B #V0Ordering part number Product name Notes 1. Products only for “A: Consumer applications (T A = –40 to +85°C)”, and "G : Industrial applications (T A = –40 to +105°C)" 2. Products only for “A: Consumer applications (TA = –40 to +85°C)”, and "D: Industrial applications (TA = –40 to +85°C)" <R> <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 4 of 200 Jun 30, 2020 Table 1-1. List of Ordering Part Numbers (1/8) Pin count Package Data flash Fields of Application Note Ordering Part Number RENESAS Code Product Name Packaging Specifications pins 20-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch) Mounted A R5F1006AASP, R5F1006CASP, R5F1006DASP, R5F1006EASP #V0, #10, #30, #X0, #50 PLSP0020JC-A D R5F1006ADSP, R5F1006CDSP, R5F1006DDSP, R5F1006EDSP G R5F1006AGSP, R5F1006CGSP, R5F1006DGSP, R5F1006EGSP Not mounted A R5F1016AASP, R5F1016CASP, R5F1016DASP, R5F1016EASP #V0, #10, #30, #X0, #50 PLSP0020JC-A D R5F1016ADSP, R5F1016CDSP, R5F1016DDSP, R5F1016EDSP 20-pin plastic TSSOP (4.4 x 6.5 mm, 0.65-mm pitch) Mounted A R5F1006AASM, R5F1006CASM, R5F1006DASM, R5F1006EASM #10, #30, #50 PTSP0020JI-A G R5F1006AGSM, R5F1006CGSM, R5F1006DGSM, R5F1006EGSM Not mounted A R5F1016AASM, R5F1016CASM, R5F1016DASM, R5F1016EASM pins 24-pin plastic HWQFN × 4 mm, 0.5-mm pitch) Mounted A R5F1007AANA, R5F1007CANA, R5F1007DANA, R5F1007EANA #U0, #W0 PWQN0024KE-A #00, #20, #40 PWQN0024KF-A D R5F1007ADNA, R5F1007CDNA, R5F1007DDNA, R5F1007EDNA #U0, #W0 PWQN0024KE-A G R5F1007AGNA, R5F1007CGNA, R5F1007DGNA, R5F1007EGNA R5F1007AGNA, R5F1007CGNA, R5F1007DGNA, R5F1007EGNA #00, #20, #40 PWQN0024KF-A Not mounted A R5F1017AANA, R5F1017CANA, R5F1017DANA, R5F1017EANA #U0, #W0 PWQN0024KE-A #00, #20, #40 PWQN0024KF-A D R5F1017ADNA, R5F1017CDNA, R5F1017DDNA, R5F1017EDNA #U0, #W0 PWQN0024KE-A pins 25-pin plastic WFLGA × 3 mm, 0.5-mm pitch) Mounted A R5F1008AALA, R5F1008CALA, R5F1008DALA, R5F1008EALA #U0, #W0 PWLG0025KA-A G R5F1008AGLA, R5F1008CGLA, R5F1008DGLA, R5F1008EGLA Not mounted A R5F1018AALA, R5F1018CALA, R5F1018DALA, R5F1018EALA #U0, #W0 PWLG0025KA-A Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 5 of 200 Jun 30, 2020 Table 1-1. List of Ordering Part Numbers (2/8) Pin count Package Data flash Fields of Application Note Ordering Part Number RENESAS Code Product Name Packaging Specifications pins 30-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch) Mounted A R5F100AAASP, R5F100ACASP, R5F100ADASP, R5F100AEASP, R5F100AFASP, R5F100AGASP #V0, #10, #30, #X0, #50 PLSP0030JB-B D R5F100AADSP, R5F100ACDSP, R5F100ADDSP, R5F100AEDSP, R5F100AFDSP, R5F100AGDSP G R5F100AAGSP, R5F100ACGSP, R5F100ADGSP, R5F100AEGSP, R5F100AFGSP, R5F100AGGSP Not mounted A R5F101AAASP, R5F101ACASP, R5F101ADASP, R5F101AEASP, R5F101AFASP, R5F101AGASP #V0, #10, #30, #X0, #50 PLSP0030JB-B D R5F101AADSP, R5F101ACDSP, R5F101ADDSP, R5F101AEDSP, R5F101AFDSP, R5F101AGDSP pins 32-pin plastic HWQFN × 5 mm, 0.5-mm pitch) Mounted A R5F100BAANA, R5F100BCANA, R5F100BDANA, R5F100BEANA, R5F100BFANA, R5F100BGANA #U0, #W0 PWQN0032KB-A #00, #20, #40 PWQN0032KE-A D R5F100BADNA, R5F100BCDNA, R5F100BDDNA, R5F100BEDNA, R5F100BFDNA, R5F100BGDNA #U0, #W0 PWQN0032KB-A G R5F100BAGNA, R5F100BCGNA, R5F100BDGNA, R5F100BEGNA, R5F100BFGNA, R5F100BGGNA R5F100BAGNA, R5F100BCGNA, R5F100BDGNA, R5F100BEGNA, R5F100BFGNA, R5F100BGGNA #00, #20, #40 PWQN0032KE-A Not mounted A R5F101BAANA, R5F101BCANA, R5F101BDANA, R5F101BEANA, R5F101BFANA, R5F101BGANA #U0, #W0 PWQN0032KB-A #00, #20, #40 PWQN0032KE-A D R5F101BADNA, R5F101BCDNA, R5F101BDDNA, R5F101BEDNA, R5F101BFDNA, R5F101BGDNA #U0, #W0 PWQN0032KB-A pins 36-pin plastic WFLGA × 4 mm, 0.5-mm pitch) Mounted A R5F100CAALA, R5F100CCALA, R5F100CDALA, R5F100CEALA, R5F100CFALA, R5F100CGALA #U0, #W0 PWLG0036KA-A G R5F100CAGLA, R5F100CCGLA, R5F100CDGLA, R5F100CEGLA, R5F100CFGLA, R5F100CGGLA Not mounted A R5F101CAALA, R5F101CCALA, R5F101CDALA, R5F101CEALA, R5F101CFALA, R5F101CGALA #U0, #W0 PWLG0036KA-A Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 6 of 200 Jun 30, 2020 Table 1-1. List of Ordering Part Numbers (3/8) Pin count Package Data flash Fields of Application Note Ordering Part Number RENESAS Code Product Name Packaging Specifications pins 40-pin plastic HWQFN × 6 mm, 0.5-mm pitch) Mounted A R5F100EAANA, R5F100ECANA, R5F100EDANA, R5F100EEANA, R5F100EFANA, R5F100EGANA, R5F100EHANA #U0, #W0 PWQN0040KC-A #00, #20, #40 PWQN0040KD-A D R5F100EADNA, R5F100ECDNA, R5F100EDDNA, R5F100EEDNA, R5F100EFDNA, R5F100EGDNA, R5F100EHDNA #U0, #W0 PWQN0040KC-A G R5F100EAGNA, R5F100ECGNA, R5F100EDGNA, R5F100EEGNA, R5F100EFGNA, R5F100EGGNA, R5F100EHGNA #U0, #W0 PWQN0040KC-A #00, #20, #40 PWQN0040KD-A Not mounted A R5F101EAANA, R5F101ECANA, R5F101EDANA, R5F101EEANA, R5F101EFANA, R5F101EGANA, R5F101EHANA #U0, #W0 PWQN0040KC-A #00, #20, #40 PWQN0040KD-A D R5F101EADNA, R5F101ECDNA, R5F101EDDNA, R5F101EEDNA, R5F101EFDNA, R5F101EGDNA, R5F101EHDNA #U0, #W0 PWQN0040KC-A pins 44-pin plastic LQFP (10 × 10 mm, 0.8-mm pitch) Mounted A R5F100FAAFP, R5F100FCAFP, R5F100FDAFP, R5F100FEAFP, R5F100FFAFP, R5F100FGAFP, R5F100FHAFP, R5F100FJAFP, R5F100FKAFP, R5F100FLAFP #V0, #X0 PLQP0044GC-A #10, #30, #50 PLQP0044GC-A/ PLQP0044GC-D D R5F100FADFP, R5F100FCDFP, R5F100FDDFP, R5F100FEDFP, R5F100FFDFP, R5F100FGDFP, R5F100FHDFP, R5F100FJDFP, R5F100FKDFP, R5F100FLDFP #V0, #X0 PLQP0044GC-A #10, #30, #50 PLQP0044GC-A/ PLQP0044GC-D G R5F100FAGFP, R5F100FCGFP, R5F100FDGFP, R5F100FEGFP, R5F100FFGFP, R5F100FGGFP, R5F100FHGFP, R5F100FJGFP #V0, #X0 PLQP0044GC-A #10, #30, #50 PLQP0044GC-A/ PLQP0044GC-D Not mounted A R5F101FAAFP, R5F101FCAFP, R5F101FDAFP, R5F101FEAFP, R5F101FFAFP, R5F101FGAFP, R5F101FHAFP, R5F101FJAFP, R5F101FKAFP, R5F101FLAFP #V0, #X0 PLQP0044GC-A #10, #30, #50 PLQP0044GC-A/ PLQP0044GC-D D R5F101FADFP, R5F101FCDFP, R5F101FDDFP, R5F101FEDFP, R5F101FFDFP, R5F101FGDFP, R5F101FHDFP, R5F101FJDFP, R5F101FKDFP, R5F101FLDFP #V0, #X0 PLQP0044GC-A #10, #30, #50 PLQP0044GC-A/ PLQP0044GC-D Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 7 of 200 Jun 30, 2020 Table 1-1. List of Ordering Part Numbers (4/8) Pin count Package Data flash Fields of Application Note Ordering Part Number RENESAS Code Product Name Packaging Specifications pins 48-pin plastic LFQFP × 7 mm, 0.5-mm pitch) Mounted A R5F100GAAFB, R5F100GCAFB, R5F100GDAFB, R5F100GEAFB, R5F100GFAFB, R5F100GGAFB, R5F100GHAFB, R5F100GJAFB, R5F100GKAFB, R5F100GLAFB #V0, #X0 PLQP0048KF-A #10, #30, #50 PLQP0048KB-B D R5F100GADFB, R5F100GCDFB, R5F100GDDFB, R5F100GEDFB, R5F100GFDFB, R5F100GGDFB, R5F100GHDFB, R5F100GJDFB, R5F100GKDFB, R5F100GLDFB #V0, #X0 PLQP0048KF-A #10, #30, #50 PLQP0048KB-B G R5F100GAGFB, R5F100GCGFB, R5F100GDGFB, R5F100GEGFB, R5F100GFGFB, R5F100GGGFB, R5F100GHGFB, R5F100GJGFB #V0, #X0 PLQP0048KF-A #10, #30, #50 PLQP0048KB-B Not mounted A R5F101GAAFB, R5F101GCAFB, R5F101GDAFB, R5F101GEAFB, R5F101GFAFB, R5F101GGAFB, R5F101GHAFB, R5F101GJAFB, R5F101GKAFB, R5F101GLAFB #V0, #X0 PLQP0048KF-A #10, #30, #50 PLQP0048KB-B D R5F101GADFB, R5F101GCDFB, R5F101GDDFB, R5F101GEDFB, R5F101GFDFB, R5F101GGDFB, R5F101GHDFB, R5F101GJDFB, R5F101GKDFB, R5F101GLDFB #V0, #X0 PLQP0048KF-A #10, #30, #50 PLQP0048KB-B 48-pin plastic HWQFN × 7 mm, 0.5-mm pitch) Mounted A R5F100GAANA, R5F100GCANA, R5F100GDANA, R5F100GEANA, R5F100GFANA, R5F100GGANA, R5F100GHANA, R5F100GJANA, R5F100GKANA, R5F100GLANA #U0, #W0 PWQN0048KB-A #00, #20, #40 PWQN0048KE-A D R5F100GADNA, R5F100GCDNA, R5F100GDDNA, R5F100GEDNA, R5F100GFDNA, R5F100GGDNA, R5F100GHDNA, R5F100GJDNA, R5F100GKDNA, R5F100GLDNA #U0, #W0 PWQN0048KB-A R5F100GKDNA, R5F100GLDNA #00, #20, #40 PWQN0048KE-A G R5F100GAGNA, R5F100GCGNA, R5F100GDGNA, R5F100GEGNA, R5F100GFGNA, R5F100GGGNA, R5F100GHGNA, R5F100GJGNA #U0, #W0 PWQN0048KB-A #00, #20, #40 PWQN0048KE-A Not mounted A R5F101GAANA, R5F101GCANA, R5F101GDANA, R5F101GEANA, R5F101GFANA, R5F101GGANA, R5F101GHANA, R5F101GJANA, R5F101GKANA, R5F101GLANA #U0, #W0 PWQN0048KB-A #00, #20, #40 PWQN0048KE-A D R5F101GADNA, R5F101GCDNA, R5F101GDDNA, R5F101GEDNA, R5F101GFDNA, R5F101GGDNA, R5F101GHDNA, R5F101GJDNA, R5F101GKDNA, R5F101GLDNA #U0, #W0 PWQN0048KB-A R5F101GKDNA, R5F101GLDNA #00, #20, #40 PWQN0048KE-A Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 8 of 200 Jun 30, 2020 Table 1-1. List of Ordering Part Numbers (5/8) Pin count Package Data flash Fields of Application Note Ordering Part Number RENESAS Code Product Name Packaging Specifications pins 52-pin plastic LQFP (10 × 10 mm, 0.65-mm pitch) Mounted A R5F100JCAFA, R5F100JDAFA, R5F100JEAFA, R5F100JFAFA, R5F100JGAFA, R5F100JHAFA, R5F100JJAFA, R5F100JKAFA, R5F100JLAFA #V0, #10, #30, #X0, #50 PLQP0052JA-A D R5F100JCDFA, R5F100JDDFA, R5F100JEDFA, R5F100JFDFA, R5F100JGDFA, R5F100JHDFA, R5F100JJDFA, R5F100JKDFA, R5F100JLDFA G R5F100JCGFA, R5F100JDGFA, R5F100JEGFA, R5F100JFGFA, R5F100JGGFA, R5F100JHGFA, R5F100JJGFA Not mounted A R5F101JCAFA, R5F101JDAFA, R5F101JEAFA, R5F101JFAFA, R5F101JGAFA, R5F101JHAFA, R5F101JJAFA, R5F101JKAFA, R5F101JLAFA #V0, #10, #30, #X0, #50 PLQP0052JA-A D R5F101JCDFA, R5F101JDDFA, R5F101JEDFA, R5F101JFDFA, R5F101JGDFA, R5F101JHDFA, R5F101JJDFA, R5F101JKDFA, R5F101JLDFA Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 9 of 200 Jun 30, 2020 Table 1-1. List of Ordering Part Numbers (6/8) Pin count Package Data flash Fields of Application Note Ordering Part Number RENESAS Code Product Name Packaging Specifications pins 64-pin plastic LQFP (12 × 12 mm, 0.65-mm pitch) Mounted A R5F100LCAFA, R5F100LDAFA, R5F100LEAFA, R5F100LFAFA, R5F100LGAFA, R5F100LHAFA, R5F100LJAFA, R5F100LKAFA, R5F100LLAFA #V0, #10, #30, #X0, #50 PLQP0064JA-A D R5F100LCDFA, R5F100LDDFA, R5F100LEDFA, R5F100LFDFA, R5F100LGDFA, R5F100LHDFA, R5F100LJDFA, R5F100LKDFA, R5F100LLDFA G R5F100LCGFA, R5F100LDGFA, R5F100LEGFA, R5F100LFGFA, R5F100LGGFA, R5F100LHGFA, R5F100LJGFA 64-pin plastic LQFP (12 × 12 mm, 0.65-mm pitch) Not mounted A R5F101LCAFA, R5F101LDAFA, R5F101LEAFA, R5F101LFAFA, R5F101LGAFA, R5F101LHAFA, R5F101LJAFA, R5F101LKAFA, R5F101LLAFA #V0, #10, #30, #X0, #50 PLQP0064JA-A D R5F101LCDFA, R5F101LDDFA, R5F101LEDFA, R5F101LFDFA, R5F101LGDFA, R5F101LHDFA, R5F101LJDFA, R5F101LKDFA, R5F101LLDFA 64-pin plastic LFQFP (10 × 10 mm, 0.5-mm pitch) Mounted A R5F100LCAFB, R5F100LDAFB, R5F100LEAFB, R5F100LFAFB, R5F100LGAFB, R5F100LHAFB, R5F100LJAFB, R5F100LKAFB, R5F100LLAFB #V0, #X0 PLQP0064KF-A #10, #30, #50 PLQP0064KB-C D R5F100LCDFB, R5F100LDDFB, R5F100LEDFB, R5F100LFDFB, R5F100LGDFB, R5F100LHDFB, R5F100LJDFB, R5F100LKDFB, R5F100LLDFB #V0, #X0 PLQP0064KF-A #10, #30, #50 PLQP0064KB-C G R5F100LCGFB, R5F100LDGFB, R5F100LEGFB, R5F100LFGFB, R5F100LGGFB, R5F100LHGFB, R5F100LJGFB #V0, #X0 PLQP0064KF-A #10, #30, #50 PLQP0064KB-C Not mounted A R5F101LCAFB, R5F101LDAFB, R5F101LEAFB, R5F101LFAFB, R5F101LGAFB, R5F101LHAFB, R5F101LJAFB, R5F101LKAFB, R5F101LLAFB #V0, #X0 PLQP0064KF-A #10, #30, #50 PLQP0064KB-C D R5F101LCDFB, R5F101LDDFB, R5F101LEDFB, R5F101LFDFB, R5F101LGDFB, R5F101LHDFB, R5F101LJDFB, R5F101LKDFB, R5F101LLDFB #V0, #X0 PLQP0064KF-A #10, #30, #50 PLQP0064KB-C 64-pin plastic VFBGA (4 × 4 mm, 0.4-mm pitch) Mounted A R5F100LCABG, R5F100LDABG, R5F100LEABG, R5F100LFABG, R5F100LGABG, R5F100LHABG, R5F100LJABG #U0, #W0 PVBG0064LA-A G R5F100LCGBG, R5F100LDGBG, R5F100LEGBG, R5F100LFGBG, R5F100LGGBG, R5F100LHGBG, R5F100LJGBG Not mounted A R5F101LCABG, R5F101LDABG, R5F101LEABG, R5F101LFABG, R5F101LGABG, R5F101LHABG, R5F101LJABG #U0, #W0 PVBG0064LA-A Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 10 of 200 Jun 30, 2020 Table 1-1. List of Ordering Part Numbers (7/8) Pin count Package Data flash Fields of Application Note Ordering Part Number RENESAS Code Product Name Packaging Specifications pins 80-pin plastic LQFP (14 × 14 mm, 0.65-mm pitch) Mounted A R5F100MFAFA, R5F100MGAFA, R5F100MHAFA, R5F100MJAFA, R5F100MKAFA, R5F100MLAFA #V0, #10, #30, #X0, #50 PLQP0080JB-E D R5F100MFDFA, R5F100MGDFA, R5F100MHDFA, R5F100MJDFA, R5F100MKDFA, R5F100MLDFA G R5F100MFGFA, R5F100MGGFA, R5F100MHGFA, R5F100MJGFA Not mounted A R5F101MFAFA, R5F101MGAFA, R5F101MHAFA, R5F101MJAFA, R5F101MKAFA, R5F101MLAFA #V0, #10, #30, #X0, #50 PLQP0080JB-E D R5F101MFDFA, R5F101MGDFA, R5F101MHDFA, R5F101MJDFA, R5F101MKDFA, R5F101MLDFA 80-pin plastic LFQFP (12 × 12 mm, 0.5-mm pitch) Mounted A R5F100MFAFB, R5F100MGAFB, R5F100MHAFB, R5F100MJAFB, R5F100MKAFB, R5F100MLAFB #V0, #X0 PLQP0080KE-A #10, #30, #50 PLQP0080KB-B D R5F100MFDFB, R5F100MGDFB, R5F100MHDFB, R5F100MJDFB, R5F100MKDFB, R5F100MLDFB #V0, #X0 PLQP0080KE-A #10, #30, #50 PLQP0080KB-B G R5F100MFGFB, R5F100MGGFB, R5F100MHGFB, R5F100MJGFB #V0, #X0 PLQP0080KE-A #10, #30, #50 PLQP0080KB-B Not mounted A R5F101MFAFB, R5F101MGAFB, R5F101MHAFB, R5F101MJAFB, R5F101MKAFB, R5F101MLAFB #V0, #X0 PLQP0080KE-A #10, #30, #50 PLQP0080KB-B D R5F101MFDFB, R5F101MGDFB, R5F101MHDFB, R5F101MJDFB, R5F101MKDFB, R5F101MLDFB #V0, #X0 PLQP0080KE-A #10, #30, #50 PLQP0080KB-B Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 11 of 200 Jun 30, 2020 Table 1-1. List of Ordering Part Numbers (8/8) Pin count Package Data flash Fields of Application Note Ordering Part Number RENESAS Code Product Name Packaging Specifications 100 pins 100-pin plastic LFQFP (14 × 14 mm, 0.5-mm pitch) Mounted A R5F100PFAFB, R5F100PGAFB, R5F100PHAFB, R5F100PJAFB, R5F100PKAFB, R5F100PLAFB #V0, #X0 PLQP0100KE-A #10, #30, #50 PLQP0100KB-B D R5F100PFDFB, R5F100PGDFB, R5F100PHDFB, R5F100PJDFB, R5F100PKDFB, R5F100PLDFB #V0, #X0 PLQP0100KE-A #10, #30, #50 PLQP0100KB-B G R5F100PFGFB, R5F100PGGFB, R5F100PHGFB, R5F100PJGFB #V0, #X0 PLQP0100KE-A #10, #30, #50 PLQP0100KB-B Not mounted A R5F101PFAFB, R5F101PGAFB, R5F101PHAFB, R5F101PJAFB, R5F101PKAFB, R5F101PLAFB #V0, #X0 PLQP0100KE-A #10, #30, #50 PLQP0100KB-B D R5F101PFDFB, R5F101PGDFB, R5F101PHDFB, R5F101PJDFB, R5F101PKDFB, R5F101PLDFB #V0, #X0 PLQP0100KE-A #10, #30, #50 PLQP0100KB-B 100-pin plastic LQFP (14 × 20 mm, 0.65-mm pitch) Mounted A R5F100PFAFA, R5F100PGAFA, R5F100PHAFA, R5F100PJAFA, R5F100PKAFA, R5F100PLAFA #V0, #10, #30, #X0, #50 PLQP0100JC-A D R5F100PFDFA, R5F100PGDFA, R5F100PHDFA, R5F100PJDFA, R5F100PKDFA, R5F100PLDFA G R5F100PFGFA, R5F100PGGFA, R5F100PHGFA, R5F100PJGFA Not mounted A R5F101PFAFA, R5F101PGAFA, R5F101PHAFA, R5F101PJAFA, R5F101PKAFA, R5F101PLAFA #V0, #10, #30, #X0, #50 PLQP0100JC-A D R5F101PFDFA, R5F101PGDFA, R5F101PHDFA, R5F101PJDFA, R5F101PKDFA, R5F101PLDFA 128 pins 128-pin plastic LFQFP (14 × 20 mm, 0.5-mm pitch) Mounted A R5F100SHAFB, R5F100SJAFB, R5F100SKAFB, R5F100SLAFB #V0, #10, #30, #X0, #50 PLQP0128KD-A D R5F100SHDFB, R5F100SJDFB, R5F100SKDFB, R5F100SLDFB Not mounted A R5F101SHAFB, R5F101SJAFB, R5F101SKAFB, R5F101SLAFB #V0, #10, #30, #X0, #50 PLQP0128KD-A D R5F101SHDFB, R5F101SJDFB, R5F101SKDFB, R5F101SLDFB Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 12 of 200 Jun 30, 2020

1.3 Pin Configuration (Top View)

1.3.1 20-pin products

20-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch)
20-pin plastic TSSOP (4.4 × 6.5 mm, 0.65-mm pitch) RL78/G13 (Top View) P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P147/ANI18 P10/SCK00/SCL00 P11/SI00/RxD0/TOOLRxD/SDA00 P12/SO00/TxD0/TOOLTxD P16/TI01/TO01/INTP5/SO11 P17/TI02/TO02/SI11/SDA11 P30/INTP3/SCK11/SCL11 P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC V SS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remark For pin identification, see 1.4 Pin Identification . <R>

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 13 of 200 Jun 30, 2020 1.3.2 24-pin products

24-pin plastic HWQFN (4 × 4 mm, 0.5-mm pitch) INDEX MARK 18 17 16 15 14 13 1234 5 6 P22/ANI2 P147/ANI18 P10/SCK00/SCL00 P11/SI00/RxD0/TOOLRxD/SDA00 P12/SO00/TxD0/TOOLTxD P16/TI01/TO01/INTP5 P17/TI02/TO02/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/SCK11/SCL11 P31/TI03/TO03/INTP4/PCLBUZ0 P61/SDAA0 P60/SCLA0 RL78/G13 (Top View) P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD exposed die pad Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification . 2. It is recommended to connect an exposed die pad to Vss.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 14 of 200 Jun 30, 2020 1.3.3 25-pin products

25-pin plastic WFLGA (3 × 3 mm, 0.50-mm pitch) RL78/G13 (Top View) INDEX MARK ABCDE EDCBA INDEX MARK Top View Bottom View A B C D E P40/TOOL0 RESET P01/ANI16/ TO00/RxD1 P22/ANI2 P147/ANI18 P122/X2/ EXCLK P137/INTP0 P00/ANI17/ TI00/TxD1 P21/ANI1/ AV REFM P10/SCK00/ SCL00 P121/X1 VDD P20/ANI0/ AV REFP P12/SO00/ TxD0/ TOOLTxD P11/SI00/ RxD0/ TOOLRxD/ SDA00 REGC VSS P30/INTP3/ SCK11/SCL11 P17/TI02/ TO02/SO11 P50/INTP1/ SI11/SDA11 P60/SCLA0 P61/SDAA0 P31/TI03/ TO03/INTP4/ PCLBUZ0 P16/TI01/ TO01/INTP5 P130 A B C D E Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remark For pin identification, see 1.4 Pin Identification .

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 15 of 200 Jun 30, 2020 1.3.4 30-pin products

30-pin plastic LSSOP (7.62 mm (300), 0.65-mm pitch) RL78/G13 (Top View) P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P120/ANI19 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0 P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P147/ANI18 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/SCK11/SCL11 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 16 of 200 Jun 30, 2020 1.3.5 32-pin products

32-pin plastic HWQFN (5 × 5 mm, 0.5-mm pitch) INDEX MARK 24 23 22 21 2019 18 17 1 2345678 RL78/G13 (Top View) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/SCK11/SCL11 P70 P31/TI03/TO03/INTP4/PCLBUZ0 P62 P61/SDAA0 P60/SCLA0 exposed die pad P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC V SS VDD P147/ANI18 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P120/ANI19 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual. 3. It is recommended to connect an exposed die pad to Vss.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 17 of 200 Jun 30, 2020 1.3.6 36-pin products

36-pin plastic WFLGA (4 × 4 mm, 0.5-mm pitch) Top View Bottom View FEDCBAABCDEF RL78/G13 (Top View) INDEX MARK A B C D E F P60/SCLA0 V DD P121/X1 P122/X2/EXCLK P137/INTP0 P40/TOOL0 P62 P61/SDAA0 V SS REGC RESET P120/ANI19 P72/SO21 P71/SI21/ SDA21 P14/RxD2/SI20/ SDA20/(SCLA0) /(TI03)/(TO03) P31/TI03/TO03/ INTP4/ PCLBUZ0 P00/TI00/TxD1 P01/TO00/RxD1 P50/INTP1/ SI11/SDA11 P70/SCK21/ SCL21 P15/PCLBUZ1/ SCK20/SCL20/ (TI02)/(TO02) P22/ANI2 P20/ANI0/ AV REFP P21/ANI1/ AV REFM 3 P30/INTP3/ SCK11/SCL11 P16/TI01/TO01/ INTP5/(RxD0) P12/SO00/ TxD0/TOOLTxD /(TI05)/(TO05) P11/SI00/RxD0/ TOOLRxD/ SDA00/(TI06)/ (TO06) P24/ANI4 P23/ANI3 P51/INTP2/ SO11 P17/TI02/TO02/ (TxD0) P13/TxD2/ SO20/(SDAA0)/ (TI04)/(TO04) P10/SCK00/ SCL00/(TI07)/ (TO07) P147/ANI18 P25/ANI5 A B C D E F Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 18 of 200 Jun 30, 2020 1.3.7 40-pin products

40-pin plastic HWQFN (6 × 6 mm, 0.5-mm pitch) INDEX MARK 40 12 345 6789 1 0 30 29 28 27 26 25 24 23 22 21 P50/INTP1/SI11/SDA11 P30/INTP3/RTC1HZ/SCK11/SCL11 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0 P62 P61/SDAA0 P60/SCLA0 P147/ANI18 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P51/INTP2/SO11 RL78/G13 (Top View) P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AV REFM P20/ANI0/AVREFP P01/TO00/RxD1 P00/TI00/TxD1 P120/ANI19 exposed die pad Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual. 3. It is recommended to connect an exposed die pad to Vss.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 19 of 200 Jun 30, 2020 1.3.8 44-pin products

44-pin plastic LQFP (10 × 10 mm, 0.8-mm pitch) 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/RTC1HZ/SCK11/SCL11 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0 P63 P62 P61/SDAA0 P60/SCLA0 RL78/G13 (Top View) P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AV REFM P20/ANI0/AVREFP P01/TO00/RxD1 P00/TI00/TxD1 P120/ANI19 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 20 of 200 Jun 30, 2020 1.3.9 48-pin products

48-pin plastic LFQFP (7 × 7 mm, 0.5-mm pitch) 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 RL78/G13 (Top View) P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4/(PCLBUZ0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK11/SCL11 P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AV REFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P120/ANI19 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 21 of 200 Jun 30, 2020

48-pin plastic HWQFN (7 × 7 mm, 0.5-mm pitch) INDEX MARK P120/ANI19 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 RL78/G13 (Top View) P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4/(PCLBUZ0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK11/SCL11 P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 exposed die pad Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual. 3. It is recommended to connect an exposed die pad to Vss.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 22 of 200 Jun 30, 2020 1.3.10 52-pin products

52-pin plastic LQFP (10 × 10 mm, 0.65-mm pitch) RL78/G13 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/RTC1HZ/SCK11/SCL11 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RxD2) P77/KR7/INTP11/(TxD2) P31/TI03/TO03/INTP4/(PCLBUZ0) P63 P62 P61/SDAA0 P60/SCLA0 P140/PCLBUZ0/INTP6 P120/ANI19 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P03/ANI16/RxD1 P02/ANI17/TxD1 P01/TO00 P00/TI00 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 23 of 200 Jun 30, 2020 1.3.11 64-pin products

64-pin plastic LQFP (12 × 12 mm, 0.65-mm pitch)
64-pin plastic LFQFP ( 10 × 10 mm, 0.5-mm pitch) RL78/G13 (Top View) 1 2 3 4 5 6 7 8 9 10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AV REFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P30/INTP3/RTC1HZ/SCK11/SCL11 P05/TI05/TO05 P06/TI06/TO06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RxD2) P77/KR7/INTP11/(TxD2) P31/TI03/TO03/INTP4/(PCLBUZ0) P63 P62 P61/SDAA0 P60/SCLA0 P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RxD0) P17/TI02/TO02/(SO00)/(TxD0) P55/(PCLBUZ1)/(SCK00) P54 P53/(INTP11) P52/(INTP10) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P120/ANI19 P43 P42/TI04/TO04 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 11 12 13 14 15 16 Cautions 1. Make EV SS0 pin the same potential as VSS pin. 2. Make V DD pin the potential that is no less than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application wher e the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD and EV DD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 24 of 200 Jun 30, 2020

64-pin plastic VFBGA (4 × 4 mm, 0.4-mm pitch) HGFEDCBA RL78/G13 (Top View) ABC D EFG H Top View Bottom View Index mark Pin No. Name Pin No. Name Pin No. Name Pin No. Name A1 P05/TI05/TO05 C1 P51/INTP2/SO11 E1 P13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04) G1 P146 A2 P30/INTP3/RTC1HZ /SCK11/SCL11 C2 P71/KR1/SI21/SDA21 E2 P14/RxD2/SI20/SDA20 /(SCLA0)/(TI03)/(TO03) G2 P25/ANI5 A3 P70/KR0/SCK21 /SCL21 C3 P74/KR4/INTP8/SI01 /SDA01 E3 P15/SCK20/SCL20/ (TI02)/(TO02) G3 P24/ANI4 A4 P75/KR5/INTP9 /SCK01/SCL01 C4 P52/(INTP10) E4 P16/TI01/TO01/INTP5 /(SI00)/(RxD0) G4 P22/ANI2 A5 P77/KR7/INTP11/ (TxD2) C5 P53/(INTP11) E5 P03/ANI16/SI10/RxD1 /SDA10 G5 P130 A6 P61/SDAA0 C6 P63 E6 P41/TI07/TO07 G6 P02/ANI17/SO10/TxD1 A7 P60/SCLA0 C7 V SS E7 RESET G7 P00/TI00 A8 EV DD0 C8 P121/X1 E8 P137/INTP0 G8 P124/XT2/EXCLKS B1 P50/INTP1/SI11 /SDA11 D1 P55/(PCLBUZ1)/ (SCK00) F1 P10/SCK00/SCL00/ (TI07)/(TO07) H1 P147/ANI18 B2 P72/KR2/SO21 D2 P06/TI06/TO06 F2 P11/SI00/RxD0 /TOOLRxD/SDA00/ (TI06)/(TO06) H2 P27/ANI7 B3 P73/KR3/SO01 D3 P17/TI02/TO02/ (SO00)/(TxD0) F3 P12/SO00/TxD0 /TOOLTxD/(INTP5)/ (TI05)/(TO05) H3 P26/ANI6 B4 P76/KR6/INTP10/ (RxD2) D4 P54 F4 P21/ANI1/AV REFM H4 P23/ANI3 B5 P31/TI03/TO03 /INTP4/(PCLBUZ0) D5 P42/TI04/TO04 F5 P04/SCK10/SCL10 H5 P20/ANI0/AV REFP B6 P62 D6 P40/TOOL0 F6 P43 H6 P141/PCLBUZ1/INTP7 B7 V DD D7 REGC F7 P01/TO00 H7 P140/PCLBUZ0/INTP6 B8 EV SS0 D8 P122/X2/EXCLK F8 P123/XT1 H8 P120/ANI19 Cautions 1. Make EV SS0 pin the same potential as VSS pin. 2. Make V DD pin the potential that is no less than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application wher e the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD and EV DD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 25 of 200 Jun 30, 2020 1.3.12 80-pin products

80-pin plastic LQFP (14 × 14 mm, 0.65-mm pitch)
80-pin plastic LFQFP ( 12 × 12 mm, 0.5-mm pitch) P153/ANI11 P100/ANI20 P147/ANI18 P146 P111/(INTP11) P110/(INTP10) P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RxD0) P17/TI02/TO02/(SO00)/(TxD0) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/INTP2/SO11 P50/INTP1/SI11/SDA11 RL78/G13 (Top View) 1 2 3 4 5 6 7 8 9 10 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P30/INTP3/RTC1HZ/SCK11/SCL11 P05/TI05/TO05 P06/TI06/TO06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RxD2) P77/KR7/INTP11/(TxD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0) P63/SDAA1 P62/SCLA1 P61/SDAA0 P60/SCLA0 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC V SS EVSS0 VDD EVDD0 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AV REFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P142/SCK30/SCL30 11 12 13 14 15 16 17 18 19 20 Cautions 1. Make EV SS0 pin the same potential as VSS pin. 2. Make V DD pin the potential that is no less than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application wher e the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD and EV DD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 26 of 200 Jun 30, 2020 1.3.13 100-pin products

100-pin plastic LFQFP (14 × 14 mm, 0.5-mm pitch) P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 P60/SCLA0 P61/SDAA0 RL78/G13 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P100/ANI20 P147/ANI18 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RxD0) P17/TI02/TO02/(SO00)/(TxD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO11 P50/SI11/SDA11 EV DD1 P30/INTP3/RTC1HZ/SCK11/SCL11 P87/(INTP9) P156/ANI14 P155/ANI13 P154/ANI12 P153/ANI11 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AV REFM P20/ANI0/AVREFP P130 P102/TI06/TO06 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P145/TI07/TO07 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P86/(INTP8) P85/(INTP7) P84/(INTP6) P83 P82/(SO10)/(TxD1) P81/(SI10)/(RxD1)/(SDA10) P80/(SCK10)/(SCL10) EV SS1 P05 P06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RxD2) P77/KR7/INTP11/(TxD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0) P63/SDAA1 P62/SCLA1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 Cautions 1. Make EV SS0 and EVSS1 pins the same potential as VSS pin. 2. Make V DD pin the potential that is no less than EVDD0 and EVDD1 pins (EVDD0 = EVDD1). 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application wher e the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD, EVDD0 and EV DD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 27 of 200 Jun 30, 2020

100-pin plastic LQFP (14 × 20 mm, 0.65-mm pitch) P120/ANI19 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 RL78/G13 (Top View) P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P142/SCK30/SCL30 P143/SI30/RxD3/SDA30 P144/SO30/TxD3 P145/TI07/TO07 P00/TI00 P01/TO00 P02/ANI17/SO10/TxD1 P03/ANI16/SI10/RxD1/SDA10 P04/SCK10/SCL10 P102/TI06/TO06 P130 P20/ANI0/AV REFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P150/ANI8 P151/ANI9 P152/ANI10 P153/ANI11 P154/ANI12 P155/ANI13 P156/ANI14 P100/ANI20 P147/ANI18 P60/SCLA0 P61/SDAA0 P62/SCLA1 P63/SDAA1 P31/TI03/TO03/INTP4/(PCLBUZ0) P64/TI10/TO10 P65/TI11/TO11 P66/TI12/TO12 P67/TI13/TO13 P77/KR7/INTP11/(TxD2) P76/KR6/INTP10/(RxD2) P75/KR5/INTP9 P74/KR4/INTP8 P73/KR3 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P06 P05 EVSS1 P80/(SCK10)/(SCL10) P81/(SI10)/(RxD1)/(SDA10) P82/(SO10)/(TxD1) P83 P84/(INTP6) P85/(INTP7) P86/(INTP8) P87/(INTP9) P30/INTP3/RTC1HZ/SCK11/SCL11 EV DD1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 100 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RxD0) P17/TI02/TO02/(SO00)/(TxD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO11 P50/SI11/SDA11 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Cautions 1. Make EV SS0 and EVSS1 pins the same potential as VSS pin. 2. Make V DD pin the potential that is no less than EVDD0 and EVDD1 pins (EVDD0 = EVDD1). 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application wher e the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD, EVDD0 and EV DD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 28 of 200 Jun 30, 2020 1.3.14 128-pin products

128-pin plastic LFQFP (14 × 20 mm, 0.5-mm pitch) RL78/G13 (Top View) P100/ANI20 P147/ANI18 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P117/ANI24 P116/ANI25 P115/ANI26 P114 P113 P112 P97/SO11 P96/SI11/SDA11 P95/SCK11/SCL11 P94 P93 P92 P91 P90 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RxD0) P17/TI02/TO02/(SO00)/(TxD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51 P50 P30/INTP3/RTC1HZ P87/(INTP9) P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19 P37/ANI21 P36/ANI22 P35/ANI23 P34 P33 P32 P106/TI17/TO17 P105/TI16/TO16 P104/TI15/TO15 P103/TI14/TO14 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 P127 P126 P125 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC V SS EVSS0 VDD EVDD0 P60/SCLA0 P61/SDAA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 102 101 100 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P86/(INTP8) P85/(INTP7) P84/(INTP6) P83 P82/(SO10)/(TxD1) P81/(SI10)/(RxD1)/(SDA10) P80/(SCK10)/(SCL10) EV DD1 EVSS1 P05 P06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RxD2) P77/KR7/INTP11/(TxD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0) P63/SDAA1 P62/SCLA1 P156/ANI14 P155/ANI13 P154/ANI12 P153/ANI11 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AV REFM P20/ANI0/AVREFP P130 P102/TI06/TO06 P07 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P145/TI07/TO07 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 6599 98 97 96 95 94 93 92 91 90 89 88 87 86 85 Cautions 1. Make EV SS0 and EVSS1 pins the same potential as VSS pin. 2. Make V DD pin the potential that is no less than EVDD0 and EVDD1 pins (EVDD0 = EVDD1). 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application wher e the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the V DD, EVDD0 and EV DD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 29 of 200 Jun 30, 2020

1.4 Pin Identification

ANI0 to ANI14, ANI16 to ANI26: Analog input AVREFM: A/D converter reference potential (– side) input AVREFP: A/D converter reference potential (+ side) input EVDD0, EVDD1: Power supply for port EVSS0, EVSS1: Ground for port EXCLK: External clock input (Main system clock) EXCLKS: External clock input (Subsystem clock) INTP0 to INTP11: Interrupt request from peripheral KR0 to KR7: Key return P00 to P07: Port 0 P10 to P17: Port 1 P20 to P27: Port 2 P30 to P37: Port 3 P40 to P47: Port 4 P50 to P57: Port 5 P60 to P67: Port 6 P70 to P77: Port 7 P80 to P87: Port 8 P90 to P97: Port 9 P100 to P106: Port 10 P110 to P117: Port 11 P120 to P127: Port 12 P130, P137: Port 13 P140 to P147: Port 14 P150 to P156: Port 15 PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer output REGC: Regulator capacitance RESET: Reset RTC1HZ: Real-time clock correction clock (1 Hz) output RxD0 to RxD3: Receive data SCLA0, SCLA1, SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, SCK31: Serial clock input/output SCL00, SCL01, SCL10, SCL11, SCL20, SCL21, SCL30, SCL31: Serial clock output SDAA0, SDAA1, SDA00, SDA01,SDA10, SDA11, SDA20,SDA21, SDA30, SDA31: Serial data input/output SI00, SI01, SI10, SI11, SI20, SI21, SI30, SI31: Serial data input SO00, SO01, SO10, SO11, SO20, SO21, SO30, SO31: Serial data output TI00 to TI07, TI10 to TI17: Timer input TO00 to TO07, TO10 to TO17: Timer output TOOL0: Data input/output for tool TOOLRxD, TOOLTxD: Data inpu t/output for external device TxD0 to TxD3: Transmit data V DD: Power supply VSS: Ground X1, X2: Crystal oscillator (main system clock) XT1, XT2: Crystal oscillator (subsystem clock)

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 30 of 200 Jun 30, 2020

1.5 Block Diagram

1.5.1 20-pin products PORT 1 P10 to P12, P16, P17 PORT 2 P20 to P223 PORT 3 P30 PORT 4 PORT 12 P121, P122 P40 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM LOW-SPEED ON-CHIP OSCILLATOR POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11 TxD0/P12 UART1RxD1/P01 TxD1/P00 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2TI02/TO02/P17 ch3 ch0 ch1 ch4 ch5 ch6 ch7 INTP0/P137 INTP3/P30 A/D CONVERTER

3 ANI0/P20 to

VSS TOOLRxD/P11, TOOLTxD/P12 VDD INTP5/P16 PORT 0 P00, P012 WINDOW WATCHDOG TIMER REAL-TIME CLOCK

3 ANI16/P01, ANI17/P00,

MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE CRC AVREFP/P20 AVREFM/P21

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 31 of 200 Jun 30, 2020 1.5.2 24-pin products PORT 1 P10 to P12, P16, P17 PORT 2 P20 to P223 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121, P122 P40 P50 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM WINDOW WATCHDOG TIMER POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11 TxD0/P12 UART1 RxD1/P01 TxD1/P00 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2 ch3 ch0 ch1 ch4 ch5 ch6 ch7 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50 A/D CONVERTER MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR PORT 0 P00, P012 PORT 6 P60, P612 PORT 14 P147 BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P31 REAL-TIME CLOCK CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE CRC LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER TOOLRxD/P11, TOOLTxD/P12 SDAA0/P61 SCLA0/P60 TOOL0/P40 TI02/TO02/P17 TI03/TO03/P31 TI00/P00 TO00/P01 TI01/TO01/P16

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 32 of 200 Jun 30, 2020 1.5.3 25-pin products PORT 1 P10 to P12, P16, P17 PORT 2 P20 to P223 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121, P122 P40 P50 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11 TxD0/P12 UART1RxD1/P01 TxD1/P00 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2TI02/TO02/P17 ch3TI03/TO03/P31 ch0 ch1 ch4 ch5 ch6 ch7 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50 A/D CONVERTER VSS TOOLRxD/P11, TOOLTxD/P12 VDD SDAA0/P61 SCLA0/P60SERIAL INTERFACE IICA0 INTP5/P16 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR PORT 0 P00, P012 PORT 6 P60, P612 PORT 14 P147 TI01/TO01/P16 BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P31 WINDOW WATCHDOG TIMER REAL-TIME CLOCK CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER CRC

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 33 of 200 Jun 30, 2020 1.5.4 30-pin products PORT 1 P10 to P17 PORT 2 P20 to P234 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121, P122 P40 P50, P512 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1RxD1/P01 TxD1/P00 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2 TI02/TO02/P17 (TI02/TO02/P15) ch3 TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4 ch5 ch6 ch7 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD2/P14 A/D CONVERTER

4 ANI0/P20 to

VSS TOOLRxD/P11, TOOLTxD/P12 VDD SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14)SERIAL INTERFACE IICA0 INTP5/P16 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR PORT 0 P00, P012 BUZZER OUTPUT CLOCK OUTPUT CONTROL

4 ANI16/P01, ANI17/P00,

ANI18/P147, ANI19/P120 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL RxD2/P14 TxD2/P13 SCL20/P15 SDA20/P14 IIC20 CSI20 SCK20/P15 SO20/P13 SI20/P14 DIRECT MEMORY ACCESS CONTROL PORT 6 P60, P612 PORT 14 P147 TI01/TO01/P16 RxD2/P14 PCLBUZ0/P31, PCLBUZ1/P152 WINDOW WATCHDOG TIMER REAL-TIME CLOCK CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) (TI07/TO07/P10) CRC LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 34 of 200 Jun 30, 2020 1.5.5 32-pin products PORT 1 P10 to P17 PORT 2 P20 to P234 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121, P122 P40 P50, P512 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 SERIAL ARRAY UNIT0 (4ch) UART0 RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1RxD1/P01 TxD1/P00 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2TI02/TO02/P17 (TI02/TO02/P15) ch3TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4 ch5 ch6 ch7 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD2/P14 A/D CONVERTER VSS TOOLRxD/P11, TOOLTxD/P12 V DD SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14)SERIAL INTERFACE IICA0 INTP5/P16 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR PORT 0 P00, P012 BUZZER OUTPUT CLOCK OUTPUT CONTROL ANI18/P147, ANI19/P120 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL RxD2/P14 TxD2/P13 SCL20/P15 SDA20/P14 IIC20 CSI20 SCK20/P15 SO20/P13 SI20/P14 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 P70 P60 to P623 PORT 14 P147 TI01/TO01/P16 RxD2/P14 PCLBUZ0/P31, PCLBUZ1/P152 WINDOW WATCHDOG TIMER REAL-TIME CLOCK CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) (TI07/TO07/P10) LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER CRC Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 35 of 200 Jun 30, 2020 1.5.6 36-pin products PORT 1 P10 to P17 PORT 2 P20 to P25 6 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121, P122 P40 P50, P512 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 SERIAL ARRAY UNIT0 (4ch) UART0 RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1RxD1/P01 TxD1/P00 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2TI02/TO02/P17 (TI02/TO02/P15) ch3TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4 ch5 ch6 ch7 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD2/P14 A/D CONVERTER

6 ANI0/P20 to

VSS TOOLRxD/P11, TOOLTxD/P12 VDD SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) SERIAL INTERFACE IICA0 INTP5/P16 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR PORT 0 P00, P012 BUZZER OUTPUT CLOCK OUTPUT CONTROL REAL-TIME CLOCK WINDOW WATCHDOG TIMER

2 ANI18/P147, ANI19/P120

UNIT1 (2ch) UART2 LINSEL RxD2/P14 TxD2/P13 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 CSI20 SCK20/P15 SO20/P13 SI20/P14 CSI21 SCK21/P70 SO21/P72 SI21/P71 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 P70 to P72 3 P60 to P62 3 PORT 14 P147 TI01/TO01/P16 RxD2/P14 PCLBUZ0/P31, PCLBUZ1/P152 CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) (TI07/TO07/P10) LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER CRC Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 36 of 200 Jun 30, 2020 1.5.7 40-pin products PORT 1 P10 to P17 PORT 2 P20 to P267 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121 to P124 P40 P50, P512 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM WINDOW WATCHDOG TIMER POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1RxD1/P01 TxD1/P00 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2TI02/TO02/P17 (TI02/TO02/P15) ch3TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4 ch5 ch6 ch7 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD2/P14 A/D CONVERTER

7 ANI0/P20 to

VSS TOOLRxD/P11, TOOLTxD/P12 V DD SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) SERIAL INTERFACE IICA0 INTP5/P16 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR XT1/P123 XT2/EXCLKS/P124 PORT 0 P00, P012 BUZZER OUTPUT CLOCK OUTPUT CONTROL KEY RETURN 4 KR0/P70 to KR3/P73 UNIT1 (2ch) UART2 LINSEL RxD2/P14 TxD2/P13 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 CSI20 SCK20/P15 SO20/P13 SI20/P14 CSI21 SCK21/P70 SO21/P72 SI21/P71 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 P70 to P734 P60 to P623 PORT 14 P147 TI01/TO01/P16 RTC1HZ/P30 PCLBUZ0/P31, PCLBUZ1/P152 CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) RxD2/P14 (TI07/TO07/P10) LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER CRC Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 37 of 200 Jun 30, 2020 1.5.8 44-pin products TxD1/P00 PORT 1 P10 to P17 PORT 2 P20 to P27 8 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121 to P124 P40, P412 P50, P512 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM WINDOW WATCHDOG TIMER POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1 RxD1/P01 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2TI02/TO02/P17 (TI02/TO02/P15) ch3TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4 ch5 ch6 ch7 INTP0/P137 INTP3/P30, INTP4/P31 INTP1/P50, INTP2/P51 RxD2/P14 A/D CONVERTER

8 ANI0/P20 to

(TI07/TO07/P10) TI00/P00 TO00/P01 BCD ADJUSTMENT CSI00 SCK00/P10 SO00/P12 SI00/P11 VSS TOOLRxD/P11, TOOLTxD/P12 VDD SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14)SERIAL INTERFACE IICA0 INTP5/P16 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR XT1/P123 XT2/EXCLKS/P124 PORT 0 P00, P012 BUZZER OUTPUT CLOCK OUTPUT CONTROL KEY RETURN 4 KR0/P70 to KR3/P73 UNIT1 (2ch) UART2 LINSEL RxD2/P14 TxD2/P13 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 CSI20 SCK20/P15 SO20/P13 SI20/P14 CSI21 SCK21/P70 SO21/P72 SI21/P71 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 P70 to P734 P60 to P63 4 PORT 14 P146, P1472 TI01/TO01/P16 RTC1HZ/P30 RxD2/P14 PCLBUZ0/P31, PCLBUZ1/P152 CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER CRC Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 38 of 200 Jun 30, 2020 1.5.9 48-pin products PORT 1 P10 to P17 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121 to P124 P40, P412 P50, P512 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM WINDOW WATCHDOG TIMER POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1RxD1/P01 TxD1/P00 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2TI02/TO02/P17 (TI02/TO02/P15) ch3TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4 ch5 ch6 ch7 INTP8/P74, INTP9/P75 INTP0/P137 INTP3/P30, INTP4/P31 INTP6/P140 INTP1/P50, INTP2/P51 RxD2/P14 A/D CONVERTER (TI07/TO07/P10) TI00/P00 TO00/P01 BCD ADJUSTMENT CSI00 SCK00/P10 SO00/P12 SI00/P11 VSS TOOLRxD/P11, TOOLTxD/P12 V DD SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14)SERIAL INTERFACE IICA0 INTP5/P16 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR XT1/P123 XT2/EXCLKS/P124 PORT 0 P00, P012 BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P15 KEY RETURN 6 KR0/P70 to KR5/P75 UNIT1 (2ch) UART2 LINSEL RxD2/P14 TxD2/P13 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 CSI20 SCK20/P15 SO20/P13 SI20/P14 CSI21 SCK21/P70 SO21/P72 SI21/P71 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 P70 to P756 P60 to P634 PORT 14 P140, P146, P147 TI01/TO01/P16 RTC1HZ/P30 RxD2/P14 CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER CRC Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 39 of 200 Jun 30, 2020 1.5.10 52-pin products PORT 1 P10 to P17 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121 to P124 P40, P412 P50, P512 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1RxD1/P03 TxD1/P02 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2TI02/TO02/P17 (TI02/TO02/P15) ch3TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4 ch5 ch6 ch7 INTP8/P74 to INTP11/P77 INTP0/P137 INTP3/P30, INTP4/P31 INTP6/P140 INTP1/P50, INTP2/P51 RxD2/P14 (RxD2/P76) A/D CONVERTER (TI07/TO07/P10) TI00/P00 TO00/P01 BCD ADJUSTMENT CSI00 SCK00/P10 SO00/P12 SI00/P11 VSS TOOLRxD/P11, TOOLTxD/P12 VDD SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14)SERIAL INTERFACE IICA0 INTP5/P16 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR XT1/P123 XT2/EXCLKS/P124 PORT 0 P00 to P034 BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P15 KEY RETURN 8 KR0/P70 to KR7/P77 WINDOW WATCHDOG TIMER

4 ANI16/P03, ANI17/P02,

ANI18/P147, ANI19/P120 CSI01 SCK01/P75 SO01/P73 SI01/P74 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 CSI20 SCK20/P15 SO20/P13 SI20/P14 CSI21 SCK21/P70 SO21/P72 SI21/P71 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 P70 to P778 P60 to P634 PORT 14 P140, P146, P1473 TI01/TO01/P16 RTC1HZ/P30 RxD2/P14 (RxD2/P76) REAL-TIME CLOCK CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER CRC Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 40 of 200 Jun 30, 2020 1.5.11 64-pin products PORT 1 P10 to P17 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 4 PORT 5 PORT 12 P121 to P124 P40 to P434 P50 to P556 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1RxD1/P03 TxD1/P02 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT (8ch) ch2TI02/TO02/P17 (TI02/TO02/P15) ch3TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4TI04/TO04/P42 (TI04/TO04/P13) ch5TI05/TO05/P05 (TI05/TO05/P12) ch6TI06/TO06/P06 (TI06/TO06/P11) ch7 INTP8/P74, INTP9/P75 INTP0/P137 INTP3/P30, INTP4/P31 INTP6/P140, INTP7/P141 INTP1/P50, INTP2/P51 RxD2/P14 (RxD2/P76) CSI10 SCK10/P04 SO10/P02 SI10/P03 A/D CONVERTER (TI07/TO07/P10) TI00/P00 TO00/P01 BCD ADJUSTMENT CSI00 SCK00/P10(SCK00/P55) SO00/P12(SO00/P17) SI00/P11(SI00/P16) VSS, EVSS0 TOOLRxD/P11, TOOLTxD/P12 V DD, EVDD0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14)SERIAL INTERFACE IICA0 INTP5/P16(INTP5/P12) MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR XT1/P123 XT2/EXCLKS/P124 PORT 0 P00 to P067 BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) KEY RETURN 8 KR0/P70 to KR7/P77 WINDOW WATCHDOG TIMER ANI18/P147, ANI19/P120 CSI01 SCK01/P75 SO01/P73 SI01/P74 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 CSI20 SCK20/P15 SO20/P13 SI20/P14 CSI21 SCK21/P70 SO21/P72 SI21/P71 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 P70 to P778 P60 to P634 PORT 14 P140, P141, P146, P147 TI01/TO01/P16 RTC1HZ/P30 RxD2/P14 (RxD2/P76) CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE INTP10/P76(INTP10/P52), INTP11/P77(INTP11/P53) LOW-SPEED ON-CHIP OSCILLATOR CRC 12- BIT INTERVAL TIMER Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 41 of 200 Jun 30, 2020 1.5.12 80-pin products PORT 1 PORT 2 P20 to P278 PORT 3 P30, P312 PORT 4 PORT 5 P10 to P178 P40 to P456 P50 to P556 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM WINDOW WATCHDOG TIMER POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG TOOL0/P40 SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1RxD1/P03 TxD1/P02 SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT0 (8ch) ch2TI02/TO02/P17 (TI02/TO02/P15) ch3TI03/TO03/P31 (TI03/TO03/P14) ch0 ch1 ch4TI04/TO04/P42 (TI04/TO04/P13) ch5TI05/TO05/P05 (TI05/TO05/P12) ch6TI06/TO06/P06 (TI06/TO06/P11) ch7 INTP8/P74, INTP9/P75 INTP0/P137 INTP3/P30, INTP4/P31 INTP6/P140, INTP7/P141 INTP1/P50, INTP2/P51 RxD2/P14 (RxD2/P76) CSI10 SCK10/P04 SO10/P02 SI10/P03 A/D CONVERTER

8 ANI0/P20 to ANI7/P27

(TI07/TO07/P10) TI00/P00 TO00/P01 BCD ADJUSTMENT CSI00 SO00/P12(SO00/P17) SI00/P11(SI00/P16) VSS, EVSS0 TOOLRxD/P11, TOOLTxD/P12 VDD, EVDD0 SCLA0/P60(SCLA0/P14)SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) INTP5/P16(INTP5/P12) MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR XT1/P123 XT2/EXCLKS/P124 PORT 0 P00 to P067 BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) KEY RETURN 8 KR0/P70 to KR7/P77

5 ANI16/P03, ANI17/P02,

ANI18/P147, ANI19/P120, ANI20/P100 CSI01 SCK01/P43 SO01/P45 SI01/P44 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 P70 to P778 P60 to P678 PORT 10 P100 TI01/TO01/P16 RTC1HZ/P30 RxD2/P14 (RxD2/P76)

4 ANI8/P150 to ANI11/P153

PORT 11 P110, P1112 PORT 12 P121 to P1244 P120 PORT 13 P130 P137 PORT 14 P140 to P144, P146, P1477 PORT 15 P150 to P1534 SERIAL ARRAY UNIT1 (4ch) RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) UART3RxD3/P143 TxD3/P144 SCL20/P15 SDA20/P14 IIC20 CSI30 SCK30/P142 SO30/P144 SI30/P143 CSI31 SCK31/P54 SO31/P52 SI31/P53 SCL21/P70 SDA21/P71 IIC21 SCL30/P142 SDA30/P143 IIC30 SCL31/P54 SDA31/P53 IIC31 CSI20 SCK20/P15 SO20/P13 SI20/P14 CSI21 SCK21/P70 SO21/P72 SI21/P71 UART2 LINSEL TIMER ARRAY UNIT1 (4ch) ch2 ch3 ch0 ch1 TI12/TO12/P66 TI13/TO13/P67 TI11/TO11/P65 TI10/TO10/P64 SDAA1/P63 SCLA1/P62 SERIAL INTERFACE IICA1 REAL-TIME CLOCK CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE INTP10/P76(INTP10/P110), INTP11/P77(INTP11/P111) SCK00/P10(SCK00/P55) CRC LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 42 of 200 Jun 30, 2020 1.5.13 100-pin products SCK10/P04(SCK10/P80) PORT 1 PORT 2 8 PORT 3 2 PORT 4 PORT 5 PORT 8 VOLTAGE REGULATOR INTERRUPT CONTROL RAM WINDOW WATCHDOG TIMER POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART1RxD1/P03(RxD1/P81) TxD1/P02(TxD1/P82) SCL00/P10 SDA00/P11 IIC00 TIMER ARRAY UNIT0 (8ch) ch2 ch3 ch0 ch1 ch4 ch5 ch6 ch7 INTP8/P74(INTP8/P86), INTP9/P75(INTP9/P87) INTP3/P30(INTP3/P57), INTP4/P31(INTP4/P146) INTP6/P140(INTP6/P84), INTP7/P141(INTP7/P85) INTP1/P46(INTP1/P56), INTP2/P47 CSI10 SO10/P02(SO10/P82) SI10/P03(SI10/P81) A/D CONVERTER CSI11 SCK11/P30 SO11/P51 SI11/P50 SCL01/P43 IIC01 SCL10/P04(SCL10/P80) SDA10/P03(SDA10/P81) IIC10 SCL11/P30 IIC11 BCD ADJUSTMENT CSI00 SCK00/P10(SCK00/P55) SO00/P12(SO00/P17) SI00/P11(SI00/P16) SCLA0/P60(SCLA0/P14)SERIAL INTERFACE IICA0 INTP5/P16(INTP5/P12) MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR PORT 0 7 KEY RETURN 8 CSI01 SCK01/P43 SO01/P45 SI01/P44 DIRECT MEMORY ACCESS CONTROL PORT 6 PORT 7 8 PORT 10 3 BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) PORT 11 2 PORT 12 4 PORT 13 PORT 14 8 PORT 15 7 SERIAL ARRAY UNIT1 (4ch) UART3 IIC20 CSI30 CSI31 IIC21 IIC30 IIC31 CSI20 CSI21 UART2 LINSEL TIMER ARRAY UNIT1 (4ch) ch2 ch3 ch0 ch1 SDAA1/P63 SCLA1/P62 SERIAL INTERFACE IICA1 CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE INTP10/P76(INTP10/P110), INTP11/P77(INTP11/P111) 2 CRC LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER P20 to P27 P30, P31 P10 to P17 P40 to P47 P50 to P57 P00 to P06 P80 to P87 P70 to P77 P60 to P67 KR0/P70 to KR7/P77 P100 to P102 P110, P111 P121 to P124 P120 P130 P137 P140 to P147 P150 to P156 REGC RESET X1/P121 X2/EXCLK/P122 TOOL0/P40 INTP0/P137 RxD2/P14 (RxD2/P76) XT1/P123 XT2/EXCLKS/P124 RTC1HZ/P30 SDAA0/P61(SDAA0/P13) VSS, EVSS0, EVSS1 TOOLRxD/P11, TOOLTxD/P12 VDD, EVDD0, EVDD1 ANI0/P20 to ANI7/P27 AVREFP/P20 AVREFM/P21 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 ANI8/P150 to ANI14/P156 TI12/TO12/P66 TI13/TO13/P67 TI11/TO11/P65 TI10/TO10/P64 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) TI04/TO04/P42 (TI04/TO04/P13) TI05/TO05/P46 (TI05/TO05/P12) TI06/TO06/P102 (TI06/TO06/P11) TI07/TO07/P145 (TI07/TO07/P10) TI00/P00 TO00/P01 TI01/TO01/P16 RxD2/P14 (RxD2/P76) SDA01/P44 SDA11/P50 RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) RxD3/P143 TxD3/P144 SCL20/P15 SDA20/P14 SCK30/P142 SO30/P144 SI30/P143 SCK31/P54 SO31/P52 SI31/P53 SCL21/P70 SDA21/P71 SCL30/P142 SDA30/P143 SCL31/P54 SDA31/P53 SCK20/P15 SO20/P13 SI20/P14 SCK21/P70 SO21/P72 SI21/P71 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 43 of 200 Jun 30, 2020 1.5.14 128-pin products TxD3/P144 PORT 1 PORT 2 8 PORT 3 P30 to P378 PORT 4 PORT 5 PORT 8 VOLTAGE REGULATOR REGC INTERRUPT CONTROL RAM POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR ON-CHIP DEBUG SERIAL ARRAY UNIT0 (4ch) UART0 UART1 IIC00 TIMER ARRAY UNIT0 (8ch) ch2 ch3 ch0 ch1 ch4 ch5 ch6 ch7 INTP8/P74 (INTP8/P86), INTP9/P75 (INTP9/P87) INTP0/P137 INTP3/P30 (INTP3/P57), INTP4/P31 (INTP4/P146) INTP6/P140 (INTP6/P84), INTP7/P141 (INTP7/P85) INTP1/P46 (INTP1/P56), INTP2/P47 RxD2/P14 (RxD2/P76) CSI10 A/D CONVERTER PORT 9 CSI11 IIC01 IIC10 IIC11 CSI00 INTP5/P16 (INTP5/P12) PORT 0 8 KEY RETURN 8

11 ANI16/P03, ANI17/P02,

ANI18/P147, ANI19/P120, ANI20/P100, ANI21/P37, ANI22/P36, ANI23/P35, ANI24/P117, ANI25/P116, ANI26/P115 CSI01 PORT 6 PORT 7 8 PORT 10 7 PORT 11 P110 to P1178 PORT 12 4 P120, P125 to P127 PORT 13 P130 P137 PORT 14 8 PORT 15 7 SERIAL ARRAY UNIT1 (4ch) RxD2/P14(RxD2/P76) UART3RxD3/P143 SCL20/P15 IIC20 CSI30 SCK30/P142 SO30/P144 SI30/P143 CSI31 SCK31/P54 SO31/P52 SI31/P53 SCL21/P70 IIC21 SCL30/P142 IIC30 SCL31/P54 IIC31 CSI20 SCK20/P15 SO20/P13 SI20/P14 CSI21 SCK21/P70 SO21/P72 SI21/P71 UART2 LINSEL TIMER ARRAY UNIT1 (8ch) ch2 ch3 ch0 ch1 ch4 ch5 ch6 ch7 WINDOW WATCHDOG TIMER REAL-TIME CLOCK BCD ADJUSTMENT SERIAL INTERFACE IICA0 MULTIPLIER& DIVIDER, MULTIPLY- ACCUMULATOR BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) DIRECT MEMORY ACCESS CONTROL SCLA1/P62 SERIAL INTERFACE IICA1 CODE FLASH MEMORY DATA FLASH MEMORY RL78 CPU CORE

2 INTP10/P76 (INTP10/P110),

INTP11/P77 (INTP11/P111) CRC LOW-SPEED ON-CHIP OSCILLATOR 12- BIT INTERVAL TIMER TI12/TO12/P66 TI13/TO13/P67 TI14/TO14/P103 TI15/TO15/P104 TI16/TO16/P105 TI17/TO17/P106 TI11/TO11/P65 TI10/TO10/P64 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) TI04/TO04/P42 (TI04/TO04/P13) TI05/TO05/P46 (TI05/TO05/P12) TI06/TO06/P102 (TI06/TO06/P11) TI07/TO07/P145 (TI07/TO07/P10) TI00/P00 TO00/P01 TI01/TO01/P16 RxD2/P14 (RxD2/P76) SCK10/P04(SCK10/P80) RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P03(RxD1/P81) TxD1/P02(TxD1/P82) SCL00/P10 SDA00/P11 SO10/P02(SO10/P82) SI10/P03(SI10/P81) SCK11/P95 SO11/P97 SI11/P96 SCL01/P43 SCL10/P04(SCL10/P80) SDA10/P03(SDA10/P81) SCL11/P95 SCK00/P10(SCK00/P55) SO00/P12(SO00/P17) SI00/P11(SI00/P16) SCK01/P43 SO01/P45 SI01/P44 SDA01/P44 SDA11/P96 AV REFP/P20 AVREFM/P21 ANI0/P20 to ANI7/P27 ANI8/P150 to ANI14/P156 VSS, EVSS0, EVSS1 TOOLRxD/P11, TOOLTxD/P12 VDD, EVDD0, EVDD1 SCLA0/P60(SCLA0/P14) SDAA1/P63 SDAA0/P61(SDAA0/P13) RTC1HZ/P30 TxD2/P13(TxD2/P77) SDA20/P14 SDA21/P71 SDA30/P143 SDA31/P53 RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 TOOL0/P40 KR0/P70 to KR7/P77 P140 to P147 P150 to P156 P100 to P106 P121 to P124 P90 to P97 P20 to P27 P10 to P17 P40 to P47 P50 to P57 P00 to P07 P80 to P87 P70 to P77 P60 to P67 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 44 of 200 Jun 30, 2020

1.6 Outline of Functions

[20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin R5F1006x R5F1016x R5F1007x R5F1017x R5F1008x R5F1018x R5F100Ax R5F101Ax R5F100Bx R5F101Bx R5F100Cx R5F101Cx Code flash memory (KB) 16 to 64 16 to 64 16 to 64 16 to 128 16 to 128 16 to 128 Data flash memory (KB) 4 – 4 – 4 – 4 to 8 – 4 to 8 – 4 to 8 – RAM (KB) 2 to 4Note1 2 to 4 Note1 2 to 4 Note1 2 to 12 Note1 2 to 12 Note1 2 to 12 Note1 Address space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (High-speed main) mode: 1 to 20 MHz (V DD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) High-speed on-chip oscillator HS (High-speed main) mode: 1 to 32 MHz (V DD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock – Low-speed on-chip oscillator 15 kHz (TYP.) General-purpose registers (8-bit register × 8) × 4 banks Minimum instruction execution time 0.03125 µs (High-speed on-chip oscillator: f IH = 32 MHz operation) 0.05 µs (High-speed system clock: fMX = 20 MHz operation) Instruction set ● Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 16 20 21 26 28 32 CMOS I/O 13 (N-ch O.D. I/O [VDD withstand voltage]: 5) (N-ch O.D. I/O [VDD withstand voltage]: 6) (N-ch O.D. I/O [VDD withstand voltage]: 6) (N-ch O.D. I/O [VDD withstand voltage]: 9) (N-ch O.D. I/O [VDD withstand voltage]: 9) (N-ch O.D. I/O [VDD withstand voltage]: 10) CMOS input 3 3 3 3 3 3 N-ch O.D. I/O (withstand voltage: 6 V) – 2 2 2 3 3 Timer 16-bit timer 8 channels Watchdog timer 1 channel Real-time clock (RTC) 1 channel Note 2 12-bit interval timer (IT) 1 channel Timer output 3 channels (PWM outputs:

2 Note 3)

(PWM outputs: 3 Note 3) 4 channels (PWM outputs: 3 Note 3), 8 channels (PWM outputs: 7 Note 3) Note 4 RTC output – Notes 1. The flash library uses RAM in self-progra mming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F100xD, R5F101xD (x = 6 to 8, A to C): Start address FF300H R5F100xE, R5F101xE (x = 6 to 8, A to C): Start address FEF00H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944).

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 45 of 200 Jun 30, 2020 Notes 2. Only the constant-period interrupt function when the low-speed on-chip oscillator clock (fIL) is selected 3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves) (see 6.9.3 Operation as multiple PWM output function in the RL78/G13 User’s Manual). 4. When setting to PIOR = 1 (2/2) Item 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin R5F1006x R5F1016x R5F1007x R5F1017x R5F1008x R5F1018x R5F100Ax R5F101Ax R5F100Bx R5F101Bx R5F100Cx R5F101Cx Clock output/buzzer output – 1 1 2 2 2 (Main system clock: f MAIN = 20 MHz operation) 8/10-bit resolution A/D converter 6 channels 6 channels 6 channels 8 channels 8 channels 8 channels Serial interface [20-pin, 24-pin, 25-pin products]

CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel [30-pin, 32-pin products]
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART (UART supporting LIN-bus): 1 channel [36-pin products]
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel I 2C bus – 1 channel 1 channel 1 channel 1 channel 1 channel Multiplier and divider/multiply- accumulator
16 bits × 16 bits = 32 bits (Unsigned or signed)
32 bits ÷ 32 bits = 32 bits (Unsigned)
16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 2 channels Vectored interrupt sources Internal 23 24 24 27 27 27 External 3 5 5 6 6 6 Key interrupt – Reset ● Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit ● Power-on-reset: 1.51 V (TYP.)
Power-down-reset: 1.50 V (TYP.) Voltage detector ● Rising edge : 1.67 V to 4.06 V (14 stages)
Falling edge : 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V (TA = -40 to +85°C) VDD = 2.4 to 5.5 V (TA = -40 to +105°C) Operating ambient temperature T A = 40 to +85°C (A: Consumer applications, D: Industrial applications ) TA = 40 to +105°C (G: Industrial applications) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execut ion not issued by emulati on with the in-circuit emul ator or on-chip debug emulator.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 46 of 200 Jun 30, 2020 [40-pin, 44-pin, 48-pin, 52-pin, 64-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 40-pin 44-pin 48-pin 52-pin 64-pin R5F100Ex R5F101Ex R5F100Fx R5F101Fx R5F100Gx R5F101Gx R5F100Jx R5F101Jx R5F100Lx R5F101Lx Code flash memory (KB) 16 to 192 16 to 512 16 to 512 32 to 512 32 to 512 Data flash memory (KB) 4 to 8 – 4 to 8 – 4 to 8 – 4 to 8 – 4 to 8 – RAM (KB) 2 to 16Note1 2 to 32 Note1 2 to 32 Note1 2 to 32 Note1 2 to 32 Note1 Address space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (High-speed main) mode: 1 to 20 MHz (V DD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (V DD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) High-speed on-chip oscillator HS (High-speed main) mode: 1 to 32 MHz (V DD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (V DD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator 15 kHz (TYP.) General-purpose registers (8-bit register × 8) × 4 banks Minimum instruction execution time 0.03125 µs (High-speed on-chip oscillator: f IH = 32 MHz operation) 0.05 µs (High-speed system clock: fMX = 20 MHz operation) 30.5 µs (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set ● Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 36 40 44 48 58 CMOS I/O 28 (N-ch O.D. I/O [VDD withstand voltage]: 10) (N-ch O.D. I/O [VDD withstand voltage]: 10) (N-ch O.D. I/O [VDD withstand voltage]: 11) (N-ch O.D. I/O [VDD withstand voltage]: 13) (N-ch O.D. I/O [VDD withstand voltage]: 15) CMOS input 5 5 5 5 5 CMOS output – – 1 1 1 N-ch O.D. I/O (withstand voltage: 6 V) 3 4 4 4 4 Timer 16-bit timer 8 channels Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer (IT) 1 channel Timer output 4 channels (PWM outputs: 3 Note 2), 8 channels (PWM outputs: 7 Note 2)Note 3 5 channels (PWM outputs: 4 Note 2), 8 channels (PWM outputs: 7 Note 2) Note 3 8 channels (PWM outputs: 7 Note 2) RTC output 1 channel
1 Hz (subsystem clock: f SUB = 32.768 kHz) Notes 1. The flash library uses RAM in self-progra mming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F100xD, R5F101xD (x = E to G, J, L): Start address FF300H R5F100xE, R5F101xE (x = E to G, J, L): Start address FEF00H R5F100xJ, R5F101xJ (x = F, G, J, L): Start address FAF00H R5F100xL, R5F101xL (x = F, G, J, L): Start address F7F00H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944).

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 47 of 200 Jun 30, 2020 Notes 2. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves) (see 6.9.3 Operation as multiple PWM output function in the RL78/G13 User’s Manual). 3. When setting to PIOR = 1 (2/2) Item 40-pin 44-pin 48-pin 52-pin 64-pin R5F100Ex R5F101Ex R5F100Fx R5F101Fx R5F100Gx R5F101Gx R5F100Jx R5F101Jx R5F100Lx R5F101Lx Clock output/buzzer output 2 2 2 2 2 (Main system clock: f MAIN = 20 MHz operation) (Subsystem clock: f SUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 9 c hannels 10 channels 10 channels 12 channels 12 channels Serial interface [40-pin, 44-pin products]

CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel [48-pin, 52-pin products]
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel [64-pin products]
CSI: 2 channels/simplified I 2C: 2 channels/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel I 2C bus 1 channel 1 channel 1 channel 1 channel 1 channel Multiplier and divider/multiply- accumulator
16 bits × 16 bits = 32 bits (Unsigned or signed)
32 bits ÷ 32 bits = 32 bits (Unsigned)
16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 2 channels Vectored interrupt sources Internal 27 27 27 27 27 External 7 7 10 12 13 Key interrupt 4 4 6 8 8 Reset ● Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit ● Power-on-reset: 1.51 V (TYP.)
Power-down-reset: 1.50 V (TYP.) Voltage detector ● Rising edge : 1.67 V to 4.06 V (14 stages)
Falling edge : 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V (TA = -40 to +85°C) VDD = 2.4 to 5.5 V (TA = -40 to +105°C) Operating ambient temperature TA = 40 to +85°C (A: Consumer applications, D: Industrial applications) TA = 40 to +105°C (G: Industrial applications) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execut ion not issued by emulati on with the in-circuit emul ator or on-chip debug emulator.

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 48 of 200 Jun 30, 2020 [80-pin, 100-pin, 128-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 80-pin 100-pin 128-pin R5F100Mx R5F101Mx R5F100Px R5F101Px R5F100Sx R5F101Sx Code flash memory (KB) 96 to 512 96 to 512 192 to 512 Data flash memory (KB) 8 – 8 – 8 – RAM (KB) 8 to 32 Note 1 8 to 32 Note 1 16 to 32 Note 1 Address space 1 MB Main system clock High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) HS (High-speed main) mode: 1 to 20 MHz (V DD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (V DD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) High-speed on-chip oscillator HS (High-speed main) mode: 1 to 32 MHz (V DD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (V DD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator 15 kHz (TYP.) General-purpose register (8-bit register × 8) × 4 banks Minimum instruction execution time 0.03125 µs (High-speed on-chip oscillator: f IH = 32 MHz operation) 0.05 µs (High-speed system clock: fMX = 20 MHz operation) 30.5 µs (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set ● Data transfer (8/16 bits)

Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 74 92 120 CMOS I/O 64 (N-ch O.D. I/O [EVDD withstand voltage]: 21) (N-ch O.D. I/O [EVDD withstand voltage]: 24) 110 (N-ch O.D. I/O [EVDD withstand voltage]: 25) CMOS input 5 5 5 CMOS output 1 1 1 N-ch O.D. I/O (withstand voltage: 6 V) 4 4 4 Timer 16-bit timer 12 channels 12 channels 16 channels Watchdog timer 1 channel 1 channel 1 channel Real-time clock (RTC) 1 channel 1 channel 1 channel 12-bit interval timer (IT) 1 channel 1 channel 1 channel Timer output 12 channels (PWM outputs: 10 Note 2) 12 channels (PWM outputs: 10 Note 2) 16 channels (PWM outputs: 14 Note 2) RTC output 1 channel
1 Hz (subsystem clock: fSUB = 32.768 kHz) Notes 1. The flash library uses RAM in self-progra mming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F100xJ, R5F101xJ (x = M, P): Start address FAF00H R5F100xL, R5F101xL (x = M, P, S): Start address F7F00H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944).

RL78/G13 1. OUTLINE R01DS0131EJ0350 Rev.3.50 49 of 200 Jun 30, 2020 Notes 2. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves) (see 6.9.3 Operation as multiple PWM output function in the RL78/G13 User’s Manual). (2/2) Item 80-pin 100-pin 128-pin R5F100Mx R5F101Mx R5F100Px R5F101Px R5F100Sx R5F101Sx Clock output/buzzer output 2 2 2 (Main system clock: f MAIN = 20 MHz operation) (Subsystem clock: f SUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 17 channels 20 channels 26 channels Serial interface [80-pin, 100-pin, 128-pin products]

CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel I 2C bus 2 channels 2 channels 2 channels Multiplier and divider/multiply- accumulator
16 bits × 16 bits = 32 bits (Unsigned or signed)
32 bits ÷ 32 bits = 32 bits (Unsigned)
16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 4 channels Vectored interrupt sources Internal 37 37 41 External 13 13 13 Key interrupt 8 8 8 Reset ● Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access Power-on-reset circuit ● Power-on-reset: 1.51 V (TYP.)
Power-down-reset: 1.50 V (TYP.) Voltage detector ● Rising edge : 1.67 V to 4.06 V (14 stages)
Falling edge : 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V (TA = -40 to +85°C) VDD = 2.4 to 5.5 V (TA = -40 to +105°C) Operating ambient temperature T A = 40 to +85°C (A: Consumer applications, D: Industrial applications ) TA = 40 to +105°C (G: Industrial applications) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execut ion not issued by emulati on with the in-circuit emul ator or on-chip debug emulator.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 50 of 200 Jun 30, 2020 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C) This chapter describes the following electrical specifications. Target products A: Consumer applications T A = −40 to +85°C R5F100xxAxx, R5F101xxAxx D: Industrial applications T A = −40 to +85°C R5F100xxDxx, R5F101xxDxx G: Industrial applications when T A = −40 to +105°C products is used in the range of TA = −40 to +85°C R5F100xxGxx Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. With products not provided with an EV DD0, EVDD1, EVSS0, or EV SS1 pin, replace EV DD0 and EV DD1 with VDD, or replace EVSS0 and EVSS1 with VSS. product in the RL78/G13 User’s Manual.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 51 of 200 Jun 30, 2020

2.1 Absolute Maximum Ratings

Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Symbols Conditions Ratings Unit Supply voltage V DD –0.5 to +6.5 V EVDD0, EVDD1 EV DD0 = EVDD1 –0.5 to +6.5 V EVSS0, EVSS1 EV SS0 = EVSS1 –0.5 to +0.3 V REGC pin input voltage V IREGC REGC –0.3 to +2.8 and –0.3 to VDD +0.3Note 1 V Input voltage VI1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 –0.3 to EV DD0 +0.3 and –0.3 to VDD +0.3Note 2 V VI2 P60 to P63 (N-ch open-drain) –0.3 to +6.5 V VI3 P20 to P27, P121 to P124, P137, P150 to P156, EXCLK, EXCLKS, RESET –0.3 to V DD +0.3Note 2 V Output voltage VO1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 –0.3 to EV DD0 +0.3 and –0.3 to VDD +0.3 Note 2 V VO2 P20 to P27, P150 to P156 –0.3 to VDD +0.3 Note 2 V Analog input voltage V AI1 ANI16 to ANI26 –0.3 to EVDD0 +0.3 and –0.3 to AVREF(+) +0.3Notes 2, 3 V VAI2 ANI0 to ANI14 –0.3 to VDD +0.3 and –0.3 to AVREF(+) +0.3Notes 2, 3 V Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 µF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. Do not exceed AV REF (+) + 0.3 V in case of A/D conversion target pin . Caution Product quality may suffer if the absolute maximum ra ting is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alter nate-function pins are the same as those of the port pins. 2. AV REF (+) : + side reference voltage of the A/D converter. 3. V SS : Reference voltage

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 52 of 200 Jun 30, 2020 Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Symbols Conditions Ratings Unit Output current, high I OH1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 –40 mA Total of all pins –170 mA P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 –70 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 –100 mA IOH2 Per pin P20 to P27, P150 to P156 –0.5 mA Total of all pins –2 mA Output current, low I OL1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 40 mA Total of all pins 170 mA P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 70 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 100 mA IOL2 Per pin P20 to P27, P150 to P156 1 mA Total of all pins 5 mA Operating ambient temperature T A In normal operation mode –40 to +85 °C In flash memory programming mode Storage temperature T stg –65 to +150 °C Caution Product quality may suffer if the absolute maximum ra ting is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 53 of 200 Jun 30, 2020

2.2 Oscillator Characteristics

2.2.1 X1, XT1 oscillator characteristics

(TA = –40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit X1 clock oscillation frequency (fX)Note Ceramic resonator/ crystal resonator

2.7 V ≤ V

DD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz 1.8 V ≤ VDD < 2.4 V 1.0 8.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.0 MHz XT1 clock oscillation frequency (f X)Note Crystal resonator 32 32.768 35 kHz Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip osc illator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscilla tion stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the o scillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G13 User’s Manual.

2.2.2 On-chip oscillator characteristics

(TA = –40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Notes 1, 2 fIH 1 32 MHz High-speed on-chip oscillator clock frequency accuracy –20 to +85°C 1.8 V ≤ V Low-speed on-chip oscillator clock frequency f IL 15 kHz Low-speed on-chip oscillator clock frequency accuracy –15 +15 % Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 54 of 200 Jun 30, 2020

2.3 DC Characteristics

2.3.1 Pin characteristics

(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, highNote 1 IOH1 Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147

1.6 V ≤ EV

DD0 ≤ 5.5 V –10.0 Note 2 mA Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V –55.0 mA 2.7 V ≤ EVDD0 < 4.0 V –10.0 mA 1.8 V ≤ EVDD0 < 2.7 V –5.0 mA 1.6 V ≤ EVDD0 < 1.8 V –2.5 mA Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V –80.0 mA 2.7 V ≤ EVDD0 < 4.0 V –19.0 mA 1.8 V ≤ EVDD0 < 2.7 V –10.0 mA 1.6 V ≤ EVDD0 < 1.8 V –5.0 mA Total of all pins (When duty ≤ 70% Note 3) 1.6 V ≤ EVDD0 ≤ 5.5 V –135.0 Note 4 mA IOH2 Per pin for P20 to P27, P150 to P156 1.6 V ≤ VDD ≤ 5.5 V –0.1 Note 2 mA Total of all pins (When duty ≤ 70% Note 3) 1.6 V ≤ VDD ≤ 5.5 V –1.5 mA Notes 1 . Value of current at which the device operation is guaranteed even if the current flows from the EV DD0, EVDD1, VDD pins to an output pin. 2. However, do not exceed the total current value. 3. Specification under conditi ons where the duty factor ≤ 70%. The output current value that has ch anged to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 80% and I OH = –10.0 mA Total output current of pins = (–10.0 × 0.7)/(80 × 0.01)  –8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. 4. The applied current for the products for indu strial application (R5F100xxDxx, R5F101xxDxx, R5F100xxGxx) is –100 mA. Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P 50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 55 of 200 Jun 30, 2020 (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, lowNote 1 IOL1 Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 20.0 Note 2 mA Per pin for P60 to P63 15.0 Note 2 mA Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V 70.0 mA 2.7 V ≤ EVDD0 < 4.0 V 15.0 mA 1.8 V ≤ EVDD0 < 2.7 V 9.0 mA 1.6 V ≤ EVDD0 < 1.8 V 4.5 mA Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V 80.0 mA 2.7 V ≤ EVDD0 < 4.0 V 35.0 mA 1.8 V ≤ EVDD0 < 2.7 V 20.0 mA 1.6 V ≤ EVDD0 < 1.8 V 10.0 mA Total of all pins (When duty ≤ 70% Note 3) 150.0 mA IOL2 Per pin for P20 to P27, P150 to P156 0.4 Note 2 mA Total of all pins (When duty ≤ 70% Note 3) 1.6 V ≤ VDD ≤ 5.5 V 5.0 mA Notes 1 . Value of current at which the devic e operation is guaranteed even if the current flows from an output pin to the EVSS0, EVSS1 and VSS pin. 2. However, do not exceed the total current value. 3. Specification under conditi ons where the duty factor ≤ 70%. The output current value that has ch anged to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 56 of 200 Jun 30, 2020 (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high VIH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 Normal input buffer 0.8EV DD0 EV DD0 V VIH2 P01, P03, P04, P10, P11, P13 to P17, P43, P44, P53 to P55, P80, P81, P142, P143 TTL input buffer

4.0 V ≤ EV

DD0 ≤ 5.5 V

2.2 EV DD0 V

3.3 V ≤ EV

DD0 < 4.0 V

2.0 EV DD0 V

DD0 < 3.3 V

1.5 EV DD0 V

VIH3 P20 to P27, P150 to P156 0.7VDD V DD V VIH4 P60 to P63 0.7EVDD0 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD V DD V Input voltage, low V IL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 Normal input buffer 0 0.2EV DD0 V VIL2 P01, P03, P04, P10, P11, P13 to P17, P43, P44, P53 to P55, P80, P81, P142, P143 TTL input buffer DD0 ≤ 5.5 V 0 0.8 V TTL input buffer DD0 < 4.0 V 0 0.5 V TTL input buffer DD0 < 3.3 V 0 0.32 V VIL3 P20 to P27, P150 to P156 0 0.3V DD V VIL4 P60 to P63 0 0.3EV DD0 V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2V DD V Caution The maximum value of V IH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 57 of 200 Jun 30, 2020 (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high VOH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD0 ≤ 5.5 V, IOH1 = –10.0 mA EVDD0 – 1.5 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOH1 = –3.0 mA EVDD0 – 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH1 = –2.0 mA EVDD0 – 0.6 V 1.8 V ≤ EVDD0 ≤ 5.5 V, IOH1 = –1.5 mA EVDD0 – 0.5 V 1.6 V ≤ EVDD0 < 5.5 V, IOH1 = –1.0 mA EVDD0 – 0.5 V VOH2 P20 to P27, P150 to P156 1.6 V ≤ VDD ≤ 5.5 V, IOH2 = –100 µA VDD – 0.5 V Output voltage, low V OL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 20 mA 1.3 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 8.5 mA 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 3.0 mA 0.6 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 1.5 mA 0.4 V 1.8 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 0.6 mA 0.4 V 1.6 V ≤ EVDD0 < 5.5 V, IOL1 = 0.3 mA 0.4 V VOL2 P20 to P27, P150 to P156 1.6 V ≤ VDD ≤ 5.5 V, IOL2 = 400 µA 0.4 V VOL3 P60 to P63 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 5.0 mA 0.4 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 3.0 mA 0.4 V 1.8 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 2.0 mA 0.4 V 1.6 V ≤ EVDD0 < 5.5 V, IOL3 = 1.0 mA 0.4 V Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P 50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 58 of 200 Jun 30, 2020 (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 V I = EVDD0 1 µA ILIH2 P20 to P27, P137, P150 to P156, RESET V I = VDD 1 µA ILIH3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) V I = VDD In input port or external clock input 1 µA In resonator connection 10 µA Input leakage current, low I LIL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 V I = EVSS0 –1 µA ILIL2 P20 to P27, P137, P150 to P156, RESET VI = VSS –1 µA ILIL3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) V I = VSS In input port or external clock input –1 µA In resonator connection –10 µA On-chip pll-up resistance R U P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 V I = EVSS0, In input port 10 20 100 k Ω Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 59 of 200 Jun 30, 2020

2.3.2 Supply current characteristics

(1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = –40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode HS (high- speed main) mode Note 5 fIH = 32 MHz Note 3 Basic operation VDD = 5.0 V 2.1 mA VDD = 3.0 V 2.1 mA Normal operation VDD = 5.0 V 4.6 7.0 mA VDD = 3.0 V 4.6 7.0 mA fIH = 24 MHz Note 3 Normal operation VDD = 5.0 V 3.7 5.5 mA VDD = 3.0 V 3.7 5.5 mA fIH = 16 MHz Note 3 Normal operation VDD = 5.0 V 2.7 4.0 mA VDD = 3.0 V 2.7 4.0 mA LS (low- speed main) mode Note 5 fIH = 8 MHz Note 3 Normal operation VDD = 3.0 V 1.2 1.8 mA VDD = 2.0 V 1.2 1.8 mA LV (low- voltage main) mode Note 5 fIH = 4 MHz Note 3 Normal operation VDD = 3.0 V 1.2 1.7 mA VDD = 2.0 V 1.2 1.7 mA HS (high- speed main) mode Note 5 fMX = 20 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 3.0 4.6 mA Resonator connection 3.2 4.8 mA fMX = 20 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 3.0 4.6 mA Resonator connection 3.2 4.8 mA fMX = 10 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 1.9 2.7 mA Resonator connection 1.9 2.7 mA fMX = 10 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 1.9 2.7 mA Resonator connection 1.9 2.7 mA LS (low- speed main) mode Note 5 fMX = 8 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 mA fMX = 8 MHzNote 2, VDD = 2.0 V Normal operation Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 mA Subsystem clock operation f SUB = 32.768 kHz Note 4 TA = –40°C Normal operation Square wave input 4.1 4.9 µA Resonator connection 4.2 5.0 µA fSUB = 32.768 kHz Note 4 TA = +25°C Normal operation Square wave input 4.1 4.9 µA Resonator connection 4.2 5.0 µA fSUB = 32.768 kHz Note 4 TA = +50°C Normal operation Square wave input 4.2 5.5 µA Resonator connection 4.3 5.6 µA fSUB = 32.768 kHz Note 4 TA = +70°C Normal operation Square wave input 4.3 6.3 µA Resonator connection 4.4 6.4 µA fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation Square wave input 4.6 7.7 µA Resonator connection 4.7 7.8 µA (Notes and Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 60 of 200 Jun 30, 2020 Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 5. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temper ature condition of the TYP. value is TA = 25°C

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 61 of 200 Jun 30, 2020 (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = –40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode HS (high- speed main) mode Note 7 fIH = 32 MHz Note 4 V DD = 5.0 V 0.54 1.63 mA VDD = 3.0 V 0.54 1.63 mA fIH = 24 MHz Note 4 V DD = 5.0 V 0.44 1.28 mA VDD = 3.0 V 0.44 1.28 mA fIH = 16 MHz Note 4 V DD = 5.0 V 0.40 1.00 mA VDD = 3.0 V 0.40 1.00 mA LS (low- speed main) mode Note 7 fIH = 8 MHz Note 4 V DD = 3.0 V 260 530 µA VDD = 2.0 V 260 530 µA LV (low- voltage main) mode Note 7 fIH = 4 MHz Note 4 V DD = 3.0 V 420 640 µA VDD = 2.0 V 420 640 µA HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 0.28 1.00 mA Resonator connection 0.45 1.17 mA fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 0.28 1.00 mA Resonator connection 0.45 1.17 mA fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 0.19 0.60 mA Resonator connection 0.26 0.67 mA fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 0.19 0.60 mA Resonator connection 0.26 0.67 mA LS (low-speed main) mode Note 7 fMX = 8 MHzNote 3, VDD = 3.0 V Square wave input 95 330 µA Resonator connection 145 380 µA fMX = 8 MHzNote 3, VDD = 2.0 V Square wave input 95 330 µA Resonator connection 145 380 µA Subsystem clock operation f SUB = 32.768 kHzNote 5 TA = –40°C Square wave input 0.25 0.57 µA Resonator connection 0.44 0.76 µA fSUB = 32.768 kHzNote 5 TA = +25°C Square wave input 0.30 0.57 µA Resonator connection 0.49 0.76 µA fSUB = 32.768 kHzNote 5 TA = +50°C Square wave input 0.37 1.17 µA Resonator connection 0.56 1.36 µA fSUB = 32.768 kHzNote 5 TA = +70°C Square wave input 0.53 1.97 µA Resonator connection 0.72 2.16 µA fSUB = 32.768 kHzNote 5 TA = +85°C Square wave input 0.82 3.37 µA Resonator connection 1.01 3.56 µA IDD3Note 6 STOP mode Note 8 TA = –40°C 0.18 0.50 µA TA = +25°C 0.23 0.50 µA TA = +50°C 0.30 1.10 µA TA = +70°C 0.46 1.90 µA TA = +85°C 0.75 3.30 µA (Notes and Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 62 of 200 Jun 30, 2020 Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RT C, 12-bit interval timer, and watchdog timer. 7. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 63 of 200 Jun 30, 2020 (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode HS (high- speed main) mode Note 5 fIH = 32 MHz Note 3 Basic operation VDD = 5.0 V 2.3 mA VDD = 3.0 V 2.3 mA Normal operation VDD = 5.0 V 5.2 8.5 mA VDD = 3.0 V 5.2 8.5 mA fIH = 24 MHz Note 3 Normal operation VDD = 5.0 V 4.1 6.6 mA VDD = 3.0 V 4.1 6.6 mA fIH = 16 MHz Note 3 Normal operation VDD = 5.0 V 3.0 4.7 mA VDD = 3.0 V 3.0 4.7 mA LS (low- speed main) mode Note 5 fIH = 8 MHz Note 3 Normal operation VDD = 3.0 V 1.3 2.1 mA VDD = 2.0 V 1.3 2.1 mA LV (low- voltage main) mode Note 5 fIH = 4 MHz Note 3 Normal operation VDD = 3.0 V 1.3 1.8 mA VDD = 2.0 V 1.3 1.8 mA HS (high- speed main) mode Note 5 fMX = 20 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 3.4 5.5 mA Resonator connection 3.6 5.7 mA fMX = 20 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 3.4 5.5 mA Resonator connection 3.6 5.7 mA fMX = 10 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 2.1 3.2 mA Resonator connection 2.1 3.2 mA fMX = 10 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 2.1 3.2 mA Resonator connection 2.1 3.2 mA LS (low- speed main) mode Note 5 fMX = 8 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 1.2 2.0 mA Resonator connection 1.2 2.0 mA fMX = 8 MHzNote 2, VDD = 2.0 V Normal operation Square wave input 1.2 2.0 mA Resonator connection 1.2 2.0 mA Subsystem clock operation f SUB = 32.768 kHz Note 4 TA = –40°C Normal operation Square wave input 4.8 5.9 µA Resonator connection 4.9 6.0 µA fSUB = 32.768 kHz Note 4 TA = +25°C Normal operation Square wave input 4.9 5.9 µA Resonator connection 5.0 6.0 µA fSUB = 32.768 kHz Note 4 TA = +50°C Normal operation Square wave input 5.0 7.6 µA Resonator connection 5.1 7.7 µA fSUB = 32.768 kHz Note 4 TA = +70°C Normal operation Square wave input 5.2 9.3 µA Resonator connection 5.3 9.4 µA fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation Square wave input 5.7 13.3 µA Resonator connection 5.8 13.4 µA (Notes and Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 64 of 200 Jun 30, 2020 Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the 12-bit interval timer and watchdog timer. 5. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temper ature condition of the TYP. value is TA = 25°C

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 65 of 200 Jun 30, 2020 (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) (Notes and Remarks are listed on the next page.) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode HS (high- speed main) mode Note 7 fIH = 32 MHz Note 4 V DD = 5.0 V 0.62 1.86 mA VDD = 3.0 V 0.62 1.86 mA fIH = 24 MHz Note 4 V DD = 5.0 V 0.50 1.45 mA VDD = 3.0 V 0.50 1.45 mA fIH = 16 MHz Note 4 V DD = 5.0 V 0.44 1.11 mA VDD = 3.0 V 0.44 1.11 mA LS (low-speed main) mode Note 7 fIH = 8 MHz Note 4 V DD = 3.0 V 290 620 µA VDD = 2.0 V 290 620 µA LV (low- voltage main) mode Note 7 fIH = 4 MHz Note 4 V DD = 3.0 V 440 680 µA VDD = 2.0 V 440 680 µA HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 0.31 1.08 mA Resonator connection 0.48 1.28 mA fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 0.31 1.08 mA Resonator connection 0.48 1.28 mA fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 0.21 0.63 mA Resonator connection 0.28 0.71 mA fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 0.21 0.63 mA Resonator connection 0.28 0.71 mA LS (low-speed main) mode Note 7 fMX = 8 MHzNote 3, VDD = 3.0 V Square wave input 110 360 µA Resonator connection 160 420 µA fMX = 8 MHzNote 3, VDD = 2.0 V Square wave input 110 360 µA Resonator connection 160 420 µA Subsystem clock operation f SUB = 32.768 kHzNote 5 TA = –40°C Square wave input 0.28 0.61 µA Resonator connection 0.47 0.80 µA fSUB = 32.768 kHzNote 5 TA = +25°C Square wave input 0.34 0.61 µA Resonator connection 0.53 0.80 µA fSUB = 32.768 kHzNote 5 TA = +50°C Square wave input 0.41 2.30 µA Resonator connection 0.60 2.49 µA fSUB = 32.768 kHzNote 5 TA = +70°C Square wave input 0.64 4.03 µA Resonator connection 0.83 4.22 µA fSUB = 32.768 kHzNote 5 TA = +85°C Square wave input 1.09 8.04 µA Resonator connection 1.28 8.23 µA IDD3Note 6 STOP mode Note 8 TA = –40°C 0.19 0.52 µA TA = +25°C 0.25 0.52 µA TA = +50°C 0.32 2.21 µA TA = +70°C 0.55 3.94 µA TA = +85°C 1.00 7.95 µA

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 66 of 200 Jun 30, 2020 Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current . However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed syst em clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RT C, 12-bit interval timer, and watchdog timer. 7. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 67 of 200 Jun 30, 2020 (3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode HS (high- speed main) mode Note 5 fIH = 32 MHz Note 3 Basic operation VDD = 5.0 V 2.6 mA VDD = 3.0 V 2.6 mA Normal operation VDD = 5.0 V 6.1 9.5 mA VDD = 3.0 V 6.1 9.5 mA fIH = 24 MHz Note 3 Normal operation VDD = 5.0 V 4.8 7.4 mA VDD = 3.0 V 4.8 7.4 mA fIH = 16 MHz Note 3 Normal operation VDD = 5.0 V 3.5 5.3 mA VDD = 3.0 V 3.5 5.3 mA LS (low- speed main) mode Note 5 fIH = 8 MHz Note 3 Normal operation VDD = 3.0 V 1.5 2.3 mA VDD = 2.0 V 1.5 2.3 mA LV (low- voltage main) mode Note 5 fIH = 4 MHz Note 3 Normal operation VDD = 3.0 V 1.5 2.0 mA VDD = 2.0 V 1.5 2.0 mA HS (high- speed main) mode Note 5 fMX = 20 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 3.9 6.1 mA Resonator connection 4.1 6.3 mA fMX = 20 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 3.9 6.1 mA Resonator connection 4.1 6.3 mA fMX = 10 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 2.5 3.7 mA Resonator connection 2.5 3.7 mA fMX = 10 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 2.5 3.7 mA Resonator connection 2.5 3.7 mA LS (low- speed main) mode Note 5 fMX = 8 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 1.4 2.2 mA Resonator connection 1.4 2.2 mA fMX = 8 MHzNote 2, VDD = 2.0 V Normal operation Square wave input 1.4 2.2 mA Resonator connection 1.4 2.2 mA Subsystem clock operation f SUB = 32.768 kHz Note 4 TA = –40°C Normal operation Square wave input 5.4 6.5 µA Resonator connection 5.5 6.6 µA fSUB = 32.768 kHz Note 4 TA = +25°C Normal operation Square wave input 5.5 6.5 µA Resonator connection 5.6 6.6 µA fSUB = 32.768 kHz Note 4 TA = +50°C Normal operation Square wave input 5.6 9.4 µA Resonator connection 5.7 9.5 µA fSUB = 32.768 kHz Note 4 TA = +70°C Normal operation Square wave input 5.9 12.0 µA Resonator connection 6.0 12.1 µA fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation Square wave input 6.6 16.3 µA Resonator connection 6.7 16.4 µA (Notes and Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 68 of 200 Jun 30, 2020 Notes 1. Total current flowing into V DD, EVDD0, and EV DD1, including the input leakage current flowing when the level of the input pin is fixed to V DD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing in to the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 5. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V @1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temper ature condition of the TYP. value is TA = 25°C

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 69 of 200 Jun 30, 2020 (3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) (Notes and Remarks are listed on the next page.) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode HS (high- speed main) mode Note 7 fIH = 32 MHz Note 4 V DD = 5.0 V 0.62 1.89 mA VDD = 3.0 V 0.62 1.89 mA fIH = 24 MHz Note 4 VDD = 5.0 V 0.50 1.48 mA VDD = 3.0 V 0.50 1.48 mA fIH = 16 MHz Note 4 V DD = 5.0 V 0.44 1.12 mA VDD = 3.0 V 0.44 1.12 mA LS (low-speed main) mode Note 7 fIH = 8 MHz Note 4 V DD = 3.0 V 290 620 µA VDD = 2.0 V 290 620 µA LV (low- voltage main) mode Note 7 fIH = 4 MHz Note 4 V DD = 3.0 V 460 700 µA VDD = 2.0 V 460 700 µA HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 0.31 1.14 mA Resonator connection 0.48 1.34 mA fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 0.31 1.14 mA Resonator connection 0.48 1.34 mA fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 0.21 0.68 mA Resonator connection 0.28 0.76 mA fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 0.21 0.68 mA Resonator connection 0.28 0.76 mA LS (low-speed main) mode Note 7 fMX = 8 MHzNote 3, VDD = 3.0 V Square wave input 110 390 µA Resonator connection 160 450 µA fMX = 8 MHzNote 3, VDD = 2.0 V Square wave input 110 390 µA Resonator connection 160 450 µA Subsystem clock operation f SUB = 32.768 kHzNote 5 TA = –40°C Square wave input 0.31 0.66 µA Resonator connection 0.50 0.85 µA fSUB = 32.768 kHzNote 5 TA = +25°C Square wave input 0.38 0.66 µA Resonator connection 0.57 0.85 µA fSUB = 32.768 kHzNote 5 TA = +50°C Square wave input 0.47 3.49 µA Resonator connection 0.66 3.68 µA fSUB = 32.768 kHzNote 5 TA = +70°C Square wave input 0.80 6.10 µA Resonator connection 0.99 6.29 µA fSUB = 32.768 kHzNote 5 TA = +85°C Square wave input 1.52 10.46 µA Resonator connection 1.71 10.65 µA IDD3Note 6 STOP mode Note 8 TA = –40°C 0.19 0.54 µA TA = +25°C 0.26 0.54 µA TA = +50°C 0.35 3.37 µA TA = +70°C 0.68 5.98 µA TA = +85°C 1.40 10.34 µA

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 70 of 200 Jun 30, 2020 Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current . However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RT C, 12-bit interval timer, and watchdog timer. 7. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V @1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 71 of 200 Jun 30, 2020 (4) Peripheral Functions (Common to all products) (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on- chip oscillator operating current I FILNote 1 0.20 µA RTC operating current I RTC Notes 1, 2, 3 0.02 µA 12-bit interval timer operating current I IT Notes 1, 2, 4 0.02 µA Watchdog timer operating current I WDT Notes 1, 2, 5 fIL = 15 kHz 0.22 µA A/D converter operating current IADC Notes 1, 6 When conversion at maximum speed Normal mode, AV REFP = VDD = 5.0 V 1.3 1.7 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA A/D converter reference voltage current IADREF Note 1 75.0 µA Temperature sensor operating current ITMPS Note 1 75.0 µA LVD operating current ILVI Notes 1, 7 0.08 µA Self- programming operating current I FSP Notes 1, 9 2.50 12.20 mA BGO operating current I BGO Notes 1, 8 2.50 12.20 mA SNOOZE operating current I SNOZ Note 1 ADC operation The mode is performed Note 10 0.50 0.60 mA The A/D conversion operations are performed, Low voltage mode, AV REFP = VDD = 3.0 V 1.20 1.44 mA CSI/UART operation 0.70 0.84 mA Notes 1. Current flowing to V DD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcont rollers is the sum of the values of either IDD1 or I DD2, and I RTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, I FIL should be added. I DD2 subsystem clock operation includes the operational current of the real-time clock. 4. Current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcont rollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including t he operating current of the low-speed on-chip oscillator). The supply current of the RL78 mi crocontrollers is the sum of I DD1, IDD2 or I DD3 and I WDT when the watchdog timer is in operation. 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 72 of 200 Jun 30, 2020 Notes 7. Current flowing only to the LVD circuit. The supply cu rrent of the RL78 microcontrollers is the sum of I DD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10. For shift time to the SNOOZE mode, see 18.3.3 SNOOZE mode in the RL78/G13 User’s Manual. Remarks 1. f IL: Low-speed on-chip oscillator clock frequency 2. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. f CLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is T A = 25°C

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 73 of 200 Jun 30, 2020

2.4 AC Characteristics

(TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY Main system clock (f MAIN) operation HS (high-speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.03125 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs LS (low-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 0.125 1 µs LV (low-voltage main) mode 1.6 V ≤ VDD ≤ 5.5 V 0.25 1 µs Subsystem clock (fSUB) operation In the self programming mode HS (high-speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.03125 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs LS (low-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 0.125 1 µs LV (low-voltage main) mode 1.8 V ≤ VDD ≤ 5.5 V 0.25 1 µs External system clock frequency f EX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz 1.8 V ≤ VDD < 2.4 V 1.0 8.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.0 MHz fEXS 32 35 kHz External system clock input high- level width, low-level width tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns 2.4 V ≤ VDD < 2.7 V 30 ns 1.8 V ≤ VDD < 2.4 V 60 ns 1.6 V ≤ VDD < 1.8 V 120 ns tEXHS, tEXLS 13.7 µs TI00 to TI07, TI10 to TI17 input high-level width, low-level width t TIH, tTIL 1/f MCK+10 ns Note TO00 to TO07, TO10 to TO17 output frequency f TO HS (high-speed main) mode 4.0 V ≤ EVDD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz 1.8 V ≤ EVDD0 < 2.7 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz LS (low-speed main) mode 1.8 V ≤ EVDD0 ≤ 5.5 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz LV (low-voltage main) mode DD0 ≤ 5.5 V 2 MHz PCLBUZ0, PCLBUZ1 output frequency f PCL HS (high-speed main) mode DD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz 1.8 V ≤ EVDD0 < 2.7 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz LS (low-speed main) mode

1.8 V ≤ EV

DD0 ≤ 5.5 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz LV (low-voltage main) mode DD0 ≤ 5.5 V 4 MHz 1.6 V ≤ EVDD0 < 1.8 V 2 MHz Interrupt input high-level width, low-level width t INTH, tINTL INTP0 1.6 V ≤ VDD ≤ 5.5 V 1 µs INTP1 to INTP11 1.6 V ≤ EVDD0 ≤ 5.5 V 1 µs Key interrupt input low-level width t KR KR0 to KR7 1.8 V ≤ EV DD0 ≤ 5.5 V 250 ns 1.6 V ≤ EVDD0 < 1.8 V 1 µs RESET low-level width tRSL 10 µs (Note and Remark are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 74 of 200 Jun 30, 2020 Note The following conditions are required for low voltage interface when EVDD0 < VDD 1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns 1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns Remark f MCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 1.0 0.1 2.7 0.01 2.4 0.03125 0.0625 0.05 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected Cycle time TCY [µs] Supply voltage VDD [V]

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 75 of 200 Jun 30, 2020 TCY vs VDD (LS (low-speed main) mode) 1.0 0.1 0.01 1.8 0.125Cycle time TCY [µs] Supply voltage VDD [V] When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected TCY vs VDD (LV (low-voltage main) mode) 1.0 0.1 0.01 1.8 0.25 1.6 Cycle time TCY [µs] Supply voltage VDD [V] When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 76 of 200 Jun 30, 2020 AC Timing Test Points VIH/VOH VIL/VOL Test points VIH/VOH VIL/VOL External System Clock Timing EXCLK/EXCLKS 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS TI/TO Timing TI00 to TI07, TI10 to TI17 tTIL tTIH TO00 to TO07, TO10 to TO17 1/fTO Interrupt Request Input Timing INTP0 to INTP11 tINTL tINTH Key Interrupt Input Timing KR0 to KR7 tKR RESET Input Timing RESET tRSL

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 77 of 200 Jun 30, 2020

2.5 Peripheral Functions Characteristics

2.5.1 Serial array unit

(1) During communication at same potential (UART mode) A = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit Transfer rate Note 1 2.4 V ≤ EVDD0 ≤ 5.5 V f MCK/6 Note 2 f MCK/6 f MCK/6 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 3 5.3 1.3 0.6 Mbps 1.8 V ≤ EVDD0 ≤ 5.5 V f MCK/6 Note 2 f MCK/6 f MCK/6 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 3 5.3 1.3 0.6 Mbps 1.7 V ≤ EVDD0 ≤ 5.5 V fMCK/6 Note 2 fMCK/6 Note 2 fMCK/6 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 3 5.3 1.3 0.6 Mbps 1.6 V ≤ EVDD0 ≤ 5.5 V – f MCK/6 Note 2 f MCK/6 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 3 – 1.3 0.6 Mbps Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The following conditions are required for low voltage interface when E VDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V ≤ EVDD0 < 1.8 V : MAX. 0.6 Mbps 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) Caution Select the normal input buffer for the RxDq pi n and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg).

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 78 of 200 Jun 30, 2020 UART mode connection diagram (during communication at same potential) RL78 microcontroller TxDq RxDq Rx Tx User device UART mode bit width (during communication at same potential) (reference) Baud rate error tolerance High-/Low-bit width 1/Transfer rate TxDq RxDq Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 79 of 200 Jun 30, 2020 (2) During communication at same pot ential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (T A = –40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCKp cycle time tKCY1 t KCY1 ≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V 62.5 250 500 ns 2.7 V ≤ EVDD0 ≤ 5.5 V 83.3 250 500 ns SCKp high-/low-level width tKH1, tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – t KCY1/2 – t KCY1/2 – ns 2.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – t KCY1/2 – t KCY1/2 – ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 23 110 110 ns 2.7 V ≤ EVDD0 ≤ 5.5 V 33 110 110 ns SIp hold time (from SCKp↑) Note 2 tKSI1 2.7 V ≤ EVDD0 ≤ 5.5 V 10 10 10 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 20 pF Note 4 10 10 10 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPm n = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. This value is valid only when CSI00’s pe ripheral I/O redirect function is not used. 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) 3. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00))

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 80 of 200 Jun 30, 2020 (3) During communication at same pot ential (CSI mode) (master mode, SCKp... internal clock output) (T A = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPm n = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCKp cycle time t KCY1 t KCY1 ≥ 4/fCLK 2.7 V ≤ EVDD0 ≤ 5.5 V 125 500 1000 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 250 500 1000 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 500 500 1000 ns 1.7 V ≤ EVDD0 ≤ 5.5 V 1000 1000 1000 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – 1000 1000 ns SCKp high-/low-level width tKH1, tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – t KCY1/2 – t KCY1/2 – ns 2.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – tKCY1/2 – tKCY1/2 – ns 2.4 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – t KCY1/2 – t KCY1/2 – ns 1.8 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – t KCY1/2 – t KCY1/2 – ns 1.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – 100 tKCY1/2 – 100 tKCY1/2 – 100 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – t KCY1/2 – 100 t KCY1/2 – 100 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 44 110 110 ns 2.7 V ≤ EVDD0 ≤ 5.5 V 44 110 110 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 75 110 110 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 110 110 110 ns 1.7 V ≤ EVDD0 ≤ 5.5 V 220 220 220 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – 220 220 ns SIp hold time (from SCKp↑) Note 2 tKSI1 1.7 V ≤ EVDD0 ≤ 5.5 V 19 19 19 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – 19 19 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 1.7 V ≤ EVDD0 ≤ 5.5 V C = 30 pFNote 4 25 25 25 ns 1.6 V ≤ EVDD0 ≤ 5.5 V C = 30 pFNote 4 – 25 25 ns

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 81 of 200 Jun 30, 2020 Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (1/2) (T A = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCKp cycle time Note 5 tKCY2 4.0 V ≤ EVDD0 ≤ 5.5 V 20 MHz < f MCK 8/f MCK – – ns fMCK ≤ 20 MHz 6/f MCK 6/f MCK 6/f MCK ns 2.7 V ≤ EVDD0 ≤ 5.5 V 16 MHz < f MCK 8/f MCK – – ns fMCK ≤ 16 MHz 6/f MCK 6/f MCK 6/f MCK ns 2.4 V ≤ EVDD0 ≤ 5.5 V 6/fMCK and 500 6/fMCK and 500 6/fMCK and 500 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 6/f MCK and 750 6/f MCK and 750 6/f MCK and 750 ns 1.7 V ≤ EVDD0 ≤ 5.5 V 6/f MCK and 1500 6/f MCK and 1500 6/f MCK and 1500 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – 6/fMCK and 1500 6/fMCK and 1500 ns SCKp high-/low- level width t KH2, tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V t KCY2/2 – 7 t KCY2/2 – 7 t KCY2/2 – 7 ns 2.7 V ≤ EVDD0 ≤ 5.5 V t KCY2/2 – 8 t KCY2/2 – 8 t KCY2/2 – 8 ns 1.8 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 – tKCY2/2 – 18 tKCY2/2 – 18 ns 1.7 V ≤ EVDD0 ≤ 5.5 V t KCY2/2 – t KCY2/2 – 66 t KCY2/2 – 66 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – t KCY2/2 – 66 t KCY2/2 – 66 ns (Notes, Caution, and Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 82 of 200 Jun 30, 2020 (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (2/2) (T A = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V ≤ EVDD0 ≤ 5.5 V 1/f MCK+20 1/f MCK+30 1/f MCK+30 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 1/f MCK+30 1/f MCK+30 1/f MCK+30 ns 1.7 V ≤ EVDD0 ≤ 5.5 V 1/f MCK+40 1/f MCK+40 1/f MCK+40 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – 1/f MCK+40 1/f MCK+40 ns SIp hold time (from SCKp↑) Note 2 tKSI2 1.8 V ≤ EVDD0 ≤ 5.5 V 1/f MCK+31 1/f MCK+31 1/f MCK+31 ns 1.7 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+ 250 1/fMCK+ 250 1/fMCK+ 250 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – 1/f MCK+ 250 1/f MCK+ 250 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ EVDD0 ≤ 5.5 V 2/f MCK+ 2/f MCK+ 110 2/f MCK+ 110 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 2/fMCK+ 2/fMCK+ 110 2/fMCK+ 110 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 2/f MCK+ 110 2/f MCK+ 110 2/f MCK+ 110 ns 1.7 V ≤ EVDD0 ≤ 5.5 V 2/f MCK+ 220 2/f MCK+ 220 2/f MCK+ 220 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – 2/fMCK+ 220 2/fMCK+ 220 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPm n = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of seri al mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 83 of 200 Jun 30, 2020 CSI mode connection diagram (during communication at same potential) RL78 microcontroller SCKp SOp SCK SI User deviceSIp SO CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) SIp Input data Output dataSOp tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) SIp Input data Output dataSOp tKCY1, 2 tKH1, 2 tKL1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 84 of 200 Jun 30, 2020 (5) During communication at same potential (simplified I 2C mode) (1/2) (T A = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCLr clock frequency f SCL 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 400 Note 1 400 Note 1 kHz 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 400 Note 1 400 Note 1 400 Note 1 kHz 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 300 Note 1 300 Note 1 300 Note 1 kHz 1.7 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 250 Note 1 250 Note 1 250 Note 1 kHz 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ – 250 Note 1 250 Note 1 kHz Hold time when SCLr = “L” t LOW 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 1150 1150 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 1150 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 1550 ns 1.7 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 1850 1850 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ – 1850 1850 ns Hold time when SCLr = “H” t HIGH 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 1150 1150 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1150 1150 1150 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1550 1550 1550 ns 1.7 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1850 1850 1850 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ – 1850 1850 ns (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 85 of 200 Jun 30, 2020 (5) During communication at same potential (simplified I 2C mode) (2/2) (T A = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit Data setup time (reception) t SU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK +

85 Note2

+ 145 Note2 1/fMCK + 145 Note2 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 145 Note2 1/fMCK + 145 Note2 1/fMCK + 145 Note2 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 230 Note2 1/fMCK + 230 Note2 1/fMCK + 230 Note2 ns 1.7 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 1/fMCK + 290 Note2 1/fMCK + 290 Note2 1/fMCK + 290 Note2 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ – 1/fMCK + 290 Note2 1/fMCK + 290 Note2 ns Data hold time (transmission) t HD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns 1.7 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 0 405 0 405 0 405 ns 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ – 0 405 0 405 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the normal input buffer and the N-ch open drain output (V DD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode re gister g (PIMg) and port output mode register h (POMh). (Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 86 of 200 Jun 30, 2020 Simplified I2C mode mode connection diagram (during communication at same potential) RL78 microcontroller SDAr SCLr User device SDA SCL VDD Rb Simplified I2C mode serial transfer timing (during communication at same potential) SDAr tLOW tHIGH tHD:DAT SCLr tSU:DAT 1/fSCL Remarks 1. R b[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14), h: POM number (g = 0, 1, 4, 5, 7 to 9, 14) 3. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 87 of 200 Jun 30, 2020 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (T A = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit Transfer rate Recep- tion 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fMCK/6 Note 1 f MCK/6 Note 1 f MCK/6 Note 1 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 4 5.3 1.3 0.6 Mbps 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 4 5.3 1.3 0.6 Mbps 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V fMCK/6 Notes 1 to 3 f MCK/6 Notes 1, 2 f MCK/6 Notes 1, 2 bps Theoretical value of the maximum transfer rate f MCK = fCLK Note 4 5.3 1.3 0.6 Mbps Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. Use it with EVDD0 ≥ Vb. 3. The following conditions are required for low voltage interface when E VDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps 4. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. V b[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 88 of 200 Jun 30, 2020 (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (T A = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high- speed main) Mode LS (low-speed main) Mode LV (low- voltage main) Mode Unit Transfer rate Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 1 Note 1 Note 1 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.8 Note 2 2.8 Note 2 2.8 Note 2 Mbps 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Note 3 Note 3 Note 3 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.2 Note 4 1.2 Note 4 1.2 Note 4 Mbps 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Notes 5, 6 Notes 5, 6 Notes 5, 6 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V 0.43 Note 7 0.43 Note 7 0.43 Note 7 Mbps Notes 1. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ EVDD0 ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Maximum transfer rate = 1 [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 2.2 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the condit ions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 89 of 200 Jun 30, 2020 Notes 3. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V Maximum transfer rate = 1 [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 2.0 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the condit ions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. Use it with EV DD0 ≥ Vb. 6. The smaller maximum transfer rate derived by using f MCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V Maximum transfer rate = 1 [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 1.5 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 7. This value as an example is calculated when the condit ions described in the “Conditions” column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128- pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and V IL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) RL78 microcontroller TxDq RxDq User device Rx Tx Vb Rb

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 90 of 200 Jun 30, 2020 UART mode bit width (during communication at different potential) (reference) TxDq RxDq Baud rate error tolerance Baud rate error tolerance Low-bit width High-/Low-bit width High-bit width 1/Transfer rate 1/Transfer rate Remarks 1. R b[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redire ction register (PIOR) is 1.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 91 of 200 Jun 30, 2020 (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (1/2) (T A = –40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCKp cycle time t KCY1 t KCY1 ≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 200 1150 1150 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 300 1150 1150 ns SCKp high-level width tKH1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 – t KCY1/2 – t KCY1/2 – ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 – 120 t KCY1/2 – 120 t KCY1/2 – 120 ns SCKp low-level width t KL1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 – tKCY1/2 – tKCY1/2 – ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 – t KCY1/2 – t KCY1/2 – ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 58 479 479 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 121 479 479 ns SIp hold time (from SCKp↑) Note 1 tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 60 60 60 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 130 130 130 ns (Notes, Caution, and Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 92 of 200 Jun 30, 2020 (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (2/2) (T A = –40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SIp setup time (to SCKp↓) Note 2 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 23 110 110 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 33 110 110 ns SIp hold time (from SCKp↓) Note 2 tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from SCKp↑ to SOp output Note 2 tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. R b[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of seri al mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. This value is valid only when CSI00’s peripheral I/O redirect function is not used.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 93 of 200 Jun 30, 2020 (T A = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCKp cycle time t KCY1 t KCY1 ≥ 4/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 300 1150 1150 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 500 1150 1150 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, Cb = 30 pF, Rb = 5.5 kΩ 1150 1150 1150 ns SCKp high-level width tKH1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 – t KCY1/2 – t KCY1/2 – ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 – 170 t KCY1/2 – 170 t KCY1/2 – 170 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 – 458 tKCY1/2 – 458 tKCY1/2 – 458 ns SCKp low-level width t KL1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 – t KCY1/2 – t KCY1/2 – ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 – t KCY1/2 – t KCY1/2 – ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 – tKCY1/2 – tKCY1/2 – ns Note Use it with EVDD0 ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed two pages after the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 94 of 200 Jun 30, 2020 (T A = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 81 479 479 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 177 479 479 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 479 479 479 ns SIp hold time (from SCKp↑) Note 1 tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 19 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 19 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 19 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 100 100 100 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 195 195 195 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 483 483 483 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. Use it with EV DD0 ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 95 of 200 Jun 30, 2020 (T A = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SIp setup time (to SCKp↓) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 44 110 110 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 44 110 110 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 110 110 110 ns SIp hold time (from SCKp↓) Note 1 tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 19 19 19 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 19 19 19 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 19 19 19 ns Delay time from SCKp↑ to SOp output Note 1 tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 30 pF, Rb = 1.4 kΩ 25 25 25 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 30 pF, Rb = 2.7 kΩ 25 25 25 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 25 25 25 ns Notes 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. Use it with EV DD0 ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 96 of 200 Jun 30, 2020 CSI mode connection diagram (during communication at different potential) Vb Rb SCKp SOp SCK SI User deviceSIp SO Vb Rb <Master> RL78 microcontroller Remarks 1. R b[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 97 of 200 Jun 30, 2020 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) SIp Input data Output dataSOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 SCKp CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) SIp Input data Output dataSOp tKCY1 tKL1tKH1 tSIK1 tKSI1 tKSO1 SCKp Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI2 1 cannot communicate at different potential. Use other CSI for communication at different potential.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 98 of 200 Jun 30, 2020 (T A = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCKp cycle time Note 1 t KCY2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

24 MHz < fMCK 14/

– – ns

20 MHz < fMCK ≤ 24 MHz 12/

– – ns

8 MHz < fMCK ≤ 20 MHz 10/

– – ns

4 MHz < fMCK ≤ 8 MHz 8/f MCK 16/

– ns fMCK ≤ 4 MHz 6/fMCK 10/ fMCK 10/ fMCK ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

24 MHz < fMCK 20/

– – ns

20 MHz < fMCK ≤ 24 MHz 16/

– – ns

16 MHz < fMCK ≤ 20 MHz 14/

– – ns

8 MHz < fMCK ≤ 16 MHz 12/

– – ns

4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/

– ns fMCK ≤ 4 MHz 6/fMCK 10/ fMCK 10/ fMCK ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2

24 MHz < fMCK 48/

– – ns

20 MHz < fMCK ≤ 24 MHz 36/

– – ns

16 MHz < fMCK ≤ 20 MHz 32/

– – ns

8 MHz < fMCK ≤ 16 MHz 26/

– – ns

4 MHz < fMCK ≤ 8 MHz 16/

– ns fMCK ≤ 4 MHz 10/ fMCK 10/ fMCK 10/ fMCK ns (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 99 of 200 Jun 30, 2020 (T A = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 – tKCY2/2 – 50 tKCY2/2 – 50 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 – tKCY2/2 – 50 tKCY2/2 – 50 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 tKCY2/2 – tKCY2/2 – 50 tKCY2/2 – 50 ns SIp setup time (to SCKp↑) Note 3 tSIK2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 20 1/f MCK + 30 1/f MCK + 30 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 1/fMCK + 30 1/f MCK + 30 1/f MCK + 30 ns SIp hold time (from SCKp↑) Note 4 tKSI2 1/fMCK + 1/fMCK + 31 1/fMCK + 31 ns Delay time from SCKp↓ to SOp output Note 5 tKSO2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2/f MCK + 120 2/f MCK + 573 2/f MCK + 573 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2/f MCK + 214 2/f MCK + 573 2/f MCK + 573 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. Use it with EVDD0 ≥ Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPm n = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 128-pin products )) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 100 of 200 Jun 30, 2020 CSI mode connection diagram (during communication at different potential) RL78 microcontroller SOp User device SCK SI SIp SO Vb Rb SCKp <Slave> Remarks 1. R b[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bi t of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13)) 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 101 of 200 Jun 30, 2020 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) SIp Input data Output dataSOp tKCY2 tKL2 tKH2 tSIK2 tKSI2 tKSO2 SCKp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) SIp Input data Output dataSOp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2 SCKp Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI2 1 cannot communicate at different potential. Use other CSI for communication at different potential.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 102 of 200 Jun 30, 2020 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) (T A = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCLr clock frequency f SCL 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 300 Note 1 300 Note 1 kHz 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 300 Note 1 300 Note 1 kHz 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 400 Note 1 300 Note 1 300 Note 1 kHz 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 400 Note 1 300 Note 1 300 ote 1 kHz 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 300 Note 1 300 Note 1 300 Note 1 kHz Hold time when SCLr = “L” tLOW 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 475 1550 1550 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 475 1550 1550 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1150 1550 1550 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1150 1550 1550 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 1550 1550 1550 ns Hold time when SCLr = “H” tHIGH 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 245 610 610 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 200 610 610 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 675 610 610 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 600 610 610 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 610 610 610 ns

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 103 of 200 Jun 30, 2020 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) (T A = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit Data setup time (reception) tSU:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK +

135 Note 3

+ 190 Note 3 1/fMCK + 190 Note 3 kHz 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + + 190 Note 3 1/fMCK + 190 Note 3 kHz 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK +

190 Note 3

+ 190 Note 3 1/fMCK + 190 Note 3 kHz 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + + 190 Note 3 1/fMCK + 190 Note 3 kHz 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK + + 190 Note 3 1/fMCK + 190 Note 3 kHz Data hold time (transmission) t HD:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 0 355 0 355 0 355 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 0 355 0 355 0 355 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 0 405 0 405 0 405 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Use it with EVDD0 ≥ Vb. 3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 128-pin products)) mode for the SDAr pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EV DD tolerance (for the 64- to 128-pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 104 of 200 Jun 30, 2020 Simplified I2C mode connection diagram (during communication at different potential) SDAr SCLr SDA SCL User device Vb Rb Vb Rb RL78 microcontroller Simplified I2C mode serial transfer timing (during communication at different potential) SDAr tLOW tHIGH tHD:DAT SCLr tSU:DAT 1/fSCL Remarks 1. R b[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 105 of 200 Jun 30, 2020

2.5.2 Serial interface IICA

(1) I 2C standard mode (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Condi tions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCLA0 clock frequency f SCL Standard mode: fCLK ≥ 1 MHz 2.7 V ≤ EVDD0 ≤ 5.5 V 0 100 0 100 0 100 kHz 1.8 V ≤ EVDD0 ≤ 5.5 V 0 100 0 100 0 100 kHz 1.7 V ≤ EVDD0 ≤ 5.5 V 0 100 0 100 0 100 kHz 1.6 V ≤ EVDD0 ≤ 5.5 V – 0 100 0 100 kHz Setup time of restart condition 1.6 V ≤ EVDD0 ≤ 5.5 V – 4.7 4.7 µs 1.6 V ≤ EVDD0 ≤ 5.5 V – 4.0 4.0 µs Hold time when SCLA0 = “L” t 1.6 V ≤ EVDD0 ≤ 5.5 V – 4.7 4.7 µs Hold time when SCLA0 = “H” t 1.6 V ≤ EVDD0 ≤ 5.5 V – 4.0 4.0 µs Data setup time (reception) t SU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 250 250 250 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 250 250 250 ns 1.7 V ≤ EVDD0 ≤ 5.5 V 250 250 250 ns 1.6 V ≤ EVDD0 ≤ 5.5 V – 250 250 ns Data hold time (transmission) Note 2 1.6 V ≤ EVDD0 ≤ 5.5 V – 0 3.45 0 3.45 µs Setup time of stop condition t 1.6 V ≤ EVDD0 ≤ 5.5 V – 4.0 4.0 µs 1.6 V ≤ EVDD0 ≤ 5.5 V – 4.7 4.7 µs (Notes, Caution and Remark are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 106 of 200 Jun 30, 2020 Notes 1. The first clock pulse is generated after this per iod when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (I OH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacit ance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: C b = 400 pF, Rb = 2.7 kΩ

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 107 of 200 Jun 30, 2020 (2) I 2C fast mode (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCLA0 clock frequency f SCL Fast mode: fCLK ≥ 3.5 MHz 2.7 V ≤ EVDD0 ≤ 5.5 V 0 400 0 400 0 400 kHz 1.8 V ≤ EVDD0 ≤ 5.5 V 0 400 0 400 0 400 kHz Setup time of restart condition Hold time when SCLA0 = “L” t Hold time when SCLA0 = “H” t Data setup time (reception) t SU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 100 100 100 µs 1.8 V ≤ EVDD0 ≤ 5.5 V 100 100 100 µs Data hold time (transmission) Note 2 Setup time of stop condition t Notes 1. The first clock pulse is generated after this per iod when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (I OH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacit ance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: C b = 320 pF, Rb = 1.1 kΩ

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 108 of 200 Jun 30, 2020 (3) I 2C fast mode plus (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit SCLA0 clock frequency f SCL Fast mode plus: fCLK ≥ 10 MHz 2.7 V ≤ EVDD0 ≤ 5.5 V 0 1000 – – kHz Setup time of restart condition tSU:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 – – µs Hold timeNote 1 t HD:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 – – µs Hold time when SCLA0 = “L” t LOW 2.7 V ≤ EVDD0 ≤ 5.5 V 0.5 – – µs Hold time when SCLA0 = “H” t HIGH 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 – – µs Data setup time (reception) t SU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 50 – – µs Data hold time (transmission) Note 2 tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 0 0.45 – – µs Setup time of stop condition t SU:STO 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 – – µs Bus-free time tBUF 2.7 V ≤ EVDD0 ≤ 5.5 V 0.5 – – µs Notes 1. The first clock pulse is generated after this per iod when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (I OH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacit ance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: C b = 120 pF, Rb = 1.1 kΩ IICA serial transfer timing tLOW tR tBUF tHIGH tF tHD:STA Stop condition Start condition Restart condition Stop condition t SU:DAT tSU:STA tSU:STOtHD:STAtHD:DAT SCLAn SDAAn Remark n = 0, 1

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 109 of 200 Jun 30, 2020

2.6 Analog Characteristics

2.6.1 A/D converter characteristics

3.6 V ≤ V

DD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs 1.6 V ≤ VDD ≤ 5.5 V 57 95 µs 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 E ZS 10-bit resolution AVREFP = VDD Note 3 1.8 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 ±0.50 %FSR Full-scale errorNotes 1, 2 E FS 10-bit resolution AV REFP = VDD Note 3 1.8 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 ±0.50 %FSR Integral linearity errorNote 1 ILE 10-bit resolution AV REFP = VDD Note 3 1.8 V ≤ AVREFP ≤ 5.5 V ±2.5 LSB 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 ±5.0 LSB Differential linearity error Note 1 DLE 10-bit resolution AV REFP = VDD Note 3 1.8 V ≤ AVREFP ≤ 5.5 V ±1.5 LSB 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 ±2.0 LSB Analog input voltage V AIN ANI2 to ANI14 0 AV REFP V Internal reference voltage (2.4 V ≤ V DD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 5 V Temperature sensor output voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 5 V (Notes are listed on the next page.)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 110 of 200 Jun 30, 2020 Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AV REFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. Values when the conversion time is set to 57 µs (min.) and 95 µs (max.). 5. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 111 of 200 Jun 30, 2020 (2) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AV REFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI26 (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EV DD1 ≤ VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, V SS = EV SS0 = EV SS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution EVDD0 = AVREFP = VDD Notes 3, 4 1.8 V ≤ AVREFP ≤ 5.5 V 1.2 ±5.0 LSB 1.6 V ≤ AVREFP ≤ 5.5 V Note 5 1.2 ±8.5 LSB Conversion time t CONV 10-bit resolution Target ANI pin : ANI16 to ANI26 DD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs 1.6 V ≤ VDD ≤ 5.5 V 57 95 µs Zero-scale errorNotes 1, 2 E ZS 10-bit resolution EVDD0 = AVREFP = VDD Notes 3, 4 1.8 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR 1.6 V ≤ AVREFP ≤ 5.5 V Note 5 ±0.60 %FSR Full-scale errorNotes 1, 2 E FS 10-bit resolution EV DD0 = AVREFP = VDD Notes 3, 4 1.8 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR 1.6 V ≤ AVREFP ≤ 5.5 V Note 5 ±0.60 %FSR Integral linearity errorNote 1 ILE 10-bit resolution EVDD0 = AVREFP = VDD Notes 3, 4 1.8 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB 1.6 V ≤ AVREFP ≤ 5.5 V Note 5 ±6.0 LSB Differential linearity error Note 1 DLE 10-bit resolution EV DD0 = AVREFP = VDD Notes 3, 4 1.8 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB 1.6 V ≤ AVREFP ≤ 5.5 V Note 5 ±2.5 LSB Analog input voltage V AIN ANI16 to ANI26 0 AV REFP and EVDD0 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AV REFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. When AV REFP < EVDD0 ≤ VDD, the MAX. values are as follows. Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD. 5. When the conversion time is set to 57 µs (min.) and 95 µs (max.).

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 112 of 200 Jun 30, 2020 (3) When reference voltage (+) = V DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = V SS (ADREFM = 0), target pin : ANI0 to ANI14, ANI16 to ANI26, internal reference voltage, and temperature sensor output voltage (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EV DD1 ≤ VDD ≤ 5.5 V, V SS = EV SS0 = EV SS1 = 0 V, Reference voltage (+) = V DD, Reference voltage (–) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB 1.6 V ≤ VDD ≤ 5.5 V Note 3 1.2 ±10.5 LSB Conversion time tCONV 10-bit resolution Target pin: ANI0 to ANI14, ANI16 to ANI26 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 1.8 V ≤ VDD ≤ 5.5 V 17 39 µs 1.6 V ≤ VDD ≤ 5.5 V 57 95 µs Conversion time tCONV 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 E ZS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR 1.6 V ≤ VDD ≤ 5.5 V Note 3 ±0.85 %FSR Full-scale errorNotes 1, 2 E FS 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±0.60 %FSR 1.6 V ≤ VDD ≤ 5.5 V Note 3 ±0.85 %FSR Integral linearity errorNote 1 ILE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±4.0 LSB 1.6 V ≤ VDD ≤ 5.5 V Note 3 ±6.5 LSB Differential linearity error Note 1 DLE 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V ±2.0 LSB 1.6 V ≤ VDD ≤ 5.5 V Note 3 ±2.5 LSB Analog input voltage V AIN ANI0 to ANI14 0 V DD V ANI16 to ANI26 0 EV DD0 V Internal reference voltage (2.4 V ≤ V DD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 4 V Temperature sensor output voltage (2.4 V ≤ V DD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 4 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When the conversion time is set to 57 µs (min.) and 95 µs (max.). 4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 113 of 200 Jun 30, 2020 (4) When reference voltage (+) = Inte rnal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI26 (TA = –40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (–) = AVREFM = 0 V Note 4, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 bit Conversion time tCONV 8-bit resolution 2.4 V ≤ V DD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 E ZS 8-bit resolution 2.4 V ≤ V DD ≤ 5.5 V ±0.60 %FSR Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Differential linearity error Note 1 DLE 8-bit resolution 2.4 V ≤ V DD ≤ 5.5 V ±1.0 LSB Analog input voltage VAIN 0 V BGR Note 3 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (–) = V SS, the MAX. values are as follows. Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (–) = AVREFM. Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (–) = AVREFM. Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (–) = AVREFM.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 114 of 200 Jun 30, 2020

2.6.2 Temperature sensor/internal reference voltage characteristics

(TA = –40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Temperature sensor output voltage V TMPS25 Setting ADS register = 80H, T A = +25°C 1.05 V Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V Temperature coefficient FVTMPS Temperature sensor that depends on the temperature –3.6 mV/°C Operation stabilization wait time t AMP 5 µs

2.6.3 POR circuit characteristics

(TA = –40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOR The power supply voltage is rising. 1.47 1.51 1.55 V VPDR The power supply voltage is falling. 1.46 1.50 1.54 V Minimum pulse widthNote T PW 300 µs Note Minimum time required for a POR reset when V DD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW VPOR VPDR or 0.7 V Supply voltage (VDD)

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 115 of 200 Jun 30, 2020

2.6.4 LVD circuit characteristics

LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = –40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVD0 The power supply voltage is rising. 3.98 4.06 4.14 V The power supply voltage is falling. 3.90 3.98 4.06 V VLVD1 The power supply voltage is rising. 3.68 3.75 3.82 V The power supply voltage is falling. 3.60 3.67 3.74 V VLVD2 The power supply voltage is rising. 3.07 3.13 3.19 V The power supply voltage is falling. 3.00 3.06 3.12 V VLVD3 The power supply voltage is rising. 2.96 3.02 3.08 V The power supply voltage is falling. 2.90 2.96 3.02 V VLVD4 The power supply voltage is rising. 2.86 2.92 2.97 V The power supply voltage is falling. 2.80 2.86 2.91 V VLVD5 The power supply voltage is rising. 2.76 2.81 2.87 V The power supply voltage is falling. 2.70 2.75 2.81 V VLVD6 The power supply voltage is rising. 2.66 2.71 2.76 V The power supply voltage is falling. 2.60 2.65 2.70 V VLVD7 The power supply voltage is rising. 2.56 2.61 2.66 V The power supply voltage is falling. 2.50 2.55 2.60 V VLVD8 The power supply voltage is rising. 2.45 2.50 2.55 V The power supply voltage is falling. 2.40 2.45 2.50 V VLVD9 The power supply voltage is rising. 2.05 2.09 2.13 V The power supply voltage is falling. 2.00 2.04 2.08 V VLVD10 The power supply voltage is rising. 1.94 1.98 2.02 V The power supply voltage is falling. 1.90 1.94 1.98 V VLVD11 The power supply voltage is rising. 1.84 1.88 1.91 V The power supply voltage is falling. 1.80 1.84 1.87 V VLVD12 The power supply voltage is rising. 1.74 1.77 1.81 V The power supply voltage is falling. 1.70 1.73 1.77 V VLVD13 The power supply voltage is rising. 1.64 1.67 1.70 V The power supply voltage is falling. 1.60 1.63 1.66 V Minimum pulse width tLW 300 µs Detection delay time 300 µs

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 116 of 200 Jun 30, 2020 LVD Detection Voltage of Interrupt & Reset Mode (TA = –40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVDA0 V POC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage 1.60 1.63 1.66 V VLVDA1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.74 1.77 1.81 V Falling interrupt voltage 1.70 1.73 1.77 V VLVDA2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 1.84 1.88 1.91 V Falling interrupt voltage 1.80 1.84 1.87 V VLVDA3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDB0 V POC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 V VLVDB1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V VLVDB2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V VLVDB3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V Falling interrupt voltage 3.00 3.06 3.12 V VLVDC0 V POC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V VLVDC1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V VLVDC2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V VLVDC3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V VLVDD0 V POC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V

2.6.5 Power supply voltage rising slope characteristics

(TA = –40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until V DD reaches the operating voltage range shown in 2.4 AC Characteristics.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 117 of 200 Jun 30, 2020

2.7 RAM Data Retention Characteristics

(TA = –40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.46Note 5.5 V Note This depends on the POR detection voltage. For a fallin g voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM data retention VDDDR Operation mode

2.8 Flash Memory Programming Characteristics

(TA = –40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit CPU/peripheral hardware clock frequency fCLK 1.8 V ≤ VDD ≤ 5.5 V 1 32 MHz Number of code flash rewrites Notes 1, 2, 3 Cerwr Retained for 20 years TA = 85°C 1,000 Times Number of data flash rewrites Notes 1, 2, 3 Retained for 1 years T A = 25°C 1,000,000 Retained for 5 years T A = 85°C 100,000 Retained for 20 years T A = 85°C 10,000 Notes 1. 1 erase + 1 write after the er ase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. These are the characteristi cs of the flash memory and the results obtai ned from reliability testing by Renesas Electronics Corporation.

RL78/G13 2. ELECTR ICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 118 of 200 Jun 30, 2020

2.9 Dedicated Flash Memory Programmer Communication (UART)

(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate During serial programming 115,200 1,000,000 bps

2.10 Timing of Entry to Flash Memory Programming Modes

(TA = –40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level t SU POR and LVD reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) t HD POR and LVD reset must be released before the external reset is released. 1 ms RESET TOOL0 tSU <4> tSUINIT 723 µs + tHD processing time 1-byte data for setting mode <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark t SUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released during this period. tSU: Time to release the exte rnal reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 119 of 200 Jun 30, 2020 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) This chapter describes the following electrical specifications. Target products G: Industrial applications T A = –40 to +105°C R5F100xxGxx Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. With products not provided with an EV DD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. product in the RL78/G13 User’s Manual. 4. Please contact Renesas Electronics sales office for derating of operation under TA = +85°C to +105°C. Derating is the systematic reduction of load for the sake of improved reliability. Remark When RL78/G13 is used in the range of TA = –40 to +85°C, see 2. ELECTRICAL SPECIFICATIONS (TA = – 40 to +85°C). There are following differences between the products "G: Industrial applications (T A = –40 to +105°C)" and the products “A: Consumer applications, and D: Industrial applications”. Parameter Application A: Consumer applications, D: Industrial applications G: Industrial applications Operating ambient temperature TA = -40 to +85°C TA = -40 to +105°C Operating mode Operating voltage range HS (high-speed main) mode: DD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode:

1.8 V ≤ V

DD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode:

1.6 V ≤ V

DD ≤ 5.5 V@1 MHz to 4 MHz HS (high-speed main) mode only: DD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz High-speed on-chip oscillator clock accuracy DD ≤ 5.5 V 1.6 V ≤ VDD < 1.8 V 2.4 V ≤ VDD ≤ 5.5 V Serial array unit UART CSI: fCLK/2 (supporting 16 Mbps), fCLK/4 Simplified I2C communication UART CSI: f CLK/4 Simplified I2C communication IICA Normal mode Fast mode Fast mode plus Normal mode Fast mode Voltage detector Rise detection voltage: 1.67 V to 4.06 V (14 levels) Fall detection voltage: 1.63 V to 3.98 V (14 levels) Rise detection voltage: 2.61 V to 4.06 V (8 levels) Fall detection voltage: 2.55 V to 3.98 V (8 levels) (Remark is listed on the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 120 of 200 Jun 30, 2020 Remark The electrical characteristics of the products G: Industrial applications (T A = -40 to +105°C) are different from those of the products “A: Consumer applications, and D: Industrial applications”. For details, refer to 3.1 to 3.10.

3.1 Absolute Maximum Ratings

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 121 of 200 Jun 30, 2020 Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Symbols Conditions Ratings Unit Output current, high I OH1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 –40 mA Total of all pins –170 mA P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 –70 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 –100 mA IOH2 Per pin P20 to P27, P150 to P156 –0.5 mA Total of all pins –2 mA Output current, low I OL1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 40 mA Total of all pins 170 mA P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 70 mA P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 100 mA IOL2 Per pin P20 to P27, P150 to P156 1 mA Total of all pins 5 mA Operating ambient temperature T A In normal operation mode –40 to +105 °C In flash memory programming mode Storage temperature T stg –65 to +150 °C Caution Product quality may suffer if the absolute maximum ra ting is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteri stics of alternate-function pins are the same as those of the port pins.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 122 of 200 Jun 30, 2020

3.2 Oscillator Characteristics

3.2.1 X1, XT1 oscillator characteristics

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Resonator Conditions MIN. TYP. MAX. Unit X1 clock oscillation frequency (fX)Note Ceramic resonator/ crystal resonator DD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz XT1 clock oscillation frequency (f X)Note Crystal resonator 32 32.768 35 kHz Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clo ck after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G13 User’s Manual.

3.2.2 On-chip oscillator characteristics

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock frequency Notes 1, 2 fIH 1 32 MHz High-speed on-chip oscillator clock frequency accuracy –20 to +85°C 2.4 V ≤ V Low-speed on-chip oscillator clock frequency f IL 15 kHz Low-speed on-chip oscillator clock frequency accuracy –15 +15 % Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 123 of 200 Jun 30, 2020

3.3 DC Characteristics

3.3.1 Pin characteristics

(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, highNote 1 IOH1 Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147

2.4 V ≤ EV

DD0 ≤ 5.5 V –3.0 Note 2 mA Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V –30.0 mA 2.7 V ≤ EVDD0 < 4.0 V –10.0 mA 2.4 V ≤ EVDD0 < 2.7 V –5.0 mA Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V –30.0 mA 2.7 V ≤ EVDD0 < 4.0 V –19.0 mA 2.4 V ≤ EVDD0 < 2.7 V –10.0 mA Total of all pins (When duty ≤ 70%Note 3) 2.4 V ≤ EVDD0 ≤ 5.5 V –60.0 mA IOH2 Per pin for P20 to P27, P150 to P156 2,4 V ≤ VDD ≤ 5.5 V –0.1 Note 2 mA Total of all pins (When duty ≤ 70% Note 3) 2.4 V ≤ VDD ≤ 5.5 V –1.5 mA Notes 1 . Value of current at which the device operation is guaranteed even if the current flows from the EV DD0, EVDD1, VDD pins to an output pin. 2. Do not exceed the total current value. 3. Specification under conditi ons where the duty factor ≤ 70%. The output current value that has ch anged to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

Total output current of pins = (IOH × 0.7)/(n × 0.01) <Example> Where n = 80% and I OH = –10.0 mA Total output current of pins = (–10.0 × 0.7)/(80 × 0.01)  –8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P 50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 124 of 200 Jun 30, 2020 (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, lowNote 1 IOL1 Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 8.5 Note 2 mA Per pin for P60 to P63 15.0 Note 2 mA Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V 40.0 mA 2.7 V ≤ EVDD0 < 4.0 V 15.0 mA 2.4 V ≤ EVDD0 < 2.7 V 9.0 mA Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V 40.0 mA 2.7 V ≤ EVDD0 < 4.0 V 35.0 mA 2,4 V ≤ EVDD0 < 2.7 V 20.0 mA Total of all pins (When duty ≤ 70% Note 3) 80.0 mA IOL2 Per pin for P20 to P27, P150 to P156 0.4 Note 2 mA Total of all pins (When duty ≤ 70% Note 3) 2,4 V ≤ VDD ≤ 5.5 V 5.0 mA Notes 1 . Value of current at which the devic e operation is guaranteed even if the current flows from an output pin to the EVSS0, EVSS1 and VSS pin. 2. Do not exceed the total current value. 3. Specification under conditi ons where the duty factor ≤ 70%. The output current value that has ch anged to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%).

Total output current of pins = (IOL × 0.7)/(n × 0.01) <Example> Where n = 80% and I OL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01)  8.7 mA However, the current that is allowed to flow into one pin does not vary depe nding on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 125 of 200 Jun 30, 2020 (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high VIH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 Normal input buffer 0.8EV DD0 EV DD0 V VIH2 P01, P03, P04, P10, P11, P13 to P17, P43, P44, P53 to P55, P80, P81, P142, P143 TTL input buffer DD0 ≤ 5.5 V DD0 < 4.0 V DD0 < 3.3 V VIH3 P20 to P27, P150 to P156 0.7VDD V DD V VIH4 P60 to P63 0.7EVDD0 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD V DD V Input voltage, low V IL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 Normal input buffer 0 0.2EV DD0 V VIL2 P01, P03, P04, P10, P11, P13 to P17, P43, P44, P53 to P55, P80, P81, P142, P143 TTL input buffer DD0 ≤ 5.5 V 0 0.8 V TTL input buffer DD0 < 4.0 V 0 0.5 V TTL input buffer DD0 < 3.3 V 0 0.32 V VIL3 P20 to P27, P150 to P156 0 0.3V DD V VIL4 P60 to P63 0 0.3EV DD0 V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2V DD V Caution The maximum value of V IH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 126 of 200 Jun 30, 2020 (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, high VOH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD0 ≤ 5.5 V, IOH1 = –3.0 mA EVDD0 – 0.7 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOH1 = –2.0 mA EVDD0 – 0.6 V 2.4 V ≤ EVDD0 ≤ 5.5 V, IOH1 = –1.5 mA EVDD0 – 0.5 V VOH2 P20 to P27, P150 to P156 2.4 V ≤ VDD ≤ 5.5 V, IOH2 = –100 µA VDD – 0.5 V Output voltage, low V OL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 8.5 mA 0.7 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 3.0 mA 0.6 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 1.5 mA 0.4 V 2.4 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 0.6 mA 0.4 V VOL2 P20 to P27, P150 to P156 2.4 V ≤ VDD ≤ 5.5 V, IOL2 = 400 µA 0.4 V VOL3 P60 to P63 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 5.0 mA 0.4 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 3.0 mA 0.4 V 2.4 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 2.0 mA 0.4 V Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P 50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 127 of 200 Jun 30, 2020 (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, high ILIH1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 V I = EVDD0 1 µA ILIH2 P20 to P27, P137, P150 to P156, RESET V I = VDD 1 µA ILIH3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) V I = VDD In input port or external clock input 1 µA In resonator connection 10 µA Input leakage current, low I LIL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 V I = EVSS0 –1 µA ILIL2 P20 to P27, P137, P150 to P156, RESET VI = VSS –1 µA ILIL3 P121 to P124 (X1, X2, XT1, XT2, EXCLK, EXCLKS) V I = VSS In input port or external clock input –1 µA In resonator connection –10 µA On-chip pll-up resistance R U P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 V I = EVSS0, In input port 10 20 100 k Ω Remark Unless specified otherwise, the charac teristics of alternate-function pins are the same as those of the port pins.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 128 of 200 Jun 30, 2020

3.3.2 Supply current characteristics

(1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = –40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode HS (high- speed main) mode Note 5 fIH = 32 MHz Note 3 Basic operation V DD = 5.0 V 2.1 mA VDD = 3.0 V 2.1 mA Normal operation V DD = 5.0 V 4.6 7.5 mA VDD = 3.0 V 4.6 7.5 mA fIH = 24 MHz Note 3 Normal operation V DD = 5.0 V 3.7 5.8 mA VDD = 3.0 V 3.7 5.8 mA fIH = 16 MHz Note 3 Normal operation V DD = 5.0 V 2.7 4.2 mA VDD = 3.0 V 2.7 4.2 mA HS (high- speed main) mode Note 5 fMX = 20 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 3.0 4.9 mA Resonator connection 3.2 5.0 mA fMX = 20 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 3.0 4.9 mA Resonator connection 3.2 5.0 mA fMX = 10 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 1.9 2.9 mA Resonator connection 1.9 2.9 mA fMX = 10 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 1.9 2.9 mA Resonator connection 1.9 2.9 mA Subsystem clock operation f SUB = 32.768 kHz Note 4 TA = –40°C Normal operation Square wave input 4.1 4.9 µA Resonator connection 4.2 5.0 µA fSUB = 32.768 kHz Note 4 TA = +25°C Normal operation Square wave input 4.1 4.9 µA Resonator connection 4.2 5.0 µA fSUB = 32.768 kHz Note 4 TA = +50°C Normal operation Square wave input 4.2 5.5 µA Resonator connection 4.3 5.6 µA fSUB = 32.768 kHz Note 4 TA = +70°C Normal operation Square wave input 4.3 6.3 µA Resonator connection 4.4 6.4 µA fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation Square wave input 4.6 7.7 µA Resonator connection 4.7 7.8 µA fSUB = 32.768 kHz Note 4 TA = +105°C Normal operation Square wave input 6.9 19.7 µA Resonator connection 7.0 19.8 µA (Notes and Remarks are listed on the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 129 of 200 Jun 30, 2020 Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 5. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temper ature condition of the TYP. value is TA = 25°C

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 130 of 200 Jun 30, 2020 (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = –40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode HS (high- speed main) mode Note 7 fIH = 32 MHz Note 4 V DD = 5.0 V 0.54 2.90 mA VDD = 3.0 V 0.54 2.90 mA fIH = 24 MHz Note 4 V DD = 5.0 V 0.44 2.30 mA VDD = 3.0 V 0.44 2.30 mA fIH = 16 MHz Note 4 V DD = 5.0 V 0.40 1.70 mA VDD = 3.0 V 0.40 1.70 mA HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 0.28 1.90 mA Resonator connection 0.45 2.00 mA fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 0.28 1.90 mA Resonator connection 0.45 2.00 mA fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 0.19 1.02 mA Resonator connection 0.26 1.10 mA fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 0.19 1.02 mA Resonator connection 0.26 1.10 mA Subsystem clock operation f SUB = 32.768 kHzNote 5 TA = –40°C Square wave input 0.25 0.57 µA Resonator connection 0.44 0.76 µA fSUB = 32.768 kHzNote 5 TA = +25°C Square wave input 0.30 0.57 µA Resonator connection 0.49 0.76 µA fSUB = 32.768 kHzNote 5 TA = +50°C Square wave input 0.37 1.17 µA Resonator connection 0.56 1.36 µA fSUB = 32.768 kHzNote 5 TA = +70°C Square wave input 0.53 1.97 µA Resonator connection 0.72 2.16 µA fSUB = 32.768 kHzNote 5 TA = +85°C Square wave input 0.82 3.37 µA Resonator connection 1.01 3.56 µA fSUB = 32.768 kHzNote 5 TA = +105°C Square wave input 3.01 15.37 µA Resonator connection 3.20 15.56 µA IDD3Note 6 STOP mode Note 8 TA = –40°C 0.18 0.50 µA TA = +25°C 0.23 0.50 µA TA = +50°C 0.30 1.10 µA TA = +70°C 0.46 1.90 µA TA = +85°C 0.75 3.30 µA TA = +105°C 2.94 15.30 µA (Notes and Remarks are listed on the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 131 of 200 Jun 30, 2020 Notes 1. Total current flowing into V DD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to V DD, EVDD0 or V SS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RT C, 12-bit interval timer, and watchdog timer. 7. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz 8. Regarding the value for current operate the subsystem cl ock in STOP mode, refer to that in HALT mode. Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 132 of 200 Jun 30, 2020 (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD1 Operating mode HS (high- speed main) mode Note 5 fIH = 32 MHz Note 3 Basic operation V DD = 5.0 V 2.3 mA VDD = 3.0 V 2.3 mA Normal operation V DD = 5.0 V 5.2 9.2 mA VDD = 3.0 V 5.2 9.2 mA fIH = 24 MHz Note 3 Normal operation V DD = 5.0 V 4.1 7.0 mA VDD = 3.0 V 4.1 7.0 mA fIH = 16 MHz Note 3 Normal operation V DD = 5.0 V 3.0 5.0 mA VDD = 3.0 V 3.0 5.0 mA HS (high- speed main) mode Note 5 fMX = 20 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 3.4 5.9 mA Resonator connection 3.6 6.0 mA fMX = 20 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 3.4 5.9 mA Resonator connection 3.6 6.0 mA fMX = 10 MHzNote 2, VDD = 5.0 V Normal operation Square wave input 2.1 3.5 mA Resonator connection 2.1 3.5 mA fMX = 10 MHzNote 2, VDD = 3.0 V Normal operation Square wave input 2.1 3.5 mA Resonator connection 2.1 3.5 mA Subsystem clock operation f SUB = 32.768 kHz Note 4 TA = –40°C Normal operation Square wave input 4.8 5.9 µA Resonator connection 4.9 6.0 µA fSUB = 32.768 kHz Note 4 TA = +25°C Normal operation Square wave input 4.9 5.9 µA Resonator connection 5.0 6.0 µA fSUB = 32.768 kHz Note 4 TA = +50°C Normal operation Square wave input 5.0 7.6 µA Resonator connection 5.1 7.7 µA fSUB = 32.768 kHz Note 4 TA = +70°C Normal operation Square wave input 5.2 9.3 µA Resonator connection 5.3 9.4 µA fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation Square wave input 5.7 13.3 µA Resonator connection 5.8 13.4 µA fSUB = 32.768 kHz Note 4 TA = +105°C Normal operation Square wave input 10.0 46.0 µA Resonator connection 10.0 46.0 µA (Notes and Remarks are listed on the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 133 of 200 Jun 30, 2020 Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed syst em clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the 12-bit interval timer and watchdog timer. 5. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temper ature condition of the TYP. value is TA = 25°C

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 134 of 200 Jun 30, 2020 (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) (Notes and Remarks are listed on the next page.) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode HS (high- speed main) mode Note 7 fIH = 32 MHz Note 4 V DD = 5.0 V 0.62 3.40 mA VDD = 3.0 V 0.62 3.40 mA fIH = 24 MHz Note 4 V DD = 5.0 V 0.50 2.70 mA VDD = 3.0 V 0.50 2.70 mA fIH = 16 MHz Note 4 V DD = 5.0 V 0.44 1.90 mA VDD = 3.0 V 0.44 1.90 mA HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V Square wave input 0.31 2.10 mA Resonator connection 0.48 2.20 mA fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input 0.31 2.10 mA Resonator connection 0.48 2.20 mA fMX = 10 MHzNote 3, VDD = 5.0 V Square wave input 0.21 1.10 mA Resonator connection 0.28 1.20 mA fMX = 10 MHzNote 3, VDD = 3.0 V Square wave input 0.21 1.10 mA Resonator connection 0.28 1.20 mA Subsystem clock operation f SUB = 32.768 kHzNote 5 TA = –40°C Square wave input 0.28 0.61 µA Resonator connection 0.47 0.80 µA fSUB = 32.768 kHzNote 5 TA = +25°C Square wave input 0.34 0.61 µA Resonator connection 0.53 0.80 µA fSUB = 32.768 kHzNote 5 TA = +50°C Square wave input 0.41 2.30 µA Resonator connection 0.60 2.49 µA fSUB = 32.768 kHzNote 5 TA = +70°C Square wave input 0.64 4.03 µA Resonator connection 0.83 4.22 µA fSUB = 32.768 kHzNote 5 TA = +85°C Square wave input 1.09 8.04 µA Resonator connection 1.28 8.23 µA fSUB = 32.768 kHzNote 5 TA = +105°C Square wave input 5.50 41.00 µA Resonator connection 5.50 41.00 µA IDD3Note 6 STOP mode Note 8 TA = –40°C 0.19 0.52 µA TA = +25°C 0.25 0.52 µA TA = +50°C 0.32 2.21 µA TA = +70°C 0.55 3.94 µA TA = +85°C 1.00 7.95 µA TA = +105°C 5.00 40.00 µA

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 135 of 200 Jun 30, 2020 Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RT C, 12-bit interval timer, and watchdog timer. 7. Relationship between operation volta ge width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz 8. Regarding the value for current operate the subsystem cl ock in STOP mode, refer to that in HALT mode. Remarks 1. f MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. f IH: High-speed on-chip oscillator clock frequency 3. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 136 of 200 Jun 30, 2020 (3) Peripheral Functions (Common to all products) (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed on- chip oscillator operating current I FIL Note 1 0.20 µA RTC operating current I RTC Notes 1, 2, 3 0.02 µA 12-bit interval timer operating current I IT Notes 1, 2, 4 0.02 µA Watchdog timer operating current I WDT Notes 1, 2, 5 fIL = 15 kHz 0.22 µA A/D converter operating current IADC Notes 1, 6 When conversion at maximum speed Normal mode, AV REFP = VDD = 5.0 V 1.3 1.7 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA A/D converter reference voltage current IADREF Note 1 75.0 µA Temperature sensor operating current ITMPS Note 1 75.0 µA LVD operating current ILVD Notes 1, 7 0.08 µA Self programming operating current I FSP Notes 1, 9 2.50 12.20 mA BGO operating current I BGO Notes 1, 8 2.50 12.20 mA SNOOZE operating current ISNOZ Note 1 ADC operation The mode is performed Note 10 0.50 1.10 mA The A/D conversion operations are performed, low-voltage mode, AV REFP = VDD = 3.0 V 1.20 2.04 mA CSI/UART operation 0.70 1.54 mA Notes 1. Current flowing to the V DD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcont rollers is the sum of the values of either IDD1 or I DD2, and I RTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, I FIL should be added. I DD2 subsystem clock operation includes the operational current of the real-time clock. 4. Current flowing only to the 12-bit interval timer (e xcluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcont rollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including t he operating current of the low-speed on-chip oscillator). The supply current of the RL78 is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter is in operation.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 137 of 200 Jun 30, 2020 Notes 7. Current flowing only to the LVD circuit. The supply cu rrent of the RL78 microcontrollers is the sum of I DD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10. For shift time to the SNOOZE mode, see 18.3.3 SNOOZE mode in the RL78/G13 User’s Manual. Remarks 1. f IL: Low-speed on-chip oscillator clock frequency 2. f SUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. f CLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is T A = 25°C

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 138 of 200 Jun 30, 2020

3.4 AC Characteristics

(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions MIN. TYP. MAX. Unit Instruction cycle (minimum instruction execution time) TCY Main system clock (f MAIN) operation HS (high-speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.03125 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs Subsystem clock (fSUB) operation In the self programming mode HS (high-speed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.03125 1 µs 2.4 V ≤ VDD < 2.7 V 0.0625 1 µs External system clock frequency f EX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz fEXS 32 35 kHz External system clock input high- level width, low-level width tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns 2.4 V ≤ VDD < 2.7 V 30 ns tEXHS, tEXLS 13.7 µs TI00 to TI07, TI10 to TI17 input high-level width, low-level width t TIH, tTIL 1/f MCK+10 ns Note TO00 to TO07, TO10 to TO17 output frequency f TO HS (high-speed main) mode 4.0 V ≤ EVDD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz 2.4 V ≤ EVDD0 < 2.7 V 4 MHz PCLBUZ0, PCLBUZ1 output frequency fPCL HS (high-speed main) mode DD0 ≤ 5.5 V 16 MHz 2.7 V ≤ EVDD0 < 4.0 V 8 MHz 2.4 V ≤ EVDD0 < 2.7 V 4 MHz Interrupt input high-level width, low-level width t INTH, tINTL INTP0 2.4 V ≤ VDD ≤ 5.5 V 1 µs INTP1 to INTP11 2.4 V ≤ EVDD0 ≤ 5.5 V 1 µs Key interrupt input low-level width t KR KR0 to KR7 2.4 V ≤ EV DD0 ≤ 5.5 V 250 ns RESET low-level width tRSL 10 µs Note The following conditions are required for low voltage interface when EVDD0 < VDD 2.4V ≤ EVDD0 < 2.7 V : MIN. 125 ns Remark f MCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7))

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 139 of 200 Jun 30, 2020 Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 1.0 0.1 2.7 0.01 2.4 0.03125 0.0625 0.05 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected Supply voltage VDD [V] Cycle time TCY [µs] AC Timing Test Points VIH/VOH VIL/VOL Test points VIH/VOH VIL/VOL External System Clock Timing EXCLK/EXCLKS 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 140 of 200 Jun 30, 2020 TI/TO Timing TI00 to TI07, TI10 to TI17 tTIL tTIH TO00 to TO07, TO10 to TO17 1/fTO Interrupt Request Input Timing INTP0 to INTP11 tINTL tINTH Key Interrupt Input Timing KR0 to KR7 tKR RESET Input Timing RESET tRSL

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 141 of 200 Jun 30, 2020

3.5 Peripheral Functions Characteristics

3.5.1 Serial array unit

(1) During communication at same potential (UART mode) A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Note 1 f MCK/12 Note 2 bps Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK

2.6 Mbps

Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The following conditions are required for low voltage interface when E VDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 1.3 Mbps Caution Select the normal input buffer for the RxDq pi n and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) RL78 microcontroller TxDq RxDq Rx Tx User device UART mode bit width (during communication at same potential) (reference) Baud rate error tolerance High-/Low-bit width 1/Transfer rate TxDq RxDq Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 142 of 200 Jun 30, 2020 (2) During communication at same pot ential (CSI mode) (master mode, SCKp... internal clock output) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPm n = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time tKCY1 t KCY1 ≥ 4/fCLK 2.7 V ≤ EVDD0 ≤ 5.5 V 250 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 500 ns SCKp high-/low-level width t KH1, tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – 24 ns 2.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – 36 ns 2.4 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 – 76 ns SIp setup time (to SCKp↑) Note 1 t SIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 66 ns 2.7 V ≤ EVDD0 ≤ 5.5 V 66 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 113 ns SIp hold time (from SCKp↑) Note 2 t KSI1 38 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 50 ns

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 143 of 200 Jun 30, 2020 (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 5 t KCY2 4.0 V ≤ EVDD0 ≤ 5.5 V 20 MHz < f MCK 16/f MCK ns fMCK ≤ 20 MHz 12/f MCK ns 2.7 V ≤ EVDD0 ≤ 5.5 V 16 MHz < f MCK 16/f MCK ns fMCK ≤ 16 MHz 12/f MCK ns 2.4 V ≤ EVDD0 ≤ 5.5 V 16/f MCK ns 12/fMCK and 1000 ns SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 – 14 ns 2.7 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 – 16 ns 2.4 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 – 36 ns SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+40 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+60 ns SIp hold time (from SCKp↑) Note 2 tKSI2 2.4 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+62 ns Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V ≤ EVDD0 ≤ 5.5 V 2/f MCK+66 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 2/f MCK+113 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPm n = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14) 2. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of seri al mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) CSI mode connection diagram (during communication at same potential) RL78 microcontroller SCKp SOp SCK SI User deviceSIp SO

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 144 of 200 Jun 30, 2020 CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) SIp Input data Output dataSOp tKCY1, 2 tKL1, 2 tKH1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) SIp Input data Output dataSOp tKCY1, 2 tKH1, 2 tKL1, 2 tSIK1, 2 tKSI1, 2 tKSO1, 2 SCKp Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 145 of 200 Jun 30, 2020 (4) During communication at same potential (simplified I 2C mode) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLr clock frequency fSCL 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ

400 Note1 kHz

2.4 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ

100 Note1 kHz

Hold time when SCLr = “L” tLOW 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1200 ns 2.4 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 4600 ns Hold time when SCLr = “H” tHIGH 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1200 ns 2.4 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 4600 ns Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 220 Note2 ns 2.4 V ≤ EVDD ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 1/fMCK + 580 Note2 ns Data hold time (transmission) tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 770 ns 2.4 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 0 1420 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the normal input buffer and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode re gister g (PIMg) and port output mode register h (POMh). (Remarks are listed on the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 146 of 200 Jun 30, 2020 Simplified I2C mode mode connection diagram (during communication at same potential) RL78 microcontroller SDAr SCLr SDA SCL User device VDD Rb Simplified I2C mode serial transfer timing (during communication at same potential) SDAr tLOW tHIGH tHD:DAT SCLr tSU:DAT 1/fSCL Remarks 1. R b[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14), h: POM number (g = 0, 1, 4, 5, 7 to 9, 14) 3. f MCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 147 of 200 Jun 30, 2020 (5) Communication at different potential (1 .8 V, 2.5 V, 3 V) (UART mode) (1/2) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Reception 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V fMCK/12 Note 1 bps Theoretical value of the maximum transfer rate f CLK = 32 MHz, fMCK = fCLK 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V fMCK/12 Note 1 bps Theoretical value of the maximum transfer rate f CLK = 32 MHz, fMCK = fCLK 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V fMCK/12 Notes 1,2 bps Theoretical value of the maximum transfer rate f CLK = 32 MHz, fMCK = fCLK Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 1.3 Mbps Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EV DD tolerance (for the 64- to 100-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. V b[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of seri al mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 148 of 200 Jun 30, 2020 (5) Communication at different potential (1 .8 V, 2.5 V, 3 V) (UART mode) (2/2) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Note 1 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V

2.6 Note 2 Mbps

2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Note 3 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V

1.2 Note 4 Mbps

2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 5 bps Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V 0.43 Note 6 Mbps Notes 1. The smaller maximum transfer rate derived by using f MCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ EVDD0 ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Maximum transfer rate = 1 [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 2.2 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the condit ions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. The smaller maximum transfer rate derived by using f MCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EV DD0 < 4.0 V and 2.4 V ≤ Vb ≤ 2.7 V Maximum transfer rate = 1 [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 2.0 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the condit ions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 149 of 200 Jun 30, 2020 Notes 5. The smaller maximum transfer rate derived by using f MCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V Maximum transfer rate = 1 [bps] Vb )} × 3 Transfer rate × 2 – {–Cb × Rb × ln (1 – 1.5 Vb )} Baud rate error (theoretical value) = × 100 [%] ( 1 Transfer rate ) × Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. 6. This value as an example is calculated when the condit ions described in the “Conditions” column are met. Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and V IL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) RL78 microcontroller TxDq RxDq Rx Tx User device Vb Rb

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 150 of 200 Jun 30, 2020 UART mode bit width (during communication at different potential) (reference) TxDq RxDq Baud rate error tolerance Baud rate error tolerance Low-bit width High-/Low-bit width High-bit width 1/Transfer rate 1/Transfer rate Remarks 1. R b[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redire ction register (PIOR) is 1.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 151 of 200 Jun 30, 2020 output) (1/3) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time t KCY1 t KCY1 ≥ 4/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 600 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1000 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 2300 ns SCKp high-level width t KH1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 – 150 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 – 340 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 – 916 ns SCKp low-level width t KL1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 – 24 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 – 36 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 – 100 ns Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed two pages after the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 152 of 200 Jun 30, 2020 output) (2/3) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SIp setup time (to SCKp↑) Note tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 162 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 354 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 958 ns SIp hold time (from SCKp↑) Note tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 38 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 38 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 2.7 kΩ 38 ns Delay time from SCKp↓ to SOp output Note tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 200 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 390 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 966 ns Note When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products )) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 153 of 200 Jun 30, 2020 output) (3/3) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SIp setup time (to SCKp↓) Note tSIK1 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 88 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 88 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 220 ns SIp hold time (from SCKp↓) Note tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 38 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 38 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 38 ns Delay time from SCKp↑ to SOp output Note tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 50 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 50 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 50 ns Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products )) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For V IH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 154 of 200 Jun 30, 2020 CSI mode connection diagram (during communication at different potential) Vb Rb SOp User device SCK SI SIp SO Vb Rb RL78 microcontroller <Master> SCKp Remarks 1. R b[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bi t of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 155 of 200 Jun 30, 2020 CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) SIp Input data Output dataSOp tKCY1 tKL1 tKH1 tSIK1 tKSI1 tKSO1 SCKp CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) SIp Input data Output dataSOp tKCY1 tKL1tKH1 tSIK1 tKSI1 tKSO1 SCKp Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 00, 01, 02, 10, 12, 13), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI2 1 cannot communicate at different potential. Use other CSI for communication at different potential.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 156 of 200 Jun 30, 2020 (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time Note 1 t KCY2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

24 MHz < fMCK 28/f MCK ns

20 MHz < fMCK ≤ 24 MHz 24/f MCK ns

8 MHz < fMCK ≤ 20 MHz 20/f MCK ns

4 MHz < fMCK ≤ 8 MHz 16/f MCK ns

fMCK ≤ 4 MHz 12/fMCK ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

24 MHz < fMCK 40/f MCK ns

20 MHz < fMCK ≤ 24 MHz 32/f MCK ns

16 MHz < fMCK ≤ 20 MHz 28/f MCK ns

8 MHz < fMCK ≤ 16 MHz 24/f MCK ns

4 MHz < fMCK ≤ 8 MHz 16/fMCK ns

fMCK ≤ 4 MHz 12/fMCK ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V

24 MHz < fMCK 96/f MCK ns

20 MHz < fMCK ≤ 24 MHz 72/f MCK ns

16 MHz < fMCK ≤ 20 MHz 64/f MCK ns

8 MHz < fMCK ≤ 16 MHz 52/f MCK ns

4 MHz < fMCK ≤ 8 MHz 32/fMCK ns

fMCK ≤ 4 MHz 20/fMCK ns SCKp high-/low-level width tKH2, tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 – 24 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 – 36 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 tKCY2/2 – 100 ns SIp setup time (to SCKp↑) Note2 tSIK2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK + 40 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK + 40 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V 1/fMCK + 60 ns SIp hold time (from SCKp↑) Note 3 tKSI2 1/fMCK + 62 ns Delay time from SCKp↓ to SOp output Note 4 tKSO2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2/f MCK + 240 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2/f MCK + 428 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Cb = 30 pF, Rb = 5.5 kΩ 2/f MCK + 1146 ns (Notes, Caution and Remarks are listed on the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 157 of 200 Jun 30, 2020 Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp setup time becomes “to SCKp ↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and C KPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPm n = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 128-pin products)) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) RL78 microcontroller SCKp <Slave> SOp User device SCK SI SIp SO Vb Rb Remarks 1. R b[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13)) 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 158 of 200 Jun 30, 2020 CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) SIp Input data Output dataSOp tKCY2 tKL2 tKH2 tSIK2 tKSI2 tKSO2 SCKp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) SIp Input data Output dataSOp tKCY2 tKL2tKH2 tSIK2 tKSI2 tKSO2 SCKp Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI2 1 cannot communicate at different potential. Use other CSI for communication at different potential.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 159 of 200 Jun 30, 2020 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCLr clock frequency fSCL 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ

400 Note 1 kHz

2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ

100 Note 1 kHz

2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ Hold time when SCLr = “L” tLOW 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1200 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1200 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 4600 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 4600 ns 2.4 V ≤ EVDD0 < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ 4650 ns Hold time when SCLr = “H” tHIGH 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 620 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 500 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 2700 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 2400 ns 2.4 V ≤ EVDD0 < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ 1830 ns (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 160 of 200 Jun 30, 2020 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) (T A = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Data setup time (reception) tSU:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 340 Note 2 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 340 Note 2 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 1/fMCK + 760 Note 2 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 1/fMCK + 760 Note 2 ns 2.4 V ≤ EVDD0 < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK + 570 Note 2 ns Data hold time (transmission) tHD:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 0 770 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 0 770 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 2.8 kΩ 0 1420 ns 2.7 V ≤ EVDD0 < 4.0 V, Cb = 100 pF, Rb = 2.7 kΩ 0 1420 ns 2.4 V ≤ EVDD0 < 3.3 V, Cb = 100 pF, Rb = 5.5 kΩ 0 1215 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EV DD tolerance (for the 64- to 100-pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 161 of 200 Jun 30, 2020 Simplified I2C mode connection diagram (during communication at different potential) SDAr SCLr SDA SCL User device Vb Rb Vb Rb RL78 microcontroller Simplified I2C mode serial transfer timing (during communication at different potential) SDAr tLOW tHIGH tHD:DAT SCLr tSU:DAT 1/fSCL Caution Select the TTL input buffer and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the N-ch open drain output (V DD tolerance (for the 20- to 52-pin products)/EV DD tolerance (for the 64- to 100-pin products)) mode for the SCLr pin by using port inpu t mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. R b[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 162 of 200 Jun 30, 2020

3.5.2 Serial interface IICA

(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit Standard Mode Fast Mode MIN. MAX. MIN. MAX. SCLA0 clock frequency fSCL Fast mode: f CLK ≥ 3.5 MHz – – 0 400 kHz Standard mode: fCLK ≥ 1 MHz 0 100 – – kHz Setup time of restart condition t SU:STA 4.7 0.6 µs Hold timeNote 1 t HD:STA 4.0 0.6 µs Hold time when SCLA0 = “L” tLOW 4.7 1.3 µs Hold time when SCLA0 = “H” tHIGH 4.0 0.6 µs Data setup time (reception) tSU:DAT 250 100 ns Data hold time (transmission)Note 2 t HD:DAT 0 3.45 0 0.9 µs Setup time of stop condition tSU:STO 4.0 0.6 µs Bus-free time tBUF 4.7 1.3 µs Notes 1. The first clock pulse is generated after this per iod when the start/restart condition is detected. 2. The maximum value (MAX.) of t HD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (I OH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacit ance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: C b = 400 pF, Rb = 2.7 kΩ Fast mode: C b = 320 pF, Rb = 1.1 kΩ IICA serial transfer timing tR tBUF tF tLOW tHIGH tHD:STA Stop condition Start condition Restart condition Stop condition t SU:DAT tSU:STA tSU:STOtHD:STAtHD:DAT SCLAn SDAAn Remark n = 0, 1

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 163 of 200 Jun 30, 2020

3.6 Analog Characteristics

3.6.1 A/D converter characteristics

Classification of A/D converter characteristics Input channel Reference Voltage Reference voltage (+) = AVREFP Reference voltage (–) = AVREFM Reference voltage (+) = VDD Reference voltage (–) = VSS Reference voltage (+) = VBGR Reference voltage (–) = AVREFM ANI16 to ANI26 Refer to 3.6.1 (2). Internal reference voltage Temperature sensor output voltage Refer to 3.6.1 (1). – (1) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AV REFM/ANI1 (ADREFM = 1), target pin : ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage (TA = –40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution AVREFP = VDD Note 3 2.4 V ≤ AVREFP ≤ 5.5 V 1.2 ±3.5 LSB Conversion time t CONV 10-bit resolution Target pin: ANI2 to ANI14 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 E ZS 10-bit resolution AVREFP = VDD Note 3 2.4 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR Full-scale errorNotes 1, 2 E FS 10-bit resolution AV REFP = VDD Note 3 2.4 V ≤ AVREFP ≤ 5.5 V ±0.25 %FSR Integral linearity error Note 1 ILE 10-bit resolution AVREFP = VDD Note 3 2.4 V ≤ AVREFP ≤ 5.5 V ±2.5 LSB Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD Note 3 2.4 V ≤ AVREFP ≤ 5.5 V ±1.5 LSB Analog input voltage V AIN ANI2 to ANI14 0 AV REFP V Internal reference voltage output (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 4 V Temperature sensor output voltage (2.4 V ≤ V DD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 4 V (Notes are listed on the next page.)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 164 of 200 Jun 30, 2020 Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AV REFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 165 of 200 Jun 30, 2020 (2) When reference voltage (+) = AV REFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (–) = AV REFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI26 (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EV DD1 ≤ VDD ≤ 5.5 V, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, V SS = EV SS0 = EV SS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (–) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution EVDD0 ≤ AVREFP = VDD Notes 3, 4 2.4 V ≤ AVREFP ≤ 5.5 V 1.2 ±5.0 LSB Conversion time t CONV 10-bit resolution Target pin : ANI16 to ANI26 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 E ZS 10-bit resolution EVDD0 ≤ AVREFP = VDD Notes 3, 4 2.4 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR Full-scale errorNotes 1, 2 E FS 10-bit resolution EV DD0 ≤ AVREFP = VDD Notes 3, 4 2.4 V ≤ AVREFP ≤ 5.5 V ±0.35 %FSR Integral linearity errorNote 1 ILE 10-bit resolution EVDD0 ≤ AVREFP = VDD Notes 3, 4 2.4 V ≤ AVREFP ≤ 5.5 V ±3.5 LSB Differential linearity error Note 1 DLE 10-bit resolution EVDD0 ≤ AVREFP = VDD Notes 3, 4 2.4 V ≤ AVREFP ≤ 5.5 V ±2.0 LSB Analog input voltage V AIN ANI16 to ANI26 0 AVREFP and EVDD0 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AV REFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. When AV REFP < EVDD0 ≤ VDD, the MAX. values are as follows. Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 166 of 200 Jun 30, 2020 (3) When reference voltage (+) = V DD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (–) = V SS (ADREFM = 0), target pin : ANI0 to ANI14, ANI16 to ANI26, internal reference voltage, and temperature sensor output voltage (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EV DD1 ≤ VDD ≤ 5.5 V, V SS = EV SS0 = EV SS1 = 0 V, Reference voltage (+) = V DD, Reference voltage (–) = VSS) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 10 bit Overall errorNote 1 AINL 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB Conversion time t CONV 10-bit resolution Target pin: ANI0 to ANI14, ANI16 to ANI26 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) DD ≤ 5.5 V 2.375 39 µs 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 µs 2.4 V ≤ VDD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 E ZS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Full-scale errorNotes 1, 2 E FS 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±0.60 %FSR Integral linearity errorNote 1 ILE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±4.0 LSB Differential linearity error Note 1 DLE 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Analog input voltage V AIN ANI0 to ANI14 0 V DD V ANI16 to ANI26 0 EV DD0 V Internal reference voltage output (2.4 V ≤ V DD ≤ 5.5 V, HS (high-speed main) mode) VBGR Note 3 V Temperature sensor output voltage (2.4 V ≤ V DD ≤ 5.5 V, HS (high-speed main) mode) VTMPS25 Note 3 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 167 of 200 Jun 30, 2020 (4) When reference voltage (+) = Internal reference vo ltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI26 (TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (–) = AVREFM Note 4 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution RES 8 bit Conversion time tCONV 8-bit resolution 2.4 V ≤ V DD ≤ 5.5 V 17 39 µs Zero-scale errorNotes 1, 2 E ZS 8-bit resolution 2.4 V ≤ V DD ≤ 5.5 V ±0.60 %FSR Integral linearity errorNote 1 ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Differential linearity error Note 1 DLE 8-bit resolution 2.4 V ≤ V DD ≤ 5.5 V ±1.0 LSB Analog input voltage VAIN 0 V BGR Note 3 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (–) = V SS, the MAX. values are as follows. Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (–) = AVREFM. Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (–) = AVREFM. Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (–) = AVREFM.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 168 of 200 Jun 30, 2020

3.6.2 Temperature sensor/internal reference voltage characteristics

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit Temperature sensor output voltage V TMPS25 Setting ADS register = 80H, T A = +25°C 1.05 V Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V Temperature coefficient FVTMPS Temperature sensor that depends on the temperature –3.6 mV/°C Operation stabilization wait time t AMP 5 µs

3.6.3 POR circuit characteristics

(TA = –40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOR The power supply voltage is rising. 1.45 1.51 1.57 V VPDR The power supply voltage is falling. 1.44 1.50 1.56 V Minimum pulse width Note T PW 300 µs Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW VPOR VPDR or 0.7 V Supply voltage (VDD)

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 169 of 200 Jun 30, 2020

3.6.4 LVD circuit characteristics

LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = –40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage Supply voltage level V LVD0 The power supply voltage is rising. 3.90 4.06 4.22 V The power supply voltage is falling. 3.83 3.98 4.13 V VLVD1 The power supply voltage is rising. 3.60 3.75 3.90 V The power supply voltage is falling. 3.53 3.67 3.81 V VLVD2 The power supply voltage is rising. 3.01 3.13 3.25 V The power supply voltage is falling. 2.94 3.06 3.18 V VLVD3 The power supply voltage is rising. 2.90 3.02 3.14 V The power supply voltage is falling. 2.85 2.96 3.07 V VLVD4 The power supply voltage is rising. 2.81 2.92 3.03 V The power supply voltage is falling. 2.75 2.86 2.97 V VLVD5 The power supply voltage is rising. 2.70 2.81 2.92 V The power supply voltage is falling. 2.64 2.75 2.86 V VLVD6 The power supply voltage is rising. 2.61 2.71 2.81 V The power supply voltage is falling. 2.55 2.65 2.75 V VLVD7 The power supply voltage is rising. 2.51 2.61 2.71 V The power supply voltage is falling. 2.45 2.55 2.65 V Minimum pulse width tLW 300 µs Detection delay time 300 µs LVD Detection Voltage of Interrupt & Reset Mode (TA = –40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Interrupt and reset mode VLVDD0 V POC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 V VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.81 2.92 3.03 V Falling interrupt voltage 2.75 2.86 2.97 V VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.90 3.02 3.14 V Falling interrupt voltage 2.85 2.96 3.07 V VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.90 4.06 4.22 V Falling interrupt voltage 3.83 3.98 4.13 V

3.6.5 Power supply voltage rising slope characteristics

A = –40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until V DD reaches the operating voltage range shown in 3.4 AC Characteristics.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 170 of 200 Jun 30, 2020

3.7 RAM Data Retention Characteristics

(TA = –40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.44Note 5.5 V Note This depends on the POR detection voltage. For a fallin g voltage, data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated. VDD STOP instruction execution Standby release signal (interrupt request) STOP mode RAM data retention VDDDR Operation mode

3.8 Flash Memory Programming Characteristics

(TA = –40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit CPU/peripheral hardware clock frequency fCLK 2.4 V ≤ VDD ≤ 5.5 V 1 32 MHz Number of code flash rewrites Notes 1, 2, 3 Cerwr Retained for 20 years TA = 85°C Note 4 1,000 Times Number of data flash rewrites Notes 1, 2, 3 Retained for 1 years T A = 25°C 1,000,000 Retained for 5 years T A = 85°C Note 4 100,000 Retained for 20 years T A = 85°C Note 4 10,000 Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewr ite.The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library. 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 4. This temperature is the average value at which data are retained.

RL78/G13 3. ELECTRICAL SPECIFIC ATIONS (G: INDUSTRIAL APPLICATIONS TA = –40 to +105°C) R01DS0131EJ0350 Rev.3.50 171 of 200 Jun 30, 2020

3.9 Dedicated Flash Memory Programmer Communication (UART)

(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate During serial programming 115,200 1,000,000 bps

3.10 Timing of Entry to Flash Memory Programming Modes

(TA = –40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released t SUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset after the TOOL0 pin is set to the low level t SU POR and LVD reset must be released before the external reset is released. 10 µs Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) t HD POR and LVD reset must be released before the external reset is released. 1 ms RESET TOOL0 tSU <4> tSUINIT 723 µs + tHD processing time 1-byte data for setting mode <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark t SUINIT: Communication for the initial setting must be complet ed within 100 ms after the external reset is released during this period. tSU: Time to release the exte rnal reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory)

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 172 of 200 Jun 30, 2020 4. PACKAGE DRAWINGS 4.1 20-pin Package P-LSSOP20-0300-0.65 PLSP0020JC-A S20MC-65-5A4-3 0.12 NS C DM M P L U T G F E B K J detail of lead end S 20 11 11 0 A H I ITEM B C I L M N A K D E F G H J P T MILLIMETERS 0.65 (T.P .) 0.475 MAX. 0.13 0.5 6.1 ±0.2 0.10 6.65 ±0.15 0.17 ±0.03 0.1 ±0.05 0.24 1.3 ±0.1 8.1 ±0.2 1.2 +0.08 −0.07 1.0 ±0.2 3°+5° −3° 0.25 0.6 ±0.15U NOTE Each lead centerline is located within 0.13 mm of its true position (T.P .) at maximum material condition. 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 173 of 200 Jun 30, 2020 <R>

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 174 of 200 Jun 30, 2020 4.2 24-pin Package Sy e Lp S xbA BM A D E A S B A D E DETAIL OF A PART EXPOSED DIE PAD P-HWQFN24-4x4-0.50 PWQN0024KE-A P24K8-50-CAB-3 0.04 18 13 1219 INDEX AREA D A Lp 0.20 2.50 0.40 4.00 4.00 2.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.18 x A 0.80 y 0.05 0.00 0.25 e Z Z c D E D E E 0.50 0.05 0.75 0.75 0.15 0.25 A1 c2 4.053.95 4.053.95 Z Z D E

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 175 of 200 Jun 30, 2020 D SEATING PLANE ccc C 24X bbb C A B ddd C b(24X) 1318 L(24X) K(24X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B AE e 18 13 1 6 EXPOSED DIE PAD INDEX AREA (D/2 X E/2) Reference Symbol Dimension in Millimeters Min. Nom. Max. A0 .80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0.18 0.25 0.30 D4 .00 BSC E4 .00 BSC e0 .50 BSC L 0.35 0.40 0.45 K 0.20 D2 2.55 2.60 2.65 E2 2.55 2.60 2.65 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN024-4x4-0.50 PWQN0024KF-A 0.04

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 176 of 200 Jun 30, 2020 4.3 25-pin Package P-WFLGA25-3x3-0.50 PWLG0025KA-A P25FC-50-2N2-2 0.01 (APERTURE OF SOLDER RESIST) ITEM DIMENSIONS D E w e A b x y ZD ZE 3.00 ±0.10 3.00 ±0.10 0.05 0.20 0.69 ±0.07 0.08 0.50 0.24 ±0.05 (UNIT:mm) 0.20 0.50 0.50 S y1 S A S DETAIL OF C PART y S x21x b B M e b 0.34±0.05 0.43±0.05 0.50±0.05 0.365±0.05 R0.17±0.05 R0.165±0.05 R0.215±0.05 0.365±0.05 0.50±0.05 0.33±0.05 0.43±0.05 B S w ZD ZE INDEX MARK B C A SAwD E 2.27 2.27 DETAIL OF D PART D ED CB A (LAND PAD) INDEX MARK 2012 Renesas Electronics Corporation. All rights reserved. A

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 177 of 200 Jun 30, 2020 4.4 30-pin Package P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 S S H J T I G D E F C B K P L U N ITEM B C I L M N A K D E F G H J P 30 16 11 5 A detail of lead end MM T MILLIMETERS 0.65 (T.P .) 0.45 MAX. 0.13 0.5 6.1± 0.2 0.10 9.85 ±0.15 0.17 ±0.03 0.1± 0.05 0.24 1.3± 0.1 8.1± 0.2 1.2 +0.08 −0.07 1.0± 0.2 3°+5° −3° 0.25 0.6 ±0.15U NOTE Each lead centerline is located within 0.13 mm of its true position (T.P .) at maximum material condition. 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 178 of 200 Jun 30, 2020 4.5 32-pin Package 2013 Renesas Electronics Corporation. All rights reserved. Sy e Lp S x bA BM A D E A S B A D E EXPOSED DIE PAD P-HWQFN32-5x5-0.50 PWQN0032KB-A P32K8-50-3B4-5 0.06 1625 INDEX AREA D A Lp 0.20 3.50 0.40 5.00 5.00 3.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.18 x A 0.80 y 0.05 0.00 0.25 e Z Z c D E D E E 0.50 0.05 0.75 0.75 0.15 0.25 A1 C2 5.054.95 5.054.95 Z Z D E 1724 DETAIL OF A PART

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 179 of 200 Jun 30, 2020 INDEX AREA (D/2 X E/2) D E SEATING PLANE ccc C 32X bbb C A B ddd C e b(32X) 1724 L(32X) K(32X) C aaa C B aaa C (A3) A1A eee C fff C A B fff C A B A 7 14 2 Reference Symbol Dimension in Millimeters Min. Nom. Max. A0 .80 A1 0.00 0.02 0.05 A3 0.203 REF. b 0.18 0.25 0.30 D5 .00 BSC E5 .00 BSC e 0.50 BSC L 0.35 0.40 0.45 K0 . 2 0 D2 3.15 3.20 3.25 E2 3.15 3.20 3.25 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 P-HWQFN032-5x5-0.50 PWQN0032KE-A 0.06

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 180 of 200 Jun 30, 2020 4.6 36-pin Package P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023 ITEM DIMENSIONS D E w e A b x y ZD ZE 4.00 ±0.10 4.00 ±0.10 0.05 0.20 0.69 ±0.07 0.08 0.50 0.24 ±0.05 (UNIT:mm) 0.20 0.75 0.75 S y1 S A Sy S x32x b A BM e SwB ZD ZE INDEX MARK B C A SwAD E E EF DC B A C DDETAIL DETAIL EDETAIL b 0.34±0.05 0.55 0.70±0.05 0.55±0.05 0.70±0.05 0.55±0.05 0.75 φ φ 0.75 0.55 0.55 R0.275±0.05 R0.35±0.05 0.75 0.55±0.05 0.70± 0.05 0.55 0.75 0.55±0.05 0.70±0.05 (LAND PAD) (APERTURE OF SOLDER RESIST) D 2.90 2.90 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 181 of 200 Jun 30, 2020 4.7 40-pin Package 2013 Renesas Electronics Corporation. All rights reserved. Sy e Lp S xbA B M A D E A S B A D E DE TAIL OF A PART EXPOSED DIE PAD P-HWQFN40-6x6-0.50 P40K8-50-4B4-5 0.09 101 2031 INDEX AREA D A Lp 0.20 4.50 0.40 6.00 6.00 4.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.18 x A 0.80 y 0.05 0.00 0.25 e Z Z c D E D E E 0.50 0.05 0.75 0.75 0.15 0.25 A1 C2 6.055.95 6.055.95 Z Z D E 2130 PWQN0040KC-A

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 182 of 200 Jun 30, 2020 <R>

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 183 of 200 Jun 30, 2020 4.8 44-pin Package P-LQFP44-10x10-0.80 PLQP0044GC-A P44GB-80-UES-2 0.36 Sy e S x bM θ L c Lp HD HE ZD ZE A D E S 0.145 +0.055 −0.045 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 10.00 ±0.20 10.00 ±0.20 12.00 ±0.20 12.00 ±0.20 1.60 MAX. 0.10 ±0.05 1.40 ±0.05 0.25 c θ e x y ZD ZE 0.80 0.20 0.10 1.00 1.00 L Lp 0.50 0.60 ±0.15 1.00 ±0.20 3°+5° −3° NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. detail of lead end 0.37 +0.08 −0.07b 44 12 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 184 of 200 Jun 30, 2020

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 185 of 200 Jun 30, 2020 4.9 48-pin Package P-LFQFP48-7x7-0.50 PLQP0048KF-A P48GA-50-8EU-1 0.16 Sy e S x bM θ L c Lp HD HE ZD ZE A D E S 0.145 +0.055 −0.045 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 7.00± 0.20 7.00± 0.20 9.00± 0.20 9.00± 0.20 1.60 MAX. 0.10± 0.05 1.40± 0.05 0.25 c θ e x y ZD ZE 0.50 0.08 0.08 0.75 0.75 L Lp 0.50 0.60± 0.15 1.00± 0.20 3°+5° −3° NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22± 0.05b 48 13 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 186 of 200 Jun 30, 2020

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 187 of 200 Jun 30, 2020 2013 Renesas Electronics Corporation. All rights reserved. Sy e Lp S xbA B M A D E A S B A D E DETAIL OF A PART EXPOSED DIE PAD P-HWQFN48-7x7-0.50 PWQN0048KB-A 48PJN-A 0.13 121 2437 INDEX AREA D A Lp 0.20 5.50 0.40 7.00 7.00 5.50 Referance Symbol Min Nom Max Dimension in Millimeters 0.30 0.30 0.50 b 0.18 x A 0.80 y 0.05 0.00 0.25 e Z Z c D E D E E 0.50 0.05 0.75 0.75 0.15 0.25 A1 c 2 7.056.95 7.056.95 Z Z D E 2536 P48K8-50-5B4-6

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 188 of 200 Jun 30, 2020 <R>

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 189 of 200 Jun 30, 2020 4.10 52-pin Package y e x bM L c HD HE A D E ITEM DIMENSIONS D E HD HE A A2 1.40 c e x y 0.65 0.13 0.10 L detail of lead end b 152 0.3P-LQFP52-10x10-0.65 PLQP0052JA-A Previous Code P52GB-65-GBS-1 MASS (TYP .) [g] NOTE 1.Dimensions “ 1” and “ 2” do not include mold flash. 2.Dimension “ 3” does not include trim offset. 2012 Renesas Electronics Corporation. All rights reserved. (UNIT:mm) 10.00± 0.10 10.00± 0.10 12.00± 0.20 12.00± 0.20 1.70 MAX. 0.10± 0.05 0.32± 0.05 0.145± 0.055 0.50± 0.15 0° to 8°

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 190 of 200 Jun 30, 2020 4.11 64-pin Package P-LQFP64-12x12-0.65 PLQP0064JA-A P64GK-65-UET -2 0.51 NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end θ L c Lp HD HE ZD ZE A D E 64 17 Sy e S x bM S 0.145 +0.055 −0.045 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 12.00 ±0.20 12.00 ±0.20 14.00 ±0.20 14.00 ±0.20 1.60 MAX. 0.10 ±0.05 1.40 ±0.05 0.25 c θ e x y ZD ZE 0.65 0.13 0.10 1.125 1.125 L Lp 0.50 0.60 ±0.15 1.00 ±0.20 3°+5° −3° 0.32 +0.08 −0.07b 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 191 of 200 Jun 30, 2020 P-LFQFP64-10x10-0.50 PLQP0064KF-A P64GB-50-UEU-2 0.35 Sy e S x bM θ L c Lp HD HE ZD ZE A D E S 0.145 +0.055 −0.045 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 10.00 ±0.20 10.00 ±0.20 12.00 ±0.20 12.00 ±0.20 1.60 MAX. 0.10 ±0.05 1.40 ±0.05 0.25 c θ e x y ZD ZE 0.50 0.08 0.08 1.25 1.25 L Lp 0.50 0.60 ±0.15 1.00 ±0.20 3°+5° −3° NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 ±0.05b 64 17 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 192 of 200 Jun 30, 2020

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 193 of 200 Jun 30, 2020 P-VFBGA64-4x4-0.40 PVBG0064LA-A P64F1-40-AA2-2 0.03 ITEM DIMENSIONS D E w A e 4.00 ±0.10 4.00 ±0.10 0.40 0.05 0.08 0.20 0.60 0.60 0.15 0.20 ± 0.05 0.05 0.89 ±0.10 0.69 0.25 (UNIT:mm) x y ZD ZE b ZDZE A INDEX MARK A1e Sw A SwB B A Sy Sy1 S SxbA BM A B C DEF G H D E INDEX MARK 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 194 of 200 Jun 30, 2020 4.12 80-pin Package RENESAS Code P-LQFP80-14x14-0.65 PLQP0080JB-E 0.69 D E HD HE A bp c Lp x 0.13 0.886 14.00 14.00 1.40 Min Nom Max Dimension in Millimeters A1 0.05 1.35 0.26 1.70 0.20 1.45 0.38 13.80 13.80 14.20 14.20 0.10 0.20 e 0.736 1.036 0° 8° A3 0.25 0.125 0.32 0.145 L 0.80 1.40 1.80 ZD 0.825 ZE 0.825 ySy e S x bpM L c Lp HD HE ZD ZE A E S detail of lead end 80 21 D A B AB P80GC-65-UBT -2 Previous Code MASS (TYP .) [g]JEIT A Package Code Referance Symbol 17.00 17.20 17.20 17.40 17.00 17.40 1.60 0.65 0.10 2012 Renesas ElectronicsCorporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 195 of 200 Jun 30, 2020 P-LFQFP80-12x12-0.50 PLQP0080KE-A P80GK-50-8EU-2 0.53 Sy e S x bM θ L c Lp HD HE ZD ZE A D E S 0.145 +0.055 −0.045 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 12.00 ±0.20 12.00 ±0.20 14.00 ±0.20 14.00 ±0.20 1.60 MAX. 0.10 ±0.05 1.40 ±0.05 0.25 c θ e x y ZD ZE 0.50 0.08 0.08 1.25 1.25 L Lp 0.50 0.60 ±0.15 1.00 ±0.20 3°+5° −3° NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.22 ±0.05b 80 21 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 196 of 200 Jun 30, 2020

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 197 of 200 Jun 30, 2020 4.13 100-pin Package Sy e S x bM L c Lp HD HE ZD ZE A D E S 0.145 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 14.00 ±0.20 14.00 ±0.20 16.00 ±0.20 16.00 ±0.20 1.60 MAX. 0.10 ±0.05 1.40 ± 0.05 0.25 c e x y ZD ZE 0.50 0.08 0.08 1.00 1.00 L Lp 0.50 0.60 ±0.15 1.00 ±0.20 3° 3° detail of lead end 0.22 0.055 0.045 b 100 26 5175 ±0.05 A B AB P-LFQFP100-14x14-0.50 PLQP0100KE-A P100GC-50-GBR-1 0.69 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 198 of 200 Jun 30, 2020

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 199 of 200 Jun 30, 2020 B Sy e S x bM L c Lp HD HE ZD ZE A D E S 0.145 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 MAX. 0.10 0.05 1.40 0.05 0.07 0.08 0.055 0.045 0.25 c e x y ZD ZE 0.65 0.13 0.10 0.575 0.825 L Lp 0.50 0.60 0.15 1.00 0.20 detail of lead end 0.32b + 100 31 A AB P-LQFP100-14x20-0.65 PLQP0100JC-A P100GF-65-GBN-1 0.92 2012 Renesas Electronics Corporation. All rights reserved.

RL78/G13 4. PACKAGE DRAWINGS R01DS0131EJ0350 Rev.3.50 200 of 200 Jun 30, 2020 4.14 128-pin Package Sy e S x bM L θ c Lp HD HE ZD ZE A D E S 0.145 (UNIT:mm) ITEM DIMENSIONS D E HD HE A 20.00± 0.20 14.00± 0.20 22.00± 0.20 16.00± 0.20 1.60 MAX. 0.10± 0.05 1.40± 0.05 0.25 ce x y ZD ZE 0.50 0.08 0.08 0.75 0.75 L Lp 0.50 0.60± 0.15 1.00± 0.20 detail of lead end b 128 39 65102 103 0.22 θ 3°+5° −3° +0.055 −0.045 ±0.05 A B AB 2012 Renesas Electronics Corporation. All rights reserved. P-LFQFP128-14x20-0.50 PLQP0128KD-A P128GF-50-GBP-1 0.92

Rev. Date

Description

1.00 Feb 29, 2012 - First Edition issued

2.00 Oct 12, 2012 7 Figure 1-1. Part Number, Me mory Size, and Package of RL78/G13: Pin count corrected. 25 1.4 Pin Identification: Description of pins INTP0 to INTP11 corrected. 40, 42, 44 1.6 Outline of F unctions: Descriptions of Subsystem clock, Low-speed on-chip oscillator, and General-purpose register corrected. 41, 43, 45 1.6 Outline of Functi ons: Lists of Descriptions changed. 59, 63, 67 Descriptions of Note 8 in a table corrected. 68 (4) Common to RL78/G13 all products: Descriptions of Notes corrected. 69 2.4 AC Characteristics: Symbol of external system clock frequency corrected. 96 to 98 2.6.1 A/D converter characterist ics: Notes of overall error corrected. 100 2.6.2 Temperature sensor charac teristics: Parameter name corrected. 104 2.8 Flash Memory Programming Characteristics: Incorrect descriptions corrected. 116 3.10 52-pin products: Package drawings of 52-pin products corrected. 120 3.12 80-pin products: Package drawings of 80-pin products corrected. 3.00 Aug 02, 2013 1 Modification of 1.1 Features 3 Modification of 1.2 List of Part Numbers 4 to 15 Modification of Table 1-1. List of Ordering Part Numbers, note, and caution 16 to 32 Modification of package type in 1.3.1 to 1.3.14 33 Modification of description in 1.4 Pin Identification 48, 50, 52 Modification of caution, table, and note in 1.6 Outline of Functions

55 Modification of description in table of Absolute Maximum Ratings (TA = 25C)

57 Modification of table, note, caution, and remark in 2.2.1 X1, XT1 oscillator characteristics 57 Modification of table in 2.2.2 On-chip oscillator characteristics 58 Modification of note 3 of table (1/5) in 2.3.1 Pin characteristics 59 Modification of note 3 of table (2/5) in 2.3.1 Pin characteristics

63 Modification of table in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products

64 Modification of notes 1 and 4 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin

65 Modification of table in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products

66 Modification of notes 1, 5, and 6 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin

68 Modification of notes 1 and 4 in (2) Flash ROM: 96 to 256 KB of 30- to 100-pin

70 Modification of notes 1, 5, and 6 in (2) Flash ROM: 96 to 256 KB of 30- to 100-

72 Modification of notes 1 and 4 in (3) Flash ROM: 384 to 512 KB of 44- to 100-

74 Modification of notes 1, 5, and 6 in (3) Flash ROM: 384 to 512 KB of 44- to

75 Modification of (4) Peripheral Functions (Common to all products)

77 Modification of table in 2.4 AC Characteristics 78, 79 Addition of Minimum Instruction Execution Time during Main System Clock Operation

80 Modification of figures of AC Timing Test Points and External System Clock

Rev. Date

3.00 Aug 02, 2013 81 Modification of figure of AC Timing Test Points

81 Modification of description and note 3 in (1) During communication at same

potential (UART mode)

83 Modification of description in (2) During communication at same potential

(CSI mode)

84 Modification of description in (3) During communication at same potential

(CSI mode)

85 Modification of description in (4) During communication at same potential

(CSI mode) (1/2)

86 Modification of description in (4) During communication at same potential

(CSI mode) (2/2)

88 Modification of table in (5) During communication at same potential (simplified

I2C mode) (1/2)

89 Modification of table and caution in (5) During communication at same

potential (simplified I 2C mode) (2/2)

91 Modification of table and notes 1 and 4 in (6) Communication at different

potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) 92, 93 Modification of table and notes 2 to 7 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) 94 Modification of remarks 1 to 4 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) 95 Modification of table in (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (1/2)

96 Modification of table and caution in (7) Communication at different potential

(2.5 V, 3 V) (CSI mode) (2/2) 97 Modification of table in (8) Communication at different potential (1.8 V, 2.5 V,

3 V) (CSI mode) (1/3)

98 Modification of table, note 1, and caution in (8) Communication at different

potential (1.8 V, 2.5 V, 3 V) (CSI mode) (2/3)

99 Modification of table, note 1, and caution in (8) Communication at different

potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3) 100 Modification of remarks 3 and 4 in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3) 102 Modification of table in (9) Communication at different potential (1.8 V, 2.5 V,

3 V) (CSI mode) (1/2)

103 Modification of table and caution in (9) Communication at different potential

(1.8 V, 2.5 V, 3 V) (CSI mode) (2/2) 106 Modification of table in (10) Communication at different potential (1.8 V, 2.5 V,

3 V) (simplified I2C mode) (1/2)

107 Modification of table, note 1, and caution in (10) Communication at different

potential (1.8 V, 2.5 V, 3 V) (simplified I 2C mode) (2/2)

109 Addition of (1) I2C standard mode

111 Addition of (2) I2C fast mode

112 Addition of (3) I2C fast mode plus

112 Modification of IICA serial transfer timing

113 Addition of table in 2.6.1 A/D converter characteristics 113 Modification of description in 2.6.1 (1) 114 Modification of notes 3 to 5 in 2.6.1 (1) 115 Modification of description and notes 2, 4, and 5 in 2.6.1 (2) 116 Modification of description and notes 3 and 4 in 2.6.1 (3) 117 Modification of description and notes 3 and 4 in 2.6.1 (4)

Rev. Date 3.00 Aug 02, 2013 118 Modification of table in 2.6.2 Temperature sensor/internal reference voltage characteristics 118 Modification of table and note in 2.6.3 POR circuit characteristics 119 Modification of table in 2.6.4 LVD circuit characteristics

120 Modification of table of LVD Detection Voltage of Interrupt & Reset Mode

120 Renamed to 2.6.5 Power supply voltage rising slope characteristics 122 Modification of table, figure, and remark in 2.10 Timing Specs for Switching Flash Memory Programming Modes

123 Modification of caution 1 and description

124 Modification of table and remark 3 in Absolute Maximum Ratings (TA = 25°C)

126 Modification of table, note, caution, and remark in 3.2.1 X1, XT1 oscillator characteristics 126 Modification of table in 3.2.2 On-chip oscillator characteristics 127 Modification of note 3 in 3.3.1 Pin characteristics (1/5) 128 Modification of note 3 in 3.3.1 Pin characteristics (2/5)

133 Modification of notes 1 and 4 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin

products (1/2)

135 Modification of notes 1, 5, and 6 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin

products (2/2)

137 Modification of notes 1 and 4 in (2) Flash ROM: 96 to 256 KB of 30- to 100-pin

products (1/2)

139 Modification of notes 1, 5, and 6 in (2) Flash ROM: 96 to 256 KB of 30- to 100-

pin products (2/2)

140 Modification of (3) Peripheral Functions (Common to all products)

142 Modification of table in 3.4 AC Characteristics

143 Addition of Minimum Instruction Execution Time during Main System Clock

143 Modification of figure of AC Timing Test Points

143 Modification of figure of External System Clock Timing

145 Modification of figure of AC Timing Test Points

145 Modification of description, note 1, and caution in (1) During communication at

same potential (UART mode)

146 Modification of description in (2) During communication at same potential

(CSI mode)

147 Modification of description in (3) During communication at same potential

(CSI mode)

149 Modification of table, note 1, and caution in (4) During communication at same

potential (simplified I2C mode)

151 Modification of table, note 1, and caution in (5) Communication at different

potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) 152 to 154 Modification of table, notes 2 to 6, caution, and remarks 1 to 4 in (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) 155 Modification of table in (6) Communication at different potential (1.8 V, 2.5 V,

156 Modification of table and caution in (6) Communication at different potential

(1.8 V, 2.5 V, 3 V) (CSI mode) (2/3) 157, 158 Modification of table, caution, and remarks 3 and 4 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3) 160, 161 Modification of table and caution in (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode)

Rev. Date 3.00 Aug 02, 2013 163 Modification of table in (8) Communication at different potential (1.8 V, 2.5 V, 164, 165 Modification of table, note 1, and caution in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) 166 Modification of table in 3.5.2 Serial interface IICA

166 Modification of IICA serial transfer timing

167 Addition of table in 3.6.1 A/D converter characteristics 167, 168 Modification of table and notes 3 and 4 in 3.6.1 (1) 169 Modification of description in 3.6.1 (2) 170 Modification of description and note 3 in 3.6.1 (3) 171 Modification of description and notes 3 and 4 in 3.6.1 (4) 172 Modification of table and note in 3.6.3 POR circuit characteristics

173 Modification of table of LVD Detection Voltage of Interrupt & Reset Mode

173 Modification from Supply Voltage Rise Time to 3.6.5 Power supply voltage rising slope characteristics 174 Modification of 3.9 Dedicated Flash Memory Programmer Communication (UART) 175 Modification of table, figure, and remark in 3.10 Timing Specs for Switching Flash Memory Programming Modes 3.10 Nov 15, 2013 123 Caution 4 added. 125 Note for operating ambient temperature in 3.1 Absolute Maximum Ratings deleted.

3.30 Mar 31, 2016 18 Modification of the position of the index mark in 25-pin plastic WFLGA (3 × 3

mm, 0.50 mm pitch) of 1.3.3 25-pin products 49 Modification of power supply voltage in 1.6 Outline of Functions [20-pin, 24- pin, 25-pin, 30-pin, 32-pin, 36-pin products] 51 Modification of power supply voltage in 1.6 Outline of Functions [40-pin, 44- pin, 48-pin, 52-pin, 64-pin products] 53 Modification of power supply voltage in 1.6 Outline of Functions [80-pin, 100- pin, 128-pin products] 110 to 112, 167 ACK corrected to ACK 3.40 May 31, 2018 172 Addition of note in 3.6.3 POR circuit characteristics

3.41 Jan 31, 2020 3 Addition of packaging specifications in Figure 1-1 Part Number, Memory Size,

4 to 28 Addition of ordering part numbers and RENESAS codes in Table 1-1 List of Ordering Part Numbers 189, 190, 192 to 194, 196 to 198, 200, 202 to 205, 207 to 209, 211, 213, 214 Modification of the titles of the subchapters and deletion of product names in Chapter 4 191 Addition of figure in 4.2 24-pin Package 195 Addition of figure in 4.3 32-pin Package 199 Addition of figure in 4.8 44-pin Package

Rev. Date 3.41 Jan 31, 2020 201 Addition of figure in 4.9 48-pin Package 206 Addition of figure in 4.11 64-pin Package 210 Addition of figure in 4.12 80-pin Package 212 Addition of figure in 4.13 100-pin Package 3.50 Jun 30, 2020 1 Modification of description in 1.1 Features

3 Modification of Figure 1-1 Part Number, Memory Size, and Package of

4 to 11 Modification of Table 1-1 List of Ordering Part Numbers 12 Addition of packaging specifications in 1.3.1 20-pin products 173 Addition of package drawing in 4.1 20-pin Package 182 Addition of package drawing in 4.7 40-pin Package 188 Addition of package drawing in 4.9 48-pin Package All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.

General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. 2. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the level at which resetting is specified. 3. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-off state as described in your product documentation. 4. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. 5. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. 6. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). 7. Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these addresses as the correct operation of the LSI is not guaranteed. 8. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system- evaluation test for the given product.

http://www.renesas.comSALES OFFICES (Rev.4.0-1 November 2017) Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). 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6024 Silver Creek Valley Road, San Jose, CA 95138, USA

Renesas Electronics Canada Limited

9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3

Tel: +1-905-237-2004 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Renesas Electronics (China) Co., Ltd. Room 101-T01, Floor 1, Building 7, Yard No. 7, 8th Street, Shangdi, Haidian District, Beijing 100085, China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai 200333, China Tel: +86-21-2226-0888, Fax: +86-21-2226-0999 Renesas Electronics Hong Kong Limited Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2265-6688, Fax: +852 2886-9022 Renesas Electronics Taiwan Co., Ltd. 13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd.

80 Bendemeer Road, #06-02 Singapore 339949

Tel: +65-6213-0200, Fax: +65-6213-0300 Renesas Electronics Malaysia Sdn.Bhd. Unit No 3A-1 Level 3A Tower 8 UOA Business Park, No 1 Jalan Pengaturcara U1/51A, Seksyen U1, 40150 Shah Alam, Selangor, Malaysia Renesas Electronics India Pvt. Ltd. No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India Tel: +91-80-67208700 Renesas Electronics Korea Co., Ltd. 17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea

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Renesas Technology Corp G13 overview.

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Source title G13 Datasheet(PDF) - Renesas Technology Corp

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