FX419 ETC
Document overview
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Publication D/419/4 May 1987 Provisional Issue Features Reqalinetions @ 1200 Baud FFSK Modem i» Mobile and Cellular Radio ® Meets Cellular and Trunked Radio Data Signalling Specifications « NMT 450/900 # Full Duplex 1200 Baud «~ Band I
2 On-Chip Rx and Tx Bandpass Filters » Radiocom 2000
e Clock Recovery and Carrier «= ZVEI Detect Facilities Personal Radio @ Single 5 Volt CMOS Process # Portable Data Terminals @ Surface Mount or DIL Package Styles .. General Purpose Applications \\o9 ——— Nous ———> Xs ———> TALL cLocK 9, CARRIER DETECT 7A, [osfitShon|>fowoen] TS TIME CONSTANT (T) BANDPASS| CLOCKED, Rx DATA ourrut RECTIFIER oS FX41 9 LIMITER RE-TRIG DATA (POWERSAVE) MONOSTABLE FILTER: TimiteR Rx DATA Tx ENABLE Tx SYNC (POWERSAVE) Ae Tx GENERATOR = Tx FILTER BUFFER Fig. 1 Internal Block Diagram af Cescription The FX419 is a single chip CMOS LSI circuit crystal is required for this purpose. The which operates as a 1200 baud FFSK device includes circuitry for carrier detect and modem. The mark and space frequencies are facility for the Rx clock recovery. An on- 1200Hz and 1800Hz phase continuous and board switched capacitor 900Hz—2100Hz the frequency transitions occur at the zero bandpass filter provides optimum carrier crossing point. The transmitter and receiver filtering. The use of switched capacitor will work independently, thus providing full analogue filters and digital signal processing duplex operation at 1200 baud. The baud results in excellent dynamic performance with rate, transmit mark and space frequencies, few external components, the CMOS process Tx synchronization and Rx synchronization and current saving techniques offer low are all derived from a crystal oscillator for standby supply current for portable battery high stability, and an external 1.008MHz powered applications.
_ ee Quad | DIL Plastic PLCC FX419J | FX419LG | FX419LH 1 1 1 Xtal/Clock: The input to an on-chip inverter for use with a 1.008MHz xtal. i Alternatively, a 1.008MHz clock may be used. | 2 2 2 Xtal: Output of on-chip inverter. | - - 3 No Connection: Leave open circuit. | 3 3 4 Tx Sync O/P: A 1200Hz squarewave used to synchronize the input of logic i \\data and transmission of the FFSK signal (See Fig. 5). \\ 4 4 56 No Connection: Leave open circuit. | 5 5 7 Tx Signal O/P: With transmitter disabled, this pin is set to a high impedance { state. When transmitter is enabled, this pin outputs the 1200/1800Hz (140 step | pseudo-sinewave) FFSK signal (See Fig. 5). i - - 8 No Connection: Leave open circuit. | 6 7 9 Tx Data I/P: Serial logic data to be transmitted, is input to this pin and synchronized by the ‘’Tx Sync 0/P’”’ (See Fig. 5). i 7 8 10 Tx Enable: A logic ‘1’ applied to this input will put the transmitter into | powersave whilst forcing “Tx Sync O/P” to logic ‘1’ and “Tx Signal O/P” toa | high impedance state. A logic ‘0’ will enable the transmitter (See Fig. 5). This pin is internally pulled to Vy. 8 9 1 Bandpass O/P: This is the output of the Rx 900-2100Hz bandpass filter. The H output impedance of this pin is typically 10kQ and may require buffering prior \\ to use. i 9 10 12 Rx Enable: A logic ‘0’ applied to this input will put the receiver into powersave | whilst forcing ‘‘Clocked Data O/P” and ‘’Carrier Detect’’ to logic ‘0’. A logic ‘1’ | will enable the receiver (See Figures 2 and 6). ‘‘Rx Sync Out’’ may be logic ‘1’ | or ‘0’ during powersave. This pin is internally pulled to Vpp. H 10 1 13 | Bias: Provides bias internally and should be decoupled externally to YW. by a [capacitor (See Fig 2). | 1 12 14 “st Negative supply. | 12 13 15 Unclocked Data O/P: This pin outputs recovered asynchronous serial data | from the receiver. | 13 14 16 | Clocked Data O/P: This pin outputs recovered synchronous serial data from | the receiver and is internally latched out by a recovered clock appearing on the “Rx Sync O/P” pin (See Figures 2 and 6). 14 15 17 Carrier Detect: This pin will output a logic ‘1’ when an FFSK signal is being received. _- - 18,19 No Connection: Leave open circuit. 15 16 20 |Rx Signal I/P: This is the FFSK signal input pin for the receiver and should be |decoupled via a capacitor C,. 16 17 21 [No Connection: Leave open circuit. 17 18 22 Rx Syne O/P: This is a flywheel 1200Hz squarewave output which upon presentation of FFSK data signal is synchronised internally to the incoming data (See Figures 2 and 6). | 18,19 | 19,20,21| 23,24, oe a 25,26 No Connection: Leave open circuit. 20 22 27 Carrier Detect Time Constant (T ): This input forms part of the carrier detect | integration function. The value of C, connected to this pin will affect the carrie { detect response time and hence noise performance (See Fig. 2, Note 4). { 21 23 - No Connection: Leave open circuit. 22 24 28 Voo : Positive supply. Hl Note: Output Loading. i Large capacitive loads could cause the output pins of this device to oscillate. If capacitive loads in excess of | 200pF are unavoidable, a resistor of typically <1002 put in series with the load should minimise this effect.
—_ Nnote2 |c, XTAL 2 N/C
217 CARRIER Component References
¢c Tx SYNC O/P_ 3 2» DETECT TC(T)
1 Unit: Tolerance
R, 1M +10 Ns Ves, Tx SIG O/P 5 18 N/C c Bp “0 TepaTAPy|, — FXA19N x Sync ov! 8 a oly v7 G Oty +10 Yo Nove 3 —TZENABLE | , Le & fA 220 vr sanppass | Rx e EMH Soecatie — OUTPUT SIGNAL 1/P com Rx ENABLE CARRIER NOTET NOTES ° “VDETECT O7P BIAS 10 3 CLOCKED DATA 0/P- c. " 2 pUNGLOCKED 3. The value of C, determines the carrier detect time constant. A long Nore? N/C: NO CONNECTION time constant results in improved Nes NOTES: noise immunity but increased 1. Bias may be decoupled to Vss and response time. C, may be varied to Vop using Cz and Cz when input trade-off response time for noise signals are referenced to the bias pin, immunity. For input signals referenced to Vss, 4. ‘The value of C7reduces xtal voltage decouple Bias to Vss using C, only. overshoot. Refer to CML Xtal 2. Use Cs when input signals are Oscillator application note D/XT/1 Fig. 2. External Component Connections —_@*erenced to Ves, to decouple Vpp- APRIL 1986. 1x10-" wal aml Lo 1x10? OF 4 Zz Be = ST ve ee 4 ¥ ae 110-4 \\ 50 100 150 200 250 300 500 700 800 Fig. 3 Typical Variation of ‘B.E.R.” with Input Signal Level INPUT SIGNAL LEVEL (mV rns) Ye Yo Ea “Incorporates an attenuator & EX 5kHz BW. noise generator. cxocxen vA sighaL newt [age pe oat poeheanreus = | NBUT | reanauurren LOUTPC | aursce rasthone PE Paey EGP enon gstuo0 RANDOM (Couronents eincutt Sn oes DETECTOR cannes ene Xe ov Ve cannien oscioscore VOLIMeTER VOuIMeTER orp ricer SerecrOn Fig. 4 FX419 Test set-up.
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage —0.3V to 7.0V Input voltage at any pin (ref W, = OV) —0.3V to (Vp + 0.3V) Output sink/source current (total) 20mA Operating temperature range: FX419J -30°C to + 85°C FX419LG/LH -30°C to + 70°C Storage temperature range: FX419J —§5°C to + 125°C FX419LGLH —40°C to + 85°C Maximum device dissipation: All versions 100mW. Operating Limits yo = +5V, Tamb = 25°C, @ = 1.008MHz (Xtal), Afg = 0 All characteristics measured using the standard test circuit (figure 4) with the following test parameters and is valid for all tests unless otherwise stated: OdB reference 300mV rms Noise (band limited 5kHz gaussian white noise) SNR ratio measured in bit rate bandwidth (1200Hz) eS Characteristics See Note Min Typ Max Unit SSSSsSSSSSSSSSSSSSSSSSsssSsSSSSSSe Static Characteristics Supply volts 4.5 5.0 5.5 Vv Supply current: Rx (Enabled) Tx (Disabled) - 3.6 - mA Rx (Enabled) Tx (Enabled) al 45 - mA Rx (Disabled) Tx (Disabled) = 650 _ uA Logic ‘1’ level 80% Voy - - Vv Logic ‘0’ level - - 20%Vpn =-V Digital O/P Impedance - 4 - kQ Analogue and Digital input impedance 100 - - kQ Tx O/P impedance - 10 - kQ. On-chip crystal oscillator: Rin 10 - ~ mo Rout 5 - 15 ka Inverter gain 10 - 20 dB Gain Bandwidth Product 3x 10° - - Crystal frequency 1 _ 1.008 - MHz Dynamic Characteristics Receiver: Signal Input: Dynamic range (50dB SNR) 2, 3 100 230 1000 mV rms Bit Error Rate: 12dB SNR 3 - 7.0 - 10-* 20dB SNR 3 - 1.0 - 10-* Receiver Synchronization 12dB SNR: 6 Probability of bit 8 being correct 0.99 Probability of bit 16 being correct 0.995, Carrier Detect 6 Probability of Carrier Detect being high: 12dB SNR after bit 8 4 0.99 0.98 12dB SNR after bit 16 4 0.999 0.995 OdB noise 0.01 Transmitter O/P Tx O/P level - 7715 - mV rms Output level variation 1200/1800Hz 0 - +1.00 dB O/P distortion - 3 5 % 3rd harmonic distortion - 2 3 % Logic ‘1’ carrier frequency 5 - 1200 _ Hz Logic ‘0’ carrier frequency 5 - 1800 - Hz Isochronous distortion 1200Hz — 1800Hz - 25 40 ey 1800Hz — 1200Hz - 20 40 us Notes: 7. Crystal tolerance depends on system requirements. 2. See Fig. 3. 3. SNR (Bit Rate Bandwidth). 4. See Fig. 2 Note 5. 5. Depending on crystal tolerance. 6. 101010 Pattern. -
| Sree 2.8 MN ih 1! 800ys MAX ENABLE ee 1 1 u i 7 7 ' i - 1 1 Tx 1 t ~ LI LILI Lo SEE NOTE 3 le. oie »! Tx 7 i DATA |'P- . i ee eeaecge a 1_SEENOTES in 7 7 Fr I 2 ' \\ I | ras ' a i 1 a} fi ', i i i} ' i 1, iH | wl i | x signar Oren ciRCUT, Lf LEN CIRCUT ore NOTES: 1. All timings are related to TX Sync Output. 2. 0,833ms for 1.008MHz Crystal Input. 3. 2us Min + Crystal tolerance. 4, DC = Don't Care, DV = Data Valid. Fig. § Transmitter Timing Diagram 2x 107? i) LoGic: LOGIC 1 1 0 ' ' 107? Rx | \\ SIGNAL INPUT | fi FX419 ' 1 IDEAL I t (COHERENT FFSK L ~ ag 107 (NOTE 1) a BE oe : 1 i 8 Rx SYNC FA OUTPUT fy (1200 Hz) Fs J 1 1 g 1 1 1 3 (NOTE 4) —> o 107% (Nore 21} | ' & 3 t a 8 y----- IL 1 § KED 4 cLocKe Loaic, Logic 3 Lt LM ~ (NOTE3) 10 01234567 8910111213 1415 16 NOTES: 1. Internal Delay-typ 1.5ms. SNR (dB) BIT RATE BANDWIDTH (LIN. SCALE) 2. From freely running to Sync in & data bits (See spec). 3. Undetermined state—2us max. 4, Min, 800us—Max. 8654s.
The FX419J, the cerdip package, is illustrated The FX419J/ LG/LH is a CMOS LSI circuit in Figure 8. The ‘LG’ version is shown in which includes input protection. However, Figure 9, and the ‘LH’ version in Figure 10. precautions should be taken to prevent static Both ‘LG’ and ‘LH’ packages are supplied in discharges which may cause damage. conductive trays for handling convenience. To allow complete identification, the é FX419LG and LH packages have an indent spot adjacent to Pin 1 and a chamfered a al , - corner between Pins 3 and 4 for LG package, STB omy | 4 between Pins 4 and 5 for LH package. Pins | _ | i number anti-clockwise when viewed from the | ARAA OA « top (indent side). 1 Ef +— Tae aie - . _ ne Datum & Symmetry : + jiu <i £ ‘be Ot . ' ; a <i 6 838 822 PIN « 4 19 128 ‘e K 15.65 — oka t a” on Ff 19 oe f a S gery fk & — Teicat 1 46 pie vy 23 TYPICAL | +, det w 0.07 ~ -— »o * | NOTE: All dimensions in mm. DIMENSION MAX MIN A 27.38 26.98 8 9.75 9.55 c 10.60 10.40 o 2.50, 25.30 “7 4] 07 B 3a TYPICAL | kyr 0.46 § DIMENSION bead | GS 4.30 4.10 Ae , H 4.27 3.99 ANDENT P= “Nn 1 14 TYPICAL PINT | | q = ke | ey | | F FX419J = -22-pin Cerdip DIL ol ° a FX419LG 24-pin quad plastic yy ' encapsulated, bent and ce cropped. FX419LH 28-lead Plastic leaded NOTE: All dimensions in mm. Angles in degrees. . . DIMENSION MAX mi chip carrier. $ BB 23 © eas? TypIGAL 5 3 TPIeaL e 08 10.0 F 0.86 TYPICAL 6 7 a fi a ES 3 4s 43 x 28 TyPICAL t v1 os M oe TyPicaL N oe TyPIcAL CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.